| 1 | /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ |
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| 2 | /* Copyright (c) 2017 - 2021 Intel Corporation */ |
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| 3 | #ifndef ICRDMA_HW_H |
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| 4 | #define ICRDMA_HW_H |
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| 5 | |
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| 6 | #include "irdma.h" |
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| 7 | |
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| 8 | #define VFPE_CQPTAIL1 0x0000a000 |
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| 9 | #define VFPE_CQPDB1 0x0000bc00 |
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| 10 | #define VFPE_CCQPSTATUS1 0x0000b800 |
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| 11 | #define VFPE_CCQPHIGH1 0x00009800 |
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| 12 | #define VFPE_CCQPLOW1 0x0000ac00 |
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| 13 | #define VFPE_CQARM1 0x0000b400 |
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| 14 | #define VFPE_CQARM1 0x0000b400 |
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| 15 | #define VFPE_CQACK1 0x0000b000 |
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| 16 | #define VFPE_AEQALLOC1 0x0000a400 |
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| 17 | #define VFPE_CQPERRCODES1 0x00009c00 |
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| 18 | #define VFPE_WQEALLOC1 0x0000c000 |
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| 19 | #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ |
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| 20 | |
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| 21 | #define PFPE_CQPTAIL 0x00500880 |
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| 22 | #define PFPE_CQPDB 0x00500800 |
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| 23 | #define PFPE_CCQPSTATUS 0x0050a000 |
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| 24 | #define PFPE_CCQPHIGH 0x0050a100 |
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| 25 | #define PFPE_CCQPLOW 0x0050a080 |
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| 26 | #define PFPE_CQARM 0x00502c00 |
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| 27 | #define PFPE_CQACK 0x00502c80 |
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| 28 | #define PFPE_AEQALLOC 0x00502d00 |
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| 29 | #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ |
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| 30 | #define GLPCI_LBARCTRL 0x0009de74 |
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| 31 | #define GLPE_CPUSTATUS0 0x0050ba5c |
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| 32 | #define GLPE_CPUSTATUS1 0x0050ba60 |
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| 33 | #define GLPE_CPUSTATUS2 0x0050ba64 |
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| 34 | #define PFINT_AEQCTL 0x0016cb00 |
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| 35 | #define PFPE_CQPERRCODES 0x0050a200 |
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| 36 | #define PFPE_WQEALLOC 0x00504400 |
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| 37 | #define GLINT_CEQCTL(_INT) (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */ |
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| 38 | #define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ |
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| 39 | #define PFHMC_PDINV 0x00520300 |
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| 40 | #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ |
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| 41 | #define GLPE_CRITERR 0x00534000 |
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| 42 | #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ |
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| 43 | |
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| 44 | #define ICRDMA_DB_ADDR_OFFSET (8 * 1024 * 1024 - 64 * 1024) |
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| 45 | |
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| 46 | #define ICRDMA_VF_DB_ADDR_OFFSET (64 * 1024) |
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| 47 | |
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| 48 | /* shifts/masks for FLD_[LS/RS]_64 macros used in device table */ |
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| 49 | #define ICRDMA_CCQPSTATUS_CCQP_DONE_S 0 |
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| 50 | #define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0) |
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| 51 | #define ICRDMA_CCQPSTATUS_CCQP_ERR_S 31 |
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| 52 | #define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31) |
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| 53 | #define ICRDMA_CQPSQ_STAG_PDID_S 46 |
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| 54 | #define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46) |
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| 55 | #define ICRDMA_CQPSQ_CQ_CEQID_S 22 |
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| 56 | #define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22) |
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| 57 | #define ICRDMA_CQPSQ_CQ_CQID_S 0 |
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| 58 | #define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0) |
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| 59 | #define ICRDMA_COMMIT_FPM_CQCNT_S 0 |
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| 60 | #define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0) |
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| 61 | |
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| 62 | enum icrdma_device_caps_const { |
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| 63 | ICRDMA_MAX_STATS_COUNT = 128, |
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| 64 | |
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| 65 | ICRDMA_MAX_IRD_SIZE = 127, |
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| 66 | ICRDMA_MAX_ORD_SIZE = 255, |
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| 67 | ICRDMA_MIN_WQ_SIZE = 8 /* WQEs */, |
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| 68 | |
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| 69 | }; |
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| 70 | |
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| 71 | void icrdma_init_hw(struct irdma_sc_dev *dev); |
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| 72 | #endif /* ICRDMA_HW_H*/ |
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| 73 | |
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