1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 */
6
7#ifndef __FSL_PAMU_H
8#define __FSL_PAMU_H
9
10#include <linux/iommu.h>
11#include <linux/pci.h>
12
13#include <asm/fsl_pamu_stash.h>
14
15/* Bit Field macros
16 * v = bit field variable; m = mask, m##_SHIFT = shift, x = value to load
17 */
18#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << m##_SHIFT) & (m)))
19#define get_bf(v, m) (((v) & (m)) >> m##_SHIFT)
20
21/* PAMU CCSR space */
22#define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */
23#define PAMU_PE 0x40000000 /* enable PAMU */
24
25/* PAMU_OFFSET to the next pamu space in ccsr */
26#define PAMU_OFFSET 0x1000
27
28#define PAMU_MMAP_REGS_BASE 0
29
30struct pamu_mmap_regs {
31 u32 ppbah;
32 u32 ppbal;
33 u32 pplah;
34 u32 pplal;
35 u32 spbah;
36 u32 spbal;
37 u32 splah;
38 u32 splal;
39 u32 obah;
40 u32 obal;
41 u32 olah;
42 u32 olal;
43};
44
45/* PAMU Error Registers */
46#define PAMU_POES1 0x0040
47#define PAMU_POES2 0x0044
48#define PAMU_POEAH 0x0048
49#define PAMU_POEAL 0x004C
50#define PAMU_AVS1 0x0050
51#define PAMU_AVS1_AV 0x1
52#define PAMU_AVS1_OTV 0x6
53#define PAMU_AVS1_APV 0x78
54#define PAMU_AVS1_WAV 0x380
55#define PAMU_AVS1_LAV 0x1c00
56#define PAMU_AVS1_GCV 0x2000
57#define PAMU_AVS1_PDV 0x4000
58#define PAMU_AV_MASK (PAMU_AVS1_AV | PAMU_AVS1_OTV | PAMU_AVS1_APV | PAMU_AVS1_WAV \
59 | PAMU_AVS1_LAV | PAMU_AVS1_GCV | PAMU_AVS1_PDV)
60#define PAMU_AVS1_LIODN_SHIFT 16
61#define PAMU_LAV_LIODN_NOT_IN_PPAACT 0x400
62
63#define PAMU_AVS2 0x0054
64#define PAMU_AVAH 0x0058
65#define PAMU_AVAL 0x005C
66#define PAMU_EECTL 0x0060
67#define PAMU_EEDIS 0x0064
68#define PAMU_EEINTEN 0x0068
69#define PAMU_EEDET 0x006C
70#define PAMU_EEATTR 0x0070
71#define PAMU_EEAHI 0x0074
72#define PAMU_EEALO 0x0078
73#define PAMU_EEDHI 0X007C
74#define PAMU_EEDLO 0x0080
75#define PAMU_EECC 0x0084
76#define PAMU_UDAD 0x0090
77
78/* PAMU Revision Registers */
79#define PAMU_PR1 0x0BF8
80#define PAMU_PR2 0x0BFC
81
82/* PAMU version mask */
83#define PAMU_PR1_MASK 0xffff
84
85/* PAMU Capabilities Registers */
86#define PAMU_PC1 0x0C00
87#define PAMU_PC2 0x0C04
88#define PAMU_PC3 0x0C08
89#define PAMU_PC4 0x0C0C
90
91/* PAMU Control Register */
92#define PAMU_PC 0x0C10
93
94/* PAMU control defs */
95#define PAMU_CONTROL 0x0C10
96#define PAMU_PC_PGC 0x80000000 /* PAMU gate closed bit */
97#define PAMU_PC_PE 0x40000000 /* PAMU enable bit */
98#define PAMU_PC_SPCC 0x00000010 /* sPAACE cache enable */
99#define PAMU_PC_PPCC 0x00000001 /* pPAACE cache enable */
100#define PAMU_PC_OCE 0x00001000 /* OMT cache enable */
101
102#define PAMU_PFA1 0x0C14
103#define PAMU_PFA2 0x0C18
104
105#define PAMU_PC2_MLIODN(X) ((X) >> 16)
106#define PAMU_PC3_MWCE(X) (((X) >> 21) & 0xf)
107
108/* PAMU Interrupt control and Status Register */
109#define PAMU_PICS 0x0C1C
110#define PAMU_ACCESS_VIOLATION_STAT 0x8
111#define PAMU_ACCESS_VIOLATION_ENABLE 0x4
112
113/* PAMU Debug Registers */
114#define PAMU_PD1 0x0F00
115#define PAMU_PD2 0x0F04
116#define PAMU_PD3 0x0F08
117#define PAMU_PD4 0x0F0C
118
119#define PAACE_AP_PERMS_DENIED 0x0
120#define PAACE_AP_PERMS_QUERY 0x1
121#define PAACE_AP_PERMS_UPDATE 0x2
122#define PAACE_AP_PERMS_ALL 0x3
123
124#define PAACE_DD_TO_HOST 0x0
125#define PAACE_DD_TO_IO 0x1
126#define PAACE_PT_PRIMARY 0x0
127#define PAACE_PT_SECONDARY 0x1
128#define PAACE_V_INVALID 0x0
129#define PAACE_V_VALID 0x1
130#define PAACE_MW_SUBWINDOWS 0x1
131
132#define PAACE_WSE_4K 0xB
133#define PAACE_WSE_8K 0xC
134#define PAACE_WSE_16K 0xD
135#define PAACE_WSE_32K 0xE
136#define PAACE_WSE_64K 0xF
137#define PAACE_WSE_128K 0x10
138#define PAACE_WSE_256K 0x11
139#define PAACE_WSE_512K 0x12
140#define PAACE_WSE_1M 0x13
141#define PAACE_WSE_2M 0x14
142#define PAACE_WSE_4M 0x15
143#define PAACE_WSE_8M 0x16
144#define PAACE_WSE_16M 0x17
145#define PAACE_WSE_32M 0x18
146#define PAACE_WSE_64M 0x19
147#define PAACE_WSE_128M 0x1A
148#define PAACE_WSE_256M 0x1B
149#define PAACE_WSE_512M 0x1C
150#define PAACE_WSE_1G 0x1D
151#define PAACE_WSE_2G 0x1E
152#define PAACE_WSE_4G 0x1F
153
154#define PAACE_DID_PCI_EXPRESS_1 0x00
155#define PAACE_DID_PCI_EXPRESS_2 0x01
156#define PAACE_DID_PCI_EXPRESS_3 0x02
157#define PAACE_DID_PCI_EXPRESS_4 0x03
158#define PAACE_DID_LOCAL_BUS 0x04
159#define PAACE_DID_SRIO 0x0C
160#define PAACE_DID_MEM_1 0x10
161#define PAACE_DID_MEM_2 0x11
162#define PAACE_DID_MEM_3 0x12
163#define PAACE_DID_MEM_4 0x13
164#define PAACE_DID_MEM_1_2 0x14
165#define PAACE_DID_MEM_3_4 0x15
166#define PAACE_DID_MEM_1_4 0x16
167#define PAACE_DID_BM_SW_PORTAL 0x18
168#define PAACE_DID_PAMU 0x1C
169#define PAACE_DID_CAAM 0x21
170#define PAACE_DID_QM_SW_PORTAL 0x3C
171#define PAACE_DID_CORE0_INST 0x80
172#define PAACE_DID_CORE0_DATA 0x81
173#define PAACE_DID_CORE1_INST 0x82
174#define PAACE_DID_CORE1_DATA 0x83
175#define PAACE_DID_CORE2_INST 0x84
176#define PAACE_DID_CORE2_DATA 0x85
177#define PAACE_DID_CORE3_INST 0x86
178#define PAACE_DID_CORE3_DATA 0x87
179#define PAACE_DID_CORE4_INST 0x88
180#define PAACE_DID_CORE4_DATA 0x89
181#define PAACE_DID_CORE5_INST 0x8A
182#define PAACE_DID_CORE5_DATA 0x8B
183#define PAACE_DID_CORE6_INST 0x8C
184#define PAACE_DID_CORE6_DATA 0x8D
185#define PAACE_DID_CORE7_INST 0x8E
186#define PAACE_DID_CORE7_DATA 0x8F
187#define PAACE_DID_BROADCAST 0xFF
188
189#define PAACE_ATM_NO_XLATE 0x00
190#define PAACE_ATM_WINDOW_XLATE 0x01
191#define PAACE_ATM_PAGE_XLATE 0x02
192#define PAACE_ATM_WIN_PG_XLATE (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
193#define PAACE_OTM_NO_XLATE 0x00
194#define PAACE_OTM_IMMEDIATE 0x01
195#define PAACE_OTM_INDEXED 0x02
196#define PAACE_OTM_RESERVED 0x03
197
198#define PAACE_M_COHERENCE_REQ 0x01
199
200#define PAACE_PID_0 0x0
201#define PAACE_PID_1 0x1
202#define PAACE_PID_2 0x2
203#define PAACE_PID_3 0x3
204#define PAACE_PID_4 0x4
205#define PAACE_PID_5 0x5
206#define PAACE_PID_6 0x6
207#define PAACE_PID_7 0x7
208
209#define PAACE_TCEF_FORMAT0_8B 0x00
210#define PAACE_TCEF_FORMAT1_RSVD 0x01
211/*
212 * Hard coded value for the PAACT size to accommodate
213 * maximum LIODN value generated by u-boot.
214 */
215#define PAACE_NUMBER_ENTRIES 0x500
216/* Hard coded value for the SPAACT size */
217#define SPAACE_NUMBER_ENTRIES 0x800
218
219#define OME_NUMBER_ENTRIES 16
220
221/* PAACE Bit Field Defines */
222#define PPAACE_AF_WBAL 0xfffff000
223#define PPAACE_AF_WBAL_SHIFT 12
224#define PPAACE_AF_WSE 0x00000fc0
225#define PPAACE_AF_WSE_SHIFT 6
226#define PPAACE_AF_MW 0x00000020
227#define PPAACE_AF_MW_SHIFT 5
228
229#define SPAACE_AF_LIODN 0xffff0000
230#define SPAACE_AF_LIODN_SHIFT 16
231
232#define PAACE_AF_AP 0x00000018
233#define PAACE_AF_AP_SHIFT 3
234#define PAACE_AF_DD 0x00000004
235#define PAACE_AF_DD_SHIFT 2
236#define PAACE_AF_PT 0x00000002
237#define PAACE_AF_PT_SHIFT 1
238#define PAACE_AF_V 0x00000001
239#define PAACE_AF_V_SHIFT 0
240
241#define PAACE_DA_HOST_CR 0x80
242#define PAACE_DA_HOST_CR_SHIFT 7
243
244#define PAACE_IA_CID 0x00FF0000
245#define PAACE_IA_CID_SHIFT 16
246#define PAACE_IA_WCE 0x000000F0
247#define PAACE_IA_WCE_SHIFT 4
248#define PAACE_IA_ATM 0x0000000C
249#define PAACE_IA_ATM_SHIFT 2
250#define PAACE_IA_OTM 0x00000003
251#define PAACE_IA_OTM_SHIFT 0
252
253#define PAACE_WIN_TWBAL 0xfffff000
254#define PAACE_WIN_TWBAL_SHIFT 12
255#define PAACE_WIN_SWSE 0x00000fc0
256#define PAACE_WIN_SWSE_SHIFT 6
257
258/* PAMU Data Structures */
259/* primary / secondary paact structure */
260struct paace {
261 /* PAACE Offset 0x00 */
262 u32 wbah; /* only valid for Primary PAACE */
263 u32 addr_bitfields; /* See P/S PAACE_AF_* */
264
265 /* PAACE Offset 0x08 */
266 /* Interpretation of first 32 bits dependent on DD above */
267 union {
268 struct {
269 /* Destination ID, see PAACE_DID_* defines */
270 u8 did;
271 /* Partition ID */
272 u8 pid;
273 /* Snoop ID */
274 u8 snpid;
275 /* coherency_required : 1 reserved : 7 */
276 u8 coherency_required; /* See PAACE_DA_* */
277 } to_host;
278 struct {
279 /* Destination ID, see PAACE_DID_* defines */
280 u8 did;
281 u8 reserved1;
282 u16 reserved2;
283 } to_io;
284 } domain_attr;
285
286 /* Implementation attributes + window count + address & operation translation modes */
287 u32 impl_attr; /* See PAACE_IA_* */
288
289 /* PAACE Offset 0x10 */
290 /* Translated window base address */
291 u32 twbah;
292 u32 win_bitfields; /* See PAACE_WIN_* */
293
294 /* PAACE Offset 0x18 */
295 /* first secondary paace entry */
296 u32 fspi; /* only valid for Primary PAACE */
297 union {
298 struct {
299 u8 ioea;
300 u8 moea;
301 u8 ioeb;
302 u8 moeb;
303 } immed_ot;
304 struct {
305 u16 reserved;
306 u16 omi;
307 } index_ot;
308 } op_encode;
309
310 /* PAACE Offsets 0x20-0x38 */
311 u32 reserved[8]; /* not currently implemented */
312};
313
314/* OME : Operation mapping entry
315 * MOE : Mapped Operation Encodings
316 * The operation mapping table is table containing operation mapping entries (OME).
317 * The index of a particular OME is programmed in the PAACE entry for translation
318 * in bound I/O operations corresponding to an LIODN. The OMT is used for translation
319 * specifically in case of the indexed translation mode. Each OME contains a 128
320 * byte mapped operation encoding (MOE), where each byte represents an MOE.
321 */
322#define NUM_MOE 128
323struct ome {
324 u8 moe[NUM_MOE];
325} __packed;
326
327#define PAACT_SIZE (sizeof(struct paace) * PAACE_NUMBER_ENTRIES)
328#define SPAACT_SIZE (sizeof(struct paace) * SPAACE_NUMBER_ENTRIES)
329#define OMT_SIZE (sizeof(struct ome) * OME_NUMBER_ENTRIES)
330
331#define PAMU_PAGE_SHIFT 12
332#define PAMU_PAGE_SIZE 4096ULL
333
334#define IOE_READ 0x00
335#define IOE_READ_IDX 0x00
336#define IOE_WRITE 0x81
337#define IOE_WRITE_IDX 0x01
338#define IOE_EREAD0 0x82 /* Enhanced read type 0 */
339#define IOE_EREAD0_IDX 0x02 /* Enhanced read type 0 */
340#define IOE_EWRITE0 0x83 /* Enhanced write type 0 */
341#define IOE_EWRITE0_IDX 0x03 /* Enhanced write type 0 */
342#define IOE_DIRECT0 0x84 /* Directive type 0 */
343#define IOE_DIRECT0_IDX 0x04 /* Directive type 0 */
344#define IOE_EREAD1 0x85 /* Enhanced read type 1 */
345#define IOE_EREAD1_IDX 0x05 /* Enhanced read type 1 */
346#define IOE_EWRITE1 0x86 /* Enhanced write type 1 */
347#define IOE_EWRITE1_IDX 0x06 /* Enhanced write type 1 */
348#define IOE_DIRECT1 0x87 /* Directive type 1 */
349#define IOE_DIRECT1_IDX 0x07 /* Directive type 1 */
350#define IOE_RAC 0x8c /* Read with Atomic clear */
351#define IOE_RAC_IDX 0x0c /* Read with Atomic clear */
352#define IOE_RAS 0x8d /* Read with Atomic set */
353#define IOE_RAS_IDX 0x0d /* Read with Atomic set */
354#define IOE_RAD 0x8e /* Read with Atomic decrement */
355#define IOE_RAD_IDX 0x0e /* Read with Atomic decrement */
356#define IOE_RAI 0x8f /* Read with Atomic increment */
357#define IOE_RAI_IDX 0x0f /* Read with Atomic increment */
358
359#define EOE_READ 0x00
360#define EOE_WRITE 0x01
361#define EOE_RAC 0x0c /* Read with Atomic clear */
362#define EOE_RAS 0x0d /* Read with Atomic set */
363#define EOE_RAD 0x0e /* Read with Atomic decrement */
364#define EOE_RAI 0x0f /* Read with Atomic increment */
365#define EOE_LDEC 0x10 /* Load external cache */
366#define EOE_LDECL 0x11 /* Load external cache with stash lock */
367#define EOE_LDECPE 0x12 /* Load external cache with preferred exclusive */
368#define EOE_LDECPEL 0x13 /* Load external cache with preferred exclusive and lock */
369#define EOE_LDECFE 0x14 /* Load external cache with forced exclusive */
370#define EOE_LDECFEL 0x15 /* Load external cache with forced exclusive and lock */
371#define EOE_RSA 0x16 /* Read with stash allocate */
372#define EOE_RSAU 0x17 /* Read with stash allocate and unlock */
373#define EOE_READI 0x18 /* Read with invalidate */
374#define EOE_RWNITC 0x19 /* Read with no intention to cache */
375#define EOE_WCI 0x1a /* Write cache inhibited */
376#define EOE_WWSA 0x1b /* Write with stash allocate */
377#define EOE_WWSAL 0x1c /* Write with stash allocate and lock */
378#define EOE_WWSAO 0x1d /* Write with stash allocate only */
379#define EOE_WWSAOL 0x1e /* Write with stash allocate only and lock */
380#define EOE_VALID 0x80
381
382/* Function prototypes */
383int pamu_domain_init(void);
384int pamu_enable_liodn(int liodn);
385int pamu_disable_liodn(int liodn);
386int pamu_config_ppaace(int liodn, u32 omi, uint32_t stashid, int prot);
387
388u32 get_stash_id(u32 stash_dest_hint, u32 vcpu);
389void get_ome_index(u32 *omi_index, struct device *dev);
390int pamu_update_paace_stash(int liodn, u32 value);
391
392#endif /* __FSL_PAMU_H */
393

source code of linux/drivers/iommu/fsl_pamu.h