| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator |
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| 4 | * ATBM8830, ATBM8831 |
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| 5 | * |
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| 6 | * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __ATBM8830_PRIV_H |
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| 10 | #define __ATBM8830_PRIV_H |
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| 11 | |
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| 12 | struct atbm_state { |
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| 13 | struct i2c_adapter *i2c; |
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| 14 | /* configuration settings */ |
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| 15 | const struct atbm8830_config *config; |
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| 16 | struct dvb_frontend frontend; |
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| 17 | }; |
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| 18 | |
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| 19 | #define REG_CHIP_ID 0x0000 |
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| 20 | #define REG_TUNER_BASEBAND 0x0001 |
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| 21 | #define REG_DEMOD_RUN 0x0004 |
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| 22 | #define REG_DSP_RESET 0x0005 |
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| 23 | #define REG_RAM_RESET 0x0006 |
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| 24 | #define REG_ADC_RESET 0x0007 |
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| 25 | #define REG_TSPORT_RESET 0x0008 |
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| 26 | #define REG_BLKERR_POL 0x000C |
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| 27 | #define REG_I2C_GATE 0x0103 |
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| 28 | #define REG_TS_SAMPLE_EDGE 0x0301 |
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| 29 | #define REG_TS_PKT_LEN_204 0x0302 |
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| 30 | #define REG_TS_PKT_LEN_AUTO 0x0303 |
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| 31 | #define REG_TS_SERIAL 0x0305 |
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| 32 | #define REG_TS_CLK_FREERUN 0x0306 |
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| 33 | #define REG_TS_VALID_MODE 0x0307 |
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| 34 | #define REG_TS_CLK_MODE 0x030B /* 1 for serial, 0 for parallel */ |
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| 35 | |
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| 36 | #define REG_TS_ERRBIT_USE 0x030C |
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| 37 | #define REG_LOCK_STATUS 0x030D |
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| 38 | #define REG_ADC_CONFIG 0x0602 |
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| 39 | #define REG_CARRIER_OFFSET 0x0827 /* 0x0827-0x0829 little endian */ |
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| 40 | #define REG_DETECTED_PN_MODE 0x082D |
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| 41 | #define REG_READ_LATCH 0x084D |
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| 42 | #define REG_IF_FREQ 0x0A00 /* 0x0A00-0x0A02 little endian */ |
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| 43 | #define REG_OSC_CLK 0x0A03 /* 0x0A03-0x0A05 little endian */ |
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| 44 | #define REG_BYPASS_CCI 0x0A06 |
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| 45 | #define REG_ANALOG_LUMA_DETECTED 0x0A25 |
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| 46 | #define REG_ANALOG_AUDIO_DETECTED 0x0A26 |
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| 47 | #define REG_ANALOG_CHROMA_DETECTED 0x0A39 |
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| 48 | #define REG_FRAME_ERR_CNT 0x0B04 |
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| 49 | #define REG_USE_EXT_ADC 0x0C00 |
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| 50 | #define REG_SWAP_I_Q 0x0C01 |
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| 51 | #define REG_TPS_MANUAL 0x0D01 |
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| 52 | #define REG_TPS_CONFIG 0x0D02 |
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| 53 | #define REG_BYPASS_DEINTERLEAVER 0x0E00 |
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| 54 | #define REG_AGC_TARGET 0x1003 /* 0x1003-0x1005 little endian */ |
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| 55 | #define REG_AGC_MIN 0x1020 |
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| 56 | #define REG_AGC_MAX 0x1023 |
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| 57 | #define REG_AGC_LOCK 0x1027 |
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| 58 | #define REG_AGC_PWM_VAL 0x1028 /* 0x1028-0x1029 little endian */ |
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| 59 | #define REG_AGC_HOLD_LOOP 0x1031 |
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| 60 | |
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| 61 | #endif |
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| 62 | |
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| 63 | |
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