1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef DIBX000_COMMON_H |
3 | #define DIBX000_COMMON_H |
4 | |
5 | enum dibx000_i2c_interface { |
6 | DIBX000_I2C_INTERFACE_TUNER = 0, |
7 | DIBX000_I2C_INTERFACE_GPIO_1_2 = 1, |
8 | DIBX000_I2C_INTERFACE_GPIO_3_4 = 2, |
9 | DIBX000_I2C_INTERFACE_GPIO_6_7 = 3 |
10 | }; |
11 | |
12 | struct dibx000_i2c_master { |
13 | #define DIB3000MC 1 |
14 | #define DIB7000 2 |
15 | #define DIB7000P 11 |
16 | #define DIB7000MC 12 |
17 | #define DIB8000 13 |
18 | u16 device_rev; |
19 | |
20 | enum dibx000_i2c_interface selected_interface; |
21 | |
22 | /* struct i2c_adapter tuner_i2c_adap; */ |
23 | struct i2c_adapter gated_tuner_i2c_adap; |
24 | struct i2c_adapter master_i2c_adap_gpio12; |
25 | struct i2c_adapter master_i2c_adap_gpio34; |
26 | struct i2c_adapter master_i2c_adap_gpio67; |
27 | |
28 | struct i2c_adapter *i2c_adap; |
29 | u8 i2c_addr; |
30 | |
31 | u16 base_reg; |
32 | |
33 | /* for the I2C transfer */ |
34 | struct i2c_msg msg[34]; |
35 | u8 i2c_write_buffer[8]; |
36 | u8 i2c_read_buffer[2]; |
37 | struct mutex i2c_buffer_lock; |
38 | }; |
39 | |
40 | extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, |
41 | u16 device_rev, struct i2c_adapter *i2c_adap, |
42 | u8 i2c_addr); |
43 | extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master |
44 | *mst, |
45 | enum dibx000_i2c_interface |
46 | intf, int gating); |
47 | extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst); |
48 | extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst); |
49 | extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed); |
50 | |
51 | #define BAND_LBAND 0x01 |
52 | #define BAND_UHF 0x02 |
53 | #define BAND_VHF 0x04 |
54 | #define BAND_SBAND 0x08 |
55 | #define BAND_FM 0x10 |
56 | #define BAND_CBAND 0x20 |
57 | |
58 | #define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \ |
59 | (freq_kHz) <= 115000 ? BAND_FM : \ |
60 | (freq_kHz) <= 250000 ? BAND_VHF : \ |
61 | (freq_kHz) <= 863000 ? BAND_UHF : \ |
62 | (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND ) |
63 | |
64 | struct dibx000_agc_config { |
65 | /* defines the capabilities of this AGC-setting - using the BAND_-defines */ |
66 | u8 band_caps; |
67 | |
68 | u16 setup; |
69 | |
70 | u16 inv_gain; |
71 | u16 time_stabiliz; |
72 | |
73 | u8 alpha_level; |
74 | u16 thlock; |
75 | |
76 | u8 wbd_inv; |
77 | u16 wbd_ref; |
78 | u8 wbd_sel; |
79 | u8 wbd_alpha; |
80 | |
81 | u16 agc1_max; |
82 | u16 agc1_min; |
83 | u16 agc2_max; |
84 | u16 agc2_min; |
85 | |
86 | u8 agc1_pt1; |
87 | u8 agc1_pt2; |
88 | u8 agc1_pt3; |
89 | |
90 | u8 agc1_slope1; |
91 | u8 agc1_slope2; |
92 | |
93 | u8 agc2_pt1; |
94 | u8 agc2_pt2; |
95 | |
96 | u8 agc2_slope1; |
97 | u8 agc2_slope2; |
98 | |
99 | u8 alpha_mant; |
100 | u8 alpha_exp; |
101 | |
102 | u8 beta_mant; |
103 | u8 beta_exp; |
104 | |
105 | u8 perform_agc_softsplit; |
106 | |
107 | struct { |
108 | u16 min; |
109 | u16 max; |
110 | u16 min_thres; |
111 | u16 max_thres; |
112 | } split; |
113 | }; |
114 | |
115 | struct dibx000_bandwidth_config { |
116 | u32 internal; |
117 | u32 sampling; |
118 | |
119 | u8 pll_prediv; |
120 | u8 pll_ratio; |
121 | u8 pll_range; |
122 | u8 pll_reset; |
123 | u8 pll_bypass; |
124 | |
125 | u8 enable_refdiv; |
126 | u8 bypclk_div; |
127 | u8 IO_CLK_en_core; |
128 | u8 ADClkSrc; |
129 | u8 modulo; |
130 | |
131 | u16 sad_cfg; |
132 | |
133 | u32 ifreq; |
134 | u32 timf; |
135 | |
136 | u32 xtal_hz; |
137 | }; |
138 | |
139 | enum dibx000_adc_states { |
140 | DIBX000_SLOW_ADC_ON = 0, |
141 | DIBX000_SLOW_ADC_OFF, |
142 | DIBX000_ADC_ON, |
143 | DIBX000_ADC_OFF, |
144 | DIBX000_VBG_ENABLE, |
145 | DIBX000_VBG_DISABLE, |
146 | }; |
147 | |
148 | #define BANDWIDTH_TO_KHZ(v) ((v) / 1000) |
149 | #define BANDWIDTH_TO_HZ(v) ((v) * 1000) |
150 | |
151 | /* Chip output mode. */ |
152 | #define OUTMODE_HIGH_Z 0 |
153 | #define OUTMODE_MPEG2_PAR_GATED_CLK 1 |
154 | #define OUTMODE_MPEG2_PAR_CONT_CLK 2 |
155 | #define OUTMODE_MPEG2_SERIAL 7 |
156 | #define OUTMODE_DIVERSITY 4 |
157 | #define OUTMODE_MPEG2_FIFO 5 |
158 | #define OUTMODE_ANALOG_ADC 6 |
159 | |
160 | #define INPUT_MODE_OFF 0x11 |
161 | #define INPUT_MODE_DIVERSITY 0x12 |
162 | #define INPUT_MODE_MPEG 0x13 |
163 | |
164 | enum frontend_tune_state { |
165 | CT_TUNER_START = 10, |
166 | CT_TUNER_STEP_0, |
167 | CT_TUNER_STEP_1, |
168 | CT_TUNER_STEP_2, |
169 | CT_TUNER_STEP_3, |
170 | CT_TUNER_STEP_4, |
171 | CT_TUNER_STEP_5, |
172 | CT_TUNER_STEP_6, |
173 | CT_TUNER_STEP_7, |
174 | CT_TUNER_STOP, |
175 | |
176 | CT_AGC_START = 20, |
177 | CT_AGC_STEP_0, |
178 | CT_AGC_STEP_1, |
179 | CT_AGC_STEP_2, |
180 | CT_AGC_STEP_3, |
181 | CT_AGC_STEP_4, |
182 | CT_AGC_STOP, |
183 | |
184 | CT_DEMOD_START = 30, |
185 | CT_DEMOD_STEP_1, |
186 | CT_DEMOD_STEP_2, |
187 | CT_DEMOD_STEP_3, |
188 | CT_DEMOD_STEP_4, |
189 | CT_DEMOD_STEP_5, |
190 | CT_DEMOD_STEP_6, |
191 | CT_DEMOD_STEP_7, |
192 | CT_DEMOD_STEP_8, |
193 | CT_DEMOD_STEP_9, |
194 | CT_DEMOD_STEP_10, |
195 | CT_DEMOD_STEP_11, |
196 | CT_DEMOD_SEARCH_NEXT = 51, |
197 | CT_DEMOD_STEP_LOCKED, |
198 | CT_DEMOD_STOP, |
199 | |
200 | CT_DONE = 100, |
201 | CT_SHUTDOWN, |
202 | |
203 | }; |
204 | |
205 | struct dvb_frontend_parametersContext { |
206 | #define CHANNEL_STATUS_PARAMETERS_UNKNOWN 0x01 |
207 | #define CHANNEL_STATUS_PARAMETERS_SET 0x02 |
208 | u8 status; |
209 | u32 tune_time_estimation[2]; |
210 | s32 tps_available; |
211 | u16 tps[9]; |
212 | }; |
213 | |
214 | #define FE_STATUS_TUNE_FAILED 0 |
215 | #define FE_STATUS_TUNE_TIMED_OUT -1 |
216 | #define FE_STATUS_TUNE_TIME_TOO_SHORT -2 |
217 | #define FE_STATUS_TUNE_PENDING -3 |
218 | #define FE_STATUS_STD_SUCCESS -4 |
219 | #define FE_STATUS_FFT_SUCCESS -5 |
220 | #define FE_STATUS_DEMOD_SUCCESS -6 |
221 | #define FE_STATUS_LOCKED -7 |
222 | #define FE_STATUS_DATA_LOCKED -8 |
223 | |
224 | #define FE_CALLBACK_TIME_NEVER 0xffffffff |
225 | |
226 | #define DATA_BUS_ACCESS_MODE_8BIT 0x01 |
227 | #define DATA_BUS_ACCESS_MODE_16BIT 0x02 |
228 | #define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10 |
229 | |
230 | struct dibGPIOFunction { |
231 | #define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1 |
232 | #define BOARD_GPIO_COMPONENT_DEMOD 2 |
233 | u8 component; |
234 | |
235 | #define BOARD_GPIO_FUNCTION_BOARD_ON 1 |
236 | #define BOARD_GPIO_FUNCTION_BOARD_OFF 2 |
237 | #define BOARD_GPIO_FUNCTION_COMPONENT_ON 3 |
238 | #define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4 |
239 | #define BOARD_GPIO_FUNCTION_SUBBAND_PWM 5 |
240 | #define BOARD_GPIO_FUNCTION_SUBBAND_GPIO 6 |
241 | u8 function; |
242 | |
243 | /* mask, direction and value are used specify which GPIO to change GPIO0 |
244 | * is LSB and possible GPIO31 is MSB. The same bit-position as in the |
245 | * mask is used for the direction and the value. Direction == 1 is OUT, |
246 | * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN |
247 | * value has no meaning. |
248 | * |
249 | * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be |
250 | * used to do the PWM. Direction gives the PWModulator to be used. |
251 | * Value gives the PWM value in device-dependent scale. |
252 | */ |
253 | u32 mask; |
254 | u32 direction; |
255 | u32 value; |
256 | }; |
257 | |
258 | #define MAX_NB_SUBBANDS 8 |
259 | struct dibSubbandSelection { |
260 | u8 size; /* Actual number of subbands. */ |
261 | struct { |
262 | u16 f_mhz; |
263 | struct dibGPIOFunction gpio; |
264 | } subband[MAX_NB_SUBBANDS]; |
265 | }; |
266 | |
267 | #define DEMOD_TIMF_SET 0x00 |
268 | #define DEMOD_TIMF_GET 0x01 |
269 | #define DEMOD_TIMF_UPDATE 0x02 |
270 | |
271 | #define MPEG_ON_DIBTX 1 |
272 | #define DIV_ON_DIBTX 2 |
273 | #define ADC_ON_DIBTX 3 |
274 | #define DEMOUT_ON_HOSTBUS 4 |
275 | #define DIBTX_ON_HOSTBUS 5 |
276 | #define MPEG_ON_HOSTBUS 6 |
277 | |
278 | #endif |
279 | |