1 | |
2 | /* |
3 | Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. |
4 | All rights reserved. |
5 | |
6 | Redistribution and use in source and binary forms, with or without |
7 | modification, are permitted provided that the following conditions are met: |
8 | |
9 | * Redistributions of source code must retain the above copyright notice, |
10 | this list of conditions and the following disclaimer. |
11 | * Redistributions in binary form must reproduce the above copyright notice, |
12 | this list of conditions and the following disclaimer in the documentation |
13 | and/or other materials provided with the distribution. |
14 | * Neither the name of Trident Microsystems nor Hauppauge Computer Works |
15 | nor the names of its contributors may be used to endorse or promote |
16 | products derived from this software without specific prior written |
17 | permission. |
18 | |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
29 | POSSIBILITY OF SUCH DAMAGE. |
30 | |
31 | DRXJ specific header file |
32 | |
33 | Authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen |
34 | */ |
35 | |
36 | #ifndef __DRXJ_H__ |
37 | #define __DRXJ_H__ |
38 | /*------------------------------------------------------------------------- |
39 | INCLUDES |
40 | -------------------------------------------------------------------------*/ |
41 | |
42 | #include "drx_driver.h" |
43 | #include "drx_dap_fasi.h" |
44 | |
45 | /* Check DRX-J specific dap condition */ |
46 | /* Multi master mode and short addr format only will not work. |
47 | RMW, CRC reset, broadcast and switching back to single master mode |
48 | cannot be done with short addr only in multi master mode. */ |
49 | #if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) |
50 | #error "Multi master mode and short addressing only is an illegal combination" |
51 | *; /* Generate a fatal compiler error to make sure it stops here, |
52 | this is necessary because not all compilers stop after a #error. */ |
53 | #endif |
54 | |
55 | /*------------------------------------------------------------------------- |
56 | TYPEDEFS |
57 | -------------------------------------------------------------------------*/ |
58 | /*============================================================================*/ |
59 | /*============================================================================*/ |
60 | /*== code support ============================================================*/ |
61 | /*============================================================================*/ |
62 | /*============================================================================*/ |
63 | |
64 | /*============================================================================*/ |
65 | /*============================================================================*/ |
66 | /*== SCU cmd if =============================================================*/ |
67 | /*============================================================================*/ |
68 | /*============================================================================*/ |
69 | |
70 | struct drxjscu_cmd { |
71 | u16 command; |
72 | /*< Command number */ |
73 | u16 parameter_len; |
74 | /*< Data length in byte */ |
75 | u16 result_len; |
76 | /*< result length in byte */ |
77 | u16 *parameter; |
78 | /*< General purpose param */ |
79 | u16 *result; |
80 | /*< General purpose param */}; |
81 | |
82 | /*============================================================================*/ |
83 | /*============================================================================*/ |
84 | /*== CTRL CFG related data structures ========================================*/ |
85 | /*============================================================================*/ |
86 | /*============================================================================*/ |
87 | |
88 | /* extra intermediate lock state for VSB,QAM,NTSC */ |
89 | #define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) |
90 | |
91 | /* OOB lock states */ |
92 | #define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ |
93 | #define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ |
94 | |
95 | /* Intermediate powermodes for DRXJ */ |
96 | #define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 |
97 | #define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 |
98 | #define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 |
99 | |
100 | /* supstition for GPIO FNC mux */ |
101 | #define APP_O (0x0000) |
102 | |
103 | /*#define DRX_CTRL_BASE (0x0000)*/ |
104 | |
105 | #define DRXJ_CTRL_CFG_BASE (0x1000) |
106 | enum drxj_cfg_type { |
107 | DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, |
108 | DRXJ_CFG_AGC_IF, |
109 | DRXJ_CFG_AGC_INTERNAL, |
110 | DRXJ_CFG_PRE_SAW, |
111 | DRXJ_CFG_AFE_GAIN, |
112 | DRXJ_CFG_SYMBOL_CLK_OFFSET, |
113 | DRXJ_CFG_ACCUM_CR_RS_CW_ERR, |
114 | DRXJ_CFG_FEC_MERS_SEQ_COUNT, |
115 | DRXJ_CFG_OOB_MISC, |
116 | DRXJ_CFG_SMART_ANT, |
117 | DRXJ_CFG_OOB_PRE_SAW, |
118 | DRXJ_CFG_VSB_MISC, |
119 | DRXJ_CFG_RESET_PACKET_ERR, |
120 | |
121 | /* ATV (FM) */ |
122 | DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ |
123 | DRXJ_CFG_ATV_MISC, |
124 | DRXJ_CFG_ATV_EQU_COEF, |
125 | DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ |
126 | |
127 | DRXJ_CFG_MPEG_OUTPUT_MISC, |
128 | DRXJ_CFG_HW_CFG, |
129 | DRXJ_CFG_OOB_LO_POW, |
130 | |
131 | DRXJ_CFG_MAX /* dummy, never to be used */}; |
132 | |
133 | /* |
134 | * /enum drxj_cfg_smart_ant_io * smart antenna i/o. |
135 | */ |
136 | enum drxj_cfg_smart_ant_io { |
137 | DRXJ_SMT_ANT_OUTPUT = 0, |
138 | DRXJ_SMT_ANT_INPUT |
139 | }; |
140 | |
141 | /* |
142 | * /struct drxj_cfg_smart_ant * Set smart antenna. |
143 | */ |
144 | struct drxj_cfg_smart_ant { |
145 | enum drxj_cfg_smart_ant_io io; |
146 | u16 ctrl_data; |
147 | }; |
148 | |
149 | /* |
150 | * /struct DRXJAGCSTATUS_t |
151 | * AGC status information from the DRXJ-IQM-AF. |
152 | */ |
153 | struct drxj_agc_status { |
154 | u16 IFAGC; |
155 | u16 RFAGC; |
156 | u16 digital_agc; |
157 | }; |
158 | |
159 | /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ |
160 | |
161 | /* |
162 | * /enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ. |
163 | */ |
164 | enum drxj_agc_ctrl_mode { |
165 | DRX_AGC_CTRL_AUTO = 0, |
166 | DRX_AGC_CTRL_USER, |
167 | DRX_AGC_CTRL_OFF}; |
168 | |
169 | /* |
170 | * /struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ. |
171 | */ |
172 | struct drxj_cfg_agc { |
173 | enum drx_standard standard; /* standard for which these settings apply */ |
174 | enum drxj_agc_ctrl_mode ctrl_mode; /* off, user, auto */ |
175 | u16 output_level; /* range dependent on AGC */ |
176 | u16 min_output_level; /* range dependent on AGC */ |
177 | u16 max_output_level; /* range dependent on AGC */ |
178 | u16 speed; /* range dependent on AGC */ |
179 | u16 top; /* rf-agc take over point */ |
180 | u16 cut_off_current; /* rf-agc is accelerated if output current |
181 | is below cut-off current */}; |
182 | |
183 | /* DRXJ_CFG_PRE_SAW */ |
184 | |
185 | /* |
186 | * /struct drxj_cfg_pre_saw * Interface to configure pre SAW sense. |
187 | */ |
188 | struct drxj_cfg_pre_saw { |
189 | enum drx_standard standard; /* standard to which these settings apply */ |
190 | u16 reference; /* pre SAW reference value, range 0 .. 31 */ |
191 | bool use_pre_saw; /* true algorithms must use pre SAW sense */}; |
192 | |
193 | /* DRXJ_CFG_AFE_GAIN */ |
194 | |
195 | /* |
196 | * /struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA). |
197 | */ |
198 | struct drxj_cfg_afe_gain { |
199 | enum drx_standard standard; /* standard to which these settings apply */ |
200 | u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */}; |
201 | |
202 | /* |
203 | * /struct drxjrs_errors |
204 | * Available failure information in DRXJ_FEC_RS. |
205 | * |
206 | * Container for errors that are received in the most recently finished measurement period |
207 | * |
208 | */ |
209 | struct drxjrs_errors { |
210 | u16 nr_bit_errors; |
211 | /*< no of pre RS bit errors */ |
212 | u16 nr_symbol_errors; |
213 | /*< no of pre RS symbol errors */ |
214 | u16 nr_packet_errors; |
215 | /*< no of pre RS packet errors */ |
216 | u16 nr_failures; |
217 | /*< no of post RS failures to decode */ |
218 | u16 nr_snc_par_fail_count; |
219 | /*< no of post RS bit erros */ |
220 | }; |
221 | |
222 | /* |
223 | * /struct drxj_cfg_vsb_misc * symbol error rate |
224 | */ |
225 | struct drxj_cfg_vsb_misc { |
226 | u32 symb_error; |
227 | /*< symbol error rate sps */}; |
228 | |
229 | /* |
230 | * /enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. |
231 | * |
232 | */ |
233 | enum drxj_mpeg_start_width { |
234 | DRXJ_MPEG_START_WIDTH_1CLKCYC, |
235 | DRXJ_MPEG_START_WIDTH_8CLKCYC}; |
236 | |
237 | /* |
238 | * /enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. |
239 | * |
240 | */ |
241 | enum drxj_mpeg_output_clock_rate { |
242 | DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, |
243 | DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, |
244 | DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, |
245 | DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, |
246 | DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, |
247 | DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, |
248 | DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K}; |
249 | |
250 | /* |
251 | * /struct DRXJCfgMisc_t |
252 | * Change TEI bit of MPEG output |
253 | * reverse MPEG output bit order |
254 | * set MPEG output clock rate |
255 | */ |
256 | struct drxj_cfg_mpeg_output_misc { |
257 | bool disable_tei_handling; /*< if true pass (not change) TEI bit */ |
258 | bool bit_reverse_mpeg_outout; /*< if true, parallel: msb on MD0; serial: lsb out first */ |
259 | enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; |
260 | /*< set MPEG output clock rate that overwirtes the derived one from symbol rate */ |
261 | enum drxj_mpeg_start_width mpeg_start_width; /*< set MPEG output start width */}; |
262 | |
263 | /* |
264 | * /enum drxj_xtal_freq * Supported external crystal reference frequency. |
265 | */ |
266 | enum drxj_xtal_freq { |
267 | DRXJ_XTAL_FREQ_RSVD, |
268 | DRXJ_XTAL_FREQ_27MHZ, |
269 | DRXJ_XTAL_FREQ_20P25MHZ, |
270 | DRXJ_XTAL_FREQ_4MHZ}; |
271 | |
272 | /* |
273 | * /enum drxj_xtal_freq * Supported external crystal reference frequency. |
274 | */ |
275 | enum drxji2c_speed { |
276 | DRXJ_I2C_SPEED_400KBPS, |
277 | DRXJ_I2C_SPEED_100KBPS}; |
278 | |
279 | /* |
280 | * /struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal |
281 | * reference frequency, I2C speed, etc... |
282 | */ |
283 | struct drxj_cfg_hw_cfg { |
284 | enum drxj_xtal_freq xtal_freq; |
285 | /*< crystal reference frequency */ |
286 | enum drxji2c_speed i2c_speed; |
287 | /*< 100 or 400 kbps */}; |
288 | |
289 | /* |
290 | * DRXJ_CFG_ATV_MISC |
291 | */ |
292 | struct drxj_cfg_atv_misc { |
293 | s16 peak_filter; /* -8 .. 15 */ |
294 | u16 noise_filter; /* 0 .. 15 */}; |
295 | |
296 | /* |
297 | * struct drxj_cfg_oob_misc */ |
298 | #define DRXJ_OOB_STATE_RESET 0x0 |
299 | #define DRXJ_OOB_STATE_AGN_HUNT 0x1 |
300 | #define DRXJ_OOB_STATE_DGN_HUNT 0x2 |
301 | #define DRXJ_OOB_STATE_AGC_HUNT 0x3 |
302 | #define DRXJ_OOB_STATE_FRQ_HUNT 0x4 |
303 | #define DRXJ_OOB_STATE_PHA_HUNT 0x8 |
304 | #define DRXJ_OOB_STATE_TIM_HUNT 0x10 |
305 | #define DRXJ_OOB_STATE_EQU_HUNT 0x20 |
306 | #define DRXJ_OOB_STATE_EQT_HUNT 0x30 |
307 | #define DRXJ_OOB_STATE_SYNC 0x40 |
308 | |
309 | struct drxj_cfg_oob_misc { |
310 | struct drxj_agc_status agc; |
311 | bool eq_lock; |
312 | bool sym_timing_lock; |
313 | bool phase_lock; |
314 | bool freq_lock; |
315 | bool dig_gain_lock; |
316 | bool ana_gain_lock; |
317 | u8 state; |
318 | }; |
319 | |
320 | /* |
321 | * Index of in array of coef |
322 | */ |
323 | enum drxj_cfg_oob_lo_power { |
324 | DRXJ_OOB_LO_POW_MINUS0DB = 0, |
325 | DRXJ_OOB_LO_POW_MINUS5DB, |
326 | DRXJ_OOB_LO_POW_MINUS10DB, |
327 | DRXJ_OOB_LO_POW_MINUS15DB, |
328 | DRXJ_OOB_LO_POW_MAX}; |
329 | |
330 | /* |
331 | * DRXJ_CFG_ATV_EQU_COEF |
332 | */ |
333 | struct drxj_cfg_atv_equ_coef { |
334 | s16 coef0; /* -256 .. 255 */ |
335 | s16 coef1; /* -256 .. 255 */ |
336 | s16 coef2; /* -256 .. 255 */ |
337 | s16 coef3; /* -256 .. 255 */}; |
338 | |
339 | /* |
340 | * Index of in array of coef |
341 | */ |
342 | enum drxj_coef_array_index { |
343 | DRXJ_COEF_IDX_MN = 0, |
344 | DRXJ_COEF_IDX_FM, |
345 | DRXJ_COEF_IDX_L, |
346 | DRXJ_COEF_IDX_LP, |
347 | DRXJ_COEF_IDX_BG, |
348 | DRXJ_COEF_IDX_DK, |
349 | DRXJ_COEF_IDX_I, |
350 | DRXJ_COEF_IDX_MAX}; |
351 | |
352 | /* |
353 | * DRXJ_CFG_ATV_OUTPUT |
354 | */ |
355 | |
356 | /* |
357 | * /enum DRXJAttenuation_t |
358 | * Attenuation setting for SIF AGC. |
359 | * |
360 | */ |
361 | enum drxjsif_attenuation { |
362 | DRXJ_SIF_ATTENUATION_0DB, |
363 | DRXJ_SIF_ATTENUATION_3DB, |
364 | DRXJ_SIF_ATTENUATION_6DB, |
365 | DRXJ_SIF_ATTENUATION_9DB}; |
366 | |
367 | /* |
368 | * /struct drxj_cfg_atv_output * SIF attenuation setting. |
369 | * |
370 | */ |
371 | struct drxj_cfg_atv_output { |
372 | bool enable_cvbs_output; /* true= enabled */ |
373 | bool enable_sif_output; /* true= enabled */ |
374 | enum drxjsif_attenuation sif_attenuation; |
375 | }; |
376 | |
377 | /* |
378 | DRXJ_CFG_ATV_AGC_STATUS (get only) |
379 | */ |
380 | /* TODO : AFE interface not yet finished, subject to change */ |
381 | struct drxj_cfg_atv_agc_status { |
382 | u16 rf_agc_gain; /* 0 .. 877 uA */ |
383 | u16 if_agc_gain; /* 0 .. 877 uA */ |
384 | s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */ |
385 | s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */ |
386 | u16 rf_agc_loop_gain; /* 0 .. 7 */ |
387 | u16 if_agc_loop_gain; /* 0 .. 7 */ |
388 | u16 video_agc_loop_gain; /* 0 .. 7 */}; |
389 | |
390 | /*============================================================================*/ |
391 | /*============================================================================*/ |
392 | /*== CTRL related data structures ============================================*/ |
393 | /*============================================================================*/ |
394 | /*============================================================================*/ |
395 | |
396 | /* NONE */ |
397 | |
398 | /*============================================================================*/ |
399 | /*============================================================================*/ |
400 | |
401 | /*========================================*/ |
402 | /* |
403 | * /struct struct drxj_data * DRXJ specific attributes. |
404 | * |
405 | * Global data container for DRXJ specific data. |
406 | * |
407 | */ |
408 | struct drxj_data { |
409 | /* device capabilities (determined during drx_open()) */ |
410 | bool has_lna; /*< true if LNA (aka PGA) present */ |
411 | bool has_oob; /*< true if OOB supported */ |
412 | bool has_ntsc; /*< true if NTSC supported */ |
413 | bool has_btsc; /*< true if BTSC supported */ |
414 | bool has_smatx; /*< true if mat_tx is available */ |
415 | bool has_smarx; /*< true if mat_rx is available */ |
416 | bool has_gpio; /*< true if GPIO is available */ |
417 | bool has_irqn; /*< true if IRQN is available */ |
418 | /* A1/A2/A... */ |
419 | u8 mfx; /*< metal fix */ |
420 | |
421 | /* tuner settings */ |
422 | bool mirror_freq_spect_oob;/*< tuner inversion (true = tuner mirrors the signal */ |
423 | |
424 | /* standard/channel settings */ |
425 | enum drx_standard standard; /*< current standard information */ |
426 | enum drx_modulation constellation; |
427 | /*< current constellation */ |
428 | s32 frequency; /*< center signal frequency in KHz */ |
429 | enum drx_bandwidth curr_bandwidth; |
430 | /*< current channel bandwidth */ |
431 | enum drx_mirror mirror; /*< current channel mirror */ |
432 | |
433 | /* signal quality information */ |
434 | u32 fec_bits_desired; /*< BER accounting period */ |
435 | u16 fec_vd_plen; /*< no of trellis symbols: VD SER measurement period */ |
436 | u16 qam_vd_prescale; /*< Viterbi Measurement Prescale */ |
437 | u16 qam_vd_period; /*< Viterbi Measurement period */ |
438 | u16 fec_rs_plen; /*< defines RS BER measurement period */ |
439 | u16 fec_rs_prescale; /*< ReedSolomon Measurement Prescale */ |
440 | u16 fec_rs_period; /*< ReedSolomon Measurement period */ |
441 | bool reset_pkt_err_acc; /*< Set a flag to reset accumulated packet error */ |
442 | u16 pkt_err_acc_start; /*< Set a flag to reset accumulated packet error */ |
443 | |
444 | /* HI configuration */ |
445 | u16 hi_cfg_timing_div; /*< HI Configure() parameter 2 */ |
446 | u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 */ |
447 | u16 hi_cfg_wake_up_key; /*< HI Configure() parameter 4 */ |
448 | u16 hi_cfg_ctrl; /*< HI Configure() parameter 5 */ |
449 | u16 hi_cfg_transmit; /*< HI Configure() parameter 6 */ |
450 | |
451 | /* UIO configuration */ |
452 | enum drxuio_mode uio_sma_rx_mode;/*< current mode of SmaRx pin */ |
453 | enum drxuio_mode uio_sma_tx_mode;/*< current mode of SmaTx pin */ |
454 | enum drxuio_mode uio_gpio_mode; /*< current mode of ASEL pin */ |
455 | enum drxuio_mode uio_irqn_mode; /*< current mode of IRQN pin */ |
456 | |
457 | /* IQM fs frequency shift and inversion */ |
458 | u32 iqm_fs_rate_ofs; /*< frequency shifter setting after setchannel */ |
459 | bool pos_image; /*< True: positive image */ |
460 | /* IQM RC frequency shift */ |
461 | u32 iqm_rc_rate_ofs; /*< frequency shifter setting after setchannel */ |
462 | |
463 | /* ATV configuration */ |
464 | u32 atv_cfg_changed_flags; /*< flag: flags cfg changes */ |
465 | s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU0__A */ |
466 | s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU1__A */ |
467 | s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU2__A */ |
468 | s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU3__A */ |
469 | bool phase_correction_bypass;/*< flag: true=bypass */ |
470 | s16 atv_top_vid_peak; /*< shadow of ATV_TOP_VID_PEAK__A */ |
471 | u16 atv_top_noise_th; /*< shadow of ATV_TOP_NOISE_TH__A */ |
472 | bool enable_cvbs_output; /*< flag CVBS output enable */ |
473 | bool enable_sif_output; /*< flag SIF output enable */ |
474 | enum drxjsif_attenuation sif_attenuation; |
475 | /*< current SIF att setting */ |
476 | /* Agc configuration for QAM and VSB */ |
477 | struct drxj_cfg_agc qam_rf_agc_cfg; /*< qam RF AGC config */ |
478 | struct drxj_cfg_agc qam_if_agc_cfg; /*< qam IF AGC config */ |
479 | struct drxj_cfg_agc vsb_rf_agc_cfg; /*< vsb RF AGC config */ |
480 | struct drxj_cfg_agc vsb_if_agc_cfg; /*< vsb IF AGC config */ |
481 | |
482 | /* PGA gain configuration for QAM and VSB */ |
483 | u16 qam_pga_cfg; /*< qam PGA config */ |
484 | u16 vsb_pga_cfg; /*< vsb PGA config */ |
485 | |
486 | /* Pre SAW configuration for QAM and VSB */ |
487 | struct drxj_cfg_pre_saw qam_pre_saw_cfg; |
488 | /*< qam pre SAW config */ |
489 | struct drxj_cfg_pre_saw vsb_pre_saw_cfg; |
490 | /*< qam pre SAW config */ |
491 | |
492 | /* Version information */ |
493 | char v_text[2][12]; /*< allocated text versions */ |
494 | struct drx_version v_version[2]; /*< allocated versions structs */ |
495 | struct drx_version_list v_list_elements[2]; |
496 | /*< allocated version list */ |
497 | |
498 | /* smart antenna configuration */ |
499 | bool smart_ant_inverted; |
500 | |
501 | /* Tracking filter setting for OOB */ |
502 | u16 oob_trk_filter_cfg[8]; |
503 | bool oob_power_on; |
504 | |
505 | /* MPEG static bitrate setting */ |
506 | u32 mpeg_ts_static_bitrate; /*< bitrate static MPEG output */ |
507 | bool disable_te_ihandling; /*< MPEG TS TEI handling */ |
508 | bool bit_reverse_mpeg_outout;/*< MPEG output bit order */ |
509 | enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; |
510 | /*< MPEG output clock rate */ |
511 | enum drxj_mpeg_start_width mpeg_start_width; |
512 | /*< MPEG Start width */ |
513 | |
514 | /* Pre SAW & Agc configuration for ATV */ |
515 | struct drxj_cfg_pre_saw atv_pre_saw_cfg; |
516 | /*< atv pre SAW config */ |
517 | struct drxj_cfg_agc atv_rf_agc_cfg; /*< atv RF AGC config */ |
518 | struct drxj_cfg_agc atv_if_agc_cfg; /*< atv IF AGC config */ |
519 | u16 atv_pga_cfg; /*< atv pga config */ |
520 | |
521 | u32 curr_symbol_rate; |
522 | |
523 | /* pin-safe mode */ |
524 | bool pdr_safe_mode; /*< PDR safe mode activated */ |
525 | u16 pdr_safe_restore_val_gpio; |
526 | u16 pdr_safe_restore_val_v_sync; |
527 | u16 pdr_safe_restore_val_sma_rx; |
528 | u16 pdr_safe_restore_val_sma_tx; |
529 | |
530 | /* OOB pre-saw value */ |
531 | u16 oob_pre_saw; |
532 | enum drxj_cfg_oob_lo_power oob_lo_pow; |
533 | |
534 | struct drx_aud_data aud_data; |
535 | /*< audio storage */}; |
536 | |
537 | /*------------------------------------------------------------------------- |
538 | Access MACROS |
539 | -------------------------------------------------------------------------*/ |
540 | /* |
541 | * \brief Compilable references to attributes |
542 | * \param d pointer to demod instance |
543 | * |
544 | * Used as main reference to an attribute field. |
545 | * Can be used by both macro implementation and function implementation. |
546 | * These macros are defined to avoid duplication of code in macro and function |
547 | * definitions that handle access of demod common or extended attributes. |
548 | * |
549 | */ |
550 | |
551 | #define DRXJ_ATTR_BTSC_DETECT(d) \ |
552 | (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect) |
553 | |
554 | /*------------------------------------------------------------------------- |
555 | DEFINES |
556 | -------------------------------------------------------------------------*/ |
557 | |
558 | /* |
559 | * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET |
560 | * \brief Offset from picture carrier to centre frequency in kHz, in RF domain |
561 | * |
562 | * For NTSC standard. |
563 | * NTSC channels are listed by their picture carrier frequency (Fpc). |
564 | * The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. |
565 | * In case the tuner module is not used the DRX-J requires that the tuner is |
566 | * tuned to the centre frequency of the channel: |
567 | * |
568 | * Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET |
569 | * |
570 | */ |
571 | #define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) |
572 | |
573 | /* |
574 | * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET |
575 | * \brief Offset from picture carrier to centre frequency in kHz, in RF domain |
576 | * |
577 | * For PAL/SECAM - BG standard. This define is needed in case the tuner module |
578 | * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). |
579 | * The DRX-J requires that the tuner is tuned to: |
580 | * Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET |
581 | * |
582 | * In case the tuner module is used the drxdriver takes care of this. |
583 | * In case the tuner module is NOT used the application programmer must take |
584 | * care of this. |
585 | * |
586 | */ |
587 | #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) |
588 | |
589 | /* |
590 | * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET |
591 | * \brief Offset from picture carrier to centre frequency in kHz, in RF domain |
592 | * |
593 | * For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module |
594 | * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). |
595 | * The DRX-J requires that the tuner is tuned to: |
596 | * Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET |
597 | * |
598 | * In case the tuner module is used the drxdriver takes care of this. |
599 | * In case the tuner module is NOT used the application programmer must take |
600 | * care of this. |
601 | * |
602 | */ |
603 | #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) |
604 | |
605 | /* |
606 | * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET |
607 | * \brief Offset from picture carrier to centre frequency in kHz, in RF domain |
608 | * |
609 | * For PAL/SECAM - LP standard. This define is needed in case the tuner module |
610 | * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). |
611 | * The DRX-J requires that the tuner is tuned to: |
612 | * Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET |
613 | * |
614 | * In case the tuner module is used the drxdriver takes care of this. |
615 | * In case the tuner module is NOT used the application programmer must take |
616 | * care of this. |
617 | */ |
618 | #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) |
619 | |
620 | /* |
621 | * \def DRXJ_FM_CARRIER_FREQ_OFFSET |
622 | * \brief Offset from sound carrier to centre frequency in kHz, in RF domain |
623 | * |
624 | * For FM standard. |
625 | * FM channels are listed by their sound carrier frequency (Fsc). |
626 | * The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as |
627 | * input. |
628 | * In case the tuner module is not used the DRX-J requires that the tuner is |
629 | * tuned to the Ffm frequency of the channel. |
630 | * |
631 | * Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET |
632 | * |
633 | */ |
634 | #define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000)) |
635 | |
636 | /* Revision types -------------------------------------------------------*/ |
637 | |
638 | #define DRXJ_TYPE_ID (0x3946000DUL) |
639 | |
640 | /* Macros ---------------------------------------------------------------*/ |
641 | |
642 | /* Convert OOB lock status to string */ |
643 | #define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ |
644 | (x == DRX_NEVER_LOCK) ? "Never" : \ |
645 | (x == DRX_NOT_LOCKED) ? "No" : \ |
646 | (x == DRX_LOCKED) ? "Locked" : \ |
647 | (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ |
648 | (x == DRX_LOCK_STATE_2) ? "sync lock" : \ |
649 | "(Invalid)") |
650 | |
651 | #endif /* __DRXJ_H__ */ |
652 | |