1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Defines for the Maxlinear MX58x family of tuners/demods |
4 | * |
5 | * Copyright (C) 2014 Digital Devices GmbH |
6 | * |
7 | * based on code: |
8 | * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved |
9 | * which was released under GPL V2 |
10 | */ |
11 | |
12 | enum MXL_BOOL_E { |
13 | MXL_DISABLE = 0, |
14 | MXL_ENABLE = 1, |
15 | |
16 | MXL_FALSE = 0, |
17 | MXL_TRUE = 1, |
18 | |
19 | MXL_INVALID = 0, |
20 | MXL_VALID = 1, |
21 | |
22 | MXL_NO = 0, |
23 | MXL_YES = 1, |
24 | |
25 | MXL_OFF = 0, |
26 | MXL_ON = 1 |
27 | }; |
28 | |
29 | /* Firmware-Host Command IDs */ |
30 | enum MXL_HYDRA_HOST_CMD_ID_E { |
31 | /* --Device command IDs-- */ |
32 | MXL_HYDRA_DEV_NO_OP_CMD = 0, /* No OP */ |
33 | |
34 | MXL_HYDRA_DEV_SET_POWER_MODE_CMD = 1, |
35 | MXL_HYDRA_DEV_SET_OVERWRITE_DEF_CMD = 2, |
36 | |
37 | /* Host-used CMD, not used by firmware */ |
38 | MXL_HYDRA_DEV_FIRMWARE_DOWNLOAD_CMD = 3, |
39 | |
40 | /* Additional CONTROL types from DTV */ |
41 | MXL_HYDRA_DEV_SET_BROADCAST_PID_STB_ID_CMD = 4, |
42 | MXL_HYDRA_DEV_GET_PMM_SLEEP_CMD = 5, |
43 | |
44 | /* --Tuner command IDs-- */ |
45 | MXL_HYDRA_TUNER_TUNE_CMD = 6, |
46 | MXL_HYDRA_TUNER_GET_STATUS_CMD = 7, |
47 | |
48 | /* --Demod command IDs-- */ |
49 | MXL_HYDRA_DEMOD_SET_PARAM_CMD = 8, |
50 | MXL_HYDRA_DEMOD_GET_STATUS_CMD = 9, |
51 | |
52 | MXL_HYDRA_DEMOD_RESET_FEC_COUNTER_CMD = 10, |
53 | |
54 | MXL_HYDRA_DEMOD_SET_PKT_NUM_CMD = 11, |
55 | |
56 | MXL_HYDRA_DEMOD_SET_IQ_SOURCE_CMD = 12, |
57 | MXL_HYDRA_DEMOD_GET_IQ_DATA_CMD = 13, |
58 | |
59 | MXL_HYDRA_DEMOD_GET_M68HC05_VER_CMD = 14, |
60 | |
61 | MXL_HYDRA_DEMOD_SET_ERROR_COUNTER_MODE_CMD = 15, |
62 | |
63 | /* --- ABORT channel tune */ |
64 | MXL_HYDRA_ABORT_TUNE_CMD = 16, /* Abort current tune command. */ |
65 | |
66 | /* --SWM/FSK command IDs-- */ |
67 | MXL_HYDRA_FSK_RESET_CMD = 17, |
68 | MXL_HYDRA_FSK_MSG_CMD = 18, |
69 | MXL_HYDRA_FSK_SET_OP_MODE_CMD = 19, |
70 | |
71 | /* --DiSeqC command IDs-- */ |
72 | MXL_HYDRA_DISEQC_MSG_CMD = 20, |
73 | MXL_HYDRA_DISEQC_COPY_MSG_TO_MAILBOX = 21, |
74 | MXL_HYDRA_DISEQC_CFG_MSG_CMD = 22, |
75 | |
76 | /* --- FFT Debug Command IDs-- */ |
77 | MXL_HYDRA_REQ_FFT_SPECTRUM_CMD = 23, |
78 | |
79 | /* -- Demod scramblle code */ |
80 | MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD = 24, |
81 | |
82 | /* ---For host to know how many commands in total */ |
83 | MXL_HYDRA_LAST_HOST_CMD = 25, |
84 | |
85 | MXL_HYDRA_DEMOD_INTR_TYPE_CMD = 47, |
86 | MXL_HYDRA_DEV_INTR_CLEAR_CMD = 48, |
87 | MXL_HYDRA_TUNER_SPECTRUM_REQ_CMD = 53, |
88 | MXL_HYDRA_TUNER_ACTIVATE_CMD = 55, |
89 | MXL_HYDRA_DEV_CFG_POWER_MODE_CMD = 56, |
90 | MXL_HYDRA_DEV_XTAL_CAP_CMD = 57, |
91 | MXL_HYDRA_DEV_CFG_SKU_CMD = 58, |
92 | MXL_HYDRA_TUNER_SPECTRUM_MIN_GAIN_CMD = 59, |
93 | MXL_HYDRA_DISEQC_CONT_TONE_CFG = 60, |
94 | MXL_HYDRA_DEV_RF_WAKE_UP_CMD = 61, |
95 | MXL_HYDRA_DEMOD_CFG_EQ_CTRL_PARAM_CMD = 62, |
96 | MXL_HYDRA_DEMOD_FREQ_OFFSET_SEARCH_RANGE_CMD = 63, |
97 | = 64, |
98 | |
99 | MXL_XCPU_PID_FLT_CFG_CMD = 65, |
100 | MXL_XCPU_SHMEM_TEST_CMD = 66, |
101 | MXL_XCPU_ABORT_TUNE_CMD = 67, |
102 | MXL_XCPU_CHAN_TUNE_CMD = 68, |
103 | MXL_XCPU_FLT_BOND_HDRS_CMD = 69, |
104 | |
105 | MXL_HYDRA_DEV_BROADCAST_WAKE_UP_CMD = 70, |
106 | MXL_HYDRA_FSK_CFG_FSK_FREQ_CMD = 71, |
107 | MXL_HYDRA_FSK_POWER_DOWN_CMD = 72, |
108 | MXL_XCPU_CLEAR_CB_STATS_CMD = 73, |
109 | MXL_XCPU_CHAN_BOND_RESTART_CMD = 74 |
110 | }; |
111 | |
112 | #define MXL_ENABLE_BIG_ENDIAN (0) |
113 | |
114 | #define MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH 248 |
115 | |
116 | #define MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN (248) |
117 | |
118 | #define MXL_HYDRA_CAP_MIN 10 |
119 | #define MXL_HYDRA_CAP_MAX 33 |
120 | |
121 | #define MXL_HYDRA_PLID_REG_READ 0xFB /* Read register PLID */ |
122 | #define MXL_HYDRA_PLID_REG_WRITE 0xFC /* Write register PLID */ |
123 | |
124 | #define MXL_HYDRA_PLID_CMD_READ 0xFD /* Command Read PLID */ |
125 | #define MXL_HYDRA_PLID_CMD_WRITE 0xFE /* Command Write PLID */ |
126 | |
127 | #define MXL_HYDRA_REG_SIZE_IN_BYTES 4 /* Hydra register size in bytes */ |
128 | #define MXL_HYDRA_I2C_HDR_SIZE (2 * sizeof(u8)) /* PLID + LEN(0xFF) */ |
129 | #define (MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE) |
130 | |
131 | #define MXL_HYDRA_SKU_ID_581 0 |
132 | #define MXL_HYDRA_SKU_ID_584 1 |
133 | #define MXL_HYDRA_SKU_ID_585 2 |
134 | #define MXL_HYDRA_SKU_ID_544 3 |
135 | #define MXL_HYDRA_SKU_ID_561 4 |
136 | #define MXL_HYDRA_SKU_ID_582 5 |
137 | #define MXL_HYDRA_SKU_ID_568 6 |
138 | |
139 | /* macro for register write data buffer size |
140 | * (PLID + LEN (0xFF) + RegAddr + RegData) |
141 | */ |
142 | #define MXL_HYDRA_REG_WRITE_LEN (MXL_HYDRA_I2C_HDR_SIZE + (2 * MXL_HYDRA_REG_SIZE_IN_BYTES)) |
143 | |
144 | /* macro to extract a single byte from 4-byte(32-bit) data */ |
145 | #define GET_BYTE(x, n) (((x) >> (8*(n))) & 0xFF) |
146 | |
147 | #define MAX_CMD_DATA 512 |
148 | |
149 | #define MXL_GET_REG_MASK_32(lsb_loc, num_of_bits) ((0xFFFFFFFF >> (32 - (num_of_bits))) << (lsb_loc)) |
150 | |
151 | #define FW_DL_SIGN (0xDEADBEEF) |
152 | |
153 | #define MBIN_FORMAT_VERSION '1' |
154 | #define 'M' |
155 | #define 'S' |
156 | #define MBIN_MAX_FILE_LENGTH (1<<23) |
157 | |
158 | struct { |
159 | u8 ; |
160 | u8 ; |
161 | u8 ; |
162 | u8 ; |
163 | u8 [4]; |
164 | u8 [3]; |
165 | u8 ; |
166 | u8 [4]; |
167 | }; |
168 | |
169 | struct MBIN_FILE_T { |
170 | struct MBIN_FILE_HEADER_T ; |
171 | u8 data[1]; |
172 | }; |
173 | |
174 | struct { |
175 | u8 ; |
176 | u8 [3]; |
177 | u8 [4]; |
178 | }; |
179 | |
180 | struct MBIN_SEGMENT_T { |
181 | struct MBIN_SEGMENT_HEADER_T ; |
182 | u8 data[1]; |
183 | }; |
184 | |
185 | enum MXL_CMD_TYPE_E { MXL_CMD_WRITE = 0, MXL_CMD_READ }; |
186 | |
187 | #define BUILD_HYDRA_CMD(cmd_id, req_type, size, data_ptr, cmd_buff) \ |
188 | do { \ |
189 | cmd_buff[0] = ((req_type == MXL_CMD_WRITE) ? MXL_HYDRA_PLID_CMD_WRITE : MXL_HYDRA_PLID_CMD_READ); \ |
190 | cmd_buff[1] = (size > 251) ? 0xff : (u8) (size + 4); \ |
191 | cmd_buff[2] = size; \ |
192 | cmd_buff[3] = cmd_id; \ |
193 | cmd_buff[4] = 0x00; \ |
194 | cmd_buff[5] = 0x00; \ |
195 | convert_endian(MXL_ENABLE_BIG_ENDIAN, size, (u8 *)data_ptr); \ |
196 | memcpy((void *)&cmd_buff[6], data_ptr, size); \ |
197 | } while (0) |
198 | |
199 | struct MXL_REG_FIELD_T { |
200 | u32 reg_addr; |
201 | u8 lsb_pos; |
202 | u8 num_of_bits; |
203 | }; |
204 | |
205 | struct MXL_DEV_CMD_DATA_T { |
206 | u32 data_size; |
207 | u8 data[MAX_CMD_DATA]; |
208 | }; |
209 | |
210 | enum MXL_HYDRA_SKU_TYPE_E { |
211 | MXL_HYDRA_SKU_TYPE_MIN = 0x00, |
212 | MXL_HYDRA_SKU_TYPE_581 = 0x00, |
213 | MXL_HYDRA_SKU_TYPE_584 = 0x01, |
214 | MXL_HYDRA_SKU_TYPE_585 = 0x02, |
215 | MXL_HYDRA_SKU_TYPE_544 = 0x03, |
216 | MXL_HYDRA_SKU_TYPE_561 = 0x04, |
217 | MXL_HYDRA_SKU_TYPE_5XX = 0x05, |
218 | MXL_HYDRA_SKU_TYPE_5YY = 0x06, |
219 | MXL_HYDRA_SKU_TYPE_511 = 0x07, |
220 | MXL_HYDRA_SKU_TYPE_561_DE = 0x08, |
221 | MXL_HYDRA_SKU_TYPE_582 = 0x09, |
222 | MXL_HYDRA_SKU_TYPE_541 = 0x0A, |
223 | MXL_HYDRA_SKU_TYPE_568 = 0x0B, |
224 | MXL_HYDRA_SKU_TYPE_542 = 0x0C, |
225 | MXL_HYDRA_SKU_TYPE_MAX = 0x0D, |
226 | }; |
227 | |
228 | struct MXL_HYDRA_SKU_COMMAND_T { |
229 | enum MXL_HYDRA_SKU_TYPE_E sku_type; |
230 | }; |
231 | |
232 | enum MXL_HYDRA_DEMOD_ID_E { |
233 | MXL_HYDRA_DEMOD_ID_0 = 0, |
234 | MXL_HYDRA_DEMOD_ID_1, |
235 | MXL_HYDRA_DEMOD_ID_2, |
236 | MXL_HYDRA_DEMOD_ID_3, |
237 | MXL_HYDRA_DEMOD_ID_4, |
238 | MXL_HYDRA_DEMOD_ID_5, |
239 | MXL_HYDRA_DEMOD_ID_6, |
240 | MXL_HYDRA_DEMOD_ID_7, |
241 | MXL_HYDRA_DEMOD_MAX |
242 | }; |
243 | |
244 | #define MXL_DEMOD_SCRAMBLE_SEQ_LEN 12 |
245 | |
246 | #define MAX_STEP_SIZE_24_XTAL_102_05_KHZ 195 |
247 | #define MAX_STEP_SIZE_24_XTAL_204_10_KHZ 215 |
248 | #define MAX_STEP_SIZE_24_XTAL_306_15_KHZ 203 |
249 | #define MAX_STEP_SIZE_24_XTAL_408_20_KHZ 177 |
250 | |
251 | #define MAX_STEP_SIZE_27_XTAL_102_05_KHZ 195 |
252 | #define MAX_STEP_SIZE_27_XTAL_204_10_KHZ 215 |
253 | #define MAX_STEP_SIZE_27_XTAL_306_15_KHZ 203 |
254 | #define MAX_STEP_SIZE_27_XTAL_408_20_KHZ 177 |
255 | |
256 | #define MXL_HYDRA_SPECTRUM_MIN_FREQ_KHZ 300000 |
257 | #define MXL_HYDRA_SPECTRUM_MAX_FREQ_KHZ 2350000 |
258 | |
259 | enum MXL_DEMOD_CHAN_PARAMS_OFFSET_E { |
260 | DMD_STANDARD_ADDR = 0, |
261 | DMD_SPECTRUM_INVERSION_ADDR, |
262 | DMD_SPECTRUM_ROLL_OFF_ADDR, |
263 | DMD_SYMBOL_RATE_ADDR, |
264 | DMD_MODULATION_SCHEME_ADDR, |
265 | DMD_FEC_CODE_RATE_ADDR, |
266 | DMD_SNR_ADDR, |
267 | DMD_FREQ_OFFSET_ADDR, |
268 | DMD_CTL_FREQ_OFFSET_ADDR, |
269 | DMD_STR_FREQ_OFFSET_ADDR, |
270 | DMD_FTL_FREQ_OFFSET_ADDR, |
271 | DMD_STR_NBC_SYNC_LOCK_ADDR, |
272 | DMD_CYCLE_SLIP_COUNT_ADDR, |
273 | DMD_DISPLAY_IQ_ADDR, |
274 | DMD_DVBS2_CRC_ERRORS_ADDR, |
275 | DMD_DVBS2_PER_COUNT_ADDR, |
276 | DMD_DVBS2_PER_WINDOW_ADDR, |
277 | DMD_DVBS_CORR_RS_ERRORS_ADDR, |
278 | DMD_DVBS_UNCORR_RS_ERRORS_ADDR, |
279 | DMD_DVBS_BER_COUNT_ADDR, |
280 | DMD_DVBS_BER_WINDOW_ADDR, |
281 | DMD_TUNER_ID_ADDR, |
282 | DMD_DVBS2_PILOT_ON_OFF_ADDR, |
283 | DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR, |
284 | |
285 | MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE, |
286 | }; |
287 | |
288 | enum MXL_HYDRA_TUNER_ID_E { |
289 | MXL_HYDRA_TUNER_ID_0 = 0, |
290 | MXL_HYDRA_TUNER_ID_1, |
291 | MXL_HYDRA_TUNER_ID_2, |
292 | MXL_HYDRA_TUNER_ID_3, |
293 | MXL_HYDRA_TUNER_MAX |
294 | }; |
295 | |
296 | enum MXL_HYDRA_BCAST_STD_E { |
297 | MXL_HYDRA_DSS = 0, |
298 | MXL_HYDRA_DVBS, |
299 | MXL_HYDRA_DVBS2, |
300 | }; |
301 | |
302 | enum MXL_HYDRA_FEC_E { |
303 | MXL_HYDRA_FEC_AUTO = 0, |
304 | MXL_HYDRA_FEC_1_2, |
305 | MXL_HYDRA_FEC_3_5, |
306 | MXL_HYDRA_FEC_2_3, |
307 | MXL_HYDRA_FEC_3_4, |
308 | MXL_HYDRA_FEC_4_5, |
309 | MXL_HYDRA_FEC_5_6, |
310 | MXL_HYDRA_FEC_6_7, |
311 | MXL_HYDRA_FEC_7_8, |
312 | MXL_HYDRA_FEC_8_9, |
313 | MXL_HYDRA_FEC_9_10, |
314 | }; |
315 | |
316 | enum MXL_HYDRA_MODULATION_E { |
317 | MXL_HYDRA_MOD_AUTO = 0, |
318 | MXL_HYDRA_MOD_QPSK, |
319 | MXL_HYDRA_MOD_8PSK |
320 | }; |
321 | |
322 | enum MXL_HYDRA_SPECTRUM_E { |
323 | MXL_HYDRA_SPECTRUM_AUTO = 0, |
324 | MXL_HYDRA_SPECTRUM_INVERTED, |
325 | MXL_HYDRA_SPECTRUM_NON_INVERTED, |
326 | }; |
327 | |
328 | enum MXL_HYDRA_ROLLOFF_E { |
329 | MXL_HYDRA_ROLLOFF_AUTO = 0, |
330 | MXL_HYDRA_ROLLOFF_0_20, |
331 | MXL_HYDRA_ROLLOFF_0_25, |
332 | MXL_HYDRA_ROLLOFF_0_35 |
333 | }; |
334 | |
335 | enum MXL_HYDRA_PILOTS_E { |
336 | MXL_HYDRA_PILOTS_OFF = 0, |
337 | MXL_HYDRA_PILOTS_ON, |
338 | MXL_HYDRA_PILOTS_AUTO |
339 | }; |
340 | |
341 | enum MXL_HYDRA_CONSTELLATION_SRC_E { |
342 | MXL_HYDRA_FORMATTER = 0, |
343 | MXL_HYDRA_LEGACY_FEC, |
344 | MXL_HYDRA_FREQ_RECOVERY, |
345 | MXL_HYDRA_NBC, |
346 | MXL_HYDRA_CTL, |
347 | MXL_HYDRA_EQ, |
348 | }; |
349 | |
350 | struct MXL_HYDRA_DEMOD_LOCK_T { |
351 | int agc_lock; /* AGC lock info */ |
352 | int fec_lock; /* Demod FEC block lock info */ |
353 | }; |
354 | |
355 | struct MXL_HYDRA_DEMOD_STATUS_DVBS_T { |
356 | u32 rs_errors; /* RS decoder err counter */ |
357 | u32 ber_window; /* Ber Windows */ |
358 | u32 ber_count; /* BER count */ |
359 | u32 ber_window_iter1; /* Ber Windows - post viterbi */ |
360 | u32 ber_count_iter1; /* BER count - post viterbi */ |
361 | }; |
362 | |
363 | struct MXL_HYDRA_DEMOD_STATUS_DSS_T { |
364 | u32 rs_errors; /* RS decoder err counter */ |
365 | u32 ber_window; /* Ber Windows */ |
366 | u32 ber_count; /* BER count */ |
367 | }; |
368 | |
369 | struct MXL_HYDRA_DEMOD_STATUS_DVBS2_T { |
370 | u32 crc_errors; /* CRC error counter */ |
371 | u32 packet_error_count; /* Number of packet errors */ |
372 | u32 total_packets; /* Total packets */ |
373 | }; |
374 | |
375 | struct MXL_HYDRA_DEMOD_STATUS_T { |
376 | enum MXL_HYDRA_BCAST_STD_E standard_mask; /* Standard DVB-S, DVB-S2 or DSS */ |
377 | |
378 | union { |
379 | struct MXL_HYDRA_DEMOD_STATUS_DVBS_T demod_status_dvbs; /* DVB-S demod status */ |
380 | struct MXL_HYDRA_DEMOD_STATUS_DVBS2_T demod_status_dvbs2; /* DVB-S2 demod status */ |
381 | struct MXL_HYDRA_DEMOD_STATUS_DSS_T demod_status_dss; /* DSS demod status */ |
382 | } u; |
383 | }; |
384 | |
385 | struct MXL_HYDRA_DEMOD_SIG_OFFSET_INFO_T { |
386 | s32 carrier_offset_in_hz; /* CRL offset info */ |
387 | s32 symbol_offset_in_symbol; /* SRL offset info */ |
388 | }; |
389 | |
390 | struct MXL_HYDRA_DEMOD_SCRAMBLE_INFO_T { |
391 | u8 scramble_sequence[MXL_DEMOD_SCRAMBLE_SEQ_LEN]; /* scramble sequence */ |
392 | u32 scramble_code; /* scramble gold code */ |
393 | }; |
394 | |
395 | enum MXL_HYDRA_SPECTRUM_STEP_SIZE_E { |
396 | MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */ |
397 | MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */ |
398 | MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */ |
399 | MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */ |
400 | |
401 | MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */ |
402 | MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */ |
403 | MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */ |
404 | MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */ |
405 | }; |
406 | |
407 | enum MXL_HYDRA_SPECTRUM_RESOLUTION_E { |
408 | MXL_HYDRA_SPECTRUM_RESOLUTION_00_1_DB, /* 0.1 dB */ |
409 | MXL_HYDRA_SPECTRUM_RESOLUTION_01_0_DB, /* 1.0 dB */ |
410 | MXL_HYDRA_SPECTRUM_RESOLUTION_05_0_DB, /* 5.0 dB */ |
411 | MXL_HYDRA_SPECTRUM_RESOLUTION_10_0_DB, /* 10 dB */ |
412 | }; |
413 | |
414 | enum MXL_HYDRA_SPECTRUM_ERROR_CODE_E { |
415 | MXL_SPECTRUM_NO_ERROR, |
416 | MXL_SPECTRUM_INVALID_PARAMETER, |
417 | MXL_SPECTRUM_INVALID_STEP_SIZE, |
418 | MXL_SPECTRUM_BW_CANNOT_BE_COVERED, |
419 | MXL_SPECTRUM_DEMOD_BUSY, |
420 | MXL_SPECTRUM_TUNER_NOT_ENABLED, |
421 | }; |
422 | |
423 | struct MXL_HYDRA_SPECTRUM_REQ_T { |
424 | u32 tuner_index; /* TUNER Ctrl: one of MXL58x_TUNER_ID_E */ |
425 | u32 demod_index; /* DEMOD Ctrl: one of MXL58x_DEMOD_ID_E */ |
426 | enum MXL_HYDRA_SPECTRUM_STEP_SIZE_E step_size_in_khz; |
427 | u32 starting_freq_ink_hz; |
428 | u32 total_steps; |
429 | enum MXL_HYDRA_SPECTRUM_RESOLUTION_E spectrum_division; |
430 | }; |
431 | |
432 | enum MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E { |
433 | MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */ |
434 | MXL_HYDRA_SEARCH_BW_PLUS_ROLLOFF, /* DMD searches for BW + ROLLOFF/2 */ |
435 | }; |
436 | |
437 | struct MXL58X_CFG_FREQ_OFF_SEARCH_RANGE_T { |
438 | u32 demod_index; |
439 | enum MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E search_type; |
440 | }; |
441 | |
442 | /* there are two slices |
443 | * slice0 - TS0, TS1, TS2 & TS3 |
444 | * slice1 - TS4, TS5, TS6 & TS7 |
445 | */ |
446 | #define MXL_HYDRA_TS_SLICE_MAX 2 |
447 | |
448 | #define MAX_FIXED_PID_NUM 32 |
449 | |
450 | #define MXL_HYDRA_NCO_CLK 418 /* 418 MHz */ |
451 | |
452 | #define MXL_HYDRA_MAX_TS_CLOCK 139 /* 139 MHz */ |
453 | |
454 | #define MXL_HYDRA_TS_FIXED_PID_FILT_SIZE 32 |
455 | |
456 | #define MXL_HYDRA_SHARED_PID_FILT_SIZE_DEFAULT 33 /* Shared PID filter size in 1-1 mux mode */ |
457 | #define MXL_HYDRA_SHARED_PID_FILT_SIZE_2_TO_1 66 /* Shared PID filter size in 2-1 mux mode */ |
458 | #define MXL_HYDRA_SHARED_PID_FILT_SIZE_4_TO_1 132 /* Shared PID filter size in 4-1 mux mode */ |
459 | |
460 | enum MXL_HYDRA_PID_BANK_TYPE_E { |
461 | MXL_HYDRA_SOFTWARE_PID_BANK = 0, |
462 | MXL_HYDRA_HARDWARE_PID_BANK, |
463 | }; |
464 | |
465 | enum MXL_HYDRA_TS_MUX_MODE_E { |
466 | MXL_HYDRA_TS_MUX_PID_REMAP = 0, |
467 | = 1, |
468 | }; |
469 | |
470 | enum MXL_HYDRA_TS_MUX_TYPE_E { |
471 | MXL_HYDRA_TS_MUX_DISABLE = 0, /* No Mux ( 1 TSIF to 1 TSIF) */ |
472 | MXL_HYDRA_TS_MUX_2_TO_1, /* Mux 2 TSIF to 1 TSIF */ |
473 | MXL_HYDRA_TS_MUX_4_TO_1, /* Mux 4 TSIF to 1 TSIF */ |
474 | }; |
475 | |
476 | enum MXL_HYDRA_TS_GROUP_E { |
477 | MXL_HYDRA_TS_GROUP_0_3 = 0, /* TS group 0 to 3 (TS0, TS1, TS2 & TS3) */ |
478 | MXL_HYDRA_TS_GROUP_4_7, /* TS group 0 to 3 (TS4, TS5, TS6 & TS7) */ |
479 | }; |
480 | |
481 | enum MXL_HYDRA_TS_PID_FLT_CTRL_E { |
482 | MXL_HYDRA_TS_PIDS_ALLOW_ALL = 0, /* Allow all pids */ |
483 | MXL_HYDRA_TS_PIDS_DROP_ALL, /* Drop all pids */ |
484 | MXL_HYDRA_TS_INVALIDATE_PID_FILTER, /* Delete current PD filter in the device */ |
485 | }; |
486 | |
487 | enum MXL_HYDRA_TS_PID_TYPE_E { |
488 | MXL_HYDRA_TS_PID_FIXED = 0, |
489 | MXL_HYDRA_TS_PID_REGULAR, |
490 | }; |
491 | |
492 | struct MXL_HYDRA_TS_PID_T { |
493 | u16 original_pid; /* pid from TS */ |
494 | u16 remapped_pid; /* remapped pid */ |
495 | enum MXL_BOOL_E enable; /* enable or disable pid */ |
496 | enum MXL_BOOL_E allow_or_drop; /* allow or drop pid */ |
497 | enum MXL_BOOL_E enable_pid_remap; /* enable or disable pid remap */ |
498 | u8 bond_id; /* Bond ID in A0 always 0 - Only for 568 Sku */ |
499 | u8 dest_id; /* Output port ID for the PID - Only for 568 Sku */ |
500 | }; |
501 | |
502 | struct { |
503 | enum MXL_BOOL_E ; |
504 | u8 ; |
505 | u8 [12]; |
506 | }; |
507 | |
508 | enum MXL_HYDRA_PID_FILTER_BANK_E { |
509 | MXL_HYDRA_PID_BANK_A = 0, |
510 | MXL_HYDRA_PID_BANK_B, |
511 | }; |
512 | |
513 | enum MXL_HYDRA_MPEG_DATA_FMT_E { |
514 | MXL_HYDRA_MPEG_SERIAL_MSB_1ST = 0, |
515 | MXL_HYDRA_MPEG_SERIAL_LSB_1ST, |
516 | |
517 | MXL_HYDRA_MPEG_SYNC_WIDTH_BIT = 0, |
518 | MXL_HYDRA_MPEG_SYNC_WIDTH_BYTE |
519 | }; |
520 | |
521 | enum MXL_HYDRA_MPEG_MODE_E { |
522 | MXL_HYDRA_MPEG_MODE_SERIAL_4_WIRE = 0, /* MPEG 4 Wire serial mode */ |
523 | MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE, /* MPEG 3 Wire serial mode */ |
524 | MXL_HYDRA_MPEG_MODE_SERIAL_2_WIRE, /* MPEG 2 Wire serial mode */ |
525 | MXL_HYDRA_MPEG_MODE_PARALLEL /* MPEG parallel mode - valid only for MxL581 */ |
526 | }; |
527 | |
528 | enum MXL_HYDRA_MPEG_CLK_TYPE_E { |
529 | MXL_HYDRA_MPEG_CLK_CONTINUOUS = 0, /* Continuous MPEG clock */ |
530 | MXL_HYDRA_MPEG_CLK_GAPPED, /* Gapped (gated) MPEG clock */ |
531 | }; |
532 | |
533 | enum MXL_HYDRA_MPEG_CLK_FMT_E { |
534 | MXL_HYDRA_MPEG_ACTIVE_LOW = 0, |
535 | MXL_HYDRA_MPEG_ACTIVE_HIGH, |
536 | |
537 | MXL_HYDRA_MPEG_CLK_NEGATIVE = 0, |
538 | MXL_HYDRA_MPEG_CLK_POSITIVE, |
539 | |
540 | MXL_HYDRA_MPEG_CLK_IN_PHASE = 0, |
541 | MXL_HYDRA_MPEG_CLK_INVERTED, |
542 | }; |
543 | |
544 | enum MXL_HYDRA_MPEG_CLK_PHASE_E { |
545 | MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG = 0, |
546 | MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_90_DEG, |
547 | MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_180_DEG, |
548 | MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_270_DEG |
549 | }; |
550 | |
551 | enum MXL_HYDRA_MPEG_ERR_INDICATION_E { |
552 | MXL_HYDRA_MPEG_ERR_REPLACE_SYNC = 0, |
553 | MXL_HYDRA_MPEG_ERR_REPLACE_VALID, |
554 | MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED |
555 | }; |
556 | |
557 | struct MXL_HYDRA_MPEGOUT_PARAM_T { |
558 | int enable; /* Enable or Disable MPEG OUT */ |
559 | enum MXL_HYDRA_MPEG_CLK_TYPE_E mpeg_clk_type; /* Continuous or gapped */ |
560 | enum MXL_HYDRA_MPEG_CLK_FMT_E mpeg_clk_pol; /* MPEG Clk polarity */ |
561 | u8 max_mpeg_clk_rate; /* Max MPEG Clk rate (0 - 104 MHz, 139 MHz) */ |
562 | enum MXL_HYDRA_MPEG_CLK_PHASE_E mpeg_clk_phase; /* MPEG Clk phase */ |
563 | enum MXL_HYDRA_MPEG_DATA_FMT_E lsb_or_msb_first; /* LSB first or MSB first in TS transmission */ |
564 | enum MXL_HYDRA_MPEG_DATA_FMT_E mpeg_sync_pulse_width; /* MPEG SYNC pulse width (1-bit or 1-byte) */ |
565 | enum MXL_HYDRA_MPEG_CLK_FMT_E mpeg_valid_pol; /* MPEG VALID polarity */ |
566 | enum MXL_HYDRA_MPEG_CLK_FMT_E mpeg_sync_pol; /* MPEG SYNC polarity */ |
567 | enum MXL_HYDRA_MPEG_MODE_E mpeg_mode; /* config 4/3/2-wire serial or parallel TS out */ |
568 | enum MXL_HYDRA_MPEG_ERR_INDICATION_E mpeg_error_indication; /* Enable or Disable MPEG error indication */ |
569 | }; |
570 | |
571 | enum MXL_HYDRA_EXT_TS_IN_ID_E { |
572 | MXL_HYDRA_EXT_TS_IN_0 = 0, |
573 | MXL_HYDRA_EXT_TS_IN_1, |
574 | MXL_HYDRA_EXT_TS_IN_2, |
575 | MXL_HYDRA_EXT_TS_IN_3, |
576 | MXL_HYDRA_EXT_TS_IN_MAX |
577 | }; |
578 | |
579 | enum MXL_HYDRA_TS_OUT_ID_E { |
580 | MXL_HYDRA_TS_OUT_0 = 0, |
581 | MXL_HYDRA_TS_OUT_1, |
582 | MXL_HYDRA_TS_OUT_2, |
583 | MXL_HYDRA_TS_OUT_3, |
584 | MXL_HYDRA_TS_OUT_4, |
585 | MXL_HYDRA_TS_OUT_5, |
586 | MXL_HYDRA_TS_OUT_6, |
587 | MXL_HYDRA_TS_OUT_7, |
588 | MXL_HYDRA_TS_OUT_MAX |
589 | }; |
590 | |
591 | enum MXL_HYDRA_TS_DRIVE_STRENGTH_E { |
592 | MXL_HYDRA_TS_DRIVE_STRENGTH_1X = 0, |
593 | MXL_HYDRA_TS_DRIVE_STRENGTH_2X, |
594 | MXL_HYDRA_TS_DRIVE_STRENGTH_3X, |
595 | MXL_HYDRA_TS_DRIVE_STRENGTH_4X, |
596 | MXL_HYDRA_TS_DRIVE_STRENGTH_5X, |
597 | MXL_HYDRA_TS_DRIVE_STRENGTH_6X, |
598 | MXL_HYDRA_TS_DRIVE_STRENGTH_7X, |
599 | MXL_HYDRA_TS_DRIVE_STRENGTH_8X |
600 | }; |
601 | |
602 | enum MXL_HYDRA_DEVICE_E { |
603 | MXL_HYDRA_DEVICE_581 = 0, |
604 | MXL_HYDRA_DEVICE_584, |
605 | MXL_HYDRA_DEVICE_585, |
606 | MXL_HYDRA_DEVICE_544, |
607 | MXL_HYDRA_DEVICE_561, |
608 | MXL_HYDRA_DEVICE_TEST, |
609 | MXL_HYDRA_DEVICE_582, |
610 | MXL_HYDRA_DEVICE_541, |
611 | MXL_HYDRA_DEVICE_568, |
612 | MXL_HYDRA_DEVICE_542, |
613 | MXL_HYDRA_DEVICE_541S, |
614 | MXL_HYDRA_DEVICE_561S, |
615 | MXL_HYDRA_DEVICE_581S, |
616 | MXL_HYDRA_DEVICE_MAX |
617 | }; |
618 | |
619 | /* Demod IQ data */ |
620 | struct MXL_HYDRA_DEMOD_IQ_SRC_T { |
621 | u32 demod_id; |
622 | u32 source_of_iq; /* == 0, it means I/Q comes from Formatter |
623 | * == 1, Legacy FEC |
624 | * == 2, Frequency Recovery |
625 | * == 3, NBC |
626 | * == 4, CTL |
627 | * == 5, EQ |
628 | * == 6, FPGA |
629 | */ |
630 | }; |
631 | |
632 | struct MXL_HYDRA_DEMOD_ABORT_TUNE_T { |
633 | u32 demod_id; |
634 | }; |
635 | |
636 | struct MXL_HYDRA_TUNER_CMD { |
637 | u8 tuner_id; |
638 | u8 enable; |
639 | }; |
640 | |
641 | /* Demod Para for Channel Tune */ |
642 | struct MXL_HYDRA_DEMOD_PARAM_T { |
643 | u32 tuner_index; |
644 | u32 demod_index; |
645 | u32 frequency_in_hz; /* Frequency */ |
646 | u32 standard; /* one of MXL_HYDRA_BCAST_STD_E */ |
647 | u32 spectrum_inversion; /* Input : Spectrum inversion. */ |
648 | u32 roll_off; /* rollOff (alpha) factor */ |
649 | u32 symbol_rate_in_hz; /* Symbol rate */ |
650 | u32 pilots; /* TRUE = pilots enabled */ |
651 | u32 modulation_scheme; /* Input : Modulation Scheme is one of MXL_HYDRA_MODULATION_E */ |
652 | u32 fec_code_rate; /* Input : Forward error correction rate. Is one of MXL_HYDRA_FEC_E */ |
653 | u32 max_carrier_offset_in_mhz; /* Maximum carrier freq offset in MHz. Same as freqSearchRangeKHz, but in unit of MHz. */ |
654 | }; |
655 | |
656 | struct MXL_HYDRA_DEMOD_SCRAMBLE_CODE_T { |
657 | u32 demod_index; |
658 | u8 scramble_sequence[12]; /* scramble sequence */ |
659 | u32 scramble_code; /* scramble gold code */ |
660 | }; |
661 | |
662 | struct MXL_INTR_CFG_T { |
663 | u32 intr_type; |
664 | u32 intr_duration_in_nano_secs; |
665 | u32 intr_mask; |
666 | }; |
667 | |
668 | struct MXL_HYDRA_POWER_MODE_CMD { |
669 | u8 power_mode; /* enumeration values are defined in MXL_HYDRA_PWR_MODE_E (device API.h) */ |
670 | }; |
671 | |
672 | struct MXL_HYDRA_RF_WAKEUP_PARAM_T { |
673 | u32 time_interval_in_seconds; /* in seconds */ |
674 | u32 tuner_index; |
675 | s32 ; |
676 | }; |
677 | |
678 | struct MXL_HYDRA_RF_WAKEUP_CFG_T { |
679 | u32 tuner_count; |
680 | struct MXL_HYDRA_RF_WAKEUP_PARAM_T params; |
681 | }; |
682 | |
683 | enum MXL_HYDRA_AUX_CTRL_MODE_E { |
684 | MXL_HYDRA_AUX_CTRL_MODE_FSK = 0, /* Select FSK controller */ |
685 | MXL_HYDRA_AUX_CTRL_MODE_DISEQC, /* Select DiSEqC controller */ |
686 | }; |
687 | |
688 | enum MXL_HYDRA_DISEQC_OPMODE_E { |
689 | MXL_HYDRA_DISEQC_ENVELOPE_MODE = 0, |
690 | MXL_HYDRA_DISEQC_TONE_MODE, |
691 | }; |
692 | |
693 | enum MXL_HYDRA_DISEQC_VER_E { |
694 | MXL_HYDRA_DISEQC_1_X = 0, /* Config DiSEqC 1.x mode */ |
695 | MXL_HYDRA_DISEQC_2_X, /* Config DiSEqC 2.x mode */ |
696 | MXL_HYDRA_DISEQC_DISABLE /* Disable DiSEqC */ |
697 | }; |
698 | |
699 | enum MXL_HYDRA_DISEQC_CARRIER_FREQ_E { |
700 | MXL_HYDRA_DISEQC_CARRIER_FREQ_22KHZ = 0, /* DiSEqC signal frequency of 22 KHz */ |
701 | MXL_HYDRA_DISEQC_CARRIER_FREQ_33KHZ, /* DiSEqC signal frequency of 33 KHz */ |
702 | MXL_HYDRA_DISEQC_CARRIER_FREQ_44KHZ /* DiSEqC signal frequency of 44 KHz */ |
703 | }; |
704 | |
705 | enum MXL_HYDRA_DISEQC_ID_E { |
706 | MXL_HYDRA_DISEQC_ID_0 = 0, |
707 | MXL_HYDRA_DISEQC_ID_1, |
708 | MXL_HYDRA_DISEQC_ID_2, |
709 | MXL_HYDRA_DISEQC_ID_3 |
710 | }; |
711 | |
712 | enum MXL_HYDRA_FSK_OP_MODE_E { |
713 | MXL_HYDRA_FSK_CFG_TYPE_39KPBS = 0, /* 39.0kbps */ |
714 | MXL_HYDRA_FSK_CFG_TYPE_39_017KPBS, /* 39.017kbps */ |
715 | MXL_HYDRA_FSK_CFG_TYPE_115_2KPBS /* 115.2kbps */ |
716 | }; |
717 | |
718 | struct MXL58X_DSQ_OP_MODE_T { |
719 | u32 diseqc_id; /* DSQ 0, 1, 2 or 3 */ |
720 | u32 op_mode; /* Envelope mode (0) or internal tone mode (1) */ |
721 | u32 version; /* 0: 1.0, 1: 1.1, 2: Disable */ |
722 | u32 center_freq; /* 0: 22KHz, 1: 33KHz and 2: 44 KHz */ |
723 | }; |
724 | |
725 | struct MXL_HYDRA_DISEQC_CFG_CONT_TONE_T { |
726 | u32 diseqc_id; |
727 | u32 cont_tone_flag; /* 1: Enable , 0: Disable */ |
728 | }; |
729 | |