| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved |
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| 4 | * |
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| 5 | * This program may alternatively be licensed under a proprietary license from |
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| 6 | * MaxLinear, Inc. |
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| 7 | * |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __MXL58X_REGISTERS_H__ |
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| 11 | #define __MXL58X_REGISTERS_H__ |
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| 12 | |
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| 13 | #define HYDRA_INTR_STATUS_REG 0x80030008 |
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| 14 | #define HYDRA_INTR_MASK_REG 0x8003000C |
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| 15 | |
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| 16 | #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */ |
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| 17 | #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */ |
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| 18 | |
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| 19 | #define HYDRA_CPU_RESET_REG 0x8003003C |
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| 20 | #define HYDRA_CPU_RESET_DATA 0x00000400 |
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| 21 | |
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| 22 | #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028 |
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| 23 | #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000 |
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| 24 | |
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| 25 | #define HYDRA_RESET_BBAND_REG 0x80030024 |
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| 26 | #define HYDRA_RESET_BBAND_DATA 0x00000000 |
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| 27 | |
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| 28 | #define HYDRA_RESET_XBAR_REG 0x80030020 |
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| 29 | #define HYDRA_RESET_XBAR_DATA 0x00000000 |
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| 30 | |
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| 31 | #define HYDRA_MODULES_CLK_1_REG 0x80030014 |
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| 32 | #define HYDRA_DISABLE_CLK_1 0x00000000 |
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| 33 | |
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| 34 | #define HYDRA_MODULES_CLK_2_REG 0x8003001C |
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| 35 | #define HYDRA_DISABLE_CLK_2 0x0000000B |
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| 36 | |
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| 37 | #define HYDRA_PRCM_ROOT_CLK_REG 0x80030018 |
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| 38 | #define HYDRA_PRCM_ROOT_CLK_DISABLE 0x00000000 |
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| 39 | |
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| 40 | #define HYDRA_CPU_RESET_CHECK_REG 0x80030008 |
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| 41 | #define HYDRA_CPU_RESET_CHECK_OFFSET 0x40000000 /* <bit 30> */ |
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| 42 | |
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| 43 | #define HYDRA_SKU_ID_REG 0x90000190 |
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| 44 | |
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| 45 | #define FW_DL_SIGN_ADDR 0x3FFFEAE0 |
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| 46 | |
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| 47 | /* Register to check if FW is running or not */ |
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| 48 | #define HYDRA_HEAR_BEAT 0x3FFFEDDC |
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| 49 | |
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| 50 | /* Firmware version */ |
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| 51 | #define HYDRA_FIRMWARE_VERSION 0x3FFFEDB8 |
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| 52 | #define HYDRA_FW_RC_VERSION 0x3FFFCFAC |
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| 53 | |
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| 54 | /* Firmware patch version */ |
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| 55 | #define HYDRA_FIRMWARE_PATCH_VERSION 0x3FFFEDC2 |
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| 56 | |
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| 57 | /* SOC operating temperature in C */ |
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| 58 | #define HYDRA_TEMPARATURE 0x3FFFEDB4 |
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| 59 | |
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| 60 | /* Demod & Tuner status registers */ |
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| 61 | /* Demod 0 status base address */ |
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| 62 | #define HYDRA_DEMOD_0_BASE_ADDR 0x3FFFC64C |
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| 63 | |
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| 64 | /* Tuner 0 status base address */ |
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| 65 | #define HYDRA_TUNER_0_BASE_ADDR 0x3FFFCE4C |
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| 66 | |
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| 67 | #define 0x3FFFEB6C |
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| 68 | |
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| 69 | /* Macros to determine base address of respective demod or tuner */ |
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| 70 | #define HYDRA_DMD_STATUS_OFFSET(demodID) ((demodID) * 0x100) |
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| 71 | #define HYDRA_TUNER_STATUS_OFFSET(tunerID) ((tunerID) * 0x40) |
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| 72 | |
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| 73 | /* Demod status address offset from respective demod's base address */ |
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| 74 | #define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET 0x3FFFC64C |
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| 75 | #define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET 0x3FFFC650 |
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| 76 | #define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET 0x3FFFC654 |
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| 77 | |
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| 78 | #define HYDRA_DMD_STANDARD_ADDR_OFFSET 0x3FFFC658 |
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| 79 | #define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET 0x3FFFC65C |
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| 80 | #define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET 0x3FFFC660 |
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| 81 | #define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET 0x3FFFC664 |
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| 82 | #define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET 0x3FFFC668 |
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| 83 | #define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET 0x3FFFC66C |
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| 84 | |
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| 85 | #define HYDRA_DMD_SNR_ADDR_OFFSET 0x3FFFC670 |
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| 86 | #define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC674 |
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| 87 | #define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC678 |
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| 88 | #define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67C |
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| 89 | #define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC680 |
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| 90 | #define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET 0x3FFFC684 |
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| 91 | #define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET 0x3FFFC688 |
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| 92 | |
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| 93 | #define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET 0x3FFFC68C |
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| 94 | #define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET 0x3FFFC68E |
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| 95 | |
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| 96 | #define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET 0x3FFFC690 |
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| 97 | #define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET 0x3FFFC694 |
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| 98 | #define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET 0x3FFFC698 |
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| 99 | |
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| 100 | #define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC69C |
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| 101 | #define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6A0 |
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| 102 | #define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET 0x3FFFC6A4 |
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| 103 | #define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET 0x3FFFC6A8 |
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| 104 | |
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| 105 | /* Debug-purpose DVB-S DMD 0 */ |
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| 106 | #define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6C8 /* corrected RS Errors: 1st iteration */ |
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| 107 | #define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6CC /* uncorrected RS Errors: 1st iteration */ |
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| 108 | #define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET 0x3FFFC6D0 |
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| 109 | #define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET 0x3FFFC6D4 |
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| 110 | |
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| 111 | #define HYDRA_DMD_TUNER_ID_ADDR_OFFSET 0x3FFFC6AC |
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| 112 | #define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET 0x3FFFC6B0 |
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| 113 | #define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET 0x3FFFC6B4 |
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| 114 | #define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET 0x3FFFC6B8 |
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| 115 | #define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR 0x3FFFC704 |
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| 116 | #define HYDRA_DMD_STATUS_INPUT_POWER_ADDR 0x3FFFC708 |
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| 117 | |
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| 118 | /* DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" */ |
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| 119 | #define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR 0x3FFFC710 /* DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */ |
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| 120 | #define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR 0x3FFFC714 /* DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */ |
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| 121 | |
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| 122 | #define DMD0_SPECTRUM_MIN_GAIN_STATUS 0x3FFFC73C |
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| 123 | #define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE 0x3FFFC740 |
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| 124 | #define DMD0_SPECTRUM_MIN_GAIN_NB_SAGC_VALUE 0x3FFFC744 |
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| 125 | |
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| 126 | #define HYDRA_DMD_STATUS_END_ADDR_OFFSET 0x3FFFC748 |
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| 127 | |
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| 128 | /* Tuner status address offset from respective tuners's base address */ |
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| 129 | #define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET 0x3FFFCE4C |
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| 130 | #define HYDRA_TUNER_AGC_LOCK_OFFSET 0x3FFFCE50 |
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| 131 | #define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET 0x3FFFCE54 |
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| 132 | #define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET 0x3FFFCE58 |
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| 133 | #define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET 0x3FFFCE5C |
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| 134 | #define HYDRA_TUNER_ENABLE_COMPLETE 0x3FFFEB78 |
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| 135 | |
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| 136 | #define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES) |
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| 137 | #define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO) |
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| 138 | |
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| 139 | #define HYDRA_VERSION 0x3FFFEDB8 |
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| 140 | #define HYDRA_DEMOD0_VERSION 0x3FFFEDBC |
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| 141 | #define HYDRA_DEMOD1_VERSION 0x3FFFEDC0 |
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| 142 | #define HYDRA_DEMOD2_VERSION 0x3FFFEDC4 |
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| 143 | #define HYDRA_DEMOD3_VERSION 0x3FFFEDC8 |
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| 144 | #define HYDRA_DEMOD4_VERSION 0x3FFFEDCC |
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| 145 | #define HYDRA_DEMOD5_VERSION 0x3FFFEDD0 |
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| 146 | #define HYDRA_DEMOD6_VERSION 0x3FFFEDD4 |
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| 147 | #define HYDRA_DEMOD7_VERSION 0x3FFFEDD8 |
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| 148 | #define HYDRA_HEAR_BEAT 0x3FFFEDDC |
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| 149 | #define HYDRA_SKU_MGMT 0x3FFFEBC0 |
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| 150 | |
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| 151 | #define MXL_HYDRA_FPGA_A_ADDRESS 0x91C00000 |
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| 152 | #define MXL_HYDRA_FPGA_B_ADDRESS 0x91D00000 |
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| 153 | |
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| 154 | /* TS control base address */ |
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| 155 | #define HYDRA_TS_CTRL_BASE_ADDR 0x90700000 |
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| 156 | |
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| 157 | #define MPEG_MUX_MODE_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08) |
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| 158 | |
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| 159 | #define MPEG_MUX_MODE_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08) |
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| 160 | |
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| 161 | #define PID_BANK_SEL_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190) |
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| 162 | #define PID_BANK_SEL_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0) |
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| 163 | |
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| 164 | #define MPEG_CLK_GATED_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x20) |
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| 165 | |
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| 166 | #define MPEG_CLK_ALWAYS_ON_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1D4) |
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| 167 | |
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| 168 | #define HYDRA_REGULAR_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190) |
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| 169 | |
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| 170 | #define HYDRA_FIXED_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190) |
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| 171 | |
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| 172 | #define HYDRA_REGULAR_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0) |
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| 173 | |
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| 174 | #define HYDRA_FIXED_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0) |
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| 175 | |
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| 176 | #define FIXED_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x9000) |
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| 177 | #define FIXED_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x9100) |
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| 178 | #define FIXED_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x9200) |
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| 179 | #define FIXED_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x9300) |
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| 180 | |
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| 181 | #define FIXED_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xB000) |
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| 182 | #define FIXED_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xB100) |
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| 183 | #define FIXED_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xB200) |
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| 184 | #define FIXED_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xB300) |
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| 185 | |
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| 186 | #define REGULAR_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x8000) |
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| 187 | #define REGULAR_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x8200) |
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| 188 | #define REGULAR_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x8400) |
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| 189 | #define REGULAR_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x8600) |
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| 190 | |
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| 191 | #define REGULAR_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xA000) |
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| 192 | #define REGULAR_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xA200) |
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| 193 | #define REGULAR_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xA400) |
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| 194 | #define REGULAR_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xA600) |
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| 195 | |
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| 196 | /***************************************************************************/ |
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| 197 | |
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| 198 | #define PAD_MUX_GPIO_00_SYNC_BASEADDR 0x90000188 |
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| 199 | |
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| 200 | |
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| 201 | #define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C |
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| 202 | |
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| 203 | #define XPT_PACKET_GAP_MIN_BASEADDR 0x90700044 |
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| 204 | #define XPT_NCO_COUNT_BASEADDR 0x90700238 |
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| 205 | |
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| 206 | #define XPT_NCO_COUNT_BASEADDR1 0x9070023C |
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| 207 | |
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| 208 | /* V2 DigRF status register */ |
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| 209 | |
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| 210 | #define XPT_PID_BASEADDR 0x90708000 |
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| 211 | |
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| 212 | #define XPT_PID_REMAP_BASEADDR 0x90708004 |
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| 213 | |
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| 214 | #define XPT_KNOWN_PID_BASEADDR 0x90709000 |
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| 215 | |
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| 216 | #define XPT_PID_BASEADDR1 0x9070A000 |
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| 217 | |
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| 218 | #define XPT_PID_REMAP_BASEADDR1 0x9070A004 |
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| 219 | |
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| 220 | #define XPT_KNOWN_PID_BASEADDR1 0x9070B000 |
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| 221 | |
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| 222 | #define XPT_BERT_LOCK_BASEADDR 0x907000B8 |
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| 223 | |
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| 224 | #define XPT_BERT_BASEADDR 0x907000BC |
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| 225 | |
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| 226 | #define XPT_BERT_INVERT_BASEADDR 0x907000C0 |
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| 227 | |
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| 228 | #define 0x907000C4 |
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| 229 | |
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| 230 | #define XPT_BERT_BASEADDR1 0x907000C8 |
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| 231 | |
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| 232 | #define XPT_BERT_BIT_COUNT0_BASEADDR 0x907000CC |
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| 233 | |
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| 234 | #define XPT_BERT_BIT_COUNT0_BASEADDR1 0x907000D0 |
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| 235 | |
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| 236 | #define XPT_BERT_BIT_COUNT1_BASEADDR 0x907000D4 |
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| 237 | |
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| 238 | #define XPT_BERT_BIT_COUNT1_BASEADDR1 0x907000D8 |
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| 239 | |
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| 240 | #define XPT_BERT_BIT_COUNT2_BASEADDR 0x907000DC |
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| 241 | |
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| 242 | #define XPT_BERT_BIT_COUNT2_BASEADDR1 0x907000E0 |
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| 243 | |
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| 244 | #define XPT_BERT_BIT_COUNT3_BASEADDR 0x907000E4 |
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| 245 | |
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| 246 | #define XPT_BERT_BIT_COUNT3_BASEADDR1 0x907000E8 |
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| 247 | |
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| 248 | #define XPT_BERT_BIT_COUNT4_BASEADDR 0x907000EC |
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| 249 | |
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| 250 | #define XPT_BERT_BIT_COUNT4_BASEADDR1 0x907000F0 |
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| 251 | |
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| 252 | #define XPT_BERT_BIT_COUNT5_BASEADDR 0x907000F4 |
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| 253 | |
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| 254 | #define XPT_BERT_BIT_COUNT5_BASEADDR1 0x907000F8 |
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| 255 | |
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| 256 | #define XPT_BERT_BIT_COUNT6_BASEADDR 0x907000FC |
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| 257 | |
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| 258 | #define XPT_BERT_BIT_COUNT6_BASEADDR1 0x90700100 |
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| 259 | |
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| 260 | #define XPT_BERT_BIT_COUNT7_BASEADDR 0x90700104 |
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| 261 | |
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| 262 | #define XPT_BERT_BIT_COUNT7_BASEADDR1 0x90700108 |
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| 263 | |
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| 264 | #define XPT_BERT_ERR_COUNT0_BASEADDR 0x9070010C |
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| 265 | |
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| 266 | #define XPT_BERT_ERR_COUNT0_BASEADDR1 0x90700110 |
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| 267 | |
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| 268 | #define XPT_BERT_ERR_COUNT1_BASEADDR 0x90700114 |
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| 269 | |
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| 270 | #define XPT_BERT_ERR_COUNT1_BASEADDR1 0x90700118 |
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| 271 | |
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| 272 | #define XPT_BERT_ERR_COUNT2_BASEADDR 0x9070011C |
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| 273 | |
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| 274 | #define XPT_BERT_ERR_COUNT2_BASEADDR1 0x90700120 |
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| 275 | |
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| 276 | #define XPT_BERT_ERR_COUNT3_BASEADDR 0x90700124 |
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| 277 | |
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| 278 | #define XPT_BERT_ERR_COUNT3_BASEADDR1 0x90700128 |
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| 279 | |
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| 280 | #define XPT_BERT_ERR_COUNT4_BASEADDR 0x9070012C |
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| 281 | |
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| 282 | #define XPT_BERT_ERR_COUNT4_BASEADDR1 0x90700130 |
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| 283 | |
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| 284 | #define XPT_BERT_ERR_COUNT5_BASEADDR 0x90700134 |
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| 285 | |
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| 286 | #define XPT_BERT_ERR_COUNT5_BASEADDR1 0x90700138 |
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| 287 | |
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| 288 | #define XPT_BERT_ERR_COUNT6_BASEADDR 0x9070013C |
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| 289 | |
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| 290 | #define XPT_BERT_ERR_COUNT6_BASEADDR1 0x90700140 |
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| 291 | |
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| 292 | #define XPT_BERT_ERR_COUNT7_BASEADDR 0x90700144 |
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| 293 | |
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| 294 | #define XPT_BERT_ERR_COUNT7_BASEADDR1 0x90700148 |
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| 295 | |
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| 296 | #define XPT_BERT_ERROR_BASEADDR 0x9070014C |
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| 297 | |
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| 298 | #define XPT_BERT_ANALYZER_BASEADDR 0x90700150 |
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| 299 | |
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| 300 | #define XPT_BERT_ANALYZER_BASEADDR1 0x90700154 |
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| 301 | |
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| 302 | #define XPT_BERT_ANALYZER_BASEADDR2 0x90700158 |
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| 303 | |
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| 304 | #define XPT_BERT_ANALYZER_BASEADDR3 0x9070015C |
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| 305 | |
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| 306 | #define XPT_BERT_ANALYZER_BASEADDR4 0x90700160 |
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| 307 | |
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| 308 | #define XPT_BERT_ANALYZER_BASEADDR5 0x90700164 |
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| 309 | |
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| 310 | #define XPT_BERT_ANALYZER_BASEADDR6 0x90700168 |
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| 311 | |
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| 312 | #define XPT_BERT_ANALYZER_BASEADDR7 0x9070016C |
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| 313 | |
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| 314 | #define XPT_BERT_ANALYZER_BASEADDR8 0x90700170 |
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| 315 | |
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| 316 | #define XPT_BERT_ANALYZER_BASEADDR9 0x90700174 |
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| 317 | |
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| 318 | #define XPT_DMD0_BASEADDR 0x9070024C |
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| 319 | |
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| 320 | /* V2 AGC Gain Freeze & step */ |
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| 321 | #define DBG_ENABLE_DISABLE_AGC (0x3FFFCF60) /* 1: DISABLE, 0:ENABLE */ |
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| 322 | #define WB_DFE0_DFE_FB_RF1_BASEADDR 0x903004A4 |
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| 323 | |
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| 324 | #define WB_DFE1_DFE_FB_RF1_BASEADDR 0x904004A4 |
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| 325 | |
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| 326 | #define WB_DFE2_DFE_FB_RF1_BASEADDR 0x905004A4 |
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| 327 | |
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| 328 | #define WB_DFE3_DFE_FB_RF1_BASEADDR 0x906004A4 |
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| 329 | |
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| 330 | #define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR 0x90200104 |
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| 331 | |
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| 332 | #define AFE_REG_AFE_REG_SPARE_BASEADDR 0x902000A0 |
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| 333 | |
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| 334 | #define AFE_REG_AFE_REG_SPARE_BASEADDR1 0x902000B4 |
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| 335 | |
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| 336 | #define AFE_REG_AFE_REG_SPARE_BASEADDR2 0x902000C4 |
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| 337 | |
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| 338 | #define AFE_REG_AFE_REG_SPARE_BASEADDR3 0x902000D4 |
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| 339 | |
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| 340 | #define WB_DFE0_DFE_FB_AGC_BASEADDR 0x90300498 |
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| 341 | |
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| 342 | #define WB_DFE1_DFE_FB_AGC_BASEADDR 0x90400498 |
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| 343 | |
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| 344 | #define WB_DFE2_DFE_FB_AGC_BASEADDR 0x90500498 |
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| 345 | |
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| 346 | #define WB_DFE3_DFE_FB_AGC_BASEADDR 0x90600498 |
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| 347 | |
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| 348 | #define WDT_WD_INT_BASEADDR 0x8002000C |
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| 349 | |
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| 350 | #define FSK_TX_FTM_BASEADDR 0x80090000 |
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| 351 | |
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| 352 | #define FSK_TX_FTM_TX_CNT_BASEADDR 0x80090018 |
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| 353 | |
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| 354 | #define AFE_REG_D2A_FSK_BIAS_BASEADDR 0x90200040 |
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| 355 | |
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| 356 | #define DMD_TEI_BASEADDR 0x3FFFEBE0 |
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| 357 | |
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| 358 | #endif /* __MXL58X_REGISTERS_H__ */ |
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| 359 | |
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