| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Public Include File for DRV6000 users |
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| 4 | * (ie. NxtWave Communications - NXT6000 demodulator driver) |
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| 5 | * |
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| 6 | * Copyright (C) 2001 NxtWave Communications, Inc. |
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| 7 | * |
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| 8 | */ |
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| 9 | |
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| 10 | /* Nxt6000 Register Addresses and Bit Masks */ |
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| 11 | |
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| 12 | /* Maximum Register Number */ |
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| 13 | #define MAXNXT6000REG (0x9A) |
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| 14 | |
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| 15 | /* 0x1B A_VIT_BER_0 aka 0x3A */ |
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| 16 | #define A_VIT_BER_0 (0x1B) |
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| 17 | |
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| 18 | /* 0x1D A_VIT_BER_TIMER_0 aka 0x38 */ |
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| 19 | #define A_VIT_BER_TIMER_0 (0x1D) |
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| 20 | |
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| 21 | /* 0x21 RS_COR_STAT */ |
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| 22 | #define RS_COR_STAT (0x21) |
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| 23 | #define RSCORESTATUS (0x03) |
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| 24 | |
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| 25 | /* 0x22 RS_COR_INTEN */ |
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| 26 | #define RS_COR_INTEN (0x22) |
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| 27 | |
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| 28 | /* 0x23 RS_COR_INSTAT */ |
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| 29 | #define RS_COR_INSTAT (0x23) |
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| 30 | #define INSTAT_ERROR (0x04) |
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| 31 | #define LOCK_LOSS_BITS (0x03) |
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| 32 | |
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| 33 | /* 0x24 RS_COR_SYNC_PARAM */ |
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| 34 | #define RS_COR_SYNC_PARAM (0x24) |
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| 35 | #define SYNC_PARAM (0x03) |
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| 36 | |
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| 37 | /* 0x25 BER_CTRL */ |
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| 38 | #define BER_CTRL (0x25) |
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| 39 | #define BER_ENABLE (0x02) |
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| 40 | #define BER_RESET (0x01) |
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| 41 | |
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| 42 | /* 0x26 BER_PAY */ |
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| 43 | #define BER_PAY (0x26) |
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| 44 | |
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| 45 | /* 0x27 BER_PKT_L */ |
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| 46 | #define BER_PKT_L (0x27) |
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| 47 | #define BER_PKTOVERFLOW (0x80) |
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| 48 | |
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| 49 | /* 0x30 VIT_COR_CTL */ |
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| 50 | #define VIT_COR_CTL (0x30) |
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| 51 | #define BER_CONTROL (0x02) |
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| 52 | #define VIT_COR_MASK (0x82) |
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| 53 | #define VIT_COR_RESYNC (0x80) |
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| 54 | |
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| 55 | |
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| 56 | /* 0x32 VIT_SYNC_STATUS */ |
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| 57 | #define VIT_SYNC_STATUS (0x32) |
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| 58 | #define VITINSYNC (0x80) |
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| 59 | |
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| 60 | /* 0x33 VIT_COR_INTEN */ |
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| 61 | #define VIT_COR_INTEN (0x33) |
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| 62 | #define GLOBAL_ENABLE (0x80) |
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| 63 | |
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| 64 | /* 0x34 VIT_COR_INTSTAT */ |
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| 65 | #define VIT_COR_INTSTAT (0x34) |
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| 66 | #define BER_DONE (0x08) |
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| 67 | #define BER_OVERFLOW (0x10) |
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| 68 | |
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| 69 | /* 0x38 VIT_BERTIME_2 */ |
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| 70 | #define VIT_BERTIME_2 (0x38) |
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| 71 | |
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| 72 | /* 0x39 VIT_BERTIME_1 */ |
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| 73 | #define VIT_BERTIME_1 (0x39) |
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| 74 | |
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| 75 | /* 0x3A VIT_BERTIME_0 */ |
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| 76 | #define VIT_BERTIME_0 (0x3a) |
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| 77 | |
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| 78 | /* 0x38 OFDM_BERTimer *//* Use the alias registers */ |
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| 79 | #define A_VIT_BER_TIMER_0 (0x1D) |
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| 80 | |
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| 81 | /* 0x3A VIT_BER_TIMER_0 *//* Use the alias registers */ |
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| 82 | #define A_VIT_BER_0 (0x1B) |
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| 83 | |
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| 84 | /* 0x3B VIT_BER_1 */ |
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| 85 | #define VIT_BER_1 (0x3b) |
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| 86 | |
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| 87 | /* 0x3C VIT_BER_0 */ |
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| 88 | #define VIT_BER_0 (0x3c) |
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| 89 | |
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| 90 | /* 0x40 OFDM_COR_CTL */ |
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| 91 | #define OFDM_COR_CTL (0x40) |
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| 92 | #define COREACT (0x20) |
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| 93 | #define HOLDSM (0x10) |
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| 94 | #define WAIT_AGC (0x02) |
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| 95 | #define WAIT_SYR (0x03) |
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| 96 | |
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| 97 | /* 0x41 OFDM_COR_STAT */ |
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| 98 | #define OFDM_COR_STAT (0x41) |
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| 99 | #define COR_STATUS (0x0F) |
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| 100 | #define MONITOR_TPS (0x06) |
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| 101 | #define TPSLOCKED (0x40) |
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| 102 | #define AGCLOCKED (0x10) |
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| 103 | |
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| 104 | /* 0x42 OFDM_COR_INTEN */ |
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| 105 | #define OFDM_COR_INTEN (0x42) |
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| 106 | #define TPSRCVBAD (0x04) |
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| 107 | #define TPSRCVCHANGED (0x02) |
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| 108 | #define TPSRCVUPDATE (0x01) |
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| 109 | |
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| 110 | /* 0x43 OFDM_COR_INSTAT */ |
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| 111 | #define OFDM_COR_INSTAT (0x43) |
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| 112 | |
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| 113 | /* 0x44 OFDM_COR_MODEGUARD */ |
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| 114 | #define OFDM_COR_MODEGUARD (0x44) |
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| 115 | #define FORCEMODE (0x08) |
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| 116 | #define FORCEMODE8K (0x04) |
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| 117 | |
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| 118 | /* 0x45 OFDM_AGC_CTL */ |
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| 119 | #define OFDM_AGC_CTL (0x45) |
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| 120 | #define INITIAL_AGC_BW (0x08) |
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| 121 | #define AGCNEG (0x02) |
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| 122 | #define AGCLAST (0x10) |
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| 123 | |
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| 124 | /* 0x48 OFDM_AGC_TARGET */ |
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| 125 | #define OFDM_AGC_TARGET (0x48) |
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| 126 | #define OFDM_AGC_TARGET_DEFAULT (0x28) |
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| 127 | #define OFDM_AGC_TARGET_IMPULSE (0x38) |
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| 128 | |
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| 129 | /* 0x49 OFDM_AGC_GAIN_1 */ |
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| 130 | #define OFDM_AGC_GAIN_1 (0x49) |
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| 131 | |
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| 132 | /* 0x4B OFDM_ITB_CTL */ |
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| 133 | #define OFDM_ITB_CTL (0x4B) |
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| 134 | #define ITBINV (0x01) |
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| 135 | |
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| 136 | /* 0x49 AGC_GAIN_1 */ |
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| 137 | #define AGC_GAIN_1 (0x49) |
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| 138 | |
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| 139 | /* 0x4A AGC_GAIN_2 */ |
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| 140 | #define AGC_GAIN_2 (0x4A) |
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| 141 | |
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| 142 | /* 0x4C OFDM_ITB_FREQ_1 */ |
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| 143 | #define OFDM_ITB_FREQ_1 (0x4C) |
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| 144 | |
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| 145 | /* 0x4D OFDM_ITB_FREQ_2 */ |
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| 146 | #define OFDM_ITB_FREQ_2 (0x4D) |
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| 147 | |
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| 148 | /* 0x4E OFDM_CAS_CTL */ |
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| 149 | #define OFDM_CAS_CTL (0x4E) |
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| 150 | #define ACSDIS (0x40) |
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| 151 | #define CCSEN (0x80) |
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| 152 | |
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| 153 | /* 0x4F CAS_FREQ */ |
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| 154 | #define CAS_FREQ (0x4F) |
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| 155 | |
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| 156 | /* 0x51 OFDM_SYR_CTL */ |
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| 157 | #define OFDM_SYR_CTL (0x51) |
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| 158 | #define SIXTH_ENABLE (0x80) |
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| 159 | #define SYR_TRACKING_DISABLE (0x01) |
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| 160 | |
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| 161 | /* 0x52 OFDM_SYR_STAT */ |
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| 162 | #define OFDM_SYR_STAT (0x52) |
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| 163 | #define GI14_2K_SYR_LOCK (0x13) |
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| 164 | #define GI14_8K_SYR_LOCK (0x17) |
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| 165 | #define GI14_SYR_LOCK (0x10) |
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| 166 | |
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| 167 | /* 0x55 OFDM_SYR_OFFSET_1 */ |
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| 168 | #define OFDM_SYR_OFFSET_1 (0x55) |
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| 169 | |
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| 170 | /* 0x56 OFDM_SYR_OFFSET_2 */ |
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| 171 | #define OFDM_SYR_OFFSET_2 (0x56) |
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| 172 | |
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| 173 | /* 0x58 OFDM_SCR_CTL */ |
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| 174 | #define OFDM_SCR_CTL (0x58) |
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| 175 | #define SYR_ADJ_DECAY_MASK (0x70) |
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| 176 | #define SYR_ADJ_DECAY (0x30) |
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| 177 | |
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| 178 | /* 0x59 OFDM_PPM_CTL_1 */ |
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| 179 | #define OFDM_PPM_CTL_1 (0x59) |
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| 180 | #define PPMMAX_MASK (0x30) |
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| 181 | #define PPM256 (0x30) |
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| 182 | |
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| 183 | /* 0x5B OFDM_TRL_NOMINALRATE_1 */ |
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| 184 | #define OFDM_TRL_NOMINALRATE_1 (0x5B) |
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| 185 | |
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| 186 | /* 0x5C OFDM_TRL_NOMINALRATE_2 */ |
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| 187 | #define OFDM_TRL_NOMINALRATE_2 (0x5C) |
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| 188 | |
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| 189 | /* 0x5D OFDM_TRL_TIME_1 */ |
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| 190 | #define OFDM_TRL_TIME_1 (0x5D) |
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| 191 | |
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| 192 | /* 0x60 OFDM_CRL_FREQ_1 */ |
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| 193 | #define OFDM_CRL_FREQ_1 (0x60) |
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| 194 | |
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| 195 | /* 0x63 OFDM_CHC_CTL_1 */ |
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| 196 | #define OFDM_CHC_CTL_1 (0x63) |
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| 197 | #define MANMEAN1 (0xF0); |
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| 198 | #define CHCFIR (0x01) |
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| 199 | |
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| 200 | /* 0x64 OFDM_CHC_SNR */ |
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| 201 | #define OFDM_CHC_SNR (0x64) |
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| 202 | |
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| 203 | /* 0x65 OFDM_BDI_CTL */ |
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| 204 | #define OFDM_BDI_CTL (0x65) |
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| 205 | #define LP_SELECT (0x02) |
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| 206 | |
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| 207 | /* 0x67 OFDM_TPS_RCVD_1 */ |
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| 208 | #define OFDM_TPS_RCVD_1 (0x67) |
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| 209 | #define TPSFRAME (0x03) |
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| 210 | |
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| 211 | /* 0x68 OFDM_TPS_RCVD_2 */ |
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| 212 | #define OFDM_TPS_RCVD_2 (0x68) |
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| 213 | |
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| 214 | /* 0x69 OFDM_TPS_RCVD_3 */ |
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| 215 | #define OFDM_TPS_RCVD_3 (0x69) |
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| 216 | |
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| 217 | /* 0x6A OFDM_TPS_RCVD_4 */ |
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| 218 | #define OFDM_TPS_RCVD_4 (0x6A) |
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| 219 | |
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| 220 | /* 0x6B OFDM_TPS_RESERVED_1 */ |
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| 221 | #define OFDM_TPS_RESERVED_1 (0x6B) |
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| 222 | |
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| 223 | /* 0x6C OFDM_TPS_RESERVED_2 */ |
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| 224 | #define OFDM_TPS_RESERVED_2 (0x6C) |
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| 225 | |
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| 226 | /* 0x73 OFDM_MSC_REV */ |
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| 227 | #define OFDM_MSC_REV (0x73) |
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| 228 | |
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| 229 | /* 0x76 OFDM_SNR_CARRIER_2 */ |
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| 230 | #define OFDM_SNR_CARRIER_2 (0x76) |
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| 231 | #define MEAN_MASK (0x80) |
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| 232 | #define MEANBIT (0x80) |
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| 233 | |
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| 234 | /* 0x80 ANALOG_CONTROL_0 */ |
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| 235 | #define ANALOG_CONTROL_0 (0x80) |
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| 236 | #define POWER_DOWN_ADC (0x40) |
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| 237 | |
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| 238 | /* 0x81 ENABLE_TUNER_IIC */ |
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| 239 | #define ENABLE_TUNER_IIC (0x81) |
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| 240 | #define ENABLE_TUNER_BIT (0x01) |
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| 241 | |
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| 242 | /* 0x82 EN_DMD_RACQ */ |
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| 243 | #define EN_DMD_RACQ (0x82) |
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| 244 | #define EN_DMD_RACQ_REG_VAL (0x81) |
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| 245 | #define EN_DMD_RACQ_REG_VAL_14 (0x01) |
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| 246 | |
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| 247 | /* 0x84 SNR_COMMAND */ |
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| 248 | #define SNR_COMMAND (0x84) |
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| 249 | #define SNRStat (0x80) |
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| 250 | |
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| 251 | /* 0x85 SNRCARRIERNUMBER_LSB */ |
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| 252 | #define SNRCARRIERNUMBER_LSB (0x85) |
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| 253 | |
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| 254 | /* 0x87 SNRMINTHRESHOLD_LSB */ |
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| 255 | #define SNRMINTHRESHOLD_LSB (0x87) |
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| 256 | |
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| 257 | /* 0x89 SNR_PER_CARRIER_LSB */ |
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| 258 | #define SNR_PER_CARRIER_LSB (0x89) |
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| 259 | |
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| 260 | /* 0x8B SNRBELOWTHRESHOLD_LSB */ |
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| 261 | #define SNRBELOWTHRESHOLD_LSB (0x8B) |
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| 262 | |
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| 263 | /* 0x91 RF_AGC_VAL_1 */ |
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| 264 | #define RF_AGC_VAL_1 (0x91) |
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| 265 | |
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| 266 | /* 0x92 RF_AGC_STATUS */ |
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| 267 | #define RF_AGC_STATUS (0x92) |
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| 268 | |
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| 269 | /* 0x98 DIAG_CONFIG */ |
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| 270 | #define DIAG_CONFIG (0x98) |
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| 271 | #define DIAG_MASK (0x70) |
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| 272 | #define TB_SET (0x10) |
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| 273 | #define TRAN_SELECT (0x07) |
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| 274 | #define SERIAL_SELECT (0x01) |
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| 275 | |
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| 276 | /* 0x99 SUB_DIAG_MODE_SEL */ |
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| 277 | #define SUB_DIAG_MODE_SEL (0x99) |
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| 278 | #define CLKINVERSION (0x01) |
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| 279 | |
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| 280 | /* 0x9A TS_FORMAT */ |
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| 281 | #define TS_FORMAT (0x9A) |
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| 282 | #define ERROR_SENSE (0x08) |
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| 283 | #define VALID_SENSE (0x04) |
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| 284 | #define SYNC_SENSE (0x02) |
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| 285 | #define GATED_CLOCK (0x01) |
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| 286 | |
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| 287 | #define NXT6000ASICDEVICE (0x0b) |
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| 288 | |
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