| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Driver for Silicon Labs SI2165 DVB-C/-T Demodulator |
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| 4 | * |
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| 5 | * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _DVB_SI2165_PRIV |
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| 9 | #define _DVB_SI2165_PRIV |
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| 10 | |
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| 11 | #define SI2165_FIRMWARE_REV_D "dvb-demod-si2165.fw" |
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| 12 | |
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| 13 | struct si2165_config { |
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| 14 | /* i2c addr |
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| 15 | * possible values: 0x64,0x65,0x66,0x67 |
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| 16 | */ |
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| 17 | u8 i2c_addr; |
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| 18 | |
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| 19 | /* external clock or XTAL */ |
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| 20 | u8 chip_mode; |
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| 21 | |
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| 22 | /* frequency of external clock or xtal in Hz |
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| 23 | * possible values: 4000000, 16000000, 20000000, 240000000, 27000000 |
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| 24 | */ |
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| 25 | u32 ref_freq_hz; |
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| 26 | |
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| 27 | /* invert the spectrum */ |
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| 28 | bool inversion; |
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| 29 | }; |
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| 30 | |
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| 31 | #define STATISTICS_PERIOD_PKT_COUNT 30000u |
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| 32 | #define STATISTICS_PERIOD_BIT_COUNT (STATISTICS_PERIOD_PKT_COUNT * 204 * 8) |
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| 33 | |
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| 34 | #define REG_CHIP_MODE 0x0000 |
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| 35 | #define REG_CHIP_REVCODE 0x0023 |
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| 36 | #define REV_CHIP_TYPE 0x0118 |
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| 37 | #define REG_CHIP_INIT 0x0050 |
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| 38 | #define REG_INIT_DONE 0x0054 |
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| 39 | #define REG_START_INIT 0x0096 |
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| 40 | #define REG_PLL_DIVL 0x00a0 |
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| 41 | #define REG_RST_ALL 0x00c0 |
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| 42 | #define REG_LOCK_TIMEOUT 0x00c4 |
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| 43 | #define REG_AUTO_RESET 0x00cb |
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| 44 | #define REG_OVERSAMP 0x00e4 |
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| 45 | #define REG_IF_FREQ_SHIFT 0x00e8 |
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| 46 | #define REG_DVB_STANDARD 0x00ec |
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| 47 | #define REG_DSP_CLOCK 0x0104 |
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| 48 | #define REG_ADC_RI8 0x0123 |
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| 49 | #define REG_ADC_RI1 0x012a |
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| 50 | #define REG_ADC_RI2 0x012b |
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| 51 | #define REG_ADC_RI3 0x012c |
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| 52 | #define REG_ADC_RI4 0x012d |
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| 53 | #define REG_ADC_RI5 0x012e |
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| 54 | #define REG_ADC_RI6 0x012f |
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| 55 | #define REG_AGC_CRESTF_DBX8 0x0150 |
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| 56 | #define REG_AGC_UNFREEZE_THR 0x015b |
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| 57 | #define REG_AGC2_MIN 0x016e |
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| 58 | #define REG_AGC2_KACQ 0x016c |
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| 59 | #define REG_AGC2_KLOC 0x016d |
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| 60 | #define REG_AGC2_OUTPUT 0x0170 |
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| 61 | #define REG_AGC2_CLKDIV 0x0171 |
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| 62 | #define REG_AGC_IF_TRI 0x018b |
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| 63 | #define REG_AGC_IF_SLR 0x0190 |
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| 64 | #define REG_AAF_CRESTF_DBX8 0x01a0 |
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| 65 | #define REG_ACI_CRESTF_DBX8 0x01c8 |
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| 66 | #define REG_SWEEP_STEP 0x0232 |
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| 67 | #define REG_KP_LOCK 0x023a |
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| 68 | #define REG_UNKNOWN_24C 0x024c |
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| 69 | #define REG_CENTRAL_TAP 0x0261 |
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| 70 | #define REG_C_N 0x026c |
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| 71 | #define REG_EQ_AUTO_CONTROL 0x0278 |
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| 72 | #define REG_UNKNOWN_27C 0x027c |
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| 73 | #define REG_START_SYNCHRO 0x02e0 |
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| 74 | #define REG_REQ_CONSTELLATION 0x02f4 |
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| 75 | #define REG_T_BANDWIDTH 0x0308 |
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| 76 | #define REG_FREQ_SYNC_RANGE 0x030c |
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| 77 | #define REG_IMPULSIVE_NOISE_REM 0x031c |
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| 78 | #define REG_WDOG_AND_BOOT 0x0341 |
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| 79 | #define REG_PATCH_VERSION 0x0344 |
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| 80 | #define REG_ADDR_JUMP 0x0348 |
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| 81 | #define REG_UNKNOWN_350 0x0350 |
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| 82 | #define REG_EN_RST_ERROR 0x035c |
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| 83 | #define REG_DCOM_CONTROL_BYTE 0x0364 |
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| 84 | #define REG_DCOM_ADDR 0x0368 |
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| 85 | #define REG_DCOM_DATA 0x036c |
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| 86 | #define REG_RST_CRC 0x0379 |
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| 87 | #define REG_GP_REG0_LSB 0x0384 |
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| 88 | #define REG_GP_REG0_MSB 0x0387 |
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| 89 | #define REG_CRC 0x037a |
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| 90 | #define REG_CHECK_SIGNAL 0x03a8 |
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| 91 | #define REG_CBER_RST 0x0424 |
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| 92 | #define REG_CBER_BIT 0x0428 |
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| 93 | #define REG_CBER_ERR 0x0430 |
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| 94 | #define REG_CBER_AVAIL 0x0434 |
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| 95 | #define REG_PS_LOCK 0x0440 |
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| 96 | #define REG_UNCOR_CNT 0x0468 |
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| 97 | #define REG_BER_RST 0x046c |
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| 98 | #define REG_BER_PKT 0x0470 |
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| 99 | #define REG_BER_BIT 0x0478 |
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| 100 | #define REG_BER_AVAIL 0x047c |
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| 101 | #define REG_FEC_LOCK 0x04e0 |
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| 102 | #define REG_TS_DATA_MODE 0x04e4 |
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| 103 | #define REG_TS_CLK_MODE 0x04e5 |
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| 104 | #define REG_TS_TRI 0x04ef |
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| 105 | #define REG_TS_SLR 0x04f4 |
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| 106 | #define 0x0641 |
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| 107 | #define 0x0646 |
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| 108 | #define REG_TS_PARALLEL_MODE 0x08f8 |
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| 109 | |
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| 110 | #endif /* _DVB_SI2165_PRIV */ |
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| 111 | |
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