1	/* SPDX-License-Identifier: GPL-2.0-or-later */
2	/*
3	* stv0367_regs.h
4	*
5	* Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
6	*
7	* Copyright (C) ST Microelectronics.
8	* Copyright (C) 2010,2011 NetUP Inc.
9	* Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
10	*/
11
12	#ifndef STV0367_REGS_H
13	#define STV0367_REGS_H
14
15	/* ID */
16	#define R367TER_ID 0xf000
17	#define F367TER_IDENTIFICATIONREG 0xf00000ff
18
19	/* I2CRPT */
20	#define R367TER_I2CRPT 0xf001
21	#define F367TER_I2CT_ON 0xf0010080
22	#define F367TER_ENARPT_LEVEL 0xf0010070
23	#define F367TER_SCLT_DELAY 0xf0010008
24	#define F367TER_SCLT_NOD 0xf0010004
25	#define F367TER_STOP_ENABLE 0xf0010002
26	#define F367TER_SDAT_NOD 0xf0010001
27
28	/* TOPCTRL */
29	#define R367TER_TOPCTRL 0xf002
30	#define F367TER_STDBY 0xf0020080
31	#define F367TER_STDBY_FEC 0xf0020040
32	#define F367TER_STDBY_CORE 0xf0020020
33	#define F367TER_QAM_COFDM 0xf0020010
34	#define F367TER_TS_DIS 0xf0020008
35	#define F367TER_DIR_CLK_216 0xf0020004
36	#define F367TER_TUNER_BB 0xf0020002
37	#define F367TER_DVBT_H 0xf0020001
38
39	/* IOCFG0 */
40	#define R367TER_IOCFG0 0xf003
41	#define F367TER_OP0_SD 0xf0030080
42	#define F367TER_OP0_VAL 0xf0030040
43	#define F367TER_OP0_OD 0xf0030020
44	#define F367TER_OP0_INV 0xf0030010
45	#define F367TER_OP0_DACVALUE_HI 0xf003000f
46
47	/* DAc0R */
48	#define R367TER_DAC0R 0xf004
49	#define F367TER_OP0_DACVALUE_LO 0xf00400ff
50
51	/* IOCFG1 */
52	#define R367TER_IOCFG1 0xf005
53	#define F367TER_IP0 0xf0050040
54	#define F367TER_OP1_OD 0xf0050020
55	#define F367TER_OP1_INV 0xf0050010
56	#define F367TER_OP1_DACVALUE_HI 0xf005000f
57
58	/* DAC1R */
59	#define R367TER_DAC1R 0xf006
60	#define F367TER_OP1_DACVALUE_LO 0xf00600ff
61
62	/* IOCFG2 */
63	#define R367TER_IOCFG2 0xf007
64	#define F367TER_OP2_LOCK_CONF 0xf00700e0
65	#define F367TER_OP2_OD 0xf0070010
66	#define F367TER_OP2_VAL 0xf0070008
67	#define F367TER_OP1_LOCK_CONF 0xf0070007
68
69	/* SDFR */
70	#define R367TER_SDFR 0xf008
71	#define F367TER_OP0_FREQ 0xf00800f0
72	#define F367TER_OP1_FREQ 0xf008000f
73
74	/* STATUS */
75	#define R367TER_STATUS 0xf009
76	#define F367TER_TPS_LOCK 0xf0090080
77	#define F367TER_SYR_LOCK 0xf0090040
78	#define F367TER_AGC_LOCK 0xf0090020
79	#define F367TER_PRF 0xf0090010
80	#define F367TER_LK 0xf0090008
81	#define F367TER_PR 0xf0090007
82
83	/* AUX_CLK */
84	#define R367TER_AUX_CLK 0xf00a
85	#define F367TER_AUXFEC_CTL 0xf00a00c0
86	#define F367TER_DIS_CKX4 0xf00a0020
87	#define F367TER_CKSEL 0xf00a0018
88	#define F367TER_CKDIV_PROG 0xf00a0006
89	#define F367TER_AUXCLK_ENA 0xf00a0001
90
91	/* FREESYS1 */
92	#define R367TER_FREESYS1 0xf00b
93	#define F367TER_FREE_SYS1 0xf00b00ff
94
95	/* FREESYS2 */
96	#define R367TER_FREESYS2 0xf00c
97	#define F367TER_FREE_SYS2 0xf00c00ff
98
99	/* FREESYS3 */
100	#define R367TER_FREESYS3 0xf00d
101	#define F367TER_FREE_SYS3 0xf00d00ff
102
103	/* GPIO_CFG */
104	#define R367TER_GPIO_CFG 0xf00e
105	#define F367TER_GPIO7_NOD 0xf00e0080
106	#define F367TER_GPIO7_CFG 0xf00e0040
107	#define F367TER_GPIO6_NOD 0xf00e0020
108	#define F367TER_GPIO6_CFG 0xf00e0010
109	#define F367TER_GPIO5_NOD 0xf00e0008
110	#define F367TER_GPIO5_CFG 0xf00e0004
111	#define F367TER_GPIO4_NOD 0xf00e0002
112	#define F367TER_GPIO4_CFG 0xf00e0001
113
114	/* GPIO_CMD */
115	#define R367TER_GPIO_CMD 0xf00f
116	#define F367TER_GPIO7_VAL 0xf00f0008
117	#define F367TER_GPIO6_VAL 0xf00f0004
118	#define F367TER_GPIO5_VAL 0xf00f0002
119	#define F367TER_GPIO4_VAL 0xf00f0001
120
121	/* AGC2MAX */
122	#define R367TER_AGC2MAX 0xf010
123	#define F367TER_AGC2_MAX 0xf01000ff
124
125	/* AGC2MIN */
126	#define R367TER_AGC2MIN 0xf011
127	#define F367TER_AGC2_MIN 0xf01100ff
128
129	/* AGC1MAX */
130	#define R367TER_AGC1MAX 0xf012
131	#define F367TER_AGC1_MAX 0xf01200ff
132
133	/* AGC1MIN */
134	#define R367TER_AGC1MIN 0xf013
135	#define F367TER_AGC1_MIN 0xf01300ff
136
137	/* AGCR */
138	#define R367TER_AGCR 0xf014
139	#define F367TER_RATIO_A 0xf01400e0
140	#define F367TER_RATIO_B 0xf0140018
141	#define F367TER_RATIO_C 0xf0140007
142
143	/* AGC2TH */
144	#define R367TER_AGC2TH 0xf015
145	#define F367TER_AGC2_THRES 0xf01500ff
146
147	/* AGC12c */
148	#define R367TER_AGC12C 0xf016
149	#define F367TER_AGC1_IV 0xf0160080
150	#define F367TER_AGC1_OD 0xf0160040
151	#define F367TER_AGC1_LOAD 0xf0160020
152	#define F367TER_AGC2_IV 0xf0160010
153	#define F367TER_AGC2_OD 0xf0160008
154	#define F367TER_AGC2_LOAD 0xf0160004
155	#define F367TER_AGC12_MODE 0xf0160003
156
157	/* AGCCTRL1 */
158	#define R367TER_AGCCTRL1 0xf017
159	#define F367TER_DAGC_ON 0xf0170080
160	#define F367TER_INVERT_AGC12 0xf0170040
161	#define F367TER_AGC1_MODE 0xf0170008
162	#define F367TER_AGC2_MODE 0xf0170007
163
164	/* AGCCTRL2 */
165	#define R367TER_AGCCTRL2 0xf018
166	#define F367TER_FRZ2_CTRL 0xf0180060
167	#define F367TER_FRZ1_CTRL 0xf0180018
168	#define F367TER_TIME_CST 0xf0180007
169
170	/* AGC1VAL1 */
171	#define R367TER_AGC1VAL1 0xf019
172	#define F367TER_AGC1_VAL_LO 0xf01900ff
173
174	/* AGC1VAL2 */
175	#define R367TER_AGC1VAL2 0xf01a
176	#define F367TER_AGC1_VAL_HI 0xf01a000f
177
178	/* AGC2VAL1 */
179	#define R367TER_AGC2VAL1 0xf01b
180	#define F367TER_AGC2_VAL_LO 0xf01b00ff
181
182	/* AGC2VAL2 */
183	#define R367TER_AGC2VAL2 0xf01c
184	#define F367TER_AGC2_VAL_HI 0xf01c000f
185
186	/* AGC2PGA */
187	#define R367TER_AGC2PGA 0xf01d
188	#define F367TER_AGC2_PGA 0xf01d00ff
189
190	/* OVF_RATE1 */
191	#define R367TER_OVF_RATE1 0xf01e
192	#define F367TER_OVF_RATE_HI 0xf01e000f
193
194	/* OVF_RATE2 */
195	#define R367TER_OVF_RATE2 0xf01f
196	#define F367TER_OVF_RATE_LO 0xf01f00ff
197
198	/* GAIN_SRC1 */
199	#define R367TER_GAIN_SRC1 0xf020
200	#define F367TER_INV_SPECTR 0xf0200080
201	#define F367TER_IQ_INVERT 0xf0200040
202	#define F367TER_INR_BYPASS 0xf0200020
203	#define F367TER_STATUS_INV_SPECRUM 0xf0200010
204	#define F367TER_GAIN_SRC_HI 0xf020000f
205
206	/* GAIN_SRC2 */
207	#define R367TER_GAIN_SRC2 0xf021
208	#define F367TER_GAIN_SRC_LO 0xf02100ff
209
210	/* INC_DEROT1 */
211	#define R367TER_INC_DEROT1 0xf022
212	#define F367TER_INC_DEROT_HI 0xf02200ff
213
214	/* INC_DEROT2 */
215	#define R367TER_INC_DEROT2 0xf023
216	#define F367TER_INC_DEROT_LO 0xf02300ff
217
218	/* PPM_CPAMP_DIR */
219	#define R367TER_PPM_CPAMP_DIR 0xf024
220	#define F367TER_PPM_CPAMP_DIRECT 0xf02400ff
221
222	/* PPM_CPAMP_INV */
223	#define R367TER_PPM_CPAMP_INV 0xf025
224	#define F367TER_PPM_CPAMP_INVER 0xf02500ff
225
226	/* FREESTFE_1 */
227	#define R367TER_FREESTFE_1 0xf026
228	#define F367TER_SYMBOL_NUMBER_INC 0xf02600c0
229	#define F367TER_SEL_LSB 0xf0260004
230	#define F367TER_AVERAGE_ON 0xf0260002
231	#define F367TER_DC_ADJ 0xf0260001
232
233	/* FREESTFE_2 */
234	#define R367TER_FREESTFE_2 0xf027
235	#define F367TER_SEL_SRCOUT 0xf02700c0
236	#define F367TER_SEL_SYRTHR 0xf027001f
237
238	/* DCOFFSET */
239	#define R367TER_DCOFFSET 0xf028
240	#define F367TER_SELECT_I_Q 0xf0280080
241	#define F367TER_DC_OFFSET 0xf028007f
242
243	/* EN_PROCESS */
244	#define R367TER_EN_PROCESS 0xf029
245	#define F367TER_FREE 0xf02900f0
246	#define F367TER_ENAB_MANUAL 0xf0290001
247
248	/* SDI_SMOOTHER */
249	#define R367TER_SDI_SMOOTHER 0xf02a
250	#define F367TER_DIS_SMOOTH 0xf02a0080
251	#define F367TER_SDI_INC_SMOOTHER 0xf02a007f
252
253	/* FE_LOOP_OPEN */
254	#define R367TER_FE_LOOP_OPEN 0xf02b
255	#define F367TER_TRL_LOOP_OP 0xf02b0002
256	#define F367TER_CRL_LOOP_OP 0xf02b0001
257
258	/* FREQOFF1 */
259	#define R367TER_FREQOFF1 0xf02c
260	#define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI 0xf02c00ff
261
262	/* FREQOFF2 */
263	#define R367TER_FREQOFF2 0xf02d
264	#define F367TER_FREQ_OFFSET_LOOP_OPEN_HI 0xf02d00ff
265
266	/* FREQOFF3 */
267	#define R367TER_FREQOFF3 0xf02e
268	#define F367TER_FREQ_OFFSET_LOOP_OPEN_LO 0xf02e00ff
269
270	/* TIMOFF1 */
271	#define R367TER_TIMOFF1 0xf02f
272	#define F367TER_TIM_OFFSET_LOOP_OPEN_HI 0xf02f00ff
273
274	/* TIMOFF2 */
275	#define R367TER_TIMOFF2 0xf030
276	#define F367TER_TIM_OFFSET_LOOP_OPEN_LO 0xf03000ff
277
278	/* EPQ */
279	#define R367TER_EPQ 0xf031
280	#define F367TER_EPQ1 0xf03100ff
281
282	/* EPQAUTO */
283	#define R367TER_EPQAUTO 0xf032
284	#define F367TER_EPQ2 0xf03200ff
285
286	/* SYR_UPDATE */
287	#define R367TER_SYR_UPDATE 0xf033
288	#define F367TER_SYR_PROTV 0xf0330080
289	#define F367TER_SYR_PROTV_GAIN 0xf0330060
290	#define F367TER_SYR_FILTER 0xf0330010
291	#define F367TER_SYR_TRACK_THRES 0xf033000c
292
293	/* CHPFREE */
294	#define R367TER_CHPFREE 0xf034
295	#define F367TER_CHP_FREE 0xf03400ff
296
297	/* PPM_STATE_MAC */
298	#define R367TER_PPM_STATE_MAC 0xf035
299	#define F367TER_PPM_STATE_MACHINE_DECODER 0xf035003f
300
301	/* INR_THRESHOLD */
302	#define R367TER_INR_THRESHOLD 0xf036
303	#define F367TER_INR_THRESH 0xf03600ff
304
305	/* EPQ_TPS_ID_CELL */
306	#define R367TER_EPQ_TPS_ID_CELL 0xf037
307	#define F367TER_ENABLE_LGTH_TO_CF 0xf0370080
308	#define F367TER_DIS_TPS_RSVD 0xf0370040
309	#define F367TER_DIS_BCH 0xf0370020
310	#define F367TER_DIS_ID_CEL 0xf0370010
311	#define F367TER_TPS_ADJUST_SYM 0xf037000f
312
313	/* EPQ_CFG */
314	#define R367TER_EPQ_CFG 0xf038
315	#define F367TER_EPQ_RANGE 0xf0380002
316	#define F367TER_EPQ_SOFT 0xf0380001
317
318	/* EPQ_STATUS */
319	#define R367TER_EPQ_STATUS 0xf039
320	#define F367TER_SLOPE_INC 0xf03900fc
321	#define F367TER_TPS_FIELD 0xf0390003
322
323	/* AUTORELOCK */
324	#define R367TER_AUTORELOCK 0xf03a
325	#define F367TER_BYPASS_BER_TEMPO 0xf03a0080
326	#define F367TER_BER_TEMPO 0xf03a0070
327	#define F367TER_BYPASS_COFDM_TEMPO 0xf03a0008
328	#define F367TER_COFDM_TEMPO 0xf03a0007
329
330	/* BER_THR_VMSB */
331	#define R367TER_BER_THR_VMSB 0xf03b
332	#define F367TER_BER_THRESHOLD_HI 0xf03b00ff
333
334	/* BER_THR_MSB */
335	#define R367TER_BER_THR_MSB 0xf03c
336	#define F367TER_BER_THRESHOLD_MID 0xf03c00ff
337
338	/* BER_THR_LSB */
339	#define R367TER_BER_THR_LSB 0xf03d
340	#define F367TER_BER_THRESHOLD_LO 0xf03d00ff
341
342	/* CCD */
343	#define R367TER_CCD 0xf03e
344	#define F367TER_CCD_DETECTED 0xf03e0080
345	#define F367TER_CCD_RESET 0xf03e0040
346	#define F367TER_CCD_THRESHOLD 0xf03e000f
347
348	/* SPECTR_CFG */
349	#define R367TER_SPECTR_CFG 0xf03f
350	#define F367TER_SPECT_CFG 0xf03f0003
351
352	/* CONSTMU_MSB */
353	#define R367TER_CONSTMU_MSB 0xf040
354	#define F367TER_CONSTMU_FREEZE 0xf0400080
355	#define F367TER_CONSTNU_FORCE_EN 0xf0400040
356	#define F367TER_CONST_MU_MSB 0xf040003f
357
358	/* CONSTMU_LSB */
359	#define R367TER_CONSTMU_LSB 0xf041
360	#define F367TER_CONST_MU_LSB 0xf04100ff
361
362	/* CONSTMU_MAX_MSB */
363	#define R367TER_CONSTMU_MAX_MSB 0xf042
364	#define F367TER_CONST_MU_MAX_MSB 0xf042003f
365
366	/* CONSTMU_MAX_LSB */
367	#define R367TER_CONSTMU_MAX_LSB 0xf043
368	#define F367TER_CONST_MU_MAX_LSB 0xf04300ff
369
370	/* ALPHANOISE */
371	#define R367TER_ALPHANOISE 0xf044
372	#define F367TER_USE_ALLFILTER 0xf0440080
373	#define F367TER_INTER_ON 0xf0440040
374	#define F367TER_ALPHA_NOISE 0xf044001f
375
376	/* MAXGP_MSB */
377	#define R367TER_MAXGP_MSB 0xf045
378	#define F367TER_MUFILTER_LENGTH 0xf04500f0
379	#define F367TER_MAX_GP_MSB 0xf045000f
380
381	/* MAXGP_LSB */
382	#define R367TER_MAXGP_LSB 0xf046
383	#define F367TER_MAX_GP_LSB 0xf04600ff
384
385	/* ALPHAMSB */
386	#define R367TER_ALPHAMSB 0xf047
387	#define F367TER_CHC_DATARATE 0xf04700c0
388	#define F367TER_ALPHA_MSB 0xf047003f
389
390	/* ALPHALSB */
391	#define R367TER_ALPHALSB 0xf048
392	#define F367TER_ALPHA_LSB 0xf04800ff
393
394	/* PILOT_ACCU */
395	#define R367TER_PILOT_ACCU 0xf049
396	#define F367TER_USE_SCAT4ADDAPT 0xf0490080
397	#define F367TER_PILOT_ACC 0xf049001f
398
399	/* PILOTMU_ACCU */
400	#define R367TER_PILOTMU_ACCU 0xf04a
401	#define F367TER_DISCARD_BAD_SP 0xf04a0080
402	#define F367TER_DISCARD_BAD_CP 0xf04a0040
403	#define F367TER_PILOT_MU_ACCU 0xf04a001f
404
405	/* FILT_CHANNEL_EST */
406	#define R367TER_FILT_CHANNEL_EST 0xf04b
407	#define F367TER_USE_FILT_PILOT 0xf04b0080
408	#define F367TER_FILT_CHANNEL 0xf04b007f
409
410	/* ALPHA_NOPISE_FREQ */
411	#define R367TER_ALPHA_NOPISE_FREQ 0xf04c
412	#define F367TER_NOISE_FREQ_FILT 0xf04c0040
413	#define F367TER_ALPHA_NOISE_FREQ 0xf04c003f
414
415	/* RATIO_PILOT */
416	#define R367TER_RATIO_PILOT 0xf04d
417	#define F367TER_RATIO_MEAN_SP 0xf04d00f0
418	#define F367TER_RATIO_MEAN_CP 0xf04d000f
419
420	/* CHC_CTL */
421	#define R367TER_CHC_CTL 0xf04e
422	#define F367TER_TRACK_EN 0xf04e0080
423	#define F367TER_NOISE_NORM_EN 0xf04e0040
424	#define F367TER_FORCE_CHC_RESET 0xf04e0020
425	#define F367TER_SHORT_TIME 0xf04e0010
426	#define F367TER_FORCE_STATE_EN 0xf04e0008
427	#define F367TER_FORCE_STATE 0xf04e0007
428
429	/* EPQ_ADJUST */
430	#define R367TER_EPQ_ADJUST 0xf04f
431	#define F367TER_ADJUST_SCAT_IND 0xf04f00c0
432	#define F367TER_ONE_SYMBOL 0xf04f0010
433	#define F367TER_EPQ_DECAY 0xf04f000e
434	#define F367TER_HOLD_SLOPE 0xf04f0001
435
436	/* EPQ_THRES */
437	#define R367TER_EPQ_THRES 0xf050
438	#define F367TER_EPQ_THR 0xf05000ff
439
440	/* OMEGA_CTL */
441	#define R367TER_OMEGA_CTL 0xf051
442	#define F367TER_OMEGA_RST 0xf0510080
443	#define F367TER_FREEZE_OMEGA 0xf0510040
444	#define F367TER_OMEGA_SEL 0xf051003f
445
446	/* GP_CTL */
447	#define R367TER_GP_CTL 0xf052
448	#define F367TER_CHC_STATE 0xf05200e0
449	#define F367TER_FREEZE_GP 0xf0520010
450	#define F367TER_GP_SEL 0xf052000f
451
452	/* MUMSB */
453	#define R367TER_MUMSB 0xf053
454	#define F367TER_MU_MSB 0xf053007f
455
456	/* MULSB */
457	#define R367TER_MULSB 0xf054
458	#define F367TER_MU_LSB 0xf05400ff
459
460	/* GPMSB */
461	#define R367TER_GPMSB 0xf055
462	#define F367TER_CSI_THRESHOLD 0xf05500e0
463	#define F367TER_GP_MSB 0xf055000f
464
465	/* GPLSB */
466	#define R367TER_GPLSB 0xf056
467	#define F367TER_GP_LSB 0xf05600ff
468
469	/* OMEGAMSB */
470	#define R367TER_OMEGAMSB 0xf057
471	#define F367TER_OMEGA_MSB 0xf057007f
472
473	/* OMEGALSB */
474	#define R367TER_OMEGALSB 0xf058
475	#define F367TER_OMEGA_LSB 0xf05800ff
476
477	/* SCAT_NB */
478	#define R367TER_SCAT_NB 0xf059
479	#define F367TER_CHC_TEST 0xf05900f8
480	#define F367TER_SCAT_NUMB 0xf0590003
481
482	/* CHC_DUMMY */
483	#define R367TER_CHC_DUMMY 0xf05a
484	#define F367TER_CHC_DUM 0xf05a00ff
485
486	/* INC_CTL */
487	#define R367TER_INC_CTL 0xf05b
488	#define F367TER_INC_BYPASS 0xf05b0080
489	#define F367TER_INC_NDEPTH 0xf05b000c
490	#define F367TER_INC_MADEPTH 0xf05b0003
491
492	/* INCTHRES_COR1 */
493	#define R367TER_INCTHRES_COR1 0xf05c
494	#define F367TER_INC_THRES_COR1 0xf05c00ff
495
496	/* INCTHRES_COR2 */
497	#define R367TER_INCTHRES_COR2 0xf05d
498	#define F367TER_INC_THRES_COR2 0xf05d00ff
499
500	/* INCTHRES_DET1 */
501	#define R367TER_INCTHRES_DET1 0xf05e
502	#define F367TER_INC_THRES_DET1 0xf05e003f
503
504	/* INCTHRES_DET2 */
505	#define R367TER_INCTHRES_DET2 0xf05f
506	#define F367TER_INC_THRES_DET2 0xf05f003f
507
508	/* IIR_CELLNB */
509	#define R367TER_IIR_CELLNB 0xf060
510	#define F367TER_NRST_IIR 0xf0600080
511	#define F367TER_IIR_CELL_NB 0xf0600007
512
513	/* IIRCX_COEFF1_MSB */
514	#define R367TER_IIRCX_COEFF1_MSB 0xf061
515	#define F367TER_IIR_CX_COEFF1_MSB 0xf06100ff
516
517	/* IIRCX_COEFF1_LSB */
518	#define R367TER_IIRCX_COEFF1_LSB 0xf062
519	#define F367TER_IIR_CX_COEFF1_LSB 0xf06200ff
520
521	/* IIRCX_COEFF2_MSB */
522	#define R367TER_IIRCX_COEFF2_MSB 0xf063
523	#define F367TER_IIR_CX_COEFF2_MSB 0xf06300ff
524
525	/* IIRCX_COEFF2_LSB */
526	#define R367TER_IIRCX_COEFF2_LSB 0xf064
527	#define F367TER_IIR_CX_COEFF2_LSB 0xf06400ff
528
529	/* IIRCX_COEFF3_MSB */
530	#define R367TER_IIRCX_COEFF3_MSB 0xf065
531	#define F367TER_IIR_CX_COEFF3_MSB 0xf06500ff
532
533	/* IIRCX_COEFF3_LSB */
534	#define R367TER_IIRCX_COEFF3_LSB 0xf066
535	#define F367TER_IIR_CX_COEFF3_LSB 0xf06600ff
536
537	/* IIRCX_COEFF4_MSB */
538	#define R367TER_IIRCX_COEFF4_MSB 0xf067
539	#define F367TER_IIR_CX_COEFF4_MSB 0xf06700ff
540
541	/* IIRCX_COEFF4_LSB */
542	#define R367TER_IIRCX_COEFF4_LSB 0xf068
543	#define F367TER_IIR_CX_COEFF4_LSB 0xf06800ff
544
545	/* IIRCX_COEFF5_MSB */
546	#define R367TER_IIRCX_COEFF5_MSB 0xf069
547	#define F367TER_IIR_CX_COEFF5_MSB 0xf06900ff
548
549	/* IIRCX_COEFF5_LSB */
550	#define R367TER_IIRCX_COEFF5_LSB 0xf06a
551	#define F367TER_IIR_CX_COEFF5_LSB 0xf06a00ff
552
553	/* FEPATH_CFG */
554	#define R367TER_FEPATH_CFG 0xf06b
555	#define F367TER_DEMUX_SWAP 0xf06b0004
556	#define F367TER_DIGAGC_SWAP 0xf06b0002
557	#define F367TER_LONGPATH_IF 0xf06b0001
558
559	/* PMC1_FUNC */
560	#define R367TER_PMC1_FUNC 0xf06c
561	#define F367TER_SOFT_RSTN 0xf06c0080
562	#define F367TER_PMC1_AVERAGE_TIME 0xf06c0078
563	#define F367TER_PMC1_WAIT_TIME 0xf06c0006
564	#define F367TER_PMC1_2N_SEL 0xf06c0001
565
566	/* PMC1_FOR */
567	#define R367TER_PMC1_FOR 0xf06d
568	#define F367TER_PMC1_FORCE 0xf06d0080
569	#define F367TER_PMC1_FORCE_VALUE 0xf06d007c
570
571	/* PMC2_FUNC */
572	#define R367TER_PMC2_FUNC 0xf06e
573	#define F367TER_PMC2_SOFT_STN 0xf06e0080
574	#define F367TER_PMC2_ACCU_TIME 0xf06e0070
575	#define F367TER_PMC2_CMDP_MN 0xf06e0008
576	#define F367TER_PMC2_SWAP 0xf06e0004
577
578	/* STATUS_ERR_DA */
579	#define R367TER_STATUS_ERR_DA 0xf06f
580	#define F367TER_COM_USEGAINTRK 0xf06f0080
581	#define F367TER_COM_AGCLOCK 0xf06f0040
582	#define F367TER_AUT_AGCLOCK 0xf06f0020
583	#define F367TER_MIN_ERR_X_LSB 0xf06f000f
584
585	/* DIG_AGC_R */
586	#define R367TER_DIG_AGC_R 0xf070
587	#define F367TER_COM_SOFT_RSTN 0xf0700080
588	#define F367TER_COM_AGC_ON 0xf0700040
589	#define F367TER_COM_EARLY 0xf0700020
590	#define F367TER_AUT_SOFT_RESETN 0xf0700010
591	#define F367TER_AUT_AGC_ON 0xf0700008
592	#define F367TER_AUT_EARLY 0xf0700004
593	#define F367TER_AUT_ROT_EN 0xf0700002
594	#define F367TER_LOCK_SOFT_RESETN 0xf0700001
595
596	/* COMAGC_TARMSB */
597	#define R367TER_COMAGC_TARMSB 0xf071
598	#define F367TER_COM_AGC_TARGET_MSB 0xf07100ff
599
600	/* COM_AGC_TAR_ENMODE */
601	#define R367TER_COM_AGC_TAR_ENMODE 0xf072
602	#define F367TER_COM_AGC_TARGET_LSB 0xf07200f0
603	#define F367TER_COM_ENMODE 0xf072000f
604
605	/* COM_AGC_CFG */
606	#define R367TER_COM_AGC_CFG 0xf073
607	#define F367TER_COM_N 0xf07300f8
608	#define F367TER_COM_STABMODE 0xf0730006
609	#define F367TER_ERR_SEL 0xf0730001
610
611	/* COM_AGC_GAIN1 */
612	#define R367TER_COM_AGC_GAIN1 0xf074
613	#define F367TER_COM_GAIN1aCK 0xf07400f0
614	#define F367TER_COM_GAIN1TRK 0xf074000f
615
616	/* AUT_AGC_TARGETMSB */
617	#define R367TER_AUT_AGC_TARGETMSB 0xf075
618	#define F367TER_AUT_AGC_TARGET_MSB 0xf07500ff
619
620	/* LOCK_DET_MSB */
621	#define R367TER_LOCK_DET_MSB 0xf076
622	#define F367TER_LOCK_DETECT_MSB 0xf07600ff
623
624	/* AGCTAR_LOCK_LSBS */
625	#define R367TER_AGCTAR_LOCK_LSBS 0xf077
626	#define F367TER_AUT_AGC_TARGET_LSB 0xf07700f0
627	#define F367TER_LOCK_DETECT_LSB 0xf077000f
628
629	/* AUT_GAIN_EN */
630	#define R367TER_AUT_GAIN_EN 0xf078
631	#define F367TER_AUT_ENMODE 0xf07800f0
632	#define F367TER_AUT_GAIN2 0xf078000f
633
634	/* AUT_CFG */
635	#define R367TER_AUT_CFG 0xf079
636	#define F367TER_AUT_N 0xf07900f8
637	#define F367TER_INT_CHOICE 0xf0790006
638	#define F367TER_INT_LOAD 0xf0790001
639
640	/* LOCKN */
641	#define R367TER_LOCKN 0xf07a
642	#define F367TER_LOCK_N 0xf07a00f8
643	#define F367TER_SEL_IQNTAR 0xf07a0004
644	#define F367TER_LOCK_DETECT_CHOICE 0xf07a0003
645
646	/* INT_X_3 */
647	#define R367TER_INT_X_3 0xf07b
648	#define F367TER_INT_X3 0xf07b00ff
649
650	/* INT_X_2 */
651	#define R367TER_INT_X_2 0xf07c
652	#define F367TER_INT_X2 0xf07c00ff
653
654	/* INT_X_1 */
655	#define R367TER_INT_X_1 0xf07d
656	#define F367TER_INT_X1 0xf07d00ff
657
658	/* INT_X_0 */
659	#define R367TER_INT_X_0 0xf07e
660	#define F367TER_INT_X0 0xf07e00ff
661
662	/* MIN_ERRX_MSB */
663	#define R367TER_MIN_ERRX_MSB 0xf07f
664	#define F367TER_MIN_ERR_X_MSB 0xf07f00ff
665
666	/* COR_CTL */
667	#define R367TER_COR_CTL 0xf080
668	#define F367TER_CORE_ACTIVE 0xf0800020
669	#define F367TER_HOLD 0xf0800010
670	#define F367TER_CORE_STATE_CTL 0xf080000f
671
672	/* COR_STAT */
673	#define R367TER_COR_STAT 0xf081
674	#define F367TER_SCATT_LOCKED 0xf0810080
675	#define F367TER_TPS_LOCKED 0xf0810040
676	#define F367TER_SYR_LOCKED_COR 0xf0810020
677	#define F367TER_AGC_LOCKED_STAT 0xf0810010
678	#define F367TER_CORE_STATE_STAT 0xf081000f
679
680	/* COR_INTEN */
681	#define R367TER_COR_INTEN 0xf082
682	#define F367TER_INTEN 0xf0820080
683	#define F367TER_INTEN_SYR 0xf0820020
684	#define F367TER_INTEN_FFT 0xf0820010
685	#define F367TER_INTEN_AGC 0xf0820008
686	#define F367TER_INTEN_TPS1 0xf0820004
687	#define F367TER_INTEN_TPS2 0xf0820002
688	#define F367TER_INTEN_TPS3 0xf0820001
689
690	/* COR_INTSTAT */
691	#define R367TER_COR_INTSTAT 0xf083
692	#define F367TER_INTSTAT_SYR 0xf0830020
693	#define F367TER_INTSTAT_FFT 0xf0830010
694	#define F367TER_INTSAT_AGC 0xf0830008
695	#define F367TER_INTSTAT_TPS1 0xf0830004
696	#define F367TER_INTSTAT_TPS2 0xf0830002
697	#define F367TER_INTSTAT_TPS3 0xf0830001
698
699	/* COR_MODEGUARD */
700	#define R367TER_COR_MODEGUARD 0xf084
701	#define F367TER_FORCE 0xf0840010
702	#define F367TER_MODE 0xf084000c
703	#define F367TER_GUARD 0xf0840003
704
705	/* AGC_CTL */
706	#define R367TER_AGC_CTL 0xf085
707	#define F367TER_AGC_TIMING_FACTOR 0xf08500e0
708	#define F367TER_AGC_LAST 0xf0850010
709	#define F367TER_AGC_GAIN 0xf085000c
710	#define F367TER_AGC_NEG 0xf0850002
711	#define F367TER_AGC_SET 0xf0850001
712
713	/* AGC_MANUAL1 */
714	#define R367TER_AGC_MANUAL1 0xf086
715	#define F367TER_AGC_VAL_LO 0xf08600ff
716
717	/* AGC_MANUAL2 */
718	#define R367TER_AGC_MANUAL2 0xf087
719	#define F367TER_AGC_VAL_HI 0xf087000f
720
721	/* AGC_TARG */
722	#define R367TER_AGC_TARG 0xf088
723	#define F367TER_AGC_TARGET 0xf08800ff
724
725	/* AGC_GAIN1 */
726	#define R367TER_AGC_GAIN1 0xf089
727	#define F367TER_AGC_GAIN_LO 0xf08900ff
728
729	/* AGC_GAIN2 */
730	#define R367TER_AGC_GAIN2 0xf08a
731	#define F367TER_AGC_LOCKED_GAIN2 0xf08a0010
732	#define F367TER_AGC_GAIN_HI 0xf08a000f
733
734	/* RESERVED_1 */
735	#define R367TER_RESERVED_1 0xf08b
736	#define F367TER_RESERVED1 0xf08b00ff
737
738	/* RESERVED_2 */
739	#define R367TER_RESERVED_2 0xf08c
740	#define F367TER_RESERVED2 0xf08c00ff
741
742	/* RESERVED_3 */
743	#define R367TER_RESERVED_3 0xf08d
744	#define F367TER_RESERVED3 0xf08d00ff
745
746	/* CAS_CTL */
747	#define R367TER_CAS_CTL 0xf08e
748	#define F367TER_CCS_ENABLE 0xf08e0080
749	#define F367TER_ACS_DISABLE 0xf08e0040
750	#define F367TER_DAGC_DIS 0xf08e0020
751	#define F367TER_DAGC_GAIN 0xf08e0018
752	#define F367TER_CCSMU 0xf08e0007
753
754	/* CAS_FREQ */
755	#define R367TER_CAS_FREQ 0xf08f
756	#define F367TER_CCS_FREQ 0xf08f00ff
757
758	/* CAS_DAGCGAIN */
759	#define R367TER_CAS_DAGCGAIN 0xf090
760	#define F367TER_CAS_DAGC_GAIN 0xf09000ff
761
762	/* SYR_CTL */
763	#define R367TER_SYR_CTL 0xf091
764	#define F367TER_SICTH_ENABLE 0xf0910080
765	#define F367TER_LONG_ECHO 0xf0910078
766	#define F367TER_AUTO_LE_EN 0xf0910004
767	#define F367TER_SYR_BYPASS 0xf0910002
768	#define F367TER_SYR_TR_DIS 0xf0910001
769
770	/* SYR_STAT */
771	#define R367TER_SYR_STAT 0xf092
772	#define F367TER_SYR_LOCKED_STAT 0xf0920010
773	#define F367TER_SYR_MODE 0xf092000c
774	#define F367TER_SYR_GUARD 0xf0920003
775
776	/* SYR_NCO1 */
777	#define R367TER_SYR_NCO1 0xf093
778	#define F367TER_SYR_NCO_LO 0xf09300ff
779
780	/* SYR_NCO2 */
781	#define R367TER_SYR_NCO2 0xf094
782	#define F367TER_SYR_NCO_HI 0xf094003f
783
784	/* SYR_OFFSET1 */
785	#define R367TER_SYR_OFFSET1 0xf095
786	#define F367TER_SYR_OFFSET_LO 0xf09500ff
787
788	/* SYR_OFFSET2 */
789	#define R367TER_SYR_OFFSET2 0xf096
790	#define F367TER_SYR_OFFSET_HI 0xf096003f
791
792	/* FFT_CTL */
793	#define R367TER_FFT_CTL 0xf097
794	#define F367TER_SHIFT_FFT_TRIG 0xf0970018
795	#define F367TER_FFT_TRIGGER 0xf0970004
796	#define F367TER_FFT_MANUAL 0xf0970002
797	#define F367TER_IFFT_MODE 0xf0970001
798
799	/* SCR_CTL */
800	#define R367TER_SCR_CTL 0xf098
801	#define F367TER_SYRADJDECAY 0xf0980070
802	#define F367TER_SCR_CPEDIS 0xf0980002
803	#define F367TER_SCR_DIS 0xf0980001
804
805	/* PPM_CTL1 */
806	#define R367TER_PPM_CTL1 0xf099
807	#define F367TER_PPM_MAXFREQ 0xf0990030
808	#define F367TER_PPM_MAXTIM 0xf0990008
809	#define F367TER_PPM_INVSEL 0xf0990004
810	#define F367TER_PPM_SCATDIS 0xf0990002
811	#define F367TER_PPM_BYP 0xf0990001
812
813	/* TRL_CTL */
814	#define R367TER_TRL_CTL 0xf09a
815	#define F367TER_TRL_NOMRATE_LSB 0xf09a0080
816	#define F367TER_TRL_GAIN_FACTOR 0xf09a0078
817	#define F367TER_TRL_LOOPGAIN 0xf09a0007
818
819	/* TRL_NOMRATE1 */
820	#define R367TER_TRL_NOMRATE1 0xf09b
821	#define F367TER_TRL_NOMRATE_LO 0xf09b00ff
822
823	/* TRL_NOMRATE2 */
824	#define R367TER_TRL_NOMRATE2 0xf09c
825	#define F367TER_TRL_NOMRATE_HI 0xf09c00ff
826
827	/* TRL_TIME1 */
828	#define R367TER_TRL_TIME1 0xf09d
829	#define F367TER_TRL_TOFFSET_LO 0xf09d00ff
830
831	/* TRL_TIME2 */
832	#define R367TER_TRL_TIME2 0xf09e
833	#define F367TER_TRL_TOFFSET_HI 0xf09e00ff
834
835	/* CRL_CTL */
836	#define R367TER_CRL_CTL 0xf09f
837	#define F367TER_CRL_DIS 0xf09f0080
838	#define F367TER_CRL_GAIN_FACTOR 0xf09f0078
839	#define F367TER_CRL_LOOPGAIN 0xf09f0007
840
841	/* CRL_FREQ1 */
842	#define R367TER_CRL_FREQ1 0xf0a0
843	#define F367TER_CRL_FOFFSET_LO 0xf0a000ff
844
845	/* CRL_FREQ2 */
846	#define R367TER_CRL_FREQ2 0xf0a1
847	#define F367TER_CRL_FOFFSET_HI 0xf0a100ff
848
849	/* CRL_FREQ3 */
850	#define R367TER_CRL_FREQ3 0xf0a2
851	#define F367TER_CRL_FOFFSET_VHI 0xf0a200ff
852
853	/* TPS_SFRAME_CTL */
854	#define R367TER_TPS_SFRAME_CTL 0xf0a3
855	#define F367TER_TPS_SFRAME_SYNC 0xf0a30001
856
857	/* CHC_SNR */
858	#define R367TER_CHC_SNR 0xf0a4
859	#define F367TER_CHCSNR 0xf0a400ff
860
861	/* BDI_CTL */
862	#define R367TER_BDI_CTL 0xf0a5
863	#define F367TER_BDI_LPSEL 0xf0a50002
864	#define F367TER_BDI_SERIAL 0xf0a50001
865
866	/* DMP_CTL */
867	#define R367TER_DMP_CTL 0xf0a6
868	#define F367TER_DMP_SCALING_FACTOR 0xf0a6001e
869	#define F367TER_DMP_SDDIS 0xf0a60001
870
871	/* TPS_RCVD1 */
872	#define R367TER_TPS_RCVD1 0xf0a7
873	#define F367TER_TPS_CHANGE 0xf0a70040
874	#define F367TER_BCH_OK 0xf0a70020
875	#define F367TER_TPS_SYNC 0xf0a70010
876	#define F367TER_TPS_FRAME 0xf0a70003
877
878	/* TPS_RCVD2 */
879	#define R367TER_TPS_RCVD2 0xf0a8
880	#define F367TER_TPS_HIERMODE 0xf0a80070
881	#define F367TER_TPS_CONST 0xf0a80003
882
883	/* TPS_RCVD3 */
884	#define R367TER_TPS_RCVD3 0xf0a9
885	#define F367TER_TPS_LPCODE 0xf0a90070
886	#define F367TER_TPS_HPCODE 0xf0a90007
887
888	/* TPS_RCVD4 */
889	#define R367TER_TPS_RCVD4 0xf0aa
890	#define F367TER_TPS_GUARD 0xf0aa0030
891	#define F367TER_TPS_MODE 0xf0aa0003
892
893	/* TPS_ID_CELL1 */
894	#define R367TER_TPS_ID_CELL1 0xf0ab
895	#define F367TER_TPS_ID_CELL_LO 0xf0ab00ff
896
897	/* TPS_ID_CELL2 */
898	#define R367TER_TPS_ID_CELL2 0xf0ac
899	#define F367TER_TPS_ID_CELL_HI 0xf0ac00ff
900
901	/* TPS_RCVD5_SET1 */
902	#define R367TER_TPS_RCVD5_SET1 0xf0ad
903	#define F367TER_TPS_NA 0xf0ad00fC
904	#define F367TER_TPS_SETFRAME 0xf0ad0003
905
906	/* TPS_SET2 */
907	#define R367TER_TPS_SET2 0xf0ae
908	#define F367TER_TPS_SETHIERMODE 0xf0ae0070
909	#define F367TER_TPS_SETCONST 0xf0ae0003
910
911	/* TPS_SET3 */
912	#define R367TER_TPS_SET3 0xf0af
913	#define F367TER_TPS_SETLPCODE 0xf0af0070
914	#define F367TER_TPS_SETHPCODE 0xf0af0007
915
916	/* TPS_CTL */
917	#define R367TER_TPS_CTL 0xf0b0
918	#define F367TER_TPS_IMM 0xf0b00004
919	#define F367TER_TPS_BCHDIS 0xf0b00002
920	#define F367TER_TPS_UPDDIS 0xf0b00001
921
922	/* CTL_FFTOSNUM */
923	#define R367TER_CTL_FFTOSNUM 0xf0b1
924	#define F367TER_SYMBOL_NUMBER 0xf0b1007f
925
926	/* TESTSELECT */
927	#define R367TER_TESTSELECT 0xf0b2
928	#define F367TER_TEST_SELECT 0xf0b2001f
929
930	/* MSC_REV */
931	#define R367TER_MSC_REV 0xf0b3
932	#define F367TER_REV_NUMBER 0xf0b300ff
933
934	/* PIR_CTL */
935	#define R367TER_PIR_CTL 0xf0b4
936	#define F367TER_FREEZE 0xf0b40001
937
938	/* SNR_CARRIER1 */
939	#define R367TER_SNR_CARRIER1 0xf0b5
940	#define F367TER_SNR_CARRIER_LO 0xf0b500ff
941
942	/* SNR_CARRIER2 */
943	#define R367TER_SNR_CARRIER2 0xf0b6
944	#define F367TER_MEAN 0xf0b600c0
945	#define F367TER_SNR_CARRIER_HI 0xf0b6001f
946
947	/* PPM_CPAMP */
948	#define R367TER_PPM_CPAMP 0xf0b7
949	#define F367TER_PPM_CPC 0xf0b700ff
950
951	/* TSM_AP0 */
952	#define R367TER_TSM_AP0 0xf0b8
953	#define F367TER_ADDRESS_BYTE_0 0xf0b800ff
954
955	/* TSM_AP1 */
956	#define R367TER_TSM_AP1 0xf0b9
957	#define F367TER_ADDRESS_BYTE_1 0xf0b900ff
958
959	/* TSM_AP2 */
960	#define R367TER_TSM_AP2 0xf0bA
961	#define F367TER_DATA_BYTE_0 0xf0ba00ff
962
963	/* TSM_AP3 */
964	#define R367TER_TSM_AP3 0xf0bB
965	#define F367TER_DATA_BYTE_1 0xf0bb00ff
966
967	/* TSM_AP4 */
968	#define R367TER_TSM_AP4 0xf0bC
969	#define F367TER_DATA_BYTE_2 0xf0bc00ff
970
971	/* TSM_AP5 */
972	#define R367TER_TSM_AP5 0xf0bD
973	#define F367TER_DATA_BYTE_3 0xf0bd00ff
974
975	/* TSM_AP6 */
976	#define R367TER_TSM_AP6 0xf0bE
977	#define F367TER_TSM_AP_6 0xf0be00ff
978
979	/* TSM_AP7 */
980	#define R367TER_TSM_AP7 0xf0bF
981	#define F367TER_MEM_SELECT_BYTE 0xf0bf00ff
982
983	/* TSTRES */
984	#define R367TER_TSTRES 0xf0c0
985	#define F367TER_FRES_DISPLAY 0xf0c00080
986	#define F367TER_FRES_FIFO_AD 0xf0c00020
987	#define F367TER_FRESRS 0xf0c00010
988	#define F367TER_FRESACS 0xf0c00008
989	#define F367TER_FRESFEC 0xf0c00004
990	#define F367TER_FRES_PRIF 0xf0c00002
991	#define F367TER_FRESCORE 0xf0c00001
992
993	/* ANACTRL */
994	#define R367TER_ANACTRL 0xf0c1
995	#define F367TER_BYPASS_XTAL 0xf0c10040
996	#define F367TER_BYPASS_PLLXN 0xf0c1000c
997	#define F367TER_DIS_PAD_OSC 0xf0c10002
998	#define F367TER_STDBY_PLLXN 0xf0c10001
999
1000	/* TSTBUS */
1001	#define R367TER_TSTBUS 0xf0c2
1002	#define F367TER_TS_BYTE_CLK_INV 0xf0c20080
1003	#define F367TER_CFG_IP 0xf0c20070
1004	#define F367TER_CFG_TST 0xf0c2000f
1005
1006	/* TSTRATE */
1007	#define R367TER_TSTRATE 0xf0c6
1008	#define F367TER_FORCEPHA 0xf0c60080
1009	#define F367TER_FNEWPHA 0xf0c60010
1010	#define F367TER_FROT90 0xf0c60008
1011	#define F367TER_FR 0xf0c60007
1012
1013	/* CONSTMODE */
1014	#define R367TER_CONSTMODE 0xf0cb
1015	#define F367TER_TST_PRIF 0xf0cb00e0
1016	#define F367TER_CAR_TYPE 0xf0cb0018
1017	#define F367TER_CONST_MODE 0xf0cb0003
1018
1019	/* CONSTCARR1 */
1020	#define R367TER_CONSTCARR1 0xf0cc
1021	#define F367TER_CONST_CARR_LO 0xf0cc00ff
1022
1023	/* CONSTCARR2 */
1024	#define R367TER_CONSTCARR2 0xf0cd
1025	#define F367TER_CONST_CARR_HI 0xf0cd001f
1026
1027	/* ICONSTEL */
1028	#define R367TER_ICONSTEL 0xf0ce
1029	#define F367TER_PICONSTEL 0xf0ce00ff
1030
1031	/* QCONSTEL */
1032	#define R367TER_QCONSTEL 0xf0cf
1033	#define F367TER_PQCONSTEL 0xf0cf00ff
1034
1035	/* TSTBISTRES0 */
1036	#define R367TER_TSTBISTRES0 0xf0d0
1037	#define F367TER_BEND_PPM 0xf0d00080
1038	#define F367TER_BBAD_PPM 0xf0d00040
1039	#define F367TER_BEND_FFTW 0xf0d00020
1040	#define F367TER_BBAD_FFTW 0xf0d00010
1041	#define F367TER_BEND_FFT_BUF 0xf0d00008
1042	#define F367TER_BBAD_FFT_BUF 0xf0d00004
1043	#define F367TER_BEND_SYR 0xf0d00002
1044	#define F367TER_BBAD_SYR 0xf0d00001
1045
1046	/* TSTBISTRES1 */
1047	#define R367TER_TSTBISTRES1 0xf0d1
1048	#define F367TER_BEND_CHC_CP 0xf0d10080
1049	#define F367TER_BBAD_CHC_CP 0xf0d10040
1050	#define F367TER_BEND_CHCI 0xf0d10020
1051	#define F367TER_BBAD_CHCI 0xf0d10010
1052	#define F367TER_BEND_BDI 0xf0d10008
1053	#define F367TER_BBAD_BDI 0xf0d10004
1054	#define F367TER_BEND_SDI 0xf0d10002
1055	#define F367TER_BBAD_SDI 0xf0d10001
1056
1057	/* TSTBISTRES2 */
1058	#define R367TER_TSTBISTRES2 0xf0d2
1059	#define F367TER_BEND_CHC_INC 0xf0d20080
1060	#define F367TER_BBAD_CHC_INC 0xf0d20040
1061	#define F367TER_BEND_CHC_SPP 0xf0d20020
1062	#define F367TER_BBAD_CHC_SPP 0xf0d20010
1063	#define F367TER_BEND_CHC_CPP 0xf0d20008
1064	#define F367TER_BBAD_CHC_CPP 0xf0d20004
1065	#define F367TER_BEND_CHC_SP 0xf0d20002
1066	#define F367TER_BBAD_CHC_SP 0xf0d20001
1067
1068	/* TSTBISTRES3 */
1069	#define R367TER_TSTBISTRES3 0xf0d3
1070	#define F367TER_BEND_QAM 0xf0d30080
1071	#define F367TER_BBAD_QAM 0xf0d30040
1072	#define F367TER_BEND_SFEC_VIT 0xf0d30020
1073	#define F367TER_BBAD_SFEC_VIT 0xf0d30010
1074	#define F367TER_BEND_SFEC_DLINE 0xf0d30008
1075	#define F367TER_BBAD_SFEC_DLINE 0xf0d30004
1076	#define F367TER_BEND_SFEC_HW 0xf0d30002
1077	#define F367TER_BBAD_SFEC_HW 0xf0d30001
1078
1079	/* RF_AGC1 */
1080	#define R367TER_RF_AGC1 0xf0d4
1081	#define F367TER_RF_AGC1_LEVEL_HI 0xf0d400ff
1082
1083	/* RF_AGC2 */
1084	#define R367TER_RF_AGC2 0xf0d5
1085	#define F367TER_REF_ADGP 0xf0d50080
1086	#define F367TER_STDBY_ADCGP 0xf0d50020
1087	#define F367TER_CHANNEL_SEL 0xf0d5001c
1088	#define F367TER_RF_AGC1_LEVEL_LO 0xf0d50003
1089
1090	/* ANADIGCTRL */
1091	#define R367TER_ANADIGCTRL 0xf0d7
1092	#define F367TER_SEL_CLKDEM 0xf0d70020
1093	#define F367TER_EN_BUFFER_Q 0xf0d70010
1094	#define F367TER_EN_BUFFER_I 0xf0d70008
1095	#define F367TER_ADC_RIS_EGDE 0xf0d70004
1096	#define F367TER_SGN_ADC 0xf0d70002
1097	#define F367TER_SEL_AD12_SYNC 0xf0d70001
1098
1099	/* PLLMDIV */
1100	#define R367TER_PLLMDIV 0xf0d8
1101	#define F367TER_PLL_MDIV 0xf0d800ff
1102
1103	/* PLLNDIV */
1104	#define R367TER_PLLNDIV 0xf0d9
1105	#define F367TER_PLL_NDIV 0xf0d900ff
1106
1107	/* PLLSETUP */
1108	#define R367TER_PLLSETUP 0xf0dA
1109	#define F367TER_PLL_PDIV 0xf0da0070
1110	#define F367TER_PLL_KDIV 0xf0da000f
1111
1112	/* DUAL_AD12 */
1113	#define R367TER_DUAL_AD12 0xf0dB
1114	#define F367TER_FS20M 0xf0db0020
1115	#define F367TER_FS50M 0xf0db0010
1116	#define F367TER_INMODe0 0xf0db0008
1117	#define F367TER_POFFQ 0xf0db0004
1118	#define F367TER_POFFI 0xf0db0002
1119	#define F367TER_INMODE1 0xf0db0001
1120
1121	/* TSTBIST */
1122	#define R367TER_TSTBIST 0xf0dC
1123	#define F367TER_TST_BYP_CLK 0xf0dc0080
1124	#define F367TER_TST_GCLKENA_STD 0xf0dc0040
1125	#define F367TER_TST_GCLKENA 0xf0dc0020
1126	#define F367TER_TST_MEMBIST 0xf0dc001f
1127
1128	/* PAD_COMP_CTRL */
1129	#define R367TER_PAD_COMP_CTRL 0xf0dD
1130	#define F367TER_COMPTQ 0xf0dd0010
1131	#define F367TER_COMPEN 0xf0dd0008
1132	#define F367TER_FREEZE2 0xf0dd0004
1133	#define F367TER_SLEEP_INHBT 0xf0dd0002
1134	#define F367TER_CHIP_SLEEP 0xf0dd0001
1135
1136	/* PAD_COMP_WR */
1137	#define R367TER_PAD_COMP_WR 0xf0de
1138	#define F367TER_WR_ASRC 0xf0de007f
1139
1140	/* PAD_COMP_RD */
1141	#define R367TER_PAD_COMP_RD 0xf0df
1142	#define F367TER_COMPOK 0xf0df0080
1143	#define F367TER_RD_ASRC 0xf0df007f
1144
1145	/* SYR_TARGET_FFTADJT_MSB */
1146	#define R367TER_SYR_TARGET_FFTADJT_MSB 0xf100
1147	#define F367TER_SYR_START 0xf1000080
1148	#define F367TER_SYR_TARGET_FFTADJ_HI 0xf100000f
1149
1150	/* SYR_TARGET_FFTADJT_LSB */
1151	#define R367TER_SYR_TARGET_FFTADJT_LSB 0xf101
1152	#define F367TER_SYR_TARGET_FFTADJ_LO 0xf10100ff
1153
1154	/* SYR_TARGET_CHCADJT_MSB */
1155	#define R367TER_SYR_TARGET_CHCADJT_MSB 0xf102
1156	#define F367TER_SYR_TARGET_CHCADJ_HI 0xf102000f
1157
1158	/* SYR_TARGET_CHCADJT_LSB */
1159	#define R367TER_SYR_TARGET_CHCADJT_LSB 0xf103
1160	#define F367TER_SYR_TARGET_CHCADJ_LO 0xf10300ff
1161
1162	/* SYR_FLAG */
1163	#define R367TER_SYR_FLAG 0xf104
1164	#define F367TER_TRIG_FLG1 0xf1040080
1165	#define F367TER_TRIG_FLG0 0xf1040040
1166	#define F367TER_FFT_FLG1 0xf1040008
1167	#define F367TER_FFT_FLG0 0xf1040004
1168	#define F367TER_CHC_FLG1 0xf1040002
1169	#define F367TER_CHC_FLG0 0xf1040001
1170
1171	/* CRL_TARGET1 */
1172	#define R367TER_CRL_TARGET1 0xf105
1173	#define F367TER_CRL_START 0xf1050080
1174	#define F367TER_CRL_TARGET_VHI 0xf105000f
1175
1176	/* CRL_TARGET2 */
1177	#define R367TER_CRL_TARGET2 0xf106
1178	#define F367TER_CRL_TARGET_HI 0xf10600ff
1179
1180	/* CRL_TARGET3 */
1181	#define R367TER_CRL_TARGET3 0xf107
1182	#define F367TER_CRL_TARGET_LO 0xf10700ff
1183
1184	/* CRL_TARGET4 */
1185	#define R367TER_CRL_TARGET4 0xf108
1186	#define F367TER_CRL_TARGET_VLO 0xf10800ff
1187
1188	/* CRL_FLAG */
1189	#define R367TER_CRL_FLAG 0xf109
1190	#define F367TER_CRL_FLAG1 0xf1090002
1191	#define F367TER_CRL_FLAG0 0xf1090001
1192
1193	/* TRL_TARGET1 */
1194	#define R367TER_TRL_TARGET1 0xf10a
1195	#define F367TER_TRL_TARGET_HI 0xf10a00ff
1196
1197	/* TRL_TARGET2 */
1198	#define R367TER_TRL_TARGET2 0xf10b
1199	#define F367TER_TRL_TARGET_LO 0xf10b00ff
1200
1201	/* TRL_CHC */
1202	#define R367TER_TRL_CHC 0xf10c
1203	#define F367TER_TRL_START 0xf10c0080
1204	#define F367TER_CHC_START 0xf10c0040
1205	#define F367TER_TRL_FLAG1 0xf10c0002
1206	#define F367TER_TRL_FLAG0 0xf10c0001
1207
1208	/* CHC_SNR_TARG */
1209	#define R367TER_CHC_SNR_TARG 0xf10d
1210	#define F367TER_CHC_SNR_TARGET 0xf10d00ff
1211
1212	/* TOP_TRACK */
1213	#define R367TER_TOP_TRACK 0xf10e
1214	#define F367TER_TOP_START 0xf10e0080
1215	#define F367TER_FIRST_FLAG 0xf10e0070
1216	#define F367TER_TOP_FLAG1 0xf10e0008
1217	#define F367TER_TOP_FLAG0 0xf10e0004
1218	#define F367TER_CHC_FLAG1 0xf10e0002
1219	#define F367TER_CHC_FLAG0 0xf10e0001
1220
1221	/* TRACKER_FREE1 */
1222	#define R367TER_TRACKER_FREE1 0xf10f
1223	#define F367TER_TRACKER_FREE_1 0xf10f00ff
1224
1225	/* ERROR_CRL1 */
1226	#define R367TER_ERROR_CRL1 0xf110
1227	#define F367TER_ERROR_CRL_VHI 0xf11000ff
1228
1229	/* ERROR_CRL2 */
1230	#define R367TER_ERROR_CRL2 0xf111
1231	#define F367TER_ERROR_CRL_HI 0xf11100ff
1232
1233	/* ERROR_CRL3 */
1234	#define R367TER_ERROR_CRL3 0xf112
1235	#define F367TER_ERROR_CRL_LOI 0xf11200ff
1236
1237	/* ERROR_CRL4 */
1238	#define R367TER_ERROR_CRL4 0xf113
1239	#define F367TER_ERROR_CRL_VLO 0xf11300ff
1240
1241	/* DEC_NCO1 */
1242	#define R367TER_DEC_NCO1 0xf114
1243	#define F367TER_DEC_NCO_VHI 0xf11400ff
1244
1245	/* DEC_NCO2 */
1246	#define R367TER_DEC_NCO2 0xf115
1247	#define F367TER_DEC_NCO_HI 0xf11500ff
1248
1249	/* DEC_NCO3 */
1250	#define R367TER_DEC_NCO3 0xf116
1251	#define F367TER_DEC_NCO_LO 0xf11600ff
1252
1253	/* SNR */
1254	#define R367TER_SNR 0xf117
1255	#define F367TER_SNRATIO 0xf11700ff
1256
1257	/* SYR_FFTADJ1 */
1258	#define R367TER_SYR_FFTADJ1 0xf118
1259	#define F367TER_SYR_FFTADJ_HI 0xf11800ff
1260
1261	/* SYR_FFTADJ2 */
1262	#define R367TER_SYR_FFTADJ2 0xf119
1263	#define F367TER_SYR_FFTADJ_LO 0xf11900ff
1264
1265	/* SYR_CHCADJ1 */
1266	#define R367TER_SYR_CHCADJ1 0xf11a
1267	#define F367TER_SYR_CHCADJ_HI 0xf11a00ff
1268
1269	/* SYR_CHCADJ2 */
1270	#define R367TER_SYR_CHCADJ2 0xf11b
1271	#define F367TER_SYR_CHCADJ_LO 0xf11b00ff
1272
1273	/* SYR_OFF */
1274	#define R367TER_SYR_OFF 0xf11c
1275	#define F367TER_SYR_OFFSET 0xf11c00ff
1276
1277	/* PPM_OFFSET1 */
1278	#define R367TER_PPM_OFFSET1 0xf11d
1279	#define F367TER_PPM_OFFSET_HI 0xf11d00ff
1280
1281	/* PPM_OFFSET2 */
1282	#define R367TER_PPM_OFFSET2 0xf11e
1283	#define F367TER_PPM_OFFSET_LO 0xf11e00ff
1284
1285	/* TRACKER_FREE2 */
1286	#define R367TER_TRACKER_FREE2 0xf11f
1287	#define F367TER_TRACKER_FREE_2 0xf11f00ff
1288
1289	/* DEBG_LT10 */
1290	#define R367TER_DEBG_LT10 0xf120
1291	#define F367TER_DEBUG_LT10 0xf12000ff
1292
1293	/* DEBG_LT11 */
1294	#define R367TER_DEBG_LT11 0xf121
1295	#define F367TER_DEBUG_LT11 0xf12100ff
1296
1297	/* DEBG_LT12 */
1298	#define R367TER_DEBG_LT12 0xf122
1299	#define F367TER_DEBUG_LT12 0xf12200ff
1300
1301	/* DEBG_LT13 */
1302	#define R367TER_DEBG_LT13 0xf123
1303	#define F367TER_DEBUG_LT13 0xf12300ff
1304
1305	/* DEBG_LT14 */
1306	#define R367TER_DEBG_LT14 0xf124
1307	#define F367TER_DEBUG_LT14 0xf12400ff
1308
1309	/* DEBG_LT15 */
1310	#define R367TER_DEBG_LT15 0xf125
1311	#define F367TER_DEBUG_LT15 0xf12500ff
1312
1313	/* DEBG_LT16 */
1314	#define R367TER_DEBG_LT16 0xf126
1315	#define F367TER_DEBUG_LT16 0xf12600ff
1316
1317	/* DEBG_LT17 */
1318	#define R367TER_DEBG_LT17 0xf127
1319	#define F367TER_DEBUG_LT17 0xf12700ff
1320
1321	/* DEBG_LT18 */
1322	#define R367TER_DEBG_LT18 0xf128
1323	#define F367TER_DEBUG_LT18 0xf12800ff
1324
1325	/* DEBG_LT19 */
1326	#define R367TER_DEBG_LT19 0xf129
1327	#define F367TER_DEBUG_LT19 0xf12900ff
1328
1329	/* DEBG_LT1a */
1330	#define R367TER_DEBG_LT1A 0xf12a
1331	#define F367TER_DEBUG_LT1A 0xf12a00ff
1332
1333	/* DEBG_LT1b */
1334	#define R367TER_DEBG_LT1B 0xf12b
1335	#define F367TER_DEBUG_LT1B 0xf12b00ff
1336
1337	/* DEBG_LT1c */
1338	#define R367TER_DEBG_LT1C 0xf12c
1339	#define F367TER_DEBUG_LT1C 0xf12c00ff
1340
1341	/* DEBG_LT1D */
1342	#define R367TER_DEBG_LT1D 0xf12d
1343	#define F367TER_DEBUG_LT1D 0xf12d00ff
1344
1345	/* DEBG_LT1E */
1346	#define R367TER_DEBG_LT1E 0xf12e
1347	#define F367TER_DEBUG_LT1E 0xf12e00ff
1348
1349	/* DEBG_LT1F */
1350	#define R367TER_DEBG_LT1F 0xf12f
1351	#define F367TER_DEBUG_LT1F 0xf12f00ff
1352
1353	/* RCCFGH */
1354	#define R367TER_RCCFGH 0xf200
1355	#define F367TER_TSRCFIFO_DVBCI 0xf2000080
1356	#define F367TER_TSRCFIFO_SERIAL 0xf2000040
1357	#define F367TER_TSRCFIFO_DISABLE 0xf2000020
1358	#define F367TER_TSFIFO_2TORC 0xf2000010
1359	#define F367TER_TSRCFIFO_HSGNLOUT 0xf2000008
1360	#define F367TER_TSRCFIFO_ERRMODE 0xf2000006
1361	#define F367TER_RCCFGH_0 0xf2000001
1362
1363	/* RCCFGM */
1364	#define R367TER_RCCFGM 0xf201
1365	#define F367TER_TSRCFIFO_MANSPEED 0xf20100c0
1366	#define F367TER_TSRCFIFO_PERMDATA 0xf2010020
1367	#define F367TER_TSRCFIFO_NONEWSGNL 0xf2010010
1368	#define F367TER_RCBYTE_OVERSAMPLING 0xf201000e
1369	#define F367TER_TSRCFIFO_INVDATA 0xf2010001
1370
1371	/* RCCFGL */
1372	#define R367TER_RCCFGL 0xf202
1373	#define F367TER_TSRCFIFO_BCLKDEL1cK 0xf20200c0
1374	#define F367TER_RCCFGL_5 0xf2020020
1375	#define F367TER_TSRCFIFO_DUTY50 0xf2020010
1376	#define F367TER_TSRCFIFO_NSGNL2dATA 0xf2020008
1377	#define F367TER_TSRCFIFO_DISSERMUX 0xf2020004
1378	#define F367TER_RCCFGL_1 0xf2020002
1379	#define F367TER_TSRCFIFO_STOPCKDIS 0xf2020001
1380
1381	/* RCINSDELH */
1382	#define R367TER_RCINSDELH 0xf203
1383	#define F367TER_TSRCDEL_SYNCBYTE 0xf2030080
1384	#define F367TER_TSRCDEL_XXHEADER 0xf2030040
1385	#define F367TER_TSRCDEL_BBHEADER 0xf2030020
1386	#define F367TER_TSRCDEL_DATAFIELD 0xf2030010
1387	#define F367TER_TSRCINSDEL_ISCR 0xf2030008
1388	#define F367TER_TSRCINSDEL_NPD 0xf2030004
1389	#define F367TER_TSRCINSDEL_RSPARITY 0xf2030002
1390	#define F367TER_TSRCINSDEL_CRC8 0xf2030001
1391
1392	/* RCINSDELM */
1393	#define R367TER_RCINSDELM 0xf204
1394	#define F367TER_TSRCINS_BBPADDING 0xf2040080
1395	#define F367TER_TSRCINS_BCHFEC 0xf2040040
1396	#define F367TER_TSRCINS_LDPCFEC 0xf2040020
1397	#define F367TER_TSRCINS_EMODCOD 0xf2040010
1398	#define F367TER_TSRCINS_TOKEN 0xf2040008
1399	#define F367TER_TSRCINS_XXXERR 0xf2040004
1400	#define F367TER_TSRCINS_MATYPE 0xf2040002
1401	#define F367TER_TSRCINS_UPL 0xf2040001
1402
1403	/* RCINSDELL */
1404	#define R367TER_RCINSDELL 0xf205
1405	#define F367TER_TSRCINS_DFL 0xf2050080
1406	#define F367TER_TSRCINS_SYNCD 0xf2050040
1407	#define F367TER_TSRCINS_BLOCLEN 0xf2050020
1408	#define F367TER_TSRCINS_SIGPCOUNT 0xf2050010
1409	#define F367TER_TSRCINS_FIFO 0xf2050008
1410	#define F367TER_TSRCINS_REALPACK 0xf2050004
1411	#define F367TER_TSRCINS_TSCONFIG 0xf2050002
1412	#define F367TER_TSRCINS_LATENCY 0xf2050001
1413
1414	/* RCSTATUS */
1415	#define R367TER_RCSTATUS 0xf206
1416	#define F367TER_TSRCFIFO_LINEOK 0xf2060080
1417	#define F367TER_TSRCFIFO_ERROR 0xf2060040
1418	#define F367TER_TSRCFIFO_DATA7 0xf2060020
1419	#define F367TER_RCSTATUS_4 0xf2060010
1420	#define F367TER_TSRCFIFO_DEMODSEL 0xf2060008
1421	#define F367TER_TSRC1FIFOSPEED_STORE 0xf2060004
1422	#define F367TER_RCSTATUS_1 0xf2060002
1423	#define F367TER_TSRCSERIAL_IMPOSSIBLE 0xf2060001
1424
1425	/* RCSPEED */
1426	#define R367TER_RCSPEED 0xf207
1427	#define F367TER_TSRCFIFO_OUTSPEED 0xf20700ff
1428
1429	/* RCDEBUGM */
1430	#define R367TER_RCDEBUGM 0xf208
1431	#define F367TER_SD_UNSYNC 0xf2080080
1432	#define F367TER_ULFLOCK_DETECTM 0xf2080040
1433	#define F367TER_SUL_SELECTOS 0xf2080020
1434	#define F367TER_DILUL_NOSCRBLE 0xf2080010
1435	#define F367TER_NUL_SCRB 0xf2080008
1436	#define F367TER_UL_SCRB 0xf2080004
1437	#define F367TER_SCRAULBAD 0xf2080002
1438	#define F367TER_SCRAUL_UNSYNC 0xf2080001
1439
1440	/* RCDEBUGL */
1441	#define R367TER_RCDEBUGL 0xf209
1442	#define F367TER_RS_ERR 0xf2090080
1443	#define F367TER_LLFLOCK_DETECTM 0xf2090040
1444	#define F367TER_NOT_SUL_SELECTOS 0xf2090020
1445	#define F367TER_DILLL_NOSCRBLE 0xf2090010
1446	#define F367TER_NLL_SCRB 0xf2090008
1447	#define F367TER_LL_SCRB 0xf2090004
1448	#define F367TER_SCRALLBAD 0xf2090002
1449	#define F367TER_SCRALL_UNSYNC 0xf2090001
1450
1451	/* RCOBSCFG */
1452	#define R367TER_RCOBSCFG 0xf20a
1453	#define F367TER_TSRCFIFO_OBSCFG 0xf20a00ff
1454
1455	/* RCOBSM */
1456	#define R367TER_RCOBSM 0xf20b
1457	#define F367TER_TSRCFIFO_OBSDATA_HI 0xf20b00ff
1458
1459	/* RCOBSL */
1460	#define R367TER_RCOBSL 0xf20c
1461	#define F367TER_TSRCFIFO_OBSDATA_LO 0xf20c00ff
1462
1463	/* RCFECSPY */
1464	#define R367TER_RCFECSPY 0xf210
1465	#define F367TER_SPYRC_ENABLE 0xf2100080
1466	#define F367TER_RCNO_SYNCBYTE 0xf2100040
1467	#define F367TER_RCSERIAL_MODE 0xf2100020
1468	#define F367TER_RCUNUSUAL_PACKET 0xf2100010
1469	#define F367TER_BERRCMETER_DATAMODE 0xf210000c
1470	#define F367TER_BERRCMETER_LMODE 0xf2100002
1471	#define F367TER_BERRCMETER_RESET 0xf2100001
1472
1473	/* RCFSPYCFG */
1474	#define R367TER_RCFSPYCFG 0xf211
1475	#define F367TER_FECSPYRC_INPUT 0xf21100c0
1476	#define F367TER_RCRST_ON_ERROR 0xf2110020
1477	#define F367TER_RCONE_SHOT 0xf2110010
1478	#define F367TER_RCI2C_MODE 0xf211000c
1479	#define F367TER_SPYRC_HSTERESIS 0xf2110003
1480
1481	/* RCFSPYDATA */
1482	#define R367TER_RCFSPYDATA 0xf212
1483	#define F367TER_SPYRC_STUFFING 0xf2120080
1484	#define F367TER_RCNOERR_PKTJITTER 0xf2120040
1485	#define F367TER_SPYRC_CNULLPKT 0xf2120020
1486	#define F367TER_SPYRC_OUTDATA_MODE 0xf212001f
1487
1488	/* RCFSPYOUT */
1489	#define R367TER_RCFSPYOUT 0xf213
1490	#define F367TER_FSPYRC_DIRECT 0xf2130080
1491	#define F367TER_RCFSPYOUT_6 0xf2130040
1492	#define F367TER_SPYRC_OUTDATA_BUS 0xf2130038
1493	#define F367TER_RCSTUFF_MODE 0xf2130007
1494
1495	/* RCFSTATUS */
1496	#define R367TER_RCFSTATUS 0xf214
1497	#define F367TER_SPYRC_ENDSIM 0xf2140080
1498	#define F367TER_RCVALID_SIM 0xf2140040
1499	#define F367TER_RCFOUND_SIGNAL 0xf2140020
1500	#define F367TER_RCDSS_SYNCBYTE 0xf2140010
1501	#define F367TER_RCRESULT_STATE 0xf214000f
1502
1503	/* RCFGOODPACK */
1504	#define R367TER_RCFGOODPACK 0xf215
1505	#define F367TER_RCGOOD_PACKET 0xf21500ff
1506
1507	/* RCFPACKCNT */
1508	#define R367TER_RCFPACKCNT 0xf216
1509	#define F367TER_RCPACKET_COUNTER 0xf21600ff
1510
1511	/* RCFSPYMISC */
1512	#define R367TER_RCFSPYMISC 0xf217
1513	#define F367TER_RCLABEL_COUNTER 0xf21700ff
1514
1515	/* RCFBERCPT4 */
1516	#define R367TER_RCFBERCPT4 0xf218
1517	#define F367TER_FBERRCMETER_CPT_MMMMSB 0xf21800ff
1518
1519	/* RCFBERCPT3 */
1520	#define R367TER_RCFBERCPT3 0xf219
1521	#define F367TER_FBERRCMETER_CPT_MMMSB 0xf21900ff
1522
1523	/* RCFBERCPT2 */
1524	#define R367TER_RCFBERCPT2 0xf21a
1525	#define F367TER_FBERRCMETER_CPT_MMSB 0xf21a00ff
1526
1527	/* RCFBERCPT1 */
1528	#define R367TER_RCFBERCPT1 0xf21b
1529	#define F367TER_FBERRCMETER_CPT_MSB 0xf21b00ff
1530
1531	/* RCFBERCPT0 */
1532	#define R367TER_RCFBERCPT0 0xf21c
1533	#define F367TER_FBERRCMETER_CPT_LSB 0xf21c00ff
1534
1535	/* RCFBERERR2 */
1536	#define R367TER_RCFBERERR2 0xf21d
1537	#define F367TER_FBERRCMETER_ERR_HI 0xf21d00ff
1538
1539	/* RCFBERERR1 */
1540	#define R367TER_RCFBERERR1 0xf21e
1541	#define F367TER_FBERRCMETER_ERR 0xf21e00ff
1542
1543	/* RCFBERERR0 */
1544	#define R367TER_RCFBERERR0 0xf21f
1545	#define F367TER_FBERRCMETER_ERR_LO 0xf21f00ff
1546
1547	/* RCFSTATESM */
1548	#define R367TER_RCFSTATESM 0xf220
1549	#define F367TER_RCRSTATE_F 0xf2200080
1550	#define F367TER_RCRSTATE_E 0xf2200040
1551	#define F367TER_RCRSTATE_D 0xf2200020
1552	#define F367TER_RCRSTATE_C 0xf2200010
1553	#define F367TER_RCRSTATE_B 0xf2200008
1554	#define F367TER_RCRSTATE_A 0xf2200004
1555	#define F367TER_RCRSTATE_9 0xf2200002
1556	#define F367TER_RCRSTATE_8 0xf2200001
1557
1558	/* RCFSTATESL */
1559	#define R367TER_RCFSTATESL 0xf221
1560	#define F367TER_RCRSTATE_7 0xf2210080
1561	#define F367TER_RCRSTATE_6 0xf2210040
1562	#define F367TER_RCRSTATE_5 0xf2210020
1563	#define F367TER_RCRSTATE_4 0xf2210010
1564	#define F367TER_RCRSTATE_3 0xf2210008
1565	#define F367TER_RCRSTATE_2 0xf2210004
1566	#define F367TER_RCRSTATE_1 0xf2210002
1567	#define F367TER_RCRSTATE_0 0xf2210001
1568
1569	/* RCFSPYBER */
1570	#define R367TER_RCFSPYBER 0xf222
1571	#define F367TER_RCFSPYBER_7 0xf2220080
1572	#define F367TER_SPYRCOBS_XORREAD 0xf2220040
1573	#define F367TER_FSPYRCBER_OBSMODE 0xf2220020
1574	#define F367TER_FSPYRCBER_SYNCBYT 0xf2220010
1575	#define F367TER_FSPYRCBER_UNSYNC 0xf2220008
1576	#define F367TER_FSPYRCBER_CTIME 0xf2220007
1577
1578	/* RCFSPYDISTM */
1579	#define R367TER_RCFSPYDISTM 0xf223
1580	#define F367TER_RCPKTTIME_DISTANCE_HI 0xf22300ff
1581
1582	/* RCFSPYDISTL */
1583	#define R367TER_RCFSPYDISTL 0xf224
1584	#define F367TER_RCPKTTIME_DISTANCE_LO 0xf22400ff
1585
1586	/* RCFSPYOBS7 */
1587	#define R367TER_RCFSPYOBS7 0xf228
1588	#define F367TER_RCSPYOBS_SPYFAIL 0xf2280080
1589	#define F367TER_RCSPYOBS_SPYFAIL1 0xf2280040
1590	#define F367TER_RCSPYOBS_ERROR 0xf2280020
1591	#define F367TER_RCSPYOBS_STROUT 0xf2280010
1592	#define F367TER_RCSPYOBS_RESULTSTATE1 0xf228000f
1593
1594	/* RCFSPYOBS6 */
1595	#define R367TER_RCFSPYOBS6 0xf229
1596	#define F367TER_RCSPYOBS_RESULTSTATe0 0xf22900f0
1597	#define F367TER_RCSPYOBS_RESULTSTATEM1 0xf229000f
1598
1599	/* RCFSPYOBS5 */
1600	#define R367TER_RCFSPYOBS5 0xf22a
1601	#define F367TER_RCSPYOBS_BYTEOFPACKET1 0xf22a00ff
1602
1603	/* RCFSPYOBS4 */
1604	#define R367TER_RCFSPYOBS4 0xf22b
1605	#define F367TER_RCSPYOBS_BYTEVALUE1 0xf22b00ff
1606
1607	/* RCFSPYOBS3 */
1608	#define R367TER_RCFSPYOBS3 0xf22c
1609	#define F367TER_RCSPYOBS_DATA1 0xf22c00ff
1610
1611	/* RCFSPYOBS2 */
1612	#define R367TER_RCFSPYOBS2 0xf22d
1613	#define F367TER_RCSPYOBS_DATa0 0xf22d00ff
1614
1615	/* RCFSPYOBS1 */
1616	#define R367TER_RCFSPYOBS1 0xf22e
1617	#define F367TER_RCSPYOBS_DATAM1 0xf22e00ff
1618
1619	/* RCFSPYOBS0 */
1620	#define R367TER_RCFSPYOBS0 0xf22f
1621	#define F367TER_RCSPYOBS_DATAM2 0xf22f00ff
1622
1623	/* TSGENERAL */
1624	#define R367TER_TSGENERAL 0xf230
1625	#define F367TER_TSGENERAL_7 0xf2300080
1626	#define F367TER_TSGENERAL_6 0xf2300040
1627	#define F367TER_TSFIFO_BCLK1aLL 0xf2300020
1628	#define F367TER_TSGENERAL_4 0xf2300010
1629	#define F367TER_MUXSTREAM_OUTMODE 0xf2300008
1630	#define F367TER_TSFIFO_PERMPARAL 0xf2300006
1631	#define F367TER_RST_REEDSOLO 0xf2300001
1632
1633	/* RC1SPEED */
1634	#define R367TER_RC1SPEED 0xf231
1635	#define F367TER_TSRCFIFO1_OUTSPEED 0xf23100ff
1636
1637	/* TSGSTATUS */
1638	#define R367TER_TSGSTATUS 0xf232
1639	#define F367TER_TSGSTATUS_7 0xf2320080
1640	#define F367TER_TSGSTATUS_6 0xf2320040
1641	#define F367TER_RSMEM_FULL 0xf2320020
1642	#define F367TER_RS_MULTCALC 0xf2320010
1643	#define F367TER_RSIN_OVERTIME 0xf2320008
1644	#define F367TER_TSFIFO3_DEMODSEL 0xf2320004
1645	#define F367TER_TSFIFO2_DEMODSEL 0xf2320002
1646	#define F367TER_TSFIFO1_DEMODSEL 0xf2320001
1647
1648
1649	/* FECM */
1650	#define R367TER_FECM 0xf233
1651	#define F367TER_DSS_DVB 0xf2330080
1652	#define F367TER_DEMOD_BYPASS 0xf2330040
1653	#define F367TER_CMP_SLOWMODE 0xf2330020
1654	#define F367TER_DSS_SRCH 0xf2330010
1655	#define F367TER_FECM_3 0xf2330008
1656	#define F367TER_DIFF_MODEVIT 0xf2330004
1657	#define F367TER_SYNCVIT 0xf2330002
1658	#define F367TER_I2CSYM 0xf2330001
1659
1660	/* VTH12 */
1661	#define R367TER_VTH12 0xf234
1662	#define F367TER_VTH_12 0xf23400ff
1663
1664	/* VTH23 */
1665	#define R367TER_VTH23 0xf235
1666	#define F367TER_VTH_23 0xf23500ff
1667
1668	/* VTH34 */
1669	#define R367TER_VTH34 0xf236
1670	#define F367TER_VTH_34 0xf23600ff
1671
1672	/* VTH56 */
1673	#define R367TER_VTH56 0xf237
1674	#define F367TER_VTH_56 0xf23700ff
1675
1676	/* VTH67 */
1677	#define R367TER_VTH67 0xf238
1678	#define F367TER_VTH_67 0xf23800ff
1679
1680	/* VTH78 */
1681	#define R367TER_VTH78 0xf239
1682	#define F367TER_VTH_78 0xf23900ff
1683
1684	/* VITCURPUN */
1685	#define R367TER_VITCURPUN 0xf23a
1686	#define F367TER_VIT_MAPPING 0xf23a00e0
1687	#define F367TER_VIT_CURPUN 0xf23a001f
1688
1689	/* VERROR */
1690	#define R367TER_VERROR 0xf23b
1691	#define F367TER_REGERR_VIT 0xf23b00ff
1692
1693	/* PRVIT */
1694	#define R367TER_PRVIT 0xf23c
1695	#define F367TER_PRVIT_7 0xf23c0080
1696	#define F367TER_DIS_VTHLOCK 0xf23c0040
1697	#define F367TER_E7_8VIT 0xf23c0020
1698	#define F367TER_E6_7VIT 0xf23c0010
1699	#define F367TER_E5_6VIT 0xf23c0008
1700	#define F367TER_E3_4VIT 0xf23c0004
1701	#define F367TER_E2_3VIT 0xf23c0002
1702	#define F367TER_E1_2VIT 0xf23c0001
1703
1704	/* VAVSRVIT */
1705	#define R367TER_VAVSRVIT 0xf23d
1706	#define F367TER_AMVIT 0xf23d0080
1707	#define F367TER_FROZENVIT 0xf23d0040
1708	#define F367TER_SNVIT 0xf23d0030
1709	#define F367TER_TOVVIT 0xf23d000c
1710	#define F367TER_HYPVIT 0xf23d0003
1711
1712	/* VSTATUSVIT */
1713	#define R367TER_VSTATUSVIT 0xf23e
1714	#define F367TER_VITERBI_ON 0xf23e0080
1715	#define F367TER_END_LOOPVIT 0xf23e0040
1716	#define F367TER_VITERBI_DEPRF 0xf23e0020
1717	#define F367TER_PRFVIT 0xf23e0010
1718	#define F367TER_LOCKEDVIT 0xf23e0008
1719	#define F367TER_VITERBI_DELOCK 0xf23e0004
1720	#define F367TER_VIT_DEMODSEL 0xf23e0002
1721	#define F367TER_VITERBI_COMPOUT 0xf23e0001
1722
1723	/* VTHINUSE */
1724	#define R367TER_VTHINUSE 0xf23f
1725	#define F367TER_VIT_INUSE 0xf23f00ff
1726
1727	/* KDIV12 */
1728	#define R367TER_KDIV12 0xf240
1729	#define F367TER_KDIV12_MANUAL 0xf2400080
1730	#define F367TER_K_DIVIDER_12 0xf240007f
1731
1732	/* KDIV23 */
1733	#define R367TER_KDIV23 0xf241
1734	#define F367TER_KDIV23_MANUAL 0xf2410080
1735	#define F367TER_K_DIVIDER_23 0xf241007f
1736
1737	/* KDIV34 */
1738	#define R367TER_KDIV34 0xf242
1739	#define F367TER_KDIV34_MANUAL 0xf2420080
1740	#define F367TER_K_DIVIDER_34 0xf242007f
1741
1742	/* KDIV56 */
1743	#define R367TER_KDIV56 0xf243
1744	#define F367TER_KDIV56_MANUAL 0xf2430080
1745	#define F367TER_K_DIVIDER_56 0xf243007f
1746
1747	/* KDIV67 */
1748	#define R367TER_KDIV67 0xf244
1749	#define F367TER_KDIV67_MANUAL 0xf2440080
1750	#define F367TER_K_DIVIDER_67 0xf244007f
1751
1752	/* KDIV78 */
1753	#define R367TER_KDIV78 0xf245
1754	#define F367TER_KDIV78_MANUAL 0xf2450080
1755	#define F367TER_K_DIVIDER_78 0xf245007f
1756
1757	/* SIGPOWER */
1758	#define R367TER_SIGPOWER 0xf246
1759	#define F367TER_SIGPOWER_MANUAL 0xf2460080
1760	#define F367TER_SIG_POWER 0xf246007f
1761
1762	/* DEMAPVIT */
1763	#define R367TER_DEMAPVIT 0xf247
1764	#define F367TER_DEMAPVIT_7 0xf2470080
1765	#define F367TER_K_DIVIDER_VIT 0xf247007f
1766
1767	/* VITSCALE */
1768	#define R367TER_VITSCALE 0xf248
1769	#define F367TER_NVTH_NOSRANGE 0xf2480080
1770	#define F367TER_VERROR_MAXMODE 0xf2480040
1771	#define F367TER_KDIV_MODE 0xf2480030
1772	#define F367TER_NSLOWSN_LOCKED 0xf2480008
1773	#define F367TER_DELOCK_PRFLOSS 0xf2480004
1774	#define F367TER_DIS_RSFLOCK 0xf2480002
1775	#define F367TER_VITSCALE_0 0xf2480001
1776
1777	/* FFEC1PRG */
1778	#define R367TER_FFEC1PRG 0xf249
1779	#define F367TER_FDSS_DVB 0xf2490080
1780	#define F367TER_FDSS_SRCH 0xf2490040
1781	#define F367TER_FFECPROG_5 0xf2490020
1782	#define F367TER_FFECPROG_4 0xf2490010
1783	#define F367TER_FFECPROG_3 0xf2490008
1784	#define F367TER_FFECPROG_2 0xf2490004
1785	#define F367TER_FTS1_DISABLE 0xf2490002
1786	#define F367TER_FTS2_DISABLE 0xf2490001
1787
1788	/* FVITCURPUN */
1789	#define R367TER_FVITCURPUN 0xf24a
1790	#define F367TER_FVIT_MAPPING 0xf24a00e0
1791	#define F367TER_FVIT_CURPUN 0xf24a001f
1792
1793	/* FVERROR */
1794	#define R367TER_FVERROR 0xf24b
1795	#define F367TER_FREGERR_VIT 0xf24b00ff
1796
1797	/* FVSTATUSVIT */
1798	#define R367TER_FVSTATUSVIT 0xf24c
1799	#define F367TER_FVITERBI_ON 0xf24c0080
1800	#define F367TER_F1END_LOOPVIT 0xf24c0040
1801	#define F367TER_FVITERBI_DEPRF 0xf24c0020
1802	#define F367TER_FPRFVIT 0xf24c0010
1803	#define F367TER_FLOCKEDVIT 0xf24c0008
1804	#define F367TER_FVITERBI_DELOCK 0xf24c0004
1805	#define F367TER_FVIT_DEMODSEL 0xf24c0002
1806	#define F367TER_FVITERBI_COMPOUT 0xf24c0001
1807
1808	/* DEBUG_LT1 */
1809	#define R367TER_DEBUG_LT1 0xf24d
1810	#define F367TER_DBG_LT1 0xf24d00ff
1811
1812	/* DEBUG_LT2 */
1813	#define R367TER_DEBUG_LT2 0xf24e
1814	#define F367TER_DBG_LT2 0xf24e00ff
1815
1816	/* DEBUG_LT3 */
1817	#define R367TER_DEBUG_LT3 0xf24f
1818	#define F367TER_DBG_LT3 0xf24f00ff
1819
1820	/* TSTSFMET */
1821	#define R367TER_TSTSFMET 0xf250
1822	#define F367TER_TSTSFEC_METRIQUES 0xf25000ff
1823
1824	/* SELOUT */
1825	#define R367TER_SELOUT 0xf252
1826	#define F367TER_EN_SYNC 0xf2520080
1827	#define F367TER_EN_TBUSDEMAP 0xf2520040
1828	#define F367TER_SELOUT_5 0xf2520020
1829	#define F367TER_SELOUT_4 0xf2520010
1830	#define F367TER_TSTSYNCHRO_MODE 0xf2520002
1831
1832	/* TSYNC */
1833	#define R367TER_TSYNC 0xf253
1834	#define F367TER_CURPUN_INCMODE 0xf2530080
1835	#define F367TER_CERR_TSTMODE 0xf2530040
1836	#define F367TER_SHIFTSOF_MODE 0xf2530030
1837	#define F367TER_SLOWPHA_MODE 0xf2530008
1838	#define F367TER_PXX_BYPALL 0xf2530004
1839	#define F367TER_FROTA45_FIRST 0xf2530002
1840	#define F367TER_TST_BCHERROR 0xf2530001
1841
1842	/* TSTERR */
1843	#define R367TER_TSTERR 0xf254
1844	#define F367TER_TST_LONGPKT 0xf2540080
1845	#define F367TER_TST_ISSYION 0xf2540040
1846	#define F367TER_TST_NPDON 0xf2540020
1847	#define F367TER_TSTERR_4 0xf2540010
1848	#define F367TER_TRACEBACK_MODE 0xf2540008
1849	#define F367TER_TST_RSPARITY 0xf2540004
1850	#define F367TER_METRIQUE_MODE 0xf2540003
1851
1852	/* TSFSYNC */
1853	#define R367TER_TSFSYNC 0xf255
1854	#define F367TER_EN_SFECSYNC 0xf2550080
1855	#define F367TER_EN_SFECDEMAP 0xf2550040
1856	#define F367TER_SFCERR_TSTMODE 0xf2550020
1857	#define F367TER_SFECPXX_BYPALL 0xf2550010
1858	#define F367TER_SFECTSTSYNCHRO_MODE 0xf255000f
1859
1860	/* TSTSFERR */
1861	#define R367TER_TSTSFERR 0xf256
1862	#define F367TER_TSTSTERR_7 0xf2560080
1863	#define F367TER_TSTSTERR_6 0xf2560040
1864	#define F367TER_TSTSTERR_5 0xf2560020
1865	#define F367TER_TSTSTERR_4 0xf2560010
1866	#define F367TER_SFECTRACEBACK_MODE 0xf2560008
1867	#define F367TER_SFEC_NCONVPROG 0xf2560004
1868	#define F367TER_SFECMETRIQUE_MODE 0xf2560003
1869
1870	/* TSTTSSF1 */
1871	#define R367TER_TSTTSSF1 0xf258
1872	#define F367TER_TSTERSSF 0xf2580080
1873	#define F367TER_TSTTSSFEN 0xf2580040
1874	#define F367TER_SFEC_OUTMODE 0xf2580030
1875	#define F367TER_XLSF_NOFTHRESHOLD 0xf2580008
1876	#define F367TER_TSTTSSF_STACKSEL 0xf2580007
1877
1878	/* TSTTSSF2 */
1879	#define R367TER_TSTTSSF2 0xf259
1880	#define F367TER_DILSF_DBBHEADER 0xf2590080
1881	#define F367TER_TSTTSSF_DISBUG 0xf2590040
1882	#define F367TER_TSTTSSF_NOBADSTART 0xf2590020
1883	#define F367TER_TSTTSSF_SELECT 0xf259001f
1884
1885	/* TSTTSSF3 */
1886	#define R367TER_TSTTSSF3 0xf25a
1887	#define F367TER_TSTTSSF3_7 0xf25a0080
1888	#define F367TER_TSTTSSF3_6 0xf25a0040
1889	#define F367TER_TSTTSSF3_5 0xf25a0020
1890	#define F367TER_TSTTSSF3_4 0xf25a0010
1891	#define F367TER_TSTTSSF3_3 0xf25a0008
1892	#define F367TER_TSTTSSF3_2 0xf25a0004
1893	#define F367TER_TSTTSSF3_1 0xf25a0002
1894	#define F367TER_DISSF_CLKENABLE 0xf25a0001
1895
1896	/* TSTTS1 */
1897	#define R367TER_TSTTS1 0xf25c
1898	#define F367TER_TSTERS 0xf25c0080
1899	#define F367TER_TSFIFO_DSSSYNCB 0xf25c0040
1900	#define F367TER_TSTTS_FSPYBEFRS 0xf25c0020
1901	#define F367TER_NFORCE_SYNCBYTE 0xf25c0010
1902	#define F367TER_XL_NOFTHRESHOLD 0xf25c0008
1903	#define F367TER_TSTTS_FRFORCEPKT 0xf25c0004
1904	#define F367TER_DESCR_NOTAUTO 0xf25c0002
1905	#define F367TER_TSTTSEN 0xf25c0001
1906
1907	/* TSTTS2 */
1908	#define R367TER_TSTTS2 0xf25d
1909	#define F367TER_DIL_DBBHEADER 0xf25d0080
1910	#define F367TER_TSTTS_NOBADXXX 0xf25d0040
1911	#define F367TER_TSFIFO_DELSPEEDUP 0xf25d0020
1912	#define F367TER_TSTTS_SELECT 0xf25d001f
1913
1914	/* TSTTS3 */
1915	#define R367TER_TSTTS3 0xf25e
1916	#define F367TER_TSTTS_NOPKTGAIN 0xf25e0080
1917	#define F367TER_TSTTS_NOPKTENE 0xf25e0040
1918	#define F367TER_TSTTS_ISOLATION 0xf25e0020
1919	#define F367TER_TSTTS_DISBUG 0xf25e0010
1920	#define F367TER_TSTTS_NOBADSTART 0xf25e0008
1921	#define F367TER_TSTTS_STACKSEL 0xf25e0007
1922
1923	/* TSTTS4 */
1924	#define R367TER_TSTTS4 0xf25f
1925	#define F367TER_TSTTS4_7 0xf25f0080
1926	#define F367TER_TSTTS4_6 0xf25f0040
1927	#define F367TER_TSTTS4_5 0xf25f0020
1928	#define F367TER_TSTTS_DISDSTATE 0xf25f0010
1929	#define F367TER_TSTTS_FASTNOSYNC 0xf25f0008
1930	#define F367TER_EXT_FECSPYIN 0xf25f0004
1931	#define F367TER_TSTTS_NODPZERO 0xf25f0002
1932	#define F367TER_TSTTS_NODIV3 0xf25f0001
1933
1934	/* TSTTSRC */
1935	#define R367TER_TSTTSRC 0xf26c
1936	#define F367TER_TSTTSRC_7 0xf26c0080
1937	#define F367TER_TSRCFIFO_DSSSYNCB 0xf26c0040
1938	#define F367TER_TSRCFIFO_DPUNACTIVE 0xf26c0020
1939	#define F367TER_TSRCFIFO_DELSPEEDUP 0xf26c0010
1940	#define F367TER_TSTTSRC_NODIV3 0xf26c0008
1941	#define F367TER_TSTTSRC_FRFORCEPKT 0xf26c0004
1942	#define F367TER_SAT25_SDDORIGINE 0xf26c0002
1943	#define F367TER_TSTTSRC_INACTIVE 0xf26c0001
1944
1945	/* TSTTSRS */
1946	#define R367TER_TSTTSRS 0xf26d
1947	#define F367TER_TSTTSRS_7 0xf26d0080
1948	#define F367TER_TSTTSRS_6 0xf26d0040
1949	#define F367TER_TSTTSRS_5 0xf26d0020
1950	#define F367TER_TSTTSRS_4 0xf26d0010
1951	#define F367TER_TSTTSRS_3 0xf26d0008
1952	#define F367TER_TSTTSRS_2 0xf26d0004
1953	#define F367TER_TSTRS_DISRS2 0xf26d0002
1954	#define F367TER_TSTRS_DISRS1 0xf26d0001
1955
1956	/* TSSTATEM */
1957	#define R367TER_TSSTATEM 0xf270
1958	#define F367TER_TSDIL_ON 0xf2700080
1959	#define F367TER_TSSKIPRS_ON 0xf2700040
1960	#define F367TER_TSRS_ON 0xf2700020
1961	#define F367TER_TSDESCRAMB_ON 0xf2700010
1962	#define F367TER_TSFRAME_MODE 0xf2700008
1963	#define F367TER_TS_DISABLE 0xf2700004
1964	#define F367TER_TSACM_MODE 0xf2700002
1965	#define F367TER_TSOUT_NOSYNC 0xf2700001
1966
1967	/* TSSTATEL */
1968	#define R367TER_TSSTATEL 0xf271
1969	#define F367TER_TSNOSYNCBYTE 0xf2710080
1970	#define F367TER_TSPARITY_ON 0xf2710040
1971	#define F367TER_TSSYNCOUTRS_ON 0xf2710020
1972	#define F367TER_TSDVBS2_MODE 0xf2710010
1973	#define F367TER_TSISSYI_ON 0xf2710008
1974	#define F367TER_TSNPD_ON 0xf2710004
1975	#define F367TER_TSCRC8_ON 0xf2710002
1976	#define F367TER_TSDSS_PACKET 0xf2710001
1977
1978	/* TSCFGH */
1979	#define R367TER_TSCFGH 0xf272
1980	#define F367TER_TSFIFO_DVBCI 0xf2720080
1981	#define F367TER_TSFIFO_SERIAL 0xf2720040
1982	#define F367TER_TSFIFO_TEIUPDATE 0xf2720020
1983	#define F367TER_TSFIFO_DUTY50 0xf2720010
1984	#define F367TER_TSFIFO_HSGNLOUT 0xf2720008
1985	#define F367TER_TSFIFO_ERRMODE 0xf2720006
1986	#define F367TER_RST_HWARE 0xf2720001
1987
1988	/* TSCFGM */
1989	#define R367TER_TSCFGM 0xf273
1990	#define F367TER_TSFIFO_MANSPEED 0xf27300c0
1991	#define F367TER_TSFIFO_PERMDATA 0xf2730020
1992	#define F367TER_TSFIFO_NONEWSGNL 0xf2730010
1993	#define F367TER_TSFIFO_BITSPEED 0xf2730008
1994	#define F367TER_NPD_SPECDVBS2 0xf2730004
1995	#define F367TER_TSFIFO_STOPCKDIS 0xf2730002
1996	#define F367TER_TSFIFO_INVDATA 0xf2730001
1997
1998	/* TSCFGL */
1999	#define R367TER_TSCFGL 0xf274
2000	#define F367TER_TSFIFO_BCLKDEL1cK 0xf27400c0
2001	#define F367TER_BCHERROR_MODE 0xf2740030
2002	#define F367TER_TSFIFO_NSGNL2dATA 0xf2740008
2003	#define F367TER_TSFIFO_EMBINDVB 0xf2740004
2004	#define F367TER_TSFIFO_DPUNACT 0xf2740002
2005	#define F367TER_TSFIFO_NPDOFF 0xf2740001
2006
2007	/* TSSYNC */
2008	#define R367TER_TSSYNC 0xf275
2009	#define F367TER_TSFIFO_PERMUTE 0xf2750080
2010	#define F367TER_TSFIFO_FISCR3B 0xf2750060
2011	#define F367TER_TSFIFO_SYNCMODE 0xf2750018
2012	#define F367TER_TSFIFO_SYNCSEL 0xf2750007
2013
2014	/* TSINSDELH */
2015	#define R367TER_TSINSDELH 0xf276
2016	#define F367TER_TSDEL_SYNCBYTE 0xf2760080
2017	#define F367TER_TSDEL_XXHEADER 0xf2760040
2018	#define F367TER_TSDEL_BBHEADER 0xf2760020
2019	#define F367TER_TSDEL_DATAFIELD 0xf2760010
2020	#define F367TER_TSINSDEL_ISCR 0xf2760008
2021	#define F367TER_TSINSDEL_NPD 0xf2760004
2022	#define F367TER_TSINSDEL_RSPARITY 0xf2760002
2023	#define F367TER_TSINSDEL_CRC8 0xf2760001
2024
2025	/* TSINSDELM */
2026	#define R367TER_TSINSDELM 0xf277
2027	#define F367TER_TSINS_BBPADDING 0xf2770080
2028	#define F367TER_TSINS_BCHFEC 0xf2770040
2029	#define F367TER_TSINS_LDPCFEC 0xf2770020
2030	#define F367TER_TSINS_EMODCOD 0xf2770010
2031	#define F367TER_TSINS_TOKEN 0xf2770008
2032	#define F367TER_TSINS_XXXERR 0xf2770004
2033	#define F367TER_TSINS_MATYPE 0xf2770002
2034	#define F367TER_TSINS_UPL 0xf2770001
2035
2036	/* TSINSDELL */
2037	#define R367TER_TSINSDELL 0xf278
2038	#define F367TER_TSINS_DFL 0xf2780080
2039	#define F367TER_TSINS_SYNCD 0xf2780040
2040	#define F367TER_TSINS_BLOCLEN 0xf2780020
2041	#define F367TER_TSINS_SIGPCOUNT 0xf2780010
2042	#define F367TER_TSINS_FIFO 0xf2780008
2043	#define F367TER_TSINS_REALPACK 0xf2780004
2044	#define F367TER_TSINS_TSCONFIG 0xf2780002
2045	#define F367TER_TSINS_LATENCY 0xf2780001
2046
2047	/* TSDIVN */
2048	#define R367TER_TSDIVN 0xf279
2049	#define F367TER_TSFIFO_LOWSPEED 0xf2790080
2050	#define F367TER_BYTE_OVERSAMPLING 0xf2790070
2051	#define F367TER_TSMANUAL_PACKETNBR 0xf279000f
2052
2053	/* TSDIVPM */
2054	#define R367TER_TSDIVPM 0xf27a
2055	#define F367TER_TSMANUAL_P_HI 0xf27a00ff
2056
2057	/* TSDIVPL */
2058	#define R367TER_TSDIVPL 0xf27b
2059	#define F367TER_TSMANUAL_P_LO 0xf27b00ff
2060
2061	/* TSDIVQM */
2062	#define R367TER_TSDIVQM 0xf27c
2063	#define F367TER_TSMANUAL_Q_HI 0xf27c00ff
2064
2065	/* TSDIVQL */
2066	#define R367TER_TSDIVQL 0xf27d
2067	#define F367TER_TSMANUAL_Q_LO 0xf27d00ff
2068
2069	/* TSDILSTKM */
2070	#define R367TER_TSDILSTKM 0xf27e
2071	#define F367TER_TSFIFO_DILSTK_HI 0xf27e00ff
2072
2073	/* TSDILSTKL */
2074	#define R367TER_TSDILSTKL 0xf27f
2075	#define F367TER_TSFIFO_DILSTK_LO 0xf27f00ff
2076
2077	/* TSSPEED */
2078	#define R367TER_TSSPEED 0xf280
2079	#define F367TER_TSFIFO_OUTSPEED 0xf28000ff
2080
2081	/* TSSTATUS */
2082	#define R367TER_TSSTATUS 0xf281
2083	#define F367TER_TSFIFO_LINEOK 0xf2810080
2084	#define F367TER_TSFIFO_ERROR 0xf2810040
2085	#define F367TER_TSFIFO_DATA7 0xf2810020
2086	#define F367TER_TSFIFO_NOSYNC 0xf2810010
2087	#define F367TER_ISCR_INITIALIZED 0xf2810008
2088	#define F367TER_ISCR_UPDATED 0xf2810004
2089	#define F367TER_SOFFIFO_UNREGUL 0xf2810002
2090	#define F367TER_DIL_READY 0xf2810001
2091
2092	/* TSSTATUS2 */
2093	#define R367TER_TSSTATUS2 0xf282
2094	#define F367TER_TSFIFO_DEMODSEL 0xf2820080
2095	#define F367TER_TSFIFOSPEED_STORE 0xf2820040
2096	#define F367TER_DILXX_RESET 0xf2820020
2097	#define F367TER_TSSERIAL_IMPOSSIBLE 0xf2820010
2098	#define F367TER_TSFIFO_UNDERSPEED 0xf2820008
2099	#define F367TER_BITSPEED_EVENT 0xf2820004
2100	#define F367TER_UL_SCRAMBDETECT 0xf2820002
2101	#define F367TER_ULDTV67_FALSELOCK 0xf2820001
2102
2103	/* TSBITRATEM */
2104	#define R367TER_TSBITRATEM 0xf283
2105	#define F367TER_TSFIFO_BITRATE_HI 0xf28300ff
2106
2107	/* TSBITRATEL */
2108	#define R367TER_TSBITRATEL 0xf284
2109	#define F367TER_TSFIFO_BITRATE_LO 0xf28400ff
2110
2111	/* TSPACKLENM */
2112	#define R367TER_TSPACKLENM 0xf285
2113	#define F367TER_TSFIFO_PACKCPT 0xf28500e0
2114	#define F367TER_DIL_RPLEN_HI 0xf285001f
2115
2116	/* TSPACKLENL */
2117	#define R367TER_TSPACKLENL 0xf286
2118	#define F367TER_DIL_RPLEN_LO 0xf28600ff
2119
2120	/* TSBLOCLENM */
2121	#define R367TER_TSBLOCLENM 0xf287
2122	#define F367TER_TSFIFO_PFLEN_HI 0xf28700ff
2123
2124	/* TSBLOCLENL */
2125	#define R367TER_TSBLOCLENL 0xf288
2126	#define F367TER_TSFIFO_PFLEN_LO 0xf28800ff
2127
2128	/* TSDLYH */
2129	#define R367TER_TSDLYH 0xf289
2130	#define F367TER_SOFFIFO_TSTIMEVALID 0xf2890080
2131	#define F367TER_SOFFIFO_SPEEDUP 0xf2890040
2132	#define F367TER_SOFFIFO_STOP 0xf2890020
2133	#define F367TER_SOFFIFO_REGULATED 0xf2890010
2134	#define F367TER_SOFFIFO_REALSBOFF_HI 0xf289000f
2135
2136	/* TSDLYM */
2137	#define R367TER_TSDLYM 0xf28a
2138	#define F367TER_SOFFIFO_REALSBOFF_MED 0xf28a00ff
2139
2140	/* TSDLYL */
2141	#define R367TER_TSDLYL 0xf28b
2142	#define F367TER_SOFFIFO_REALSBOFF_LO 0xf28b00ff
2143
2144	/* TSNPDAV */
2145	#define R367TER_TSNPDAV 0xf28c
2146	#define F367TER_TSNPD_AVERAGE 0xf28c00ff
2147
2148	/* TSBUFSTATH */
2149	#define R367TER_TSBUFSTATH 0xf28d
2150	#define F367TER_TSISCR_3BYTES 0xf28d0080
2151	#define F367TER_TSISCR_NEWDATA 0xf28d0040
2152	#define F367TER_TSISCR_BUFSTAT_HI 0xf28d003f
2153
2154	/* TSBUFSTATM */
2155	#define R367TER_TSBUFSTATM 0xf28e
2156	#define F367TER_TSISCR_BUFSTAT_MED 0xf28e00ff
2157
2158	/* TSBUFSTATL */
2159	#define R367TER_TSBUFSTATL 0xf28f
2160	#define F367TER_TSISCR_BUFSTAT_LO 0xf28f00ff
2161
2162	/* TSDEBUGM */
2163	#define R367TER_TSDEBUGM 0xf290
2164	#define F367TER_TSFIFO_ILLPACKET 0xf2900080
2165	#define F367TER_DIL_NOSYNC 0xf2900040
2166	#define F367TER_DIL_ISCR 0xf2900020
2167	#define F367TER_DILOUT_BSYNCB 0xf2900010
2168	#define F367TER_TSFIFO_EMPTYPKT 0xf2900008
2169	#define F367TER_TSFIFO_EMPTYRD 0xf2900004
2170	#define F367TER_SOFFIFO_STOPM 0xf2900002
2171	#define F367TER_SOFFIFO_SPEEDUPM 0xf2900001
2172
2173	/* TSDEBUGL */
2174	#define R367TER_TSDEBUGL 0xf291
2175	#define F367TER_TSFIFO_PACKLENFAIL 0xf2910080
2176	#define F367TER_TSFIFO_SYNCBFAIL 0xf2910040
2177	#define F367TER_TSFIFO_VITLIBRE 0xf2910020
2178	#define F367TER_TSFIFO_BOOSTSPEEDM 0xf2910010
2179	#define F367TER_TSFIFO_UNDERSPEEDM 0xf2910008
2180	#define F367TER_TSFIFO_ERROR_EVNT 0xf2910004
2181	#define F367TER_TSFIFO_FULL 0xf2910002
2182	#define F367TER_TSFIFO_OVERFLOWM 0xf2910001
2183
2184	/* TSDLYSETH */
2185	#define R367TER_TSDLYSETH 0xf292
2186	#define F367TER_SOFFIFO_OFFSET 0xf29200e0
2187	#define F367TER_SOFFIFO_SYMBOFFSET_HI 0xf292001f
2188
2189	/* TSDLYSETM */
2190	#define R367TER_TSDLYSETM 0xf293
2191	#define F367TER_SOFFIFO_SYMBOFFSET_MED 0xf29300ff
2192
2193	/* TSDLYSETL */
2194	#define R367TER_TSDLYSETL 0xf294
2195	#define F367TER_SOFFIFO_SYMBOFFSET_LO 0xf29400ff
2196
2197	/* TSOBSCFG */
2198	#define R367TER_TSOBSCFG 0xf295
2199	#define F367TER_TSFIFO_OBSCFG 0xf29500ff
2200
2201	/* TSOBSM */
2202	#define R367TER_TSOBSM 0xf296
2203	#define F367TER_TSFIFO_OBSDATA_HI 0xf29600ff
2204
2205	/* TSOBSL */
2206	#define R367TER_TSOBSL 0xf297
2207	#define F367TER_TSFIFO_OBSDATA_LO 0xf29700ff
2208
2209	/* ERRCTRL1 */
2210	#define R367TER_ERRCTRL1 0xf298
2211	#define F367TER_ERR_SRC1 0xf29800f0
2212	#define F367TER_ERRCTRL1_3 0xf2980008
2213	#define F367TER_NUM_EVT1 0xf2980007
2214
2215	/* ERRCNT1H */
2216	#define R367TER_ERRCNT1H 0xf299
2217	#define F367TER_ERRCNT1_OLDVALUE 0xf2990080
2218	#define F367TER_ERR_CNT1 0xf299007f
2219
2220	/* ERRCNT1M */
2221	#define R367TER_ERRCNT1M 0xf29a
2222	#define F367TER_ERR_CNT1_HI 0xf29a00ff
2223
2224	/* ERRCNT1L */
2225	#define R367TER_ERRCNT1L 0xf29b
2226	#define F367TER_ERR_CNT1_LO 0xf29b00ff
2227
2228	/* ERRCTRL2 */
2229	#define R367TER_ERRCTRL2 0xf29c
2230	#define F367TER_ERR_SRC2 0xf29c00f0
2231	#define F367TER_ERRCTRL2_3 0xf29c0008
2232	#define F367TER_NUM_EVT2 0xf29c0007
2233
2234	/* ERRCNT2H */
2235	#define R367TER_ERRCNT2H 0xf29d
2236	#define F367TER_ERRCNT2_OLDVALUE 0xf29d0080
2237	#define F367TER_ERR_CNT2_HI 0xf29d007f
2238
2239	/* ERRCNT2M */
2240	#define R367TER_ERRCNT2M 0xf29e
2241	#define F367TER_ERR_CNT2_MED 0xf29e00ff
2242
2243	/* ERRCNT2L */
2244	#define R367TER_ERRCNT2L 0xf29f
2245	#define F367TER_ERR_CNT2_LO 0xf29f00ff
2246
2247	/* FECSPY */
2248	#define R367TER_FECSPY 0xf2a0
2249	#define F367TER_SPY_ENABLE 0xf2a00080
2250	#define F367TER_NO_SYNCBYTE 0xf2a00040
2251	#define F367TER_SERIAL_MODE 0xf2a00020
2252	#define F367TER_UNUSUAL_PACKET 0xf2a00010
2253	#define F367TER_BERMETER_DATAMODE 0xf2a0000c
2254	#define F367TER_BERMETER_LMODE 0xf2a00002
2255	#define F367TER_BERMETER_RESET 0xf2a00001
2256
2257	/* FSPYCFG */
2258	#define R367TER_FSPYCFG 0xf2a1
2259	#define F367TER_FECSPY_INPUT 0xf2a100c0
2260	#define F367TER_RST_ON_ERROR 0xf2a10020
2261	#define F367TER_ONE_SHOT 0xf2a10010
2262	#define F367TER_I2C_MOD 0xf2a1000c
2263	#define F367TER_SPY_HYSTERESIS 0xf2a10003
2264
2265	/* FSPYDATA */
2266	#define R367TER_FSPYDATA 0xf2a2
2267	#define F367TER_SPY_STUFFING 0xf2a20080
2268	#define F367TER_NOERROR_PKTJITTER 0xf2a20040
2269	#define F367TER_SPY_CNULLPKT 0xf2a20020
2270	#define F367TER_SPY_OUTDATA_MODE 0xf2a2001f
2271
2272	/* FSPYOUT */
2273	#define R367TER_FSPYOUT 0xf2a3
2274	#define F367TER_FSPY_DIRECT 0xf2a30080
2275	#define F367TER_FSPYOUT_6 0xf2a30040
2276	#define F367TER_SPY_OUTDATA_BUS 0xf2a30038
2277	#define F367TER_STUFF_MODE 0xf2a30007
2278
2279	/* FSTATUS */
2280	#define R367TER_FSTATUS 0xf2a4
2281	#define F367TER_SPY_ENDSIM 0xf2a40080
2282	#define F367TER_VALID_SIM 0xf2a40040
2283	#define F367TER_FOUND_SIGNAL 0xf2a40020
2284	#define F367TER_DSS_SYNCBYTE 0xf2a40010
2285	#define F367TER_RESULT_STATE 0xf2a4000f
2286
2287	/* FGOODPACK */
2288	#define R367TER_FGOODPACK 0xf2a5
2289	#define F367TER_FGOOD_PACKET 0xf2a500ff
2290
2291	/* FPACKCNT */
2292	#define R367TER_FPACKCNT 0xf2a6
2293	#define F367TER_FPACKET_COUNTER 0xf2a600ff
2294
2295	/* FSPYMISC */
2296	#define R367TER_FSPYMISC 0xf2a7
2297	#define F367TER_FLABEL_COUNTER 0xf2a700ff
2298
2299	/* FBERCPT4 */
2300	#define R367TER_FBERCPT4 0xf2a8
2301	#define F367TER_FBERMETER_CPT5 0xf2a800ff
2302
2303	/* FBERCPT3 */
2304	#define R367TER_FBERCPT3 0xf2a9
2305	#define F367TER_FBERMETER_CPT4 0xf2a900ff
2306
2307	/* FBERCPT2 */
2308	#define R367TER_FBERCPT2 0xf2aa
2309	#define F367TER_FBERMETER_CPT3 0xf2aa00ff
2310
2311	/* FBERCPT1 */
2312	#define R367TER_FBERCPT1 0xf2ab
2313	#define F367TER_FBERMETER_CPT2 0xf2ab00ff
2314
2315	/* FBERCPT0 */
2316	#define R367TER_FBERCPT0 0xf2ac
2317	#define F367TER_FBERMETER_CPT1 0xf2ac00ff
2318
2319	/* FBERERR2 */
2320	#define R367TER_FBERERR2 0xf2ad
2321	#define F367TER_FBERMETER_ERR_HI 0xf2ad00ff
2322
2323	/* FBERERR1 */
2324	#define R367TER_FBERERR1 0xf2ae
2325	#define F367TER_FBERMETER_ERR_MED 0xf2ae00ff
2326
2327	/* FBERERR0 */
2328	#define R367TER_FBERERR0 0xf2af
2329	#define F367TER_FBERMETER_ERR_LO 0xf2af00ff
2330
2331	/* FSTATESM */
2332	#define R367TER_FSTATESM 0xf2b0
2333	#define F367TER_RSTATE_F 0xf2b00080
2334	#define F367TER_RSTATE_E 0xf2b00040
2335	#define F367TER_RSTATE_D 0xf2b00020
2336	#define F367TER_RSTATE_C 0xf2b00010
2337	#define F367TER_RSTATE_B 0xf2b00008
2338	#define F367TER_RSTATE_A 0xf2b00004
2339	#define F367TER_RSTATE_9 0xf2b00002
2340	#define F367TER_RSTATE_8 0xf2b00001
2341
2342	/* FSTATESL */
2343	#define R367TER_FSTATESL 0xf2b1
2344	#define F367TER_RSTATE_7 0xf2b10080
2345	#define F367TER_RSTATE_6 0xf2b10040
2346	#define F367TER_RSTATE_5 0xf2b10020
2347	#define F367TER_RSTATE_4 0xf2b10010
2348	#define F367TER_RSTATE_3 0xf2b10008
2349	#define F367TER_RSTATE_2 0xf2b10004
2350	#define F367TER_RSTATE_1 0xf2b10002
2351	#define F367TER_RSTATE_0 0xf2b10001
2352
2353	/* FSPYBER */
2354	#define R367TER_FSPYBER 0xf2b2
2355	#define F367TER_FSPYBER_7 0xf2b20080
2356	#define F367TER_FSPYOBS_XORREAD 0xf2b20040
2357	#define F367TER_FSPYBER_OBSMODE 0xf2b20020
2358	#define F367TER_FSPYBER_SYNCBYTE 0xf2b20010
2359	#define F367TER_FSPYBER_UNSYNC 0xf2b20008
2360	#define F367TER_FSPYBER_CTIME 0xf2b20007
2361
2362	/* FSPYDISTM */
2363	#define R367TER_FSPYDISTM 0xf2b3
2364	#define F367TER_PKTTIME_DISTANCE_HI 0xf2b300ff
2365
2366	/* FSPYDISTL */
2367	#define R367TER_FSPYDISTL 0xf2b4
2368	#define F367TER_PKTTIME_DISTANCE_LO 0xf2b400ff
2369
2370	/* FSPYOBS7 */
2371	#define R367TER_FSPYOBS7 0xf2b8
2372	#define F367TER_FSPYOBS_SPYFAIL 0xf2b80080
2373	#define F367TER_FSPYOBS_SPYFAIL1 0xf2b80040
2374	#define F367TER_FSPYOBS_ERROR 0xf2b80020
2375	#define F367TER_FSPYOBS_STROUT 0xf2b80010
2376	#define F367TER_FSPYOBS_RESULTSTATE1 0xf2b8000f
2377
2378	/* FSPYOBS6 */
2379	#define R367TER_FSPYOBS6 0xf2b9
2380	#define F367TER_FSPYOBS_RESULTSTATe0 0xf2b900f0
2381	#define F367TER_FSPYOBS_RESULTSTATEM1 0xf2b9000f
2382
2383	/* FSPYOBS5 */
2384	#define R367TER_FSPYOBS5 0xf2ba
2385	#define F367TER_FSPYOBS_BYTEOFPACKET1 0xf2ba00ff
2386
2387	/* FSPYOBS4 */
2388	#define R367TER_FSPYOBS4 0xf2bb
2389	#define F367TER_FSPYOBS_BYTEVALUE1 0xf2bb00ff
2390
2391	/* FSPYOBS3 */
2392	#define R367TER_FSPYOBS3 0xf2bc
2393	#define F367TER_FSPYOBS_DATA1 0xf2bc00ff
2394
2395	/* FSPYOBS2 */
2396	#define R367TER_FSPYOBS2 0xf2bd
2397	#define F367TER_FSPYOBS_DATa0 0xf2bd00ff
2398
2399	/* FSPYOBS1 */
2400	#define R367TER_FSPYOBS1 0xf2be
2401	#define F367TER_FSPYOBS_DATAM1 0xf2be00ff
2402
2403	/* FSPYOBS0 */
2404	#define R367TER_FSPYOBS0 0xf2bf
2405	#define F367TER_FSPYOBS_DATAM2 0xf2bf00ff
2406
2407	/* SFDEMAP */
2408	#define R367TER_SFDEMAP 0xf2c0
2409	#define F367TER_SFDEMAP_7 0xf2c00080
2410	#define F367TER_SFEC_K_DIVIDER_VIT 0xf2c0007f
2411
2412	/* SFERROR */
2413	#define R367TER_SFERROR 0xf2c1
2414	#define F367TER_SFEC_REGERR_VIT 0xf2c100ff
2415
2416	/* SFAVSR */
2417	#define R367TER_SFAVSR 0xf2c2
2418	#define F367TER_SFEC_SUMERRORS 0xf2c20080
2419	#define F367TER_SERROR_MAXMODE 0xf2c20040
2420	#define F367TER_SN_SFEC 0xf2c20030
2421	#define F367TER_KDIV_MODE_SFEC 0xf2c2000c
2422	#define F367TER_SFAVSR_1 0xf2c20002
2423	#define F367TER_SFAVSR_0 0xf2c20001
2424
2425	/* SFECSTATUS */
2426	#define R367TER_SFECSTATUS 0xf2c3
2427	#define F367TER_SFEC_ON 0xf2c30080
2428	#define F367TER_SFSTATUS_6 0xf2c30040
2429	#define F367TER_SFSTATUS_5 0xf2c30020
2430	#define F367TER_SFSTATUS_4 0xf2c30010
2431	#define F367TER_LOCKEDSFEC 0xf2c30008
2432	#define F367TER_SFEC_DELOCK 0xf2c30004
2433	#define F367TER_SFEC_DEMODSEL1 0xf2c30002
2434	#define F367TER_SFEC_OVFON 0xf2c30001
2435
2436	/* SFKDIV12 */
2437	#define R367TER_SFKDIV12 0xf2c4
2438	#define F367TER_SFECKDIV12_MAN 0xf2c40080
2439	#define F367TER_SFEC_K_DIVIDER_12 0xf2c4007f
2440
2441	/* SFKDIV23 */
2442	#define R367TER_SFKDIV23 0xf2c5
2443	#define F367TER_SFECKDIV23_MAN 0xf2c50080
2444	#define F367TER_SFEC_K_DIVIDER_23 0xf2c5007f
2445
2446	/* SFKDIV34 */
2447	#define R367TER_SFKDIV34 0xf2c6
2448	#define F367TER_SFECKDIV34_MAN 0xf2c60080
2449	#define F367TER_SFEC_K_DIVIDER_34 0xf2c6007f
2450
2451	/* SFKDIV56 */
2452	#define R367TER_SFKDIV56 0xf2c7
2453	#define F367TER_SFECKDIV56_MAN 0xf2c70080
2454	#define F367TER_SFEC_K_DIVIDER_56 0xf2c7007f
2455
2456	/* SFKDIV67 */
2457	#define R367TER_SFKDIV67 0xf2c8
2458	#define F367TER_SFECKDIV67_MAN 0xf2c80080
2459	#define F367TER_SFEC_K_DIVIDER_67 0xf2c8007f
2460
2461	/* SFKDIV78 */
2462	#define R367TER_SFKDIV78 0xf2c9
2463	#define F367TER_SFECKDIV78_MAN 0xf2c90080
2464	#define F367TER_SFEC_K_DIVIDER_78 0xf2c9007f
2465
2466	/* SFDILSTKM */
2467	#define R367TER_SFDILSTKM 0xf2ca
2468	#define F367TER_SFEC_PACKCPT 0xf2ca00e0
2469	#define F367TER_SFEC_DILSTK_HI 0xf2ca001f
2470
2471	/* SFDILSTKL */
2472	#define R367TER_SFDILSTKL 0xf2cb
2473	#define F367TER_SFEC_DILSTK_LO 0xf2cb00ff
2474
2475	/* SFSTATUS */
2476	#define R367TER_SFSTATUS 0xf2cc
2477	#define F367TER_SFEC_LINEOK 0xf2cc0080
2478	#define F367TER_SFEC_ERROR 0xf2cc0040
2479	#define F367TER_SFEC_DATA7 0xf2cc0020
2480	#define F367TER_SFEC_OVERFLOW 0xf2cc0010
2481	#define F367TER_SFEC_DEMODSEL2 0xf2cc0008
2482	#define F367TER_SFEC_NOSYNC 0xf2cc0004
2483	#define F367TER_SFEC_UNREGULA 0xf2cc0002
2484	#define F367TER_SFEC_READY 0xf2cc0001
2485
2486	/* SFDLYH */
2487	#define R367TER_SFDLYH 0xf2cd
2488	#define F367TER_SFEC_TSTIMEVALID 0xf2cd0080
2489	#define F367TER_SFEC_SPEEDUP 0xf2cd0040
2490	#define F367TER_SFEC_STOP 0xf2cd0020
2491	#define F367TER_SFEC_REGULATED 0xf2cd0010
2492	#define F367TER_SFEC_REALSYMBOFFSET 0xf2cd000f
2493
2494	/* SFDLYM */
2495	#define R367TER_SFDLYM 0xf2ce
2496	#define F367TER_SFEC_REALSYMBOFFSET_HI 0xf2ce00ff
2497
2498	/* SFDLYL */
2499	#define R367TER_SFDLYL 0xf2cf
2500	#define F367TER_SFEC_REALSYMBOFFSET_LO 0xf2cf00ff
2501
2502	/* SFDLYSETH */
2503	#define R367TER_SFDLYSETH 0xf2d0
2504	#define F367TER_SFEC_OFFSET 0xf2d000e0
2505	#define F367TER_SFECDLYSETH_4 0xf2d00010
2506	#define F367TER_RST_SFEC 0xf2d00008
2507	#define F367TER_SFECDLYSETH_2 0xf2d00004
2508	#define F367TER_SFEC_DISABLE 0xf2d00002
2509	#define F367TER_SFEC_UNREGUL 0xf2d00001
2510
2511	/* SFDLYSETM */
2512	#define R367TER_SFDLYSETM 0xf2d1
2513	#define F367TER_SFECDLYSETM_7 0xf2d10080
2514	#define F367TER_SFEC_SYMBOFFSET_HI 0xf2d1007f
2515
2516	/* SFDLYSETL */
2517	#define R367TER_SFDLYSETL 0xf2d2
2518	#define F367TER_SFEC_SYMBOFFSET_LO 0xf2d200ff
2519
2520	/* SFOBSCFG */
2521	#define R367TER_SFOBSCFG 0xf2d3
2522	#define F367TER_SFEC_OBSCFG 0xf2d300ff
2523
2524	/* SFOBSM */
2525	#define R367TER_SFOBSM 0xf2d4
2526	#define F367TER_SFEC_OBSDATA_HI 0xf2d400ff
2527
2528	/* SFOBSL */
2529	#define R367TER_SFOBSL 0xf2d5
2530	#define F367TER_SFEC_OBSDATA_LO 0xf2d500ff
2531
2532	/* SFECINFO */
2533	#define R367TER_SFECINFO 0xf2d6
2534	#define F367TER_SFECINFO_7 0xf2d60080
2535	#define F367TER_SFEC_SYNCDLSB 0xf2d60070
2536	#define F367TER_SFCE_S1cPHASE 0xf2d6000f
2537
2538	/* SFERRCTRL */
2539	#define R367TER_SFERRCTRL 0xf2d8
2540	#define F367TER_SFEC_ERR_SOURCE 0xf2d800f0
2541	#define F367TER_SFERRCTRL_3 0xf2d80008
2542	#define F367TER_SFEC_NUM_EVENT 0xf2d80007
2543
2544	/* SFERRCNTH */
2545	#define R367TER_SFERRCNTH 0xf2d9
2546	#define F367TER_SFERRC_OLDVALUE 0xf2d90080
2547	#define F367TER_SFEC_ERR_CNT 0xf2d9007f
2548
2549	/* SFERRCNTM */
2550	#define R367TER_SFERRCNTM 0xf2da
2551	#define F367TER_SFEC_ERR_CNT_HI 0xf2da00ff
2552
2553	/* SFERRCNTL */
2554	#define R367TER_SFERRCNTL 0xf2db
2555	#define F367TER_SFEC_ERR_CNT_LO 0xf2db00ff
2556
2557	/* SYMBRATEM */
2558	#define R367TER_SYMBRATEM 0xf2e0
2559	#define F367TER_DEFGEN_SYMBRATE_HI 0xf2e000ff
2560
2561	/* SYMBRATEL */
2562	#define R367TER_SYMBRATEL 0xf2e1
2563	#define F367TER_DEFGEN_SYMBRATE_LO 0xf2e100ff
2564
2565	/* SYMBSTATUS */
2566	#define R367TER_SYMBSTATUS 0xf2e2
2567	#define F367TER_SYMBDLINE2_OFF 0xf2e20080
2568	#define F367TER_SDDL_REINIT1 0xf2e20040
2569	#define F367TER_SDD_REINIT1 0xf2e20020
2570	#define F367TER_TOKENID_ERROR 0xf2e20010
2571	#define F367TER_SYMBRATE_OVERFLOW 0xf2e20008
2572	#define F367TER_SYMBRATE_UNDERFLOW 0xf2e20004
2573	#define F367TER_TOKENID_RSTEVENT 0xf2e20002
2574	#define F367TER_TOKENID_RESET1 0xf2e20001
2575
2576	/* SYMBCFG */
2577	#define R367TER_SYMBCFG 0xf2e3
2578	#define F367TER_SYMBCFG_7 0xf2e30080
2579	#define F367TER_SYMBCFG_6 0xf2e30040
2580	#define F367TER_SYMBCFG_5 0xf2e30020
2581	#define F367TER_SYMBCFG_4 0xf2e30010
2582	#define F367TER_SYMRATE_FSPEED 0xf2e3000c
2583	#define F367TER_SYMRATE_SSPEED 0xf2e30003
2584
2585	/* SYMBFIFOM */
2586	#define R367TER_SYMBFIFOM 0xf2e4
2587	#define F367TER_SYMBFIFOM_7 0xf2e40080
2588	#define F367TER_SYMBFIFOM_6 0xf2e40040
2589	#define F367TER_DEFGEN_SYMFIFO_HI 0xf2e4003f
2590
2591	/* SYMBFIFOL */
2592	#define R367TER_SYMBFIFOL 0xf2e5
2593	#define F367TER_DEFGEN_SYMFIFO_LO 0xf2e500ff
2594
2595	/* SYMBOFFSM */
2596	#define R367TER_SYMBOFFSM 0xf2e6
2597	#define F367TER_TOKENID_RESET2 0xf2e60080
2598	#define F367TER_SDDL_REINIT2 0xf2e60040
2599	#define F367TER_SDD_REINIT2 0xf2e60020
2600	#define F367TER_SYMBOFFSM_4 0xf2e60010
2601	#define F367TER_SYMBOFFSM_3 0xf2e60008
2602	#define F367TER_DEFGEN_SYMBOFFSET_HI 0xf2e60007
2603
2604	/* SYMBOFFSL */
2605	#define R367TER_SYMBOFFSL 0xf2e7
2606	#define F367TER_DEFGEN_SYMBOFFSET_LO 0xf2e700ff
2607
2608	/* DEBUG_LT4 */
2609	#define R367TER_DEBUG_LT4 0xf400
2610	#define F367TER_F_DEBUG_LT4 0xf40000ff
2611
2612	/* DEBUG_LT5 */
2613	#define R367TER_DEBUG_LT5 0xf401
2614	#define F367TER_F_DEBUG_LT5 0xf40100ff
2615
2616	/* DEBUG_LT6 */
2617	#define R367TER_DEBUG_LT6 0xf402
2618	#define F367TER_F_DEBUG_LT6 0xf40200ff
2619
2620	/* DEBUG_LT7 */
2621	#define R367TER_DEBUG_LT7 0xf403
2622	#define F367TER_F_DEBUG_LT7 0xf40300ff
2623
2624	/* DEBUG_LT8 */
2625	#define R367TER_DEBUG_LT8 0xf404
2626	#define F367TER_F_DEBUG_LT8 0xf40400ff
2627
2628	/* DEBUG_LT9 */
2629	#define R367TER_DEBUG_LT9 0xf405
2630	#define F367TER_F_DEBUG_LT9 0xf40500ff
2631
2632	/* ID */
2633	#define R367CAB_ID 0xf000
2634	#define F367CAB_IDENTIFICATIONREGISTER 0xf00000ff
2635
2636	/* I2CRPT */
2637	#define R367CAB_I2CRPT 0xf001
2638	#define F367CAB_I2CT_ON 0xf0010080
2639	#define F367CAB_ENARPT_LEVEL 0xf0010070
2640	#define F367CAB_SCLT_DELAY 0xf0010008
2641	#define F367CAB_SCLT_NOD 0xf0010004
2642	#define F367CAB_STOP_ENABLE 0xf0010002
2643	#define F367CAB_SDAT_NOD 0xf0010001
2644
2645	/* TOPCTRL */
2646	#define R367CAB_TOPCTRL 0xf002
2647	#define F367CAB_STDBY 0xf0020080
2648	#define F367CAB_STDBY_CORE 0xf0020020
2649	#define F367CAB_QAM_COFDM 0xf0020010
2650	#define F367CAB_TS_DIS 0xf0020008
2651	#define F367CAB_DIR_CLK_216 0xf0020004
2652
2653	/* IOCFG0 */
2654	#define R367CAB_IOCFG0 0xf003
2655	#define F367CAB_OP0_SD 0xf0030080
2656	#define F367CAB_OP0_VAL 0xf0030040
2657	#define F367CAB_OP0_OD 0xf0030020
2658	#define F367CAB_OP0_INV 0xf0030010
2659	#define F367CAB_OP0_DACVALUE_HI 0xf003000f
2660
2661	/* DAc0R */
2662	#define R367CAB_DAC0R 0xf004
2663	#define F367CAB_OP0_DACVALUE_LO 0xf00400ff
2664
2665	/* IOCFG1 */
2666	#define R367CAB_IOCFG1 0xf005
2667	#define F367CAB_IP0 0xf0050040
2668	#define F367CAB_OP1_OD 0xf0050020
2669	#define F367CAB_OP1_INV 0xf0050010
2670	#define F367CAB_OP1_DACVALUE_HI 0xf005000f
2671
2672	/* DAC1R */
2673	#define R367CAB_DAC1R 0xf006
2674	#define F367CAB_OP1_DACVALUE_LO 0xf00600ff
2675
2676	/* IOCFG2 */
2677	#define R367CAB_IOCFG2 0xf007
2678	#define F367CAB_OP2_LOCK_CONF 0xf00700e0
2679	#define F367CAB_OP2_OD 0xf0070010
2680	#define F367CAB_OP2_VAL 0xf0070008
2681	#define F367CAB_OP1_LOCK_CONF 0xf0070007
2682
2683	/* SDFR */
2684	#define R367CAB_SDFR 0xf008
2685	#define F367CAB_OP0_FREQ 0xf00800f0
2686	#define F367CAB_OP1_FREQ 0xf008000f
2687
2688	/* AUX_CLK */
2689	#define R367CAB_AUX_CLK 0xf00a
2690	#define F367CAB_AUXFEC_CTL 0xf00a00c0
2691	#define F367CAB_DIS_CKX4 0xf00a0020
2692	#define F367CAB_CKSEL 0xf00a0018
2693	#define F367CAB_CKDIV_PROG 0xf00a0006
2694	#define F367CAB_AUXCLK_ENA 0xf00a0001
2695
2696	/* FREESYS1 */
2697	#define R367CAB_FREESYS1 0xf00b
2698	#define F367CAB_FREESYS_1 0xf00b00ff
2699
2700	/* FREESYS2 */
2701	#define R367CAB_FREESYS2 0xf00c
2702	#define F367CAB_FREESYS_2 0xf00c00ff
2703
2704	/* FREESYS3 */
2705	#define R367CAB_FREESYS3 0xf00d
2706	#define F367CAB_FREESYS_3 0xf00d00ff
2707
2708	/* GPIO_CFG */
2709	#define R367CAB_GPIO_CFG 0xf00e
2710	#define F367CAB_GPIO7_OD 0xf00e0080
2711	#define F367CAB_GPIO7_CFG 0xf00e0040
2712	#define F367CAB_GPIO6_OD 0xf00e0020
2713	#define F367CAB_GPIO6_CFG 0xf00e0010
2714	#define F367CAB_GPIO5_OD 0xf00e0008
2715	#define F367CAB_GPIO5_CFG 0xf00e0004
2716	#define F367CAB_GPIO4_OD 0xf00e0002
2717	#define F367CAB_GPIO4_CFG 0xf00e0001
2718
2719	/* GPIO_CMD */
2720	#define R367CAB_GPIO_CMD 0xf00f
2721	#define F367CAB_GPIO7_VAL 0xf00f0008
2722	#define F367CAB_GPIO6_VAL 0xf00f0004
2723	#define F367CAB_GPIO5_VAL 0xf00f0002
2724	#define F367CAB_GPIO4_VAL 0xf00f0001
2725
2726	/* TSTRES */
2727	#define R367CAB_TSTRES 0xf0c0
2728	#define F367CAB_FRES_DISPLAY 0xf0c00080
2729	#define F367CAB_FRES_FIFO_AD 0xf0c00020
2730	#define F367CAB_FRESRS 0xf0c00010
2731	#define F367CAB_FRESACS 0xf0c00008
2732	#define F367CAB_FRESFEC 0xf0c00004
2733	#define F367CAB_FRES_PRIF 0xf0c00002
2734	#define F367CAB_FRESCORE 0xf0c00001
2735
2736	/* ANACTRL */
2737	#define R367CAB_ANACTRL 0xf0c1
2738	#define F367CAB_BYPASS_XTAL 0xf0c10040
2739	#define F367CAB_BYPASS_PLLXN 0xf0c1000c
2740	#define F367CAB_DIS_PAD_OSC 0xf0c10002
2741	#define F367CAB_STDBY_PLLXN 0xf0c10001
2742
2743	/* TSTBUS */
2744	#define R367CAB_TSTBUS 0xf0c2
2745	#define F367CAB_TS_BYTE_CLK_INV 0xf0c20080
2746	#define F367CAB_CFG_IP 0xf0c20070
2747	#define F367CAB_CFG_TST 0xf0c2000f
2748
2749	/* RF_AGC1 */
2750	#define R367CAB_RF_AGC1 0xf0d4
2751	#define F367CAB_RF_AGC1_LEVEL_HI 0xf0d400ff
2752
2753	/* RF_AGC2 */
2754	#define R367CAB_RF_AGC2 0xf0d5
2755	#define F367CAB_REF_ADGP 0xf0d50080
2756	#define F367CAB_STDBY_ADCGP 0xf0d50020
2757	#define F367CAB_RF_AGC1_LEVEL_LO 0xf0d50003
2758
2759	/* ANADIGCTRL */
2760	#define R367CAB_ANADIGCTRL 0xf0d7
2761	#define F367CAB_SEL_CLKDEM 0xf0d70020
2762	#define F367CAB_EN_BUFFER_Q 0xf0d70010
2763	#define F367CAB_EN_BUFFER_I 0xf0d70008
2764	#define F367CAB_ADC_RIS_EGDE 0xf0d70004
2765	#define F367CAB_SGN_ADC 0xf0d70002
2766	#define F367CAB_SEL_AD12_SYNC 0xf0d70001
2767
2768	/* PLLMDIV */
2769	#define R367CAB_PLLMDIV 0xf0d8
2770	#define F367CAB_PLL_MDIV 0xf0d800ff
2771
2772	/* PLLNDIV */
2773	#define R367CAB_PLLNDIV 0xf0d9
2774	#define F367CAB_PLL_NDIV 0xf0d900ff
2775
2776	/* PLLSETUP */
2777	#define R367CAB_PLLSETUP 0xf0da
2778	#define F367CAB_PLL_PDIV 0xf0da0070
2779	#define F367CAB_PLL_KDIV 0xf0da000f
2780
2781	/* DUAL_AD12 */
2782	#define R367CAB_DUAL_AD12 0xf0db
2783	#define F367CAB_FS20M 0xf0db0020
2784	#define F367CAB_FS50M 0xf0db0010
2785	#define F367CAB_INMODe0 0xf0db0008
2786	#define F367CAB_POFFQ 0xf0db0004
2787	#define F367CAB_POFFI 0xf0db0002
2788	#define F367CAB_INMODE1 0xf0db0001
2789
2790	/* TSTBIST */
2791	#define R367CAB_TSTBIST 0xf0dc
2792	#define F367CAB_TST_BYP_CLK 0xf0dc0080
2793	#define F367CAB_TST_GCLKENA_STD 0xf0dc0040
2794	#define F367CAB_TST_GCLKENA 0xf0dc0020
2795	#define F367CAB_TST_MEMBIST 0xf0dc001f
2796
2797	/* CTRL_1 */
2798	#define R367CAB_CTRL_1 0xf402
2799	#define F367CAB_SOFT_RST 0xf4020080
2800	#define F367CAB_EQU_RST 0xf4020008
2801	#define F367CAB_CRL_RST 0xf4020004
2802	#define F367CAB_TRL_RST 0xf4020002
2803	#define F367CAB_AGC_RST 0xf4020001
2804
2805	/* CTRL_2 */
2806	#define R367CAB_CTRL_2 0xf403
2807	#define F367CAB_DEINT_RST 0xf4030008
2808	#define F367CAB_RS_RST 0xf4030004
2809
2810	/* IT_STATUS1 */
2811	#define R367CAB_IT_STATUS1 0xf408
2812	#define F367CAB_SWEEP_OUT 0xf4080080
2813	#define F367CAB_FSM_CRL 0xf4080040
2814	#define F367CAB_CRL_LOCK 0xf4080020
2815	#define F367CAB_MFSM 0xf4080010
2816	#define F367CAB_TRL_LOCK 0xf4080008
2817	#define F367CAB_TRL_AGC_LIMIT 0xf4080004
2818	#define F367CAB_ADJ_AGC_LOCK 0xf4080002
2819	#define F367CAB_AGC_QAM_LOCK 0xf4080001
2820
2821	/* IT_STATUS2 */
2822	#define R367CAB_IT_STATUS2 0xf409
2823	#define F367CAB_TSMF_CNT 0xf4090080
2824	#define F367CAB_TSMF_EOF 0xf4090040
2825	#define F367CAB_TSMF_RDY 0xf4090020
2826	#define F367CAB_FEC_NOCORR 0xf4090010
2827	#define F367CAB_SYNCSTATE 0xf4090008
2828	#define F367CAB_DEINT_LOCK 0xf4090004
2829	#define F367CAB_FADDING_FRZ 0xf4090002
2830	#define F367CAB_TAPMON_ALARM 0xf4090001
2831
2832	/* IT_EN1 */
2833	#define R367CAB_IT_EN1 0xf40a
2834	#define F367CAB_SWEEP_OUTE 0xf40a0080
2835	#define F367CAB_FSM_CRLE 0xf40a0040
2836	#define F367CAB_CRL_LOCKE 0xf40a0020
2837	#define F367CAB_MFSME 0xf40a0010
2838	#define F367CAB_TRL_LOCKE 0xf40a0008
2839	#define F367CAB_TRL_AGC_LIMITE 0xf40a0004
2840	#define F367CAB_ADJ_AGC_LOCKE 0xf40a0002
2841	#define F367CAB_AGC_LOCKE 0xf40a0001
2842
2843	/* IT_EN2 */
2844	#define R367CAB_IT_EN2 0xf40b
2845	#define F367CAB_TSMF_CNTE 0xf40b0080
2846	#define F367CAB_TSMF_EOFE 0xf40b0040
2847	#define F367CAB_TSMF_RDYE 0xf40b0020
2848	#define F367CAB_FEC_NOCORRE 0xf40b0010
2849	#define F367CAB_SYNCSTATEE 0xf40b0008
2850	#define F367CAB_DEINT_LOCKE 0xf40b0004
2851	#define F367CAB_FADDING_FRZE 0xf40b0002
2852	#define F367CAB_TAPMON_ALARME 0xf40b0001
2853
2854	/* CTRL_STATUS */
2855	#define R367CAB_CTRL_STATUS 0xf40c
2856	#define F367CAB_QAMFEC_LOCK 0xf40c0004
2857	#define F367CAB_TSMF_LOCK 0xf40c0002
2858	#define F367CAB_TSMF_ERROR 0xf40c0001
2859
2860	/* TEST_CTL */
2861	#define R367CAB_TEST_CTL 0xf40f
2862	#define F367CAB_TST_BLK_SEL 0xf40f0060
2863	#define F367CAB_TST_BUS_SEL 0xf40f001f
2864
2865	/* AGC_CTL */
2866	#define R367CAB_AGC_CTL 0xf410
2867	#define F367CAB_AGC_LCK_TH 0xf41000f0
2868	#define F367CAB_AGC_ACCUMRSTSEL 0xf4100007
2869
2870	/* AGC_IF_CFG */
2871	#define R367CAB_AGC_IF_CFG 0xf411
2872	#define F367CAB_AGC_IF_BWSEL 0xf41100f0
2873	#define F367CAB_AGC_IF_FREEZE 0xf4110002
2874
2875	/* AGC_RF_CFG */
2876	#define R367CAB_AGC_RF_CFG 0xf412
2877	#define F367CAB_AGC_RF_BWSEL 0xf4120070
2878	#define F367CAB_AGC_RF_FREEZE 0xf4120002
2879
2880	/* AGC_PWM_CFG */
2881	#define R367CAB_AGC_PWM_CFG 0xf413
2882	#define F367CAB_AGC_RF_PWM_TST 0xf4130080
2883	#define F367CAB_AGC_RF_PWM_INV 0xf4130040
2884	#define F367CAB_AGC_IF_PWM_TST 0xf4130008
2885	#define F367CAB_AGC_IF_PWM_INV 0xf4130004
2886	#define F367CAB_AGC_PWM_CLKDIV 0xf4130003
2887
2888	/* AGC_PWR_REF_L */
2889	#define R367CAB_AGC_PWR_REF_L 0xf414
2890	#define F367CAB_AGC_PWRREF_LO 0xf41400ff
2891
2892	/* AGC_PWR_REF_H */
2893	#define R367CAB_AGC_PWR_REF_H 0xf415
2894	#define F367CAB_AGC_PWRREF_HI 0xf4150003
2895
2896	/* AGC_RF_TH_L */
2897	#define R367CAB_AGC_RF_TH_L 0xf416
2898	#define F367CAB_AGC_RF_TH_LO 0xf41600ff
2899
2900	/* AGC_RF_TH_H */
2901	#define R367CAB_AGC_RF_TH_H 0xf417
2902	#define F367CAB_AGC_RF_TH_HI 0xf417000f
2903
2904	/* AGC_IF_LTH_L */
2905	#define R367CAB_AGC_IF_LTH_L 0xf418
2906	#define F367CAB_AGC_IF_THLO_LO 0xf41800ff
2907
2908	/* AGC_IF_LTH_H */
2909	#define R367CAB_AGC_IF_LTH_H 0xf419
2910	#define F367CAB_AGC_IF_THLO_HI 0xf419000f
2911
2912	/* AGC_IF_HTH_L */
2913	#define R367CAB_AGC_IF_HTH_L 0xf41a
2914	#define F367CAB_AGC_IF_THHI_LO 0xf41a00ff
2915
2916	/* AGC_IF_HTH_H */
2917	#define R367CAB_AGC_IF_HTH_H 0xf41b
2918	#define F367CAB_AGC_IF_THHI_HI 0xf41b000f
2919
2920	/* AGC_PWR_RD_L */
2921	#define R367CAB_AGC_PWR_RD_L 0xf41c
2922	#define F367CAB_AGC_PWR_WORD_LO 0xf41c00ff
2923
2924	/* AGC_PWR_RD_M */
2925	#define R367CAB_AGC_PWR_RD_M 0xf41d
2926	#define F367CAB_AGC_PWR_WORD_ME 0xf41d00ff
2927
2928	/* AGC_PWR_RD_H */
2929	#define R367CAB_AGC_PWR_RD_H 0xf41e
2930	#define F367CAB_AGC_PWR_WORD_HI 0xf41e0003
2931
2932	/* AGC_PWM_IFCMD_L */
2933	#define R367CAB_AGC_PWM_IFCMD_L 0xf420
2934	#define F367CAB_AGC_IF_PWMCMD_LO 0xf42000ff
2935
2936	/* AGC_PWM_IFCMD_H */
2937	#define R367CAB_AGC_PWM_IFCMD_H 0xf421
2938	#define F367CAB_AGC_IF_PWMCMD_HI 0xf421000f
2939
2940	/* AGC_PWM_RFCMD_L */
2941	#define R367CAB_AGC_PWM_RFCMD_L 0xf422
2942	#define F367CAB_AGC_RF_PWMCMD_LO 0xf42200ff
2943
2944	/* AGC_PWM_RFCMD_H */
2945	#define R367CAB_AGC_PWM_RFCMD_H 0xf423
2946	#define F367CAB_AGC_RF_PWMCMD_HI 0xf423000f
2947
2948	/* IQDEM_CFG */
2949	#define R367CAB_IQDEM_CFG 0xf424
2950	#define F367CAB_IQDEM_CLK_SEL 0xf4240004
2951	#define F367CAB_IQDEM_INVIQ 0xf4240002
2952	#define F367CAB_IQDEM_A2dTYPE 0xf4240001
2953
2954	/* MIX_NCO_LL */
2955	#define R367CAB_MIX_NCO_LL 0xf425
2956	#define F367CAB_MIX_NCO_INC_LL 0xf42500ff
2957
2958	/* MIX_NCO_HL */
2959	#define R367CAB_MIX_NCO_HL 0xf426
2960	#define F367CAB_MIX_NCO_INC_HL 0xf42600ff
2961
2962	/* MIX_NCO_HH */
2963	#define R367CAB_MIX_NCO_HH 0xf427
2964	#define F367CAB_MIX_NCO_INVCNST 0xf4270080
2965	#define F367CAB_MIX_NCO_INC_HH 0xf427007f
2966
2967	/* SRC_NCO_LL */
2968	#define R367CAB_SRC_NCO_LL 0xf428
2969	#define F367CAB_SRC_NCO_INC_LL 0xf42800ff
2970
2971	/* SRC_NCO_LH */
2972	#define R367CAB_SRC_NCO_LH 0xf429
2973	#define F367CAB_SRC_NCO_INC_LH 0xf42900ff
2974
2975	/* SRC_NCO_HL */
2976	#define R367CAB_SRC_NCO_HL 0xf42a
2977	#define F367CAB_SRC_NCO_INC_HL 0xf42a00ff
2978
2979	/* SRC_NCO_HH */
2980	#define R367CAB_SRC_NCO_HH 0xf42b
2981	#define F367CAB_SRC_NCO_INC_HH 0xf42b007f
2982
2983	/* IQDEM_GAIN_SRC_L */
2984	#define R367CAB_IQDEM_GAIN_SRC_L 0xf42c
2985	#define F367CAB_GAIN_SRC_LO 0xf42c00ff
2986
2987	/* IQDEM_GAIN_SRC_H */
2988	#define R367CAB_IQDEM_GAIN_SRC_H 0xf42d
2989	#define F367CAB_GAIN_SRC_HI 0xf42d0003
2990
2991	/* IQDEM_DCRM_CFG_LL */
2992	#define R367CAB_IQDEM_DCRM_CFG_LL 0xf430
2993	#define F367CAB_DCRM0_DCIN_L 0xf43000ff
2994
2995	/* IQDEM_DCRM_CFG_LH */
2996	#define R367CAB_IQDEM_DCRM_CFG_LH 0xf431
2997	#define F367CAB_DCRM1_I_DCIN_L 0xf43100fc
2998	#define F367CAB_DCRM0_DCIN_H 0xf4310003
2999
3000	/* IQDEM_DCRM_CFG_HL */
3001	#define R367CAB_IQDEM_DCRM_CFG_HL 0xf432
3002	#define F367CAB_DCRM1_Q_DCIN_L 0xf43200f0
3003	#define F367CAB_DCRM1_I_DCIN_H 0xf432000f
3004
3005	/* IQDEM_DCRM_CFG_HH */
3006	#define R367CAB_IQDEM_DCRM_CFG_HH 0xf433
3007	#define F367CAB_DCRM1_FRZ 0xf4330080
3008	#define F367CAB_DCRM0_FRZ 0xf4330040
3009	#define F367CAB_DCRM1_Q_DCIN_H 0xf433003f
3010
3011	/* IQDEM_ADJ_COEFf0 */
3012	#define R367CAB_IQDEM_ADJ_COEFF0 0xf434
3013	#define F367CAB_ADJIIR_COEFF10_L 0xf43400ff
3014
3015	/* IQDEM_ADJ_COEFF1 */
3016	#define R367CAB_IQDEM_ADJ_COEFF1 0xf435
3017	#define F367CAB_ADJIIR_COEFF11_L 0xf43500fc
3018	#define F367CAB_ADJIIR_COEFF10_H 0xf4350003
3019
3020	/* IQDEM_ADJ_COEFF2 */
3021	#define R367CAB_IQDEM_ADJ_COEFF2 0xf436
3022	#define F367CAB_ADJIIR_COEFF12_L 0xf43600f0
3023	#define F367CAB_ADJIIR_COEFF11_H 0xf436000f
3024
3025	/* IQDEM_ADJ_COEFF3 */
3026	#define R367CAB_IQDEM_ADJ_COEFF3 0xf437
3027	#define F367CAB_ADJIIR_COEFF20_L 0xf43700c0
3028	#define F367CAB_ADJIIR_COEFF12_H 0xf437003f
3029
3030	/* IQDEM_ADJ_COEFF4 */
3031	#define R367CAB_IQDEM_ADJ_COEFF4 0xf438
3032	#define F367CAB_ADJIIR_COEFF20_H 0xf43800ff
3033
3034	/* IQDEM_ADJ_COEFF5 */
3035	#define R367CAB_IQDEM_ADJ_COEFF5 0xf439
3036	#define F367CAB_ADJIIR_COEFF21_L 0xf43900ff
3037
3038	/* IQDEM_ADJ_COEFF6 */
3039	#define R367CAB_IQDEM_ADJ_COEFF6 0xf43a
3040	#define F367CAB_ADJIIR_COEFF22_L 0xf43a00fc
3041	#define F367CAB_ADJIIR_COEFF21_H 0xf43a0003
3042
3043	/* IQDEM_ADJ_COEFF7 */
3044	#define R367CAB_IQDEM_ADJ_COEFF7 0xf43b
3045	#define F367CAB_ADJIIR_COEFF22_H 0xf43b000f
3046
3047	/* IQDEM_ADJ_EN */
3048	#define R367CAB_IQDEM_ADJ_EN 0xf43c
3049	#define F367CAB_ALLPASSFILT_EN 0xf43c0008
3050	#define F367CAB_ADJ_AGC_EN 0xf43c0004
3051	#define F367CAB_ADJ_COEFF_FRZ 0xf43c0002
3052	#define F367CAB_ADJ_EN 0xf43c0001
3053
3054	/* IQDEM_ADJ_AGC_REF */
3055	#define R367CAB_IQDEM_ADJ_AGC_REF 0xf43d
3056	#define F367CAB_ADJ_AGC_REF 0xf43d00ff
3057
3058	/* ALLPASSFILT1 */
3059	#define R367CAB_ALLPASSFILT1 0xf440
3060	#define F367CAB_ALLPASSFILT_COEFF1_LO 0xf44000ff
3061
3062	/* ALLPASSFILT2 */
3063	#define R367CAB_ALLPASSFILT2 0xf441
3064	#define F367CAB_ALLPASSFILT_COEFF1_ME 0xf44100ff
3065
3066	/* ALLPASSFILT3 */
3067	#define R367CAB_ALLPASSFILT3 0xf442
3068	#define F367CAB_ALLPASSFILT_COEFF2_LO 0xf44200c0
3069	#define F367CAB_ALLPASSFILT_COEFF1_HI 0xf442003f
3070
3071	/* ALLPASSFILT4 */
3072	#define R367CAB_ALLPASSFILT4 0xf443
3073	#define F367CAB_ALLPASSFILT_COEFF2_MEL 0xf44300ff
3074
3075	/* ALLPASSFILT5 */
3076	#define R367CAB_ALLPASSFILT5 0xf444
3077	#define F367CAB_ALLPASSFILT_COEFF2_MEH 0xf44400ff
3078
3079	/* ALLPASSFILT6 */
3080	#define R367CAB_ALLPASSFILT6 0xf445
3081	#define F367CAB_ALLPASSFILT_COEFF3_LO 0xf44500f0
3082	#define F367CAB_ALLPASSFILT_COEFF2_HI 0xf445000f
3083
3084	/* ALLPASSFILT7 */
3085	#define R367CAB_ALLPASSFILT7 0xf446
3086	#define F367CAB_ALLPASSFILT_COEFF3_MEL 0xf44600ff
3087
3088	/* ALLPASSFILT8 */
3089	#define R367CAB_ALLPASSFILT8 0xf447
3090	#define F367CAB_ALLPASSFILT_COEFF3_MEH 0xf44700ff
3091
3092	/* ALLPASSFILT9 */
3093	#define R367CAB_ALLPASSFILT9 0xf448
3094	#define F367CAB_ALLPASSFILT_COEFF4_LO 0xf44800fc
3095	#define F367CAB_ALLPASSFILT_COEFF3_HI 0xf4480003
3096
3097	/* ALLPASSFILT10 */
3098	#define R367CAB_ALLPASSFILT10 0xf449
3099	#define F367CAB_ALLPASSFILT_COEFF4_ME 0xf44900ff
3100
3101	/* ALLPASSFILT11 */
3102	#define R367CAB_ALLPASSFILT11 0xf44a
3103	#define F367CAB_ALLPASSFILT_COEFF4_HI 0xf44a00ff
3104
3105	/* TRL_AGC_CFG */
3106	#define R367CAB_TRL_AGC_CFG 0xf450
3107	#define F367CAB_TRL_AGC_FREEZE 0xf4500080
3108	#define F367CAB_TRL_AGC_REF 0xf450007f
3109
3110	/* TRL_LPF_CFG */
3111	#define R367CAB_TRL_LPF_CFG 0xf454
3112	#define F367CAB_NYQPOINT_INV 0xf4540040
3113	#define F367CAB_TRL_SHIFT 0xf4540030
3114	#define F367CAB_NYQ_COEFF_SEL 0xf454000c
3115	#define F367CAB_TRL_LPF_FREEZE 0xf4540002
3116	#define F367CAB_TRL_LPF_CRT 0xf4540001
3117
3118	/* TRL_LPF_ACQ_GAIN */
3119	#define R367CAB_TRL_LPF_ACQ_GAIN 0xf455
3120	#define F367CAB_TRL_GDIR_ACQ 0xf4550070
3121	#define F367CAB_TRL_GINT_ACQ 0xf4550007
3122
3123	/* TRL_LPF_TRK_GAIN */
3124	#define R367CAB_TRL_LPF_TRK_GAIN 0xf456
3125	#define F367CAB_TRL_GDIR_TRK 0xf4560070
3126	#define F367CAB_TRL_GINT_TRK 0xf4560007
3127
3128	/* TRL_LPF_OUT_GAIN */
3129	#define R367CAB_TRL_LPF_OUT_GAIN 0xf457
3130	#define F367CAB_TRL_GAIN_OUT 0xf4570007
3131
3132	/* TRL_LOCKDET_LTH */
3133	#define R367CAB_TRL_LOCKDET_LTH 0xf458
3134	#define F367CAB_TRL_LCK_THLO 0xf4580007
3135
3136	/* TRL_LOCKDET_HTH */
3137	#define R367CAB_TRL_LOCKDET_HTH 0xf459
3138	#define F367CAB_TRL_LCK_THHI 0xf45900ff
3139
3140	/* TRL_LOCKDET_TRGVAL */
3141	#define R367CAB_TRL_LOCKDET_TRGVAL 0xf45a
3142	#define F367CAB_TRL_LCK_TRG 0xf45a00ff
3143
3144	/* IQ_QAM */
3145	#define R367CAB_IQ_QAM 0xf45c
3146	#define F367CAB_IQ_INPUT 0xf45c0008
3147	#define F367CAB_DETECT_MODE 0xf45c0007
3148
3149	/* FSM_STATE */
3150	#define R367CAB_FSM_STATE 0xf460
3151	#define F367CAB_CRL_DFE 0xf4600080
3152	#define F367CAB_DFE_START 0xf4600040
3153	#define F367CAB_CTRLG_START 0xf4600030
3154	#define F367CAB_FSM_FORCESTATE 0xf460000f
3155
3156	/* FSM_CTL */
3157	#define R367CAB_FSM_CTL 0xf461
3158	#define F367CAB_FEC2_EN 0xf4610040
3159	#define F367CAB_SIT_EN 0xf4610020
3160	#define F367CAB_TRL_AHEAD 0xf4610010
3161	#define F367CAB_TRL2_EN 0xf4610008
3162	#define F367CAB_FSM_EQA1_EN 0xf4610004
3163	#define F367CAB_FSM_BKP_DIS 0xf4610002
3164	#define F367CAB_FSM_FORCE_EN 0xf4610001
3165
3166	/* FSM_STS */
3167	#define R367CAB_FSM_STS 0xf462
3168	#define F367CAB_FSM_STATUS 0xf462000f
3169
3170	/* FSM_SNR0_HTH */
3171	#define R367CAB_FSM_SNR0_HTH 0xf463
3172	#define F367CAB_SNR0_HTH 0xf46300ff
3173
3174	/* FSM_SNR1_HTH */
3175	#define R367CAB_FSM_SNR1_HTH 0xf464
3176	#define F367CAB_SNR1_HTH 0xf46400ff
3177
3178	/* FSM_SNR2_HTH */
3179	#define R367CAB_FSM_SNR2_HTH 0xf465
3180	#define F367CAB_SNR2_HTH 0xf46500ff
3181
3182	/* FSM_SNR0_LTH */
3183	#define R367CAB_FSM_SNR0_LTH 0xf466
3184	#define F367CAB_SNR0_LTH 0xf46600ff
3185
3186	/* FSM_SNR1_LTH */
3187	#define R367CAB_FSM_SNR1_LTH 0xf467
3188	#define F367CAB_SNR1_LTH 0xf46700ff
3189
3190	/* FSM_EQA1_HTH */
3191	#define R367CAB_FSM_EQA1_HTH 0xf468
3192	#define F367CAB_SNR3_HTH_LO 0xf46800f0
3193	#define F367CAB_EQA1_HTH 0xf468000f
3194
3195	/* FSM_TEMPO */
3196	#define R367CAB_FSM_TEMPO 0xf469
3197	#define F367CAB_SIT 0xf46900c0
3198	#define F367CAB_WST 0xf4690038
3199	#define F367CAB_ELT 0xf4690006
3200	#define F367CAB_SNR3_HTH_HI 0xf4690001
3201
3202	/* FSM_CONFIG */
3203	#define R367CAB_FSM_CONFIG 0xf46a
3204	#define F367CAB_FEC2_DFEOFF 0xf46a0004
3205	#define F367CAB_PRIT_STATE 0xf46a0002
3206	#define F367CAB_MODMAP_STATE 0xf46a0001
3207
3208	/* EQU_I_TESTTAP_L */
3209	#define R367CAB_EQU_I_TESTTAP_L 0xf474
3210	#define F367CAB_I_TEST_TAP_L 0xf47400ff
3211
3212	/* EQU_I_TESTTAP_M */
3213	#define R367CAB_EQU_I_TESTTAP_M 0xf475
3214	#define F367CAB_I_TEST_TAP_M 0xf47500ff
3215
3216	/* EQU_I_TESTTAP_H */
3217	#define R367CAB_EQU_I_TESTTAP_H 0xf476
3218	#define F367CAB_I_TEST_TAP_H 0xf476001f
3219
3220	/* EQU_TESTAP_CFG */
3221	#define R367CAB_EQU_TESTAP_CFG 0xf477
3222	#define F367CAB_TEST_FFE_DFE_SEL 0xf4770040
3223	#define F367CAB_TEST_TAP_SELECT 0xf477003f
3224
3225	/* EQU_Q_TESTTAP_L */
3226	#define R367CAB_EQU_Q_TESTTAP_L 0xf478
3227	#define F367CAB_Q_TEST_TAP_L 0xf47800ff
3228
3229	/* EQU_Q_TESTTAP_M */
3230	#define R367CAB_EQU_Q_TESTTAP_M 0xf479
3231	#define F367CAB_Q_TEST_TAP_M 0xf47900ff
3232
3233	/* EQU_Q_TESTTAP_H */
3234	#define R367CAB_EQU_Q_TESTTAP_H 0xf47a
3235	#define F367CAB_Q_TEST_TAP_H 0xf47a001f
3236
3237	/* EQU_TAP_CTRL */
3238	#define R367CAB_EQU_TAP_CTRL 0xf47b
3239	#define F367CAB_MTAP_FRZ 0xf47b0010
3240	#define F367CAB_PRE_FREEZE 0xf47b0008
3241	#define F367CAB_DFE_TAPMON_EN 0xf47b0004
3242	#define F367CAB_FFE_TAPMON_EN 0xf47b0002
3243	#define F367CAB_MTAP_ONLY 0xf47b0001
3244
3245	/* EQU_CTR_CRL_CONTROL_L */
3246	#define R367CAB_EQU_CTR_CRL_CONTROL_L 0xf47c
3247	#define F367CAB_EQU_CTR_CRL_CONTROL_LO 0xf47c00ff
3248
3249	/* EQU_CTR_CRL_CONTROL_H */
3250	#define R367CAB_EQU_CTR_CRL_CONTROL_H 0xf47d
3251	#define F367CAB_EQU_CTR_CRL_CONTROL_HI 0xf47d00ff
3252
3253	/* EQU_CTR_HIPOW_L */
3254	#define R367CAB_EQU_CTR_HIPOW_L 0xf47e
3255	#define F367CAB_CTR_HIPOW_L 0xf47e00ff
3256
3257	/* EQU_CTR_HIPOW_H */
3258	#define R367CAB_EQU_CTR_HIPOW_H 0xf47f
3259	#define F367CAB_CTR_HIPOW_H 0xf47f00ff
3260
3261	/* EQU_I_EQU_LO */
3262	#define R367CAB_EQU_I_EQU_LO 0xf480
3263	#define F367CAB_EQU_I_EQU_L 0xf48000ff
3264
3265	/* EQU_I_EQU_HI */
3266	#define R367CAB_EQU_I_EQU_HI 0xf481
3267	#define F367CAB_EQU_I_EQU_H 0xf4810003
3268
3269	/* EQU_Q_EQU_LO */
3270	#define R367CAB_EQU_Q_EQU_LO 0xf482
3271	#define F367CAB_EQU_Q_EQU_L 0xf48200ff
3272
3273	/* EQU_Q_EQU_HI */
3274	#define R367CAB_EQU_Q_EQU_HI 0xf483
3275	#define F367CAB_EQU_Q_EQU_H 0xf4830003
3276
3277	/* EQU_MAPPER */
3278	#define R367CAB_EQU_MAPPER 0xf484
3279	#define F367CAB_QUAD_AUTO 0xf4840080
3280	#define F367CAB_QUAD_INV 0xf4840040
3281	#define F367CAB_QAM_MODE 0xf4840007
3282
3283	/* EQU_SWEEP_RATE */
3284	#define R367CAB_EQU_SWEEP_RATE 0xf485
3285	#define F367CAB_SNR_PER 0xf48500c0
3286	#define F367CAB_SWEEP_RATE 0xf485003f
3287
3288	/* EQU_SNR_LO */
3289	#define R367CAB_EQU_SNR_LO 0xf486
3290	#define F367CAB_SNR_LO 0xf48600ff
3291
3292	/* EQU_SNR_HI */
3293	#define R367CAB_EQU_SNR_HI 0xf487
3294	#define F367CAB_SNR_HI 0xf48700ff
3295
3296	/* EQU_GAMMA_LO */
3297	#define R367CAB_EQU_GAMMA_LO 0xf488
3298	#define F367CAB_GAMMA_LO 0xf48800ff
3299
3300	/* EQU_GAMMA_HI */
3301	#define R367CAB_EQU_GAMMA_HI 0xf489
3302	#define F367CAB_GAMMA_ME 0xf48900ff
3303
3304	/* EQU_ERR_GAIN */
3305	#define R367CAB_EQU_ERR_GAIN 0xf48a
3306	#define F367CAB_EQA1MU 0xf48a0070
3307	#define F367CAB_CRL2MU 0xf48a000e
3308	#define F367CAB_GAMMA_HI 0xf48a0001
3309
3310	/* EQU_RADIUS */
3311	#define R367CAB_EQU_RADIUS 0xf48b
3312	#define F367CAB_RADIUS 0xf48b00ff
3313
3314	/* EQU_FFE_MAINTAP */
3315	#define R367CAB_EQU_FFE_MAINTAP 0xf48c
3316	#define F367CAB_FFE_MAINTAP_INIT 0xf48c00ff
3317
3318	/* EQU_FFE_LEAKAGE */
3319	#define R367CAB_EQU_FFE_LEAKAGE 0xf48e
3320	#define F367CAB_LEAK_PER 0xf48e00f0
3321	#define F367CAB_EQU_OUTSEL 0xf48e0002
3322	#define F367CAB_PNT2dFE 0xf48e0001
3323
3324	/* EQU_FFE_MAINTAP_POS */
3325	#define R367CAB_EQU_FFE_MAINTAP_POS 0xf48f
3326	#define F367CAB_FFE_LEAK_EN 0xf48f0080
3327	#define F367CAB_DFE_LEAK_EN 0xf48f0040
3328	#define F367CAB_FFE_MAINTAP_POS 0xf48f003f
3329
3330	/* EQU_GAIN_WIDE */
3331	#define R367CAB_EQU_GAIN_WIDE 0xf490
3332	#define F367CAB_DFE_GAIN_WIDE 0xf49000f0
3333	#define F367CAB_FFE_GAIN_WIDE 0xf490000f
3334
3335	/* EQU_GAIN_NARROW */
3336	#define R367CAB_EQU_GAIN_NARROW 0xf491
3337	#define F367CAB_DFE_GAIN_NARROW 0xf49100f0
3338	#define F367CAB_FFE_GAIN_NARROW 0xf491000f
3339
3340	/* EQU_CTR_LPF_GAIN */
3341	#define R367CAB_EQU_CTR_LPF_GAIN 0xf492
3342	#define F367CAB_CTR_GTO 0xf4920080
3343	#define F367CAB_CTR_GDIR 0xf4920070
3344	#define F367CAB_SWEEP_EN 0xf4920008
3345	#define F367CAB_CTR_GINT 0xf4920007
3346
3347	/* EQU_CRL_LPF_GAIN */
3348	#define R367CAB_EQU_CRL_LPF_GAIN 0xf493
3349	#define F367CAB_CRL_GTO 0xf4930080
3350	#define F367CAB_CRL_GDIR 0xf4930070
3351	#define F367CAB_SWEEP_DIR 0xf4930008
3352	#define F367CAB_CRL_GINT 0xf4930007
3353
3354	/* EQU_GLOBAL_GAIN */
3355	#define R367CAB_EQU_GLOBAL_GAIN 0xf494
3356	#define F367CAB_CRL_GAIN 0xf49400f8
3357	#define F367CAB_CTR_INC_GAIN 0xf4940004
3358	#define F367CAB_CTR_FRAC 0xf4940003
3359
3360	/* EQU_CRL_LD_SEN */
3361	#define R367CAB_EQU_CRL_LD_SEN 0xf495
3362	#define F367CAB_CTR_BADPOINT_EN 0xf4950080
3363	#define F367CAB_CTR_GAIN 0xf4950070
3364	#define F367CAB_LIMANEN 0xf4950008
3365	#define F367CAB_CRL_LD_SEN 0xf4950007
3366
3367	/* EQU_CRL_LD_VAL */
3368	#define R367CAB_EQU_CRL_LD_VAL 0xf496
3369	#define F367CAB_CRL_BISTH_LIMIT 0xf4960080
3370	#define F367CAB_CARE_EN 0xf4960040
3371	#define F367CAB_CRL_LD_PER 0xf4960030
3372	#define F367CAB_CRL_LD_WST 0xf496000c
3373	#define F367CAB_CRL_LD_TFS 0xf4960003
3374
3375	/* EQU_CRL_TFR */
3376	#define R367CAB_EQU_CRL_TFR 0xf497
3377	#define F367CAB_CRL_LD_TFR 0xf49700ff
3378
3379	/* EQU_CRL_BISTH_LO */
3380	#define R367CAB_EQU_CRL_BISTH_LO 0xf498
3381	#define F367CAB_CRL_BISTH_LO 0xf49800ff
3382
3383	/* EQU_CRL_BISTH_HI */
3384	#define R367CAB_EQU_CRL_BISTH_HI 0xf499
3385	#define F367CAB_CRL_BISTH_HI 0xf49900ff
3386
3387	/* EQU_SWEEP_RANGE_LO */
3388	#define R367CAB_EQU_SWEEP_RANGE_LO 0xf49a
3389	#define F367CAB_SWEEP_RANGE_LO 0xf49a00ff
3390
3391	/* EQU_SWEEP_RANGE_HI */
3392	#define R367CAB_EQU_SWEEP_RANGE_HI 0xf49b
3393	#define F367CAB_SWEEP_RANGE_HI 0xf49b00ff
3394
3395	/* EQU_CRL_LIMITER */
3396	#define R367CAB_EQU_CRL_LIMITER 0xf49c
3397	#define F367CAB_BISECTOR_EN 0xf49c0080
3398	#define F367CAB_PHEST128_EN 0xf49c0040
3399	#define F367CAB_CRL_LIM 0xf49c003f
3400
3401	/* EQU_MODULUS_MAP */
3402	#define R367CAB_EQU_MODULUS_MAP 0xf49d
3403	#define F367CAB_PNT_DEPTH 0xf49d00e0
3404	#define F367CAB_MODULUS_CMP 0xf49d001f
3405
3406	/* EQU_PNT_GAIN */
3407	#define R367CAB_EQU_PNT_GAIN 0xf49e
3408	#define F367CAB_PNT_EN 0xf49e0080
3409	#define F367CAB_MODULUSMAP_EN 0xf49e0040
3410	#define F367CAB_PNT_GAIN 0xf49e003f
3411
3412	/* FEC_AC_CTR_0 */
3413	#define R367CAB_FEC_AC_CTR_0 0xf4a8
3414	#define F367CAB_BE_BYPASS 0xf4a80020
3415	#define F367CAB_REFRESH47 0xf4a80010
3416	#define F367CAB_CT_NBST 0xf4a80008
3417	#define F367CAB_TEI_ENA 0xf4a80004
3418	#define F367CAB_DS_ENA 0xf4a80002
3419	#define F367CAB_TSMF_EN 0xf4a80001
3420
3421	/* FEC_AC_CTR_1 */
3422	#define R367CAB_FEC_AC_CTR_1 0xf4a9
3423	#define F367CAB_DEINT_DEPTH 0xf4a900ff
3424
3425	/* FEC_AC_CTR_2 */
3426	#define R367CAB_FEC_AC_CTR_2 0xf4aa
3427	#define F367CAB_DEINT_M 0xf4aa00f8
3428	#define F367CAB_DIS_UNLOCK 0xf4aa0004
3429	#define F367CAB_DESCR_MODE 0xf4aa0003
3430
3431	/* FEC_AC_CTR_3 */
3432	#define R367CAB_FEC_AC_CTR_3 0xf4ab
3433	#define F367CAB_DI_UNLOCK 0xf4ab0080
3434	#define F367CAB_DI_FREEZE 0xf4ab0040
3435	#define F367CAB_MISMATCH 0xf4ab0030
3436	#define F367CAB_ACQ_MODE 0xf4ab000c
3437	#define F367CAB_TRK_MODE 0xf4ab0003
3438
3439	/* FEC_STATUS */
3440	#define R367CAB_FEC_STATUS 0xf4ac
3441	#define F367CAB_DEINT_SMCNTR 0xf4ac00e0
3442	#define F367CAB_DEINT_SYNCSTATE 0xf4ac0018
3443	#define F367CAB_DEINT_SYNLOST 0xf4ac0004
3444	#define F367CAB_DESCR_SYNCSTATE 0xf4ac0002
3445
3446	/* RS_COUNTER_0 */
3447	#define R367CAB_RS_COUNTER_0 0xf4ae
3448	#define F367CAB_BK_CT_L 0xf4ae00ff
3449
3450	/* RS_COUNTER_1 */
3451	#define R367CAB_RS_COUNTER_1 0xf4af
3452	#define F367CAB_BK_CT_H 0xf4af00ff
3453
3454	/* RS_COUNTER_2 */
3455	#define R367CAB_RS_COUNTER_2 0xf4b0
3456	#define F367CAB_CORR_CT_L 0xf4b000ff
3457
3458	/* RS_COUNTER_3 */
3459	#define R367CAB_RS_COUNTER_3 0xf4b1
3460	#define F367CAB_CORR_CT_H 0xf4b100ff
3461
3462	/* RS_COUNTER_4 */
3463	#define R367CAB_RS_COUNTER_4 0xf4b2
3464	#define F367CAB_UNCORR_CT_L 0xf4b200ff
3465
3466	/* RS_COUNTER_5 */
3467	#define R367CAB_RS_COUNTER_5 0xf4b3
3468	#define F367CAB_UNCORR_CT_H 0xf4b300ff
3469
3470	/* BERT_0 */
3471	#define R367CAB_BERT_0 0xf4b4
3472	#define F367CAB_RS_NOCORR 0xf4b40004
3473	#define F367CAB_CT_HOLD 0xf4b40002
3474	#define F367CAB_CT_CLEAR 0xf4b40001
3475
3476	/* BERT_1 */
3477	#define R367CAB_BERT_1 0xf4b5
3478	#define F367CAB_BERT_ON 0xf4b50020
3479	#define F367CAB_BERT_ERR_SRC 0xf4b50010
3480	#define F367CAB_BERT_ERR_MODE 0xf4b50008
3481	#define F367CAB_BERT_NBYTE 0xf4b50007
3482
3483	/* BERT_2 */
3484	#define R367CAB_BERT_2 0xf4b6
3485	#define F367CAB_BERT_ERRCOUNT_L 0xf4b600ff
3486
3487	/* BERT_3 */
3488	#define R367CAB_BERT_3 0xf4b7
3489	#define F367CAB_BERT_ERRCOUNT_H 0xf4b700ff
3490
3491	/* OUTFORMAT_0 */
3492	#define R367CAB_OUTFORMAT_0 0xf4b8
3493	#define F367CAB_CLK_POLARITY 0xf4b80080
3494	#define F367CAB_FEC_TYPE 0xf4b80040
3495	#define F367CAB_SYNC_STRIP 0xf4b80008
3496	#define F367CAB_TS_SWAP 0xf4b80004
3497	#define F367CAB_OUTFORMAT 0xf4b80003
3498
3499	/* OUTFORMAT_1 */
3500	#define R367CAB_OUTFORMAT_1 0xf4b9
3501	#define F367CAB_CI_DIVRANGE 0xf4b900ff
3502
3503	/* SMOOTHER_2 */
3504	#define R367CAB_SMOOTHER_2 0xf4be
3505	#define F367CAB_FIFO_BYPASS 0xf4be0020
3506
3507	/* TSMF_CTRL_0 */
3508	#define R367CAB_TSMF_CTRL_0 0xf4c0
3509	#define F367CAB_TS_NUMBER 0xf4c0001e
3510	#define F367CAB_SEL_MODE 0xf4c00001
3511
3512	/* TSMF_CTRL_1 */
3513	#define R367CAB_TSMF_CTRL_1 0xf4c1
3514	#define F367CAB_CHECK_ERROR_BIT 0xf4c10080
3515	#define F367CAB_CHCK_F_SYNC 0xf4c10040
3516	#define F367CAB_H_MODE 0xf4c10008
3517	#define F367CAB_D_V_MODE 0xf4c10004
3518	#define F367CAB_MODE 0xf4c10003
3519
3520	/* TSMF_CTRL_3 */
3521	#define R367CAB_TSMF_CTRL_3 0xf4c3
3522	#define F367CAB_SYNC_IN_COUNT 0xf4c300f0
3523	#define F367CAB_SYNC_OUT_COUNT 0xf4c3000f
3524
3525	/* TS_ON_ID_0 */
3526	#define R367CAB_TS_ON_ID_0 0xf4c4
3527	#define F367CAB_TS_ID_L 0xf4c400ff
3528
3529	/* TS_ON_ID_1 */
3530	#define R367CAB_TS_ON_ID_1 0xf4c5
3531	#define F367CAB_TS_ID_H 0xf4c500ff
3532
3533	/* TS_ON_ID_2 */
3534	#define R367CAB_TS_ON_ID_2 0xf4c6
3535	#define F367CAB_ON_ID_L 0xf4c600ff
3536
3537	/* TS_ON_ID_3 */
3538	#define R367CAB_TS_ON_ID_3 0xf4c7
3539	#define F367CAB_ON_ID_H 0xf4c700ff
3540
3541	/* RE_STATUS_0 */
3542	#define R367CAB_RE_STATUS_0 0xf4c8
3543	#define F367CAB_RECEIVE_STATUS_L 0xf4c800ff
3544
3545	/* RE_STATUS_1 */
3546	#define R367CAB_RE_STATUS_1 0xf4c9
3547	#define F367CAB_RECEIVE_STATUS_LH 0xf4c900ff
3548
3549	/* RE_STATUS_2 */
3550	#define R367CAB_RE_STATUS_2 0xf4ca
3551	#define F367CAB_RECEIVE_STATUS_HL 0xf4ca00ff
3552
3553	/* RE_STATUS_3 */
3554	#define R367CAB_RE_STATUS_3 0xf4cb
3555	#define F367CAB_RECEIVE_STATUS_HH 0xf4cb003f
3556
3557	/* TS_STATUS_0 */
3558	#define R367CAB_TS_STATUS_0 0xf4cc
3559	#define F367CAB_TS_STATUS_L 0xf4cc00ff
3560
3561	/* TS_STATUS_1 */
3562	#define R367CAB_TS_STATUS_1 0xf4cd
3563	#define F367CAB_TS_STATUS_H 0xf4cd007f
3564
3565	/* TS_STATUS_2 */
3566	#define R367CAB_TS_STATUS_2 0xf4ce
3567	#define F367CAB_ERROR 0xf4ce0080
3568	#define F367CAB_EMERGENCY 0xf4ce0040
3569	#define F367CAB_CRE_TS 0xf4ce0030
3570	#define F367CAB_VER 0xf4ce000e
3571	#define F367CAB_M_LOCK 0xf4ce0001
3572
3573	/* TS_STATUS_3 */
3574	#define R367CAB_TS_STATUS_3 0xf4cf
3575	#define F367CAB_UPDATE_READY 0xf4cf0080
3576	#define F367CAB_END_FRAME_HEADER 0xf4cf0040
3577	#define F367CAB_CONTCNT 0xf4cf0020
3578	#define F367CAB_TS_IDENTIFIER_SEL 0xf4cf000f
3579
3580	/* T_O_ID_0 */
3581	#define R367CAB_T_O_ID_0 0xf4d0
3582	#define F367CAB_ON_ID_I_L 0xf4d000ff
3583
3584	/* T_O_ID_1 */
3585	#define R367CAB_T_O_ID_1 0xf4d1
3586	#define F367CAB_ON_ID_I_H 0xf4d100ff
3587
3588	/* T_O_ID_2 */
3589	#define R367CAB_T_O_ID_2 0xf4d2
3590	#define F367CAB_TS_ID_I_L 0xf4d200ff
3591
3592	/* T_O_ID_3 */
3593	#define R367CAB_T_O_ID_3 0xf4d3
3594	#define F367CAB_TS_ID_I_H 0xf4d300ff
3595
3596	#endif
3597