1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * stv0900_reg.h
4 *
5 * Driver for ST STV0900 satellite demodulator IC.
6 *
7 * Copyright (C) ST Microelectronics.
8 * Copyright (C) 2009 NetUP Inc.
9 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
10 */
11
12#ifndef STV0900_REG_H
13#define STV0900_REG_H
14
15extern s32 shiftx(s32 x, int demod, s32 shift);
16
17#define REGx(x) shiftx(x, demod, 0x200)
18#define FLDx(x) shiftx(x, demod, 0x2000000)
19
20/*MID*/
21#define R0900_MID 0xf100
22#define F0900_MCHIP_IDENT 0xf10000f0
23#define F0900_MRELEASE 0xf100000f
24
25/*DACR1*/
26#define R0900_DACR1 0xf113
27#define F0900_DAC_MODE 0xf11300e0
28#define F0900_DAC_VALUE1 0xf113000f
29
30/*DACR2*/
31#define R0900_DACR2 0xf114
32#define F0900_DAC_VALUE0 0xf11400ff
33
34/*OUTCFG*/
35#define R0900_OUTCFG 0xf11c
36#define F0900_OUTSERRS1_HZ 0xf11c0040
37#define F0900_OUTSERRS2_HZ 0xf11c0020
38#define F0900_OUTSERRS3_HZ 0xf11c0010
39#define F0900_OUTPARRS3_HZ 0xf11c0008
40
41/*IRQSTATUS3*/
42#define R0900_IRQSTATUS3 0xf120
43#define F0900_SPLL_LOCK 0xf1200020
44#define F0900_SSTREAM_LCK_3 0xf1200010
45#define F0900_SSTREAM_LCK_2 0xf1200008
46#define F0900_SSTREAM_LCK_1 0xf1200004
47#define F0900_SDVBS1_PRF_2 0xf1200002
48#define F0900_SDVBS1_PRF_1 0xf1200001
49
50/*IRQSTATUS2*/
51#define R0900_IRQSTATUS2 0xf121
52#define F0900_SSPY_ENDSIM_3 0xf1210080
53#define F0900_SSPY_ENDSIM_2 0xf1210040
54#define F0900_SSPY_ENDSIM_1 0xf1210020
55#define F0900_SPKTDEL_ERROR_2 0xf1210010
56#define F0900_SPKTDEL_LOCKB_2 0xf1210008
57#define F0900_SPKTDEL_LOCK_2 0xf1210004
58#define F0900_SPKTDEL_ERROR_1 0xf1210002
59#define F0900_SPKTDEL_LOCKB_1 0xf1210001
60
61/*IRQSTATUS1*/
62#define R0900_IRQSTATUS1 0xf122
63#define F0900_SPKTDEL_LOCK_1 0xf1220080
64#define F0900_SDEMOD_LOCKB_2 0xf1220004
65#define F0900_SDEMOD_LOCK_2 0xf1220002
66#define F0900_SDEMOD_IRQ_2 0xf1220001
67
68/*IRQSTATUS0*/
69#define R0900_IRQSTATUS0 0xf123
70#define F0900_SDEMOD_LOCKB_1 0xf1230080
71#define F0900_SDEMOD_LOCK_1 0xf1230040
72#define F0900_SDEMOD_IRQ_1 0xf1230020
73#define F0900_SBCH_ERRFLAG 0xf1230010
74#define F0900_SDISEQC2RX_IRQ 0xf1230008
75#define F0900_SDISEQC2TX_IRQ 0xf1230004
76#define F0900_SDISEQC1RX_IRQ 0xf1230002
77#define F0900_SDISEQC1TX_IRQ 0xf1230001
78
79/*IRQMASK3*/
80#define R0900_IRQMASK3 0xf124
81#define F0900_MPLL_LOCK 0xf1240020
82#define F0900_MSTREAM_LCK_3 0xf1240010
83#define F0900_MSTREAM_LCK_2 0xf1240008
84#define F0900_MSTREAM_LCK_1 0xf1240004
85#define F0900_MDVBS1_PRF_2 0xf1240002
86#define F0900_MDVBS1_PRF_1 0xf1240001
87
88/*IRQMASK2*/
89#define R0900_IRQMASK2 0xf125
90#define F0900_MSPY_ENDSIM_3 0xf1250080
91#define F0900_MSPY_ENDSIM_2 0xf1250040
92#define F0900_MSPY_ENDSIM_1 0xf1250020
93#define F0900_MPKTDEL_ERROR_2 0xf1250010
94#define F0900_MPKTDEL_LOCKB_2 0xf1250008
95#define F0900_MPKTDEL_LOCK_2 0xf1250004
96#define F0900_MPKTDEL_ERROR_1 0xf1250002
97#define F0900_MPKTDEL_LOCKB_1 0xf1250001
98
99/*IRQMASK1*/
100#define R0900_IRQMASK1 0xf126
101#define F0900_MPKTDEL_LOCK_1 0xf1260080
102#define F0900_MEXTPINB2 0xf1260040
103#define F0900_MEXTPIN2 0xf1260020
104#define F0900_MEXTPINB1 0xf1260010
105#define F0900_MEXTPIN1 0xf1260008
106#define F0900_MDEMOD_LOCKB_2 0xf1260004
107#define F0900_MDEMOD_LOCK_2 0xf1260002
108#define F0900_MDEMOD_IRQ_2 0xf1260001
109
110/*IRQMASK0*/
111#define R0900_IRQMASK0 0xf127
112#define F0900_MDEMOD_LOCKB_1 0xf1270080
113#define F0900_MDEMOD_LOCK_1 0xf1270040
114#define F0900_MDEMOD_IRQ_1 0xf1270020
115#define F0900_MBCH_ERRFLAG 0xf1270010
116#define F0900_MDISEQC2RX_IRQ 0xf1270008
117#define F0900_MDISEQC2TX_IRQ 0xf1270004
118#define F0900_MDISEQC1RX_IRQ 0xf1270002
119#define F0900_MDISEQC1TX_IRQ 0xf1270001
120
121/*I2CCFG*/
122#define R0900_I2CCFG 0xf129
123#define F0900_I2C_FASTMODE 0xf1290008
124#define F0900_I2CADDR_INC 0xf1290003
125
126/*P1_I2CRPT*/
127#define R0900_P1_I2CRPT 0xf12a
128#define I2CRPT shiftx(R0900_P1_I2CRPT, demod, -1)
129#define F0900_P1_I2CT_ON 0xf12a0080
130#define I2CT_ON shiftx(F0900_P1_I2CT_ON, demod, -0x10000)
131#define F0900_P1_ENARPT_LEVEL 0xf12a0070
132#define F0900_P1_SCLT_DELAY 0xf12a0008
133#define F0900_P1_STOP_ENABLE 0xf12a0004
134#define F0900_P1_STOP_SDAT2SDA 0xf12a0002
135
136/*P2_I2CRPT*/
137#define R0900_P2_I2CRPT 0xf12b
138#define F0900_P2_I2CT_ON 0xf12b0080
139#define F0900_P2_ENARPT_LEVEL 0xf12b0070
140#define F0900_P2_SCLT_DELAY 0xf12b0008
141#define F0900_P2_STOP_ENABLE 0xf12b0004
142#define F0900_P2_STOP_SDAT2SDA 0xf12b0002
143
144/*IOPVALUE6*/
145#define R0900_IOPVALUE6 0xf138
146#define F0900_VSCL 0xf1380004
147#define F0900_VSDA 0xf1380002
148#define F0900_VDATA3_0 0xf1380001
149
150/*IOPVALUE5*/
151#define R0900_IOPVALUE5 0xf139
152#define F0900_VDATA3_1 0xf1390080
153#define F0900_VDATA3_2 0xf1390040
154#define F0900_VDATA3_3 0xf1390020
155#define F0900_VDATA3_4 0xf1390010
156#define F0900_VDATA3_5 0xf1390008
157#define F0900_VDATA3_6 0xf1390004
158#define F0900_VDATA3_7 0xf1390002
159#define F0900_VCLKOUT3 0xf1390001
160
161/*IOPVALUE4*/
162#define R0900_IOPVALUE4 0xf13a
163#define F0900_VSTROUT3 0xf13a0080
164#define F0900_VDPN3 0xf13a0040
165#define F0900_VERROR3 0xf13a0020
166#define F0900_VDATA2_7 0xf13a0010
167#define F0900_VCLKOUT2 0xf13a0008
168#define F0900_VSTROUT2 0xf13a0004
169#define F0900_VDPN2 0xf13a0002
170#define F0900_VERROR2 0xf13a0001
171
172/*IOPVALUE3*/
173#define R0900_IOPVALUE3 0xf13b
174#define F0900_VDATA1_7 0xf13b0080
175#define F0900_VCLKOUT1 0xf13b0040
176#define F0900_VSTROUT1 0xf13b0020
177#define F0900_VDPN1 0xf13b0010
178#define F0900_VERROR1 0xf13b0008
179#define F0900_VCLKOUT27 0xf13b0004
180#define F0900_VDISEQCOUT2 0xf13b0002
181#define F0900_VSCLT2 0xf13b0001
182
183/*IOPVALUE2*/
184#define R0900_IOPVALUE2 0xf13c
185#define F0900_VSDAT2 0xf13c0080
186#define F0900_VAGCRF2 0xf13c0040
187#define F0900_VDISEQCOUT1 0xf13c0020
188#define F0900_VSCLT1 0xf13c0010
189#define F0900_VSDAT1 0xf13c0008
190#define F0900_VAGCRF1 0xf13c0004
191#define F0900_VDIRCLK 0xf13c0002
192#define F0900_VSTDBY 0xf13c0001
193
194/*IOPVALUE1*/
195#define R0900_IOPVALUE1 0xf13d
196#define F0900_VCS1 0xf13d0080
197#define F0900_VCS0 0xf13d0040
198#define F0900_VGPIO13 0xf13d0020
199#define F0900_VGPIO12 0xf13d0010
200#define F0900_VGPIO11 0xf13d0008
201#define F0900_VGPIO10 0xf13d0004
202#define F0900_VGPIO9 0xf13d0002
203#define F0900_VGPIO8 0xf13d0001
204
205/*IOPVALUE0*/
206#define R0900_IOPVALUE0 0xf13e
207#define F0900_VGPIO7 0xf13e0080
208#define F0900_VGPIO6 0xf13e0040
209#define F0900_VGPIO5 0xf13e0020
210#define F0900_VGPIO4 0xf13e0010
211#define F0900_VGPIO3 0xf13e0008
212#define F0900_VGPIO2 0xf13e0004
213#define F0900_VGPIO1 0xf13e0002
214#define F0900_VCLKI2 0xf13e0001
215
216/*CLKI2CFG*/
217#define R0900_CLKI2CFG 0xf140
218#define F0900_CLKI2_OPD 0xf1400080
219#define F0900_CLKI2_CONFIG 0xf140007e
220#define F0900_CLKI2_XOR 0xf1400001
221
222/*GPIO1CFG*/
223#define R0900_GPIO1CFG 0xf141
224#define F0900_GPIO1_OPD 0xf1410080
225#define F0900_GPIO1_CONFIG 0xf141007e
226#define F0900_GPIO1_XOR 0xf1410001
227
228/*GPIO2CFG*/
229#define R0900_GPIO2CFG 0xf142
230#define F0900_GPIO2_OPD 0xf1420080
231#define F0900_GPIO2_CONFIG 0xf142007e
232#define F0900_GPIO2_XOR 0xf1420001
233
234/*GPIO3CFG*/
235#define R0900_GPIO3CFG 0xf143
236#define F0900_GPIO3_OPD 0xf1430080
237#define F0900_GPIO3_CONFIG 0xf143007e
238#define F0900_GPIO3_XOR 0xf1430001
239
240/*GPIO4CFG*/
241#define R0900_GPIO4CFG 0xf144
242#define F0900_GPIO4_OPD 0xf1440080
243#define F0900_GPIO4_CONFIG 0xf144007e
244#define F0900_GPIO4_XOR 0xf1440001
245
246/*GPIO5CFG*/
247#define R0900_GPIO5CFG 0xf145
248#define F0900_GPIO5_OPD 0xf1450080
249#define F0900_GPIO5_CONFIG 0xf145007e
250#define F0900_GPIO5_XOR 0xf1450001
251
252/*GPIO6CFG*/
253#define R0900_GPIO6CFG 0xf146
254#define F0900_GPIO6_OPD 0xf1460080
255#define F0900_GPIO6_CONFIG 0xf146007e
256#define F0900_GPIO6_XOR 0xf1460001
257
258/*GPIO7CFG*/
259#define R0900_GPIO7CFG 0xf147
260#define F0900_GPIO7_OPD 0xf1470080
261#define F0900_GPIO7_CONFIG 0xf147007e
262#define F0900_GPIO7_XOR 0xf1470001
263
264/*GPIO8CFG*/
265#define R0900_GPIO8CFG 0xf148
266#define F0900_GPIO8_OPD 0xf1480080
267#define F0900_GPIO8_CONFIG 0xf148007e
268#define F0900_GPIO8_XOR 0xf1480001
269
270/*GPIO9CFG*/
271#define R0900_GPIO9CFG 0xf149
272#define F0900_GPIO9_OPD 0xf1490080
273#define F0900_GPIO9_CONFIG 0xf149007e
274#define F0900_GPIO9_XOR 0xf1490001
275
276/*GPIO10CFG*/
277#define R0900_GPIO10CFG 0xf14a
278#define F0900_GPIO10_OPD 0xf14a0080
279#define F0900_GPIO10_CONFIG 0xf14a007e
280#define F0900_GPIO10_XOR 0xf14a0001
281
282/*GPIO11CFG*/
283#define R0900_GPIO11CFG 0xf14b
284#define F0900_GPIO11_OPD 0xf14b0080
285#define F0900_GPIO11_CONFIG 0xf14b007e
286#define F0900_GPIO11_XOR 0xf14b0001
287
288/*GPIO12CFG*/
289#define R0900_GPIO12CFG 0xf14c
290#define F0900_GPIO12_OPD 0xf14c0080
291#define F0900_GPIO12_CONFIG 0xf14c007e
292#define F0900_GPIO12_XOR 0xf14c0001
293
294/*GPIO13CFG*/
295#define R0900_GPIO13CFG 0xf14d
296#define F0900_GPIO13_OPD 0xf14d0080
297#define F0900_GPIO13_CONFIG 0xf14d007e
298#define F0900_GPIO13_XOR 0xf14d0001
299
300/*CS0CFG*/
301#define R0900_CS0CFG 0xf14e
302#define F0900_CS0_OPD 0xf14e0080
303#define F0900_CS0_CONFIG 0xf14e007e
304#define F0900_CS0_XOR 0xf14e0001
305
306/*CS1CFG*/
307#define R0900_CS1CFG 0xf14f
308#define F0900_CS1_OPD 0xf14f0080
309#define F0900_CS1_CONFIG 0xf14f007e
310#define F0900_CS1_XOR 0xf14f0001
311
312/*STDBYCFG*/
313#define R0900_STDBYCFG 0xf150
314#define F0900_STDBY_OPD 0xf1500080
315#define F0900_STDBY_CONFIG 0xf150007e
316#define F0900_STBDY_XOR 0xf1500001
317
318/*DIRCLKCFG*/
319#define R0900_DIRCLKCFG 0xf151
320#define F0900_DIRCLK_OPD 0xf1510080
321#define F0900_DIRCLK_CONFIG 0xf151007e
322#define F0900_DIRCLK_XOR 0xf1510001
323
324/*AGCRF1CFG*/
325#define R0900_AGCRF1CFG 0xf152
326#define F0900_AGCRF1_OPD 0xf1520080
327#define F0900_AGCRF1_CONFIG 0xf152007e
328#define F0900_AGCRF1_XOR 0xf1520001
329
330/*SDAT1CFG*/
331#define R0900_SDAT1CFG 0xf153
332#define F0900_SDAT1_OPD 0xf1530080
333#define F0900_SDAT1_CONFIG 0xf153007e
334#define F0900_SDAT1_XOR 0xf1530001
335
336/*SCLT1CFG*/
337#define R0900_SCLT1CFG 0xf154
338#define F0900_SCLT1_OPD 0xf1540080
339#define F0900_SCLT1_CONFIG 0xf154007e
340#define F0900_SCLT1_XOR 0xf1540001
341
342/*DISEQCO1CFG*/
343#define R0900_DISEQCO1CFG 0xf155
344#define F0900_DISEQCO1_OPD 0xf1550080
345#define F0900_DISEQCO1_CONFIG 0xf155007e
346#define F0900_DISEQC1_XOR 0xf1550001
347
348/*AGCRF2CFG*/
349#define R0900_AGCRF2CFG 0xf156
350#define F0900_AGCRF2_OPD 0xf1560080
351#define F0900_AGCRF2_CONFIG 0xf156007e
352#define F0900_AGCRF2_XOR 0xf1560001
353
354/*SDAT2CFG*/
355#define R0900_SDAT2CFG 0xf157
356#define F0900_SDAT2_OPD 0xf1570080
357#define F0900_SDAT2_CONFIG 0xf157007e
358#define F0900_SDAT2_XOR 0xf1570001
359
360/*SCLT2CFG*/
361#define R0900_SCLT2CFG 0xf158
362#define F0900_SCLT2_OPD 0xf1580080
363#define F0900_SCLT2_CONFIG 0xf158007e
364#define F0900_SCLT2_XOR 0xf1580001
365
366/*DISEQCO2CFG*/
367#define R0900_DISEQCO2CFG 0xf159
368#define F0900_DISEQCO2_OPD 0xf1590080
369#define F0900_DISEQCO2_CONFIG 0xf159007e
370#define F0900_DISEQC2_XOR 0xf1590001
371
372/*CLKOUT27CFG*/
373#define R0900_CLKOUT27CFG 0xf15a
374#define F0900_CLKOUT27_OPD 0xf15a0080
375#define F0900_CLKOUT27_CONFIG 0xf15a007e
376#define F0900_CLKOUT27_XOR 0xf15a0001
377
378/*ERROR1CFG*/
379#define R0900_ERROR1CFG 0xf15b
380#define F0900_ERROR1_OPD 0xf15b0080
381#define F0900_ERROR1_CONFIG 0xf15b007e
382#define F0900_ERROR1_XOR 0xf15b0001
383
384/*DPN1CFG*/
385#define R0900_DPN1CFG 0xf15c
386#define F0900_DPN1_OPD 0xf15c0080
387#define F0900_DPN1_CONFIG 0xf15c007e
388#define F0900_DPN1_XOR 0xf15c0001
389
390/*STROUT1CFG*/
391#define R0900_STROUT1CFG 0xf15d
392#define F0900_STROUT1_OPD 0xf15d0080
393#define F0900_STROUT1_CONFIG 0xf15d007e
394#define F0900_STROUT1_XOR 0xf15d0001
395
396/*CLKOUT1CFG*/
397#define R0900_CLKOUT1CFG 0xf15e
398#define F0900_CLKOUT1_OPD 0xf15e0080
399#define F0900_CLKOUT1_CONFIG 0xf15e007e
400#define F0900_CLKOUT1_XOR 0xf15e0001
401
402/*DATA71CFG*/
403#define R0900_DATA71CFG 0xf15f
404#define F0900_DATA71_OPD 0xf15f0080
405#define F0900_DATA71_CONFIG 0xf15f007e
406#define F0900_DATA71_XOR 0xf15f0001
407
408/*ERROR2CFG*/
409#define R0900_ERROR2CFG 0xf160
410#define F0900_ERROR2_OPD 0xf1600080
411#define F0900_ERROR2_CONFIG 0xf160007e
412#define F0900_ERROR2_XOR 0xf1600001
413
414/*DPN2CFG*/
415#define R0900_DPN2CFG 0xf161
416#define F0900_DPN2_OPD 0xf1610080
417#define F0900_DPN2_CONFIG 0xf161007e
418#define F0900_DPN2_XOR 0xf1610001
419
420/*STROUT2CFG*/
421#define R0900_STROUT2CFG 0xf162
422#define F0900_STROUT2_OPD 0xf1620080
423#define F0900_STROUT2_CONFIG 0xf162007e
424#define F0900_STROUT2_XOR 0xf1620001
425
426/*CLKOUT2CFG*/
427#define R0900_CLKOUT2CFG 0xf163
428#define F0900_CLKOUT2_OPD 0xf1630080
429#define F0900_CLKOUT2_CONFIG 0xf163007e
430#define F0900_CLKOUT2_XOR 0xf1630001
431
432/*DATA72CFG*/
433#define R0900_DATA72CFG 0xf164
434#define F0900_DATA72_OPD 0xf1640080
435#define F0900_DATA72_CONFIG 0xf164007e
436#define F0900_DATA72_XOR 0xf1640001
437
438/*ERROR3CFG*/
439#define R0900_ERROR3CFG 0xf165
440#define F0900_ERROR3_OPD 0xf1650080
441#define F0900_ERROR3_CONFIG 0xf165007e
442#define F0900_ERROR3_XOR 0xf1650001
443
444/*DPN3CFG*/
445#define R0900_DPN3CFG 0xf166
446#define F0900_DPN3_OPD 0xf1660080
447#define F0900_DPN3_CONFIG 0xf166007e
448#define F0900_DPN3_XOR 0xf1660001
449
450/*STROUT3CFG*/
451#define R0900_STROUT3CFG 0xf167
452#define F0900_STROUT3_OPD 0xf1670080
453#define F0900_STROUT3_CONFIG 0xf167007e
454#define F0900_STROUT3_XOR 0xf1670001
455
456/*CLKOUT3CFG*/
457#define R0900_CLKOUT3CFG 0xf168
458#define F0900_CLKOUT3_OPD 0xf1680080
459#define F0900_CLKOUT3_CONFIG 0xf168007e
460#define F0900_CLKOUT3_XOR 0xf1680001
461
462/*DATA73CFG*/
463#define R0900_DATA73CFG 0xf169
464#define F0900_DATA73_OPD 0xf1690080
465#define F0900_DATA73_CONFIG 0xf169007e
466#define F0900_DATA73_XOR 0xf1690001
467
468/*STRSTATUS1*/
469#define R0900_STRSTATUS1 0xf16a
470#define F0900_STRSTATUS_SEL2 0xf16a00f0
471#define F0900_STRSTATUS_SEL1 0xf16a000f
472
473/*STRSTATUS2*/
474#define R0900_STRSTATUS2 0xf16b
475#define F0900_STRSTATUS_SEL4 0xf16b00f0
476#define F0900_STRSTATUS_SEL3 0xf16b000f
477
478/*STRSTATUS3*/
479#define R0900_STRSTATUS3 0xf16c
480#define F0900_STRSTATUS_SEL6 0xf16c00f0
481#define F0900_STRSTATUS_SEL5 0xf16c000f
482
483/*FSKTFC2*/
484#define R0900_FSKTFC2 0xf170
485#define F0900_FSKT_KMOD 0xf17000fc
486#define F0900_FSKT_CAR2 0xf1700003
487
488/*FSKTFC1*/
489#define R0900_FSKTFC1 0xf171
490#define F0900_FSKT_CAR1 0xf17100ff
491
492/*FSKTFC0*/
493#define R0900_FSKTFC0 0xf172
494#define F0900_FSKT_CAR0 0xf17200ff
495
496/*FSKTDELTAF1*/
497#define R0900_FSKTDELTAF1 0xf173
498#define F0900_FSKT_DELTAF1 0xf173000f
499
500/*FSKTDELTAF0*/
501#define R0900_FSKTDELTAF0 0xf174
502#define F0900_FSKT_DELTAF0 0xf17400ff
503
504/*FSKTCTRL*/
505#define R0900_FSKTCTRL 0xf175
506#define F0900_FSKT_EN_SGN 0xf1750040
507#define F0900_FSKT_MOD_SGN 0xf1750020
508#define F0900_FSKT_MOD_EN 0xf175001c
509#define F0900_FSKT_DACMODE 0xf1750003
510
511/*FSKRFC2*/
512#define R0900_FSKRFC2 0xf176
513#define F0900_FSKR_DETSGN 0xf1760040
514#define F0900_FSKR_OUTSGN 0xf1760020
515#define F0900_FSKR_KAGC 0xf176001c
516#define F0900_FSKR_CAR2 0xf1760003
517
518/*FSKRFC1*/
519#define R0900_FSKRFC1 0xf177
520#define F0900_FSKR_CAR1 0xf17700ff
521
522/*FSKRFC0*/
523#define R0900_FSKRFC0 0xf178
524#define F0900_FSKR_CAR0 0xf17800ff
525
526/*FSKRK1*/
527#define R0900_FSKRK1 0xf179
528#define F0900_FSKR_K1_EXP 0xf17900e0
529#define F0900_FSKR_K1_MANT 0xf179001f
530
531/*FSKRK2*/
532#define R0900_FSKRK2 0xf17a
533#define F0900_FSKR_K2_EXP 0xf17a00e0
534#define F0900_FSKR_K2_MANT 0xf17a001f
535
536/*FSKRAGCR*/
537#define R0900_FSKRAGCR 0xf17b
538#define F0900_FSKR_OUTCTL 0xf17b00c0
539#define F0900_FSKR_AGC_REF 0xf17b003f
540
541/*FSKRAGC*/
542#define R0900_FSKRAGC 0xf17c
543#define F0900_FSKR_AGC_ACCU 0xf17c00ff
544
545/*FSKRALPHA*/
546#define R0900_FSKRALPHA 0xf17d
547#define F0900_FSKR_ALPHA_EXP 0xf17d001c
548#define F0900_FSKR_ALPHA_M 0xf17d0003
549
550/*FSKRPLTH1*/
551#define R0900_FSKRPLTH1 0xf17e
552#define F0900_FSKR_BETA 0xf17e00f0
553#define F0900_FSKR_PLL_TRESH1 0xf17e000f
554
555/*FSKRPLTH0*/
556#define R0900_FSKRPLTH0 0xf17f
557#define F0900_FSKR_PLL_TRESH0 0xf17f00ff
558
559/*FSKRDF1*/
560#define R0900_FSKRDF1 0xf180
561#define F0900_FSKR_OUT 0xf1800080
562#define F0900_FSKR_DELTAF1 0xf180001f
563
564/*FSKRDF0*/
565#define R0900_FSKRDF0 0xf181
566#define F0900_FSKR_DELTAF0 0xf18100ff
567
568/*FSKRSTEPP*/
569#define R0900_FSKRSTEPP 0xf182
570#define F0900_FSKR_STEP_PLUS 0xf18200ff
571
572/*FSKRSTEPM*/
573#define R0900_FSKRSTEPM 0xf183
574#define F0900_FSKR_STEP_MINUS 0xf18300ff
575
576/*FSKRDET1*/
577#define R0900_FSKRDET1 0xf184
578#define F0900_FSKR_DETECT 0xf1840080
579#define F0900_FSKR_CARDET_ACCU1 0xf184000f
580
581/*FSKRDET0*/
582#define R0900_FSKRDET0 0xf185
583#define F0900_FSKR_CARDET_ACCU0 0xf18500ff
584
585/*FSKRDTH1*/
586#define R0900_FSKRDTH1 0xf186
587#define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0
588#define F0900_FSKR_CARDET_THRESH1 0xf186000f
589
590/*FSKRDTH0*/
591#define R0900_FSKRDTH0 0xf187
592#define F0900_FSKR_CARDET_THRESH0 0xf18700ff
593
594/*FSKRLOSS*/
595#define R0900_FSKRLOSS 0xf188
596#define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff
597
598/*P2_DISTXCTL*/
599#define R0900_P2_DISTXCTL 0xf190
600#define F0900_P2_TIM_OFF 0xf1900080
601#define F0900_P2_DISEQC_RESET 0xf1900040
602#define F0900_P2_TIM_CMD 0xf1900030
603#define F0900_P2_DIS_PRECHARGE 0xf1900008
604#define F0900_P2_DISTX_MODE 0xf1900007
605
606/*P2_DISRXCTL*/
607#define R0900_P2_DISRXCTL 0xf191
608#define F0900_P2_RECEIVER_ON 0xf1910080
609#define F0900_P2_IGNO_SHORT22K 0xf1910040
610#define F0900_P2_ONECHIP_TRX 0xf1910020
611#define F0900_P2_EXT_ENVELOP 0xf1910010
612#define F0900_P2_PIN_SELECT0 0xf191000c
613#define F0900_P2_IRQ_RXEND 0xf1910002
614#define F0900_P2_IRQ_4NBYTES 0xf1910001
615
616/*P2_DISRX_ST0*/
617#define R0900_P2_DISRX_ST0 0xf194
618#define F0900_P2_RX_END 0xf1940080
619#define F0900_P2_RX_ACTIVE 0xf1940040
620#define F0900_P2_SHORT_22KHZ 0xf1940020
621#define F0900_P2_CONT_TONE 0xf1940010
622#define F0900_P2_FIFO_4BREADY 0xf1940008
623#define F0900_P2_FIFO_EMPTY 0xf1940004
624#define F0900_P2_ABORT_DISRX 0xf1940001
625
626/*P2_DISRX_ST1*/
627#define R0900_P2_DISRX_ST1 0xf195
628#define F0900_P2_RX_FAIL 0xf1950080
629#define F0900_P2_FIFO_PARITYFAIL 0xf1950040
630#define F0900_P2_RX_NONBYTE 0xf1950020
631#define F0900_P2_FIFO_OVERFLOW 0xf1950010
632#define F0900_P2_FIFO_BYTENBR 0xf195000f
633
634/*P2_DISRXDATA*/
635#define R0900_P2_DISRXDATA 0xf196
636#define F0900_P2_DISRX_DATA 0xf19600ff
637
638/*P2_DISTXDATA*/
639#define R0900_P2_DISTXDATA 0xf197
640#define F0900_P2_DISEQC_FIFO 0xf19700ff
641
642/*P2_DISTXSTATUS*/
643#define R0900_P2_DISTXSTATUS 0xf198
644#define F0900_P2_TX_FAIL 0xf1980080
645#define F0900_P2_FIFO_FULL 0xf1980040
646#define F0900_P2_TX_IDLE 0xf1980020
647#define F0900_P2_GAP_BURST 0xf1980010
648#define F0900_P2_TXFIFO_BYTES 0xf198000f
649
650/*P2_F22TX*/
651#define R0900_P2_F22TX 0xf199
652#define F0900_P2_F22_REG 0xf19900ff
653
654/*P2_F22RX*/
655#define R0900_P2_F22RX 0xf19a
656#define F0900_P2_F22RX_REG 0xf19a00ff
657
658/*P2_ACRPRESC*/
659#define R0900_P2_ACRPRESC 0xf19c
660#define F0900_P2_ACR_PRESC 0xf19c0007
661
662/*P2_ACRDIV*/
663#define R0900_P2_ACRDIV 0xf19d
664#define F0900_P2_ACR_DIV 0xf19d00ff
665
666/*P1_DISTXCTL*/
667#define R0900_P1_DISTXCTL 0xf1a0
668#define DISTXCTL shiftx(R0900_P1_DISTXCTL, demod, 0x10)
669#define F0900_P1_TIM_OFF 0xf1a00080
670#define F0900_P1_DISEQC_RESET 0xf1a00040
671#define DISEQC_RESET shiftx(F0900_P1_DISEQC_RESET, demod, 0x100000)
672#define F0900_P1_TIM_CMD 0xf1a00030
673#define F0900_P1_DIS_PRECHARGE 0xf1a00008
674#define DIS_PRECHARGE shiftx(F0900_P1_DIS_PRECHARGE, demod, 0x100000)
675#define F0900_P1_DISTX_MODE 0xf1a00007
676#define DISTX_MODE shiftx(F0900_P1_DISTX_MODE, demod, 0x100000)
677
678/*P1_DISRXCTL*/
679#define R0900_P1_DISRXCTL 0xf1a1
680#define DISRXCTL shiftx(R0900_P1_DISRXCTL, demod, 0x10)
681#define F0900_P1_RECEIVER_ON 0xf1a10080
682#define F0900_P1_IGNO_SHORT22K 0xf1a10040
683#define F0900_P1_ONECHIP_TRX 0xf1a10020
684#define F0900_P1_EXT_ENVELOP 0xf1a10010
685#define F0900_P1_PIN_SELECT0 0xf1a1000c
686#define F0900_P1_IRQ_RXEND 0xf1a10002
687#define F0900_P1_IRQ_4NBYTES 0xf1a10001
688
689/*P1_DISRX_ST0*/
690#define R0900_P1_DISRX_ST0 0xf1a4
691#define DISRX_ST0 shiftx(R0900_P1_DISRX_ST0, demod, 0x10)
692#define F0900_P1_RX_END 0xf1a40080
693#define RX_END shiftx(F0900_P1_RX_END, demod, 0x100000)
694#define F0900_P1_RX_ACTIVE 0xf1a40040
695#define F0900_P1_SHORT_22KHZ 0xf1a40020
696#define F0900_P1_CONT_TONE 0xf1a40010
697#define F0900_P1_FIFO_4BREADY 0xf1a40008
698#define F0900_P1_FIFO_EMPTY 0xf1a40004
699#define F0900_P1_ABORT_DISRX 0xf1a40001
700
701/*P1_DISRX_ST1*/
702#define R0900_P1_DISRX_ST1 0xf1a5
703#define DISRX_ST1 shiftx(R0900_P1_DISRX_ST1, demod, 0x10)
704#define F0900_P1_RX_FAIL 0xf1a50080
705#define F0900_P1_FIFO_PARITYFAIL 0xf1a50040
706#define F0900_P1_RX_NONBYTE 0xf1a50020
707#define F0900_P1_FIFO_OVERFLOW 0xf1a50010
708#define F0900_P1_FIFO_BYTENBR 0xf1a5000f
709#define FIFO_BYTENBR shiftx(F0900_P1_FIFO_BYTENBR, demod, 0x100000)
710
711/*P1_DISRXDATA*/
712#define R0900_P1_DISRXDATA 0xf1a6
713#define DISRXDATA shiftx(R0900_P1_DISRXDATA, demod, 0x10)
714#define F0900_P1_DISRX_DATA 0xf1a600ff
715
716/*P1_DISTXDATA*/
717#define R0900_P1_DISTXDATA 0xf1a7
718#define DISTXDATA shiftx(R0900_P1_DISTXDATA, demod, 0x10)
719#define F0900_P1_DISEQC_FIFO 0xf1a700ff
720
721/*P1_DISTXSTATUS*/
722#define R0900_P1_DISTXSTATUS 0xf1a8
723#define F0900_P1_TX_FAIL 0xf1a80080
724#define F0900_P1_FIFO_FULL 0xf1a80040
725#define FIFO_FULL shiftx(F0900_P1_FIFO_FULL, demod, 0x100000)
726#define F0900_P1_TX_IDLE 0xf1a80020
727#define TX_IDLE shiftx(F0900_P1_TX_IDLE, demod, 0x100000)
728#define F0900_P1_GAP_BURST 0xf1a80010
729#define F0900_P1_TXFIFO_BYTES 0xf1a8000f
730
731/*P1_F22TX*/
732#define R0900_P1_F22TX 0xf1a9
733#define F22TX shiftx(R0900_P1_F22TX, demod, 0x10)
734#define F0900_P1_F22_REG 0xf1a900ff
735
736/*P1_F22RX*/
737#define R0900_P1_F22RX 0xf1aa
738#define F22RX shiftx(R0900_P1_F22RX, demod, 0x10)
739#define F0900_P1_F22RX_REG 0xf1aa00ff
740
741/*P1_ACRPRESC*/
742#define R0900_P1_ACRPRESC 0xf1ac
743#define ACRPRESC shiftx(R0900_P1_ACRPRESC, demod, 0x10)
744#define F0900_P1_ACR_PRESC 0xf1ac0007
745
746/*P1_ACRDIV*/
747#define R0900_P1_ACRDIV 0xf1ad
748#define ACRDIV shiftx(R0900_P1_ACRDIV, demod, 0x10)
749#define F0900_P1_ACR_DIV 0xf1ad00ff
750
751/*NCOARSE*/
752#define R0900_NCOARSE 0xf1b3
753#define F0900_M_DIV 0xf1b300ff
754
755/*SYNTCTRL*/
756#define R0900_SYNTCTRL 0xf1b6
757#define F0900_STANDBY 0xf1b60080
758#define F0900_BYPASSPLLCORE 0xf1b60040
759#define F0900_SELX1RATIO 0xf1b60020
760#define F0900_STOP_PLL 0xf1b60008
761#define F0900_BYPASSPLLFSK 0xf1b60004
762#define F0900_SELOSCI 0xf1b60002
763#define F0900_BYPASSPLLADC 0xf1b60001
764
765/*FILTCTRL*/
766#define R0900_FILTCTRL 0xf1b7
767#define F0900_INV_CLK135 0xf1b70080
768#define F0900_SEL_FSKCKDIV 0xf1b70004
769#define F0900_INV_CLKFSK 0xf1b70002
770#define F0900_BYPASS_APPLI 0xf1b70001
771
772/*PLLSTAT*/
773#define R0900_PLLSTAT 0xf1b8
774#define F0900_PLLLOCK 0xf1b80001
775
776/*STOPCLK1*/
777#define R0900_STOPCLK1 0xf1c2
778#define F0900_STOP_CLKPKDT2 0xf1c20040
779#define F0900_STOP_CLKPKDT1 0xf1c20020
780#define F0900_STOP_CLKFEC 0xf1c20010
781#define F0900_STOP_CLKADCI2 0xf1c20008
782#define F0900_INV_CLKADCI2 0xf1c20004
783#define F0900_STOP_CLKADCI1 0xf1c20002
784#define F0900_INV_CLKADCI1 0xf1c20001
785
786/*STOPCLK2*/
787#define R0900_STOPCLK2 0xf1c3
788#define F0900_STOP_CLKSAMP2 0xf1c30010
789#define F0900_STOP_CLKSAMP1 0xf1c30008
790#define F0900_STOP_CLKVIT2 0xf1c30004
791#define F0900_STOP_CLKVIT1 0xf1c30002
792#define STOP_CLKVIT shiftx(F0900_STOP_CLKVIT1, demod, -2)
793#define F0900_STOP_CLKTS 0xf1c30001
794
795/*TSTTNR0*/
796#define R0900_TSTTNR0 0xf1df
797#define F0900_SEL_FSK 0xf1df0080
798#define F0900_FSK_PON 0xf1df0004
799
800/*TSTTNR1*/
801#define R0900_TSTTNR1 0xf1e0
802#define F0900_ADC1_PON 0xf1e00002
803#define F0900_ADC1_INMODE 0xf1e00001
804
805/*TSTTNR2*/
806#define R0900_TSTTNR2 0xf1e1
807#define F0900_DISEQC1_PON 0xf1e10020
808
809/*TSTTNR3*/
810#define R0900_TSTTNR3 0xf1e2
811#define F0900_ADC2_PON 0xf1e20002
812#define F0900_ADC2_INMODE 0xf1e20001
813
814/*TSTTNR4*/
815#define R0900_TSTTNR4 0xf1e3
816#define F0900_DISEQC2_PON 0xf1e30020
817
818/*P2_IQCONST*/
819#define R0900_P2_IQCONST 0xf200
820#define F0900_P2_CONSTEL_SELECT 0xf2000060
821#define F0900_P2_IQSYMB_SEL 0xf200001f
822
823/*P2_NOSCFG*/
824#define R0900_P2_NOSCFG 0xf201
825#define F0900_P2_DUMMYPL_NOSDATA 0xf2010020
826#define F0900_P2_NOSPLH_BETA 0xf2010018
827#define F0900_P2_NOSDATA_BETA 0xf2010007
828
829/*P2_ISYMB*/
830#define R0900_P2_ISYMB 0xf202
831#define F0900_P2_I_SYMBOL 0xf20201ff
832
833/*P2_QSYMB*/
834#define R0900_P2_QSYMB 0xf203
835#define F0900_P2_Q_SYMBOL 0xf20301ff
836
837/*P2_AGC1CFG*/
838#define R0900_P2_AGC1CFG 0xf204
839#define F0900_P2_DC_FROZEN 0xf2040080
840#define F0900_P2_DC_CORRECT 0xf2040040
841#define F0900_P2_AMM_FROZEN 0xf2040020
842#define F0900_P2_AMM_CORRECT 0xf2040010
843#define F0900_P2_QUAD_FROZEN 0xf2040008
844#define F0900_P2_QUAD_CORRECT 0xf2040004
845
846/*P2_AGC1CN*/
847#define R0900_P2_AGC1CN 0xf206
848#define F0900_P2_AGC1_LOCKED 0xf2060080
849#define F0900_P2_AGC1_MINPOWER 0xf2060010
850#define F0900_P2_AGCOUT_FAST 0xf2060008
851#define F0900_P2_AGCIQ_BETA 0xf2060007
852
853/*P2_AGC1REF*/
854#define R0900_P2_AGC1REF 0xf207
855#define F0900_P2_AGCIQ_REF 0xf20700ff
856
857/*P2_IDCCOMP*/
858#define R0900_P2_IDCCOMP 0xf208
859#define F0900_P2_IAVERAGE_ADJ 0xf20801ff
860
861/*P2_QDCCOMP*/
862#define R0900_P2_QDCCOMP 0xf209
863#define F0900_P2_QAVERAGE_ADJ 0xf20901ff
864
865/*P2_POWERI*/
866#define R0900_P2_POWERI 0xf20a
867#define F0900_P2_POWER_I 0xf20a00ff
868
869/*P2_POWERQ*/
870#define R0900_P2_POWERQ 0xf20b
871#define F0900_P2_POWER_Q 0xf20b00ff
872
873/*P2_AGC1AMM*/
874#define R0900_P2_AGC1AMM 0xf20c
875#define F0900_P2_AMM_VALUE 0xf20c00ff
876
877/*P2_AGC1QUAD*/
878#define R0900_P2_AGC1QUAD 0xf20d
879#define F0900_P2_QUAD_VALUE 0xf20d01ff
880
881/*P2_AGCIQIN1*/
882#define R0900_P2_AGCIQIN1 0xf20e
883#define F0900_P2_AGCIQ_VALUE1 0xf20e00ff
884
885/*P2_AGCIQIN0*/
886#define R0900_P2_AGCIQIN0 0xf20f
887#define F0900_P2_AGCIQ_VALUE0 0xf20f00ff
888
889/*P2_DEMOD*/
890#define R0900_P2_DEMOD 0xf210
891#define F0900_P2_MANUALS2_ROLLOFF 0xf2100080
892#define F0900_P2_SPECINV_CONTROL 0xf2100030
893#define F0900_P2_FORCE_ENASAMP 0xf2100008
894#define F0900_P2_MANUALSX_ROLLOFF 0xf2100004
895#define F0900_P2_ROLLOFF_CONTROL 0xf2100003
896
897/*P2_DMDMODCOD*/
898#define R0900_P2_DMDMODCOD 0xf211
899#define F0900_P2_MANUAL_MODCOD 0xf2110080
900#define F0900_P2_DEMOD_MODCOD 0xf211007c
901#define F0900_P2_DEMOD_TYPE 0xf2110003
902
903/*P2_DSTATUS*/
904#define R0900_P2_DSTATUS 0xf212
905#define F0900_P2_CAR_LOCK 0xf2120080
906#define F0900_P2_TMGLOCK_QUALITY 0xf2120060
907#define F0900_P2_LOCK_DEFINITIF 0xf2120008
908#define F0900_P2_OVADC_DETECT 0xf2120001
909
910/*P2_DSTATUS2*/
911#define R0900_P2_DSTATUS2 0xf213
912#define F0900_P2_DEMOD_DELOCK 0xf2130080
913#define F0900_P2_AGC1_NOSIGNALACK 0xf2130008
914#define F0900_P2_AGC2_OVERFLOW 0xf2130004
915#define F0900_P2_CFR_OVERFLOW 0xf2130002
916#define F0900_P2_GAMMA_OVERUNDER 0xf2130001
917
918/*P2_DMDCFGMD*/
919#define R0900_P2_DMDCFGMD 0xf214
920#define F0900_P2_DVBS2_ENABLE 0xf2140080
921#define F0900_P2_DVBS1_ENABLE 0xf2140040
922#define F0900_P2_SCAN_ENABLE 0xf2140010
923#define F0900_P2_CFR_AUTOSCAN 0xf2140008
924#define F0900_P2_TUN_RNG 0xf2140003
925
926/*P2_DMDCFG2*/
927#define R0900_P2_DMDCFG2 0xf215
928#define F0900_P2_S1S2_SEQUENTIAL 0xf2150040
929#define F0900_P2_INFINITE_RELOCK 0xf2150010
930
931/*P2_DMDISTATE*/
932#define R0900_P2_DMDISTATE 0xf216
933#define F0900_P2_I2C_DEMOD_MODE 0xf216001f
934
935/*P2_DMDT0M*/
936#define R0900_P2_DMDT0M 0xf217
937#define F0900_P2_DMDT0_MIN 0xf21700ff
938
939/*P2_DMDSTATE*/
940#define R0900_P2_DMDSTATE 0xf21b
941#define F0900_P2_HEADER_MODE 0xf21b0060
942
943/*P2_DMDFLYW*/
944#define R0900_P2_DMDFLYW 0xf21c
945#define F0900_P2_I2C_IRQVAL 0xf21c00f0
946#define F0900_P2_FLYWHEEL_CPT 0xf21c000f
947
948/*P2_DSTATUS3*/
949#define R0900_P2_DSTATUS3 0xf21d
950#define F0900_P2_DEMOD_CFGMODE 0xf21d0060
951
952/*P2_DMDCFG3*/
953#define R0900_P2_DMDCFG3 0xf21e
954#define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008
955
956/*P2_DMDCFG4*/
957#define R0900_P2_DMDCFG4 0xf21f
958#define F0900_P2_TUNER_NRELAUNCH 0xf21f0008
959
960/*P2_CORRELMANT*/
961#define R0900_P2_CORRELMANT 0xf220
962#define F0900_P2_CORREL_MANT 0xf22000ff
963
964/*P2_CORRELABS*/
965#define R0900_P2_CORRELABS 0xf221
966#define F0900_P2_CORREL_ABS 0xf22100ff
967
968/*P2_CORRELEXP*/
969#define R0900_P2_CORRELEXP 0xf222
970#define F0900_P2_CORREL_ABSEXP 0xf22200f0
971#define F0900_P2_CORREL_EXP 0xf222000f
972
973/*P2_PLHMODCOD*/
974#define R0900_P2_PLHMODCOD 0xf224
975#define F0900_P2_SPECINV_DEMOD 0xf2240080
976#define F0900_P2_PLH_MODCOD 0xf224007c
977#define F0900_P2_PLH_TYPE 0xf2240003
978
979/*P2_DMDREG*/
980#define R0900_P2_DMDREG 0xf225
981#define F0900_P2_DECIM_PLFRAMES 0xf2250001
982
983/*P2_AGC2O*/
984#define R0900_P2_AGC2O 0xf22c
985#define F0900_P2_AGC2_COEF 0xf22c0007
986
987/*P2_AGC2REF*/
988#define R0900_P2_AGC2REF 0xf22d
989#define F0900_P2_AGC2_REF 0xf22d00ff
990
991/*P2_AGC1ADJ*/
992#define R0900_P2_AGC1ADJ 0xf22e
993#define F0900_P2_AGC1_ADJUSTED 0xf22e007f
994
995/*P2_AGC2I1*/
996#define R0900_P2_AGC2I1 0xf236
997#define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff
998
999/*P2_AGC2I0*/
1000#define R0900_P2_AGC2I0 0xf237
1001#define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff
1002
1003/*P2_CARCFG*/
1004#define R0900_P2_CARCFG 0xf238
1005#define F0900_P2_CFRUPLOW_AUTO 0xf2380080
1006#define F0900_P2_CFRUPLOW_TEST 0xf2380040
1007#define F0900_P2_ROTAON 0xf2380004
1008#define F0900_P2_PH_DET_ALGO 0xf2380003
1009
1010/*P2_ACLC*/
1011#define R0900_P2_ACLC 0xf239
1012#define F0900_P2_CAR_ALPHA_MANT 0xf2390030
1013#define F0900_P2_CAR_ALPHA_EXP 0xf239000f
1014
1015/*P2_BCLC*/
1016#define R0900_P2_BCLC 0xf23a
1017#define F0900_P2_CAR_BETA_MANT 0xf23a0030
1018#define F0900_P2_CAR_BETA_EXP 0xf23a000f
1019
1020/*P2_CARFREQ*/
1021#define R0900_P2_CARFREQ 0xf23d
1022#define F0900_P2_KC_COARSE_EXP 0xf23d00f0
1023#define F0900_P2_BETA_FREQ 0xf23d000f
1024
1025/*P2_CARHDR*/
1026#define R0900_P2_CARHDR 0xf23e
1027#define F0900_P2_K_FREQ_HDR 0xf23e00ff
1028
1029/*P2_LDT*/
1030#define R0900_P2_LDT 0xf23f
1031#define F0900_P2_CARLOCK_THRES 0xf23f01ff
1032
1033/*P2_LDT2*/
1034#define R0900_P2_LDT2 0xf240
1035#define F0900_P2_CARLOCK_THRES2 0xf24001ff
1036
1037/*P2_CFRICFG*/
1038#define R0900_P2_CFRICFG 0xf241
1039#define F0900_P2_NEG_CFRSTEP 0xf2410001
1040
1041/*P2_CFRUP1*/
1042#define R0900_P2_CFRUP1 0xf242
1043#define F0900_P2_CFR_UP1 0xf24201ff
1044
1045/*P2_CFRUP0*/
1046#define R0900_P2_CFRUP0 0xf243
1047#define F0900_P2_CFR_UP0 0xf24300ff
1048
1049/*P2_CFRLOW1*/
1050#define R0900_P2_CFRLOW1 0xf246
1051#define F0900_P2_CFR_LOW1 0xf24601ff
1052
1053/*P2_CFRLOW0*/
1054#define R0900_P2_CFRLOW0 0xf247
1055#define F0900_P2_CFR_LOW0 0xf24700ff
1056
1057/*P2_CFRINIT1*/
1058#define R0900_P2_CFRINIT1 0xf248
1059#define F0900_P2_CFR_INIT1 0xf24801ff
1060
1061/*P2_CFRINIT0*/
1062#define R0900_P2_CFRINIT0 0xf249
1063#define F0900_P2_CFR_INIT0 0xf24900ff
1064
1065/*P2_CFRINC1*/
1066#define R0900_P2_CFRINC1 0xf24a
1067#define F0900_P2_MANUAL_CFRINC 0xf24a0080
1068#define F0900_P2_CFR_INC1 0xf24a003f
1069
1070/*P2_CFRINC0*/
1071#define R0900_P2_CFRINC0 0xf24b
1072#define F0900_P2_CFR_INC0 0xf24b00f8
1073
1074/*P2_CFR2*/
1075#define R0900_P2_CFR2 0xf24c
1076#define F0900_P2_CAR_FREQ2 0xf24c01ff
1077
1078/*P2_CFR1*/
1079#define R0900_P2_CFR1 0xf24d
1080#define F0900_P2_CAR_FREQ1 0xf24d00ff
1081
1082/*P2_CFR0*/
1083#define R0900_P2_CFR0 0xf24e
1084#define F0900_P2_CAR_FREQ0 0xf24e00ff
1085
1086/*P2_LDI*/
1087#define R0900_P2_LDI 0xf24f
1088#define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff
1089
1090/*P2_TMGCFG*/
1091#define R0900_P2_TMGCFG 0xf250
1092#define F0900_P2_TMGLOCK_BETA 0xf25000c0
1093#define F0900_P2_DO_TIMING_CORR 0xf2500010
1094#define F0900_P2_TMG_MINFREQ 0xf2500003
1095
1096/*P2_RTC*/
1097#define R0900_P2_RTC 0xf251
1098#define F0900_P2_TMGALPHA_EXP 0xf25100f0
1099#define F0900_P2_TMGBETA_EXP 0xf251000f
1100
1101/*P2_RTCS2*/
1102#define R0900_P2_RTCS2 0xf252
1103#define F0900_P2_TMGALPHAS2_EXP 0xf25200f0
1104#define F0900_P2_TMGBETAS2_EXP 0xf252000f
1105
1106/*P2_TMGTHRISE*/
1107#define R0900_P2_TMGTHRISE 0xf253
1108#define F0900_P2_TMGLOCK_THRISE 0xf25300ff
1109
1110/*P2_TMGTHFALL*/
1111#define R0900_P2_TMGTHFALL 0xf254
1112#define F0900_P2_TMGLOCK_THFALL 0xf25400ff
1113
1114/*P2_SFRUPRATIO*/
1115#define R0900_P2_SFRUPRATIO 0xf255
1116#define F0900_P2_SFR_UPRATIO 0xf25500ff
1117
1118/*P2_SFRLOWRATIO*/
1119#define R0900_P2_SFRLOWRATIO 0xf256
1120#define F0900_P2_SFR_LOWRATIO 0xf25600ff
1121
1122/*P2_KREFTMG*/
1123#define R0900_P2_KREFTMG 0xf258
1124#define F0900_P2_KREF_TMG 0xf25800ff
1125
1126/*P2_SFRSTEP*/
1127#define R0900_P2_SFRSTEP 0xf259
1128#define F0900_P2_SFR_SCANSTEP 0xf25900f0
1129#define F0900_P2_SFR_CENTERSTEP 0xf259000f
1130
1131/*P2_TMGCFG2*/
1132#define R0900_P2_TMGCFG2 0xf25a
1133#define F0900_P2_SFRRATIO_FINE 0xf25a0001
1134
1135/*P2_KREFTMG2*/
1136#define R0900_P2_KREFTMG2 0xf25b
1137#define F0900_P2_KREF_TMG2 0xf25b00ff
1138
1139/*P2_SFRINIT1*/
1140#define R0900_P2_SFRINIT1 0xf25e
1141#define F0900_P2_SFR_INIT1 0xf25e007f
1142
1143/*P2_SFRINIT0*/
1144#define R0900_P2_SFRINIT0 0xf25f
1145#define F0900_P2_SFR_INIT0 0xf25f00ff
1146
1147/*P2_SFRUP1*/
1148#define R0900_P2_SFRUP1 0xf260
1149#define F0900_P2_AUTO_GUP 0xf2600080
1150#define F0900_P2_SYMB_FREQ_UP1 0xf260007f
1151
1152/*P2_SFRUP0*/
1153#define R0900_P2_SFRUP0 0xf261
1154#define F0900_P2_SYMB_FREQ_UP0 0xf26100ff
1155
1156/*P2_SFRLOW1*/
1157#define R0900_P2_SFRLOW1 0xf262
1158#define F0900_P2_AUTO_GLOW 0xf2620080
1159#define F0900_P2_SYMB_FREQ_LOW1 0xf262007f
1160
1161/*P2_SFRLOW0*/
1162#define R0900_P2_SFRLOW0 0xf263
1163#define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff
1164
1165/*P2_SFR3*/
1166#define R0900_P2_SFR3 0xf264
1167#define F0900_P2_SYMB_FREQ3 0xf26400ff
1168
1169/*P2_SFR2*/
1170#define R0900_P2_SFR2 0xf265
1171#define F0900_P2_SYMB_FREQ2 0xf26500ff
1172
1173/*P2_SFR1*/
1174#define R0900_P2_SFR1 0xf266
1175#define F0900_P2_SYMB_FREQ1 0xf26600ff
1176
1177/*P2_SFR0*/
1178#define R0900_P2_SFR0 0xf267
1179#define F0900_P2_SYMB_FREQ0 0xf26700ff
1180
1181/*P2_TMGREG2*/
1182#define R0900_P2_TMGREG2 0xf268
1183#define F0900_P2_TMGREG2 0xf26800ff
1184
1185/*P2_TMGREG1*/
1186#define R0900_P2_TMGREG1 0xf269
1187#define F0900_P2_TMGREG1 0xf26900ff
1188
1189/*P2_TMGREG0*/
1190#define R0900_P2_TMGREG0 0xf26a
1191#define F0900_P2_TMGREG0 0xf26a00ff
1192
1193/*P2_TMGLOCK1*/
1194#define R0900_P2_TMGLOCK1 0xf26b
1195#define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff
1196
1197/*P2_TMGLOCK0*/
1198#define R0900_P2_TMGLOCK0 0xf26c
1199#define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff
1200
1201/*P2_TMGOBS*/
1202#define R0900_P2_TMGOBS 0xf26d
1203#define F0900_P2_ROLLOFF_STATUS 0xf26d00c0
1204
1205/*P2_EQUALCFG*/
1206#define R0900_P2_EQUALCFG 0xf26f
1207#define F0900_P2_EQUAL_ON 0xf26f0040
1208#define F0900_P2_MU_EQUALDFE 0xf26f0007
1209
1210/*P2_EQUAI1*/
1211#define R0900_P2_EQUAI1 0xf270
1212#define F0900_P2_EQUA_ACCI1 0xf27001ff
1213
1214/*P2_EQUAQ1*/
1215#define R0900_P2_EQUAQ1 0xf271
1216#define F0900_P2_EQUA_ACCQ1 0xf27101ff
1217
1218/*P2_EQUAI2*/
1219#define R0900_P2_EQUAI2 0xf272
1220#define F0900_P2_EQUA_ACCI2 0xf27201ff
1221
1222/*P2_EQUAQ2*/
1223#define R0900_P2_EQUAQ2 0xf273
1224#define F0900_P2_EQUA_ACCQ2 0xf27301ff
1225
1226/*P2_EQUAI3*/
1227#define R0900_P2_EQUAI3 0xf274
1228#define F0900_P2_EQUA_ACCI3 0xf27401ff
1229
1230/*P2_EQUAQ3*/
1231#define R0900_P2_EQUAQ3 0xf275
1232#define F0900_P2_EQUA_ACCQ3 0xf27501ff
1233
1234/*P2_EQUAI4*/
1235#define R0900_P2_EQUAI4 0xf276
1236#define F0900_P2_EQUA_ACCI4 0xf27601ff
1237
1238/*P2_EQUAQ4*/
1239#define R0900_P2_EQUAQ4 0xf277
1240#define F0900_P2_EQUA_ACCQ4 0xf27701ff
1241
1242/*P2_EQUAI5*/
1243#define R0900_P2_EQUAI5 0xf278
1244#define F0900_P2_EQUA_ACCI5 0xf27801ff
1245
1246/*P2_EQUAQ5*/
1247#define R0900_P2_EQUAQ5 0xf279
1248#define F0900_P2_EQUA_ACCQ5 0xf27901ff
1249
1250/*P2_EQUAI6*/
1251#define R0900_P2_EQUAI6 0xf27a
1252#define F0900_P2_EQUA_ACCI6 0xf27a01ff
1253
1254/*P2_EQUAQ6*/
1255#define R0900_P2_EQUAQ6 0xf27b
1256#define F0900_P2_EQUA_ACCQ6 0xf27b01ff
1257
1258/*P2_EQUAI7*/
1259#define R0900_P2_EQUAI7 0xf27c
1260#define F0900_P2_EQUA_ACCI7 0xf27c01ff
1261
1262/*P2_EQUAQ7*/
1263#define R0900_P2_EQUAQ7 0xf27d
1264#define F0900_P2_EQUA_ACCQ7 0xf27d01ff
1265
1266/*P2_EQUAI8*/
1267#define R0900_P2_EQUAI8 0xf27e
1268#define F0900_P2_EQUA_ACCI8 0xf27e01ff
1269
1270/*P2_EQUAQ8*/
1271#define R0900_P2_EQUAQ8 0xf27f
1272#define F0900_P2_EQUA_ACCQ8 0xf27f01ff
1273
1274/*P2_NNOSDATAT1*/
1275#define R0900_P2_NNOSDATAT1 0xf280
1276#define F0900_P2_NOSDATAT_NORMED1 0xf28000ff
1277
1278/*P2_NNOSDATAT0*/
1279#define R0900_P2_NNOSDATAT0 0xf281
1280#define F0900_P2_NOSDATAT_NORMED0 0xf28100ff
1281
1282/*P2_NNOSDATA1*/
1283#define R0900_P2_NNOSDATA1 0xf282
1284#define F0900_P2_NOSDATA_NORMED1 0xf28200ff
1285
1286/*P2_NNOSDATA0*/
1287#define R0900_P2_NNOSDATA0 0xf283
1288#define F0900_P2_NOSDATA_NORMED0 0xf28300ff
1289
1290/*P2_NNOSPLHT1*/
1291#define R0900_P2_NNOSPLHT1 0xf284
1292#define F0900_P2_NOSPLHT_NORMED1 0xf28400ff
1293
1294/*P2_NNOSPLHT0*/
1295#define R0900_P2_NNOSPLHT0 0xf285
1296#define F0900_P2_NOSPLHT_NORMED0 0xf28500ff
1297
1298/*P2_NNOSPLH1*/
1299#define R0900_P2_NNOSPLH1 0xf286
1300#define F0900_P2_NOSPLH_NORMED1 0xf28600ff
1301
1302/*P2_NNOSPLH0*/
1303#define R0900_P2_NNOSPLH0 0xf287
1304#define F0900_P2_NOSPLH_NORMED0 0xf28700ff
1305
1306/*P2_NOSDATAT1*/
1307#define R0900_P2_NOSDATAT1 0xf288
1308#define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff
1309
1310/*P2_NOSDATAT0*/
1311#define R0900_P2_NOSDATAT0 0xf289
1312#define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff
1313
1314/*P2_NOSDATA1*/
1315#define R0900_P2_NOSDATA1 0xf28a
1316#define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff
1317
1318/*P2_NOSDATA0*/
1319#define R0900_P2_NOSDATA0 0xf28b
1320#define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff
1321
1322/*P2_NOSPLHT1*/
1323#define R0900_P2_NOSPLHT1 0xf28c
1324#define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff
1325
1326/*P2_NOSPLHT0*/
1327#define R0900_P2_NOSPLHT0 0xf28d
1328#define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff
1329
1330/*P2_NOSPLH1*/
1331#define R0900_P2_NOSPLH1 0xf28e
1332#define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff
1333
1334/*P2_NOSPLH0*/
1335#define R0900_P2_NOSPLH0 0xf28f
1336#define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff
1337
1338/*P2_CAR2CFG*/
1339#define R0900_P2_CAR2CFG 0xf290
1340#define F0900_P2_CARRIER3_DISABLE 0xf2900040
1341#define F0900_P2_ROTA2ON 0xf2900004
1342#define F0900_P2_PH_DET_ALGO2 0xf2900003
1343
1344/*P2_CFR2CFR1*/
1345#define R0900_P2_CFR2CFR1 0xf291
1346#define F0900_P2_CFR2TOCFR1_DVBS1 0xf29100c0
1347#define F0900_P2_EN_S2CAR2CENTER 0xf2910020
1348#define F0900_P2_DIS_BCHERRCFR2 0xf2910010
1349#define F0900_P2_CFR2TOCFR1_BETA 0xf2910007
1350
1351/*P2_CFR22*/
1352#define R0900_P2_CFR22 0xf293
1353#define F0900_P2_CAR2_FREQ2 0xf29301ff
1354
1355/*P2_CFR21*/
1356#define R0900_P2_CFR21 0xf294
1357#define F0900_P2_CAR2_FREQ1 0xf29400ff
1358
1359/*P2_CFR20*/
1360#define R0900_P2_CFR20 0xf295
1361#define F0900_P2_CAR2_FREQ0 0xf29500ff
1362
1363/*P2_ACLC2S2Q*/
1364#define R0900_P2_ACLC2S2Q 0xf297
1365#define F0900_P2_ENAB_SPSKSYMB 0xf2970080
1366#define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030
1367#define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f
1368
1369/*P2_ACLC2S28*/
1370#define R0900_P2_ACLC2S28 0xf298
1371#define F0900_P2_OLDI3Q_MODE 0xf2980080
1372#define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030
1373#define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f
1374
1375/*P2_ACLC2S216A*/
1376#define R0900_P2_ACLC2S216A 0xf299
1377#define F0900_P2_DIS_C3STOPA2 0xf2990080
1378#define F0900_P2_CAR2S2_16ADERAT 0xf2990040
1379#define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030
1380#define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f
1381
1382/*P2_ACLC2S232A*/
1383#define R0900_P2_ACLC2S232A 0xf29a
1384#define F0900_P2_CAR2S2_32ADERAT 0xf29a0040
1385#define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030
1386#define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f
1387
1388/*P2_BCLC2S2Q*/
1389#define R0900_P2_BCLC2S2Q 0xf29c
1390#define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030
1391#define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f
1392
1393/*P2_BCLC2S28*/
1394#define R0900_P2_BCLC2S28 0xf29d
1395#define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030
1396#define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f
1397
1398/*P2_BCLC2S216A*/
1399#define R0900_P2_BCLC2S216A 0xf29e
1400
1401/*P2_BCLC2S232A*/
1402#define R0900_P2_BCLC2S232A 0xf29f
1403
1404/*P2_PLROOT2*/
1405#define R0900_P2_PLROOT2 0xf2ac
1406#define F0900_P2_PLSCRAMB_MODE 0xf2ac000c
1407#define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003
1408
1409/*P2_PLROOT1*/
1410#define R0900_P2_PLROOT1 0xf2ad
1411#define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff
1412
1413/*P2_PLROOT0*/
1414#define R0900_P2_PLROOT0 0xf2ae
1415#define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff
1416
1417/*P2_MODCODLST0*/
1418#define R0900_P2_MODCODLST0 0xf2b0
1419
1420/*P2_MODCODLST1*/
1421#define R0900_P2_MODCODLST1 0xf2b1
1422#define F0900_P2_DIS_MODCOD29 0xf2b100f0
1423#define F0900_P2_DIS_32PSK_9_10 0xf2b1000f
1424
1425/*P2_MODCODLST2*/
1426#define R0900_P2_MODCODLST2 0xf2b2
1427#define F0900_P2_DIS_32PSK_8_9 0xf2b200f0
1428#define F0900_P2_DIS_32PSK_5_6 0xf2b2000f
1429
1430/*P2_MODCODLST3*/
1431#define R0900_P2_MODCODLST3 0xf2b3
1432#define F0900_P2_DIS_32PSK_4_5 0xf2b300f0
1433#define F0900_P2_DIS_32PSK_3_4 0xf2b3000f
1434
1435/*P2_MODCODLST4*/
1436#define R0900_P2_MODCODLST4 0xf2b4
1437#define F0900_P2_DIS_16PSK_9_10 0xf2b400f0
1438#define F0900_P2_DIS_16PSK_8_9 0xf2b4000f
1439
1440/*P2_MODCODLST5*/
1441#define R0900_P2_MODCODLST5 0xf2b5
1442#define F0900_P2_DIS_16PSK_5_6 0xf2b500f0
1443#define F0900_P2_DIS_16PSK_4_5 0xf2b5000f
1444
1445/*P2_MODCODLST6*/
1446#define R0900_P2_MODCODLST6 0xf2b6
1447#define F0900_P2_DIS_16PSK_3_4 0xf2b600f0
1448#define F0900_P2_DIS_16PSK_2_3 0xf2b6000f
1449
1450/*P2_MODCODLST7*/
1451#define R0900_P2_MODCODLST7 0xf2b7
1452#define F0900_P2_DIS_8P_9_10 0xf2b700f0
1453#define F0900_P2_DIS_8P_8_9 0xf2b7000f
1454
1455/*P2_MODCODLST8*/
1456#define R0900_P2_MODCODLST8 0xf2b8
1457#define F0900_P2_DIS_8P_5_6 0xf2b800f0
1458#define F0900_P2_DIS_8P_3_4 0xf2b8000f
1459
1460/*P2_MODCODLST9*/
1461#define R0900_P2_MODCODLST9 0xf2b9
1462#define F0900_P2_DIS_8P_2_3 0xf2b900f0
1463#define F0900_P2_DIS_8P_3_5 0xf2b9000f
1464
1465/*P2_MODCODLSTA*/
1466#define R0900_P2_MODCODLSTA 0xf2ba
1467#define F0900_P2_DIS_QP_9_10 0xf2ba00f0
1468#define F0900_P2_DIS_QP_8_9 0xf2ba000f
1469
1470/*P2_MODCODLSTB*/
1471#define R0900_P2_MODCODLSTB 0xf2bb
1472#define F0900_P2_DIS_QP_5_6 0xf2bb00f0
1473#define F0900_P2_DIS_QP_4_5 0xf2bb000f
1474
1475/*P2_MODCODLSTC*/
1476#define R0900_P2_MODCODLSTC 0xf2bc
1477#define F0900_P2_DIS_QP_3_4 0xf2bc00f0
1478#define F0900_P2_DIS_QP_2_3 0xf2bc000f
1479
1480/*P2_MODCODLSTD*/
1481#define R0900_P2_MODCODLSTD 0xf2bd
1482#define F0900_P2_DIS_QP_3_5 0xf2bd00f0
1483#define F0900_P2_DIS_QP_1_2 0xf2bd000f
1484
1485/*P2_MODCODLSTE*/
1486#define R0900_P2_MODCODLSTE 0xf2be
1487#define F0900_P2_DIS_QP_2_5 0xf2be00f0
1488#define F0900_P2_DIS_QP_1_3 0xf2be000f
1489
1490/*P2_MODCODLSTF*/
1491#define R0900_P2_MODCODLSTF 0xf2bf
1492#define F0900_P2_DIS_QP_1_4 0xf2bf00f0
1493
1494/*P2_GAUSSR0*/
1495#define R0900_P2_GAUSSR0 0xf2c0
1496#define F0900_P2_EN_CCIMODE 0xf2c00080
1497#define F0900_P2_R0_GAUSSIEN 0xf2c0007f
1498
1499/*P2_CCIR0*/
1500#define R0900_P2_CCIR0 0xf2c1
1501#define F0900_P2_CCIDETECT_PLHONLY 0xf2c10080
1502#define F0900_P2_R0_CCI 0xf2c1007f
1503
1504/*P2_CCIQUANT*/
1505#define R0900_P2_CCIQUANT 0xf2c2
1506#define F0900_P2_CCI_BETA 0xf2c200e0
1507#define F0900_P2_CCI_QUANT 0xf2c2001f
1508
1509/*P2_CCITHRES*/
1510#define R0900_P2_CCITHRES 0xf2c3
1511#define F0900_P2_CCI_THRESHOLD 0xf2c300ff
1512
1513/*P2_CCIACC*/
1514#define R0900_P2_CCIACC 0xf2c4
1515#define F0900_P2_CCI_VALUE 0xf2c400ff
1516
1517/*P2_DMDRESCFG*/
1518#define R0900_P2_DMDRESCFG 0xf2c6
1519#define F0900_P2_DMDRES_RESET 0xf2c60080
1520#define F0900_P2_DMDRES_STRALL 0xf2c60008
1521#define F0900_P2_DMDRES_NEWONLY 0xf2c60004
1522#define F0900_P2_DMDRES_NOSTORE 0xf2c60002
1523
1524/*P2_DMDRESADR*/
1525#define R0900_P2_DMDRESADR 0xf2c7
1526#define F0900_P2_DMDRES_VALIDCFR 0xf2c70040
1527#define F0900_P2_DMDRES_MEMFULL 0xf2c70030
1528#define F0900_P2_DMDRES_RESNBR 0xf2c7000f
1529
1530/*P2_DMDRESDATA7*/
1531#define R0900_P2_DMDRESDATA7 0xf2c8
1532#define F0900_P2_DMDRES_DATA7 0xf2c800ff
1533
1534/*P2_DMDRESDATA6*/
1535#define R0900_P2_DMDRESDATA6 0xf2c9
1536#define F0900_P2_DMDRES_DATA6 0xf2c900ff
1537
1538/*P2_DMDRESDATA5*/
1539#define R0900_P2_DMDRESDATA5 0xf2ca
1540#define F0900_P2_DMDRES_DATA5 0xf2ca00ff
1541
1542/*P2_DMDRESDATA4*/
1543#define R0900_P2_DMDRESDATA4 0xf2cb
1544#define F0900_P2_DMDRES_DATA4 0xf2cb00ff
1545
1546/*P2_DMDRESDATA3*/
1547#define R0900_P2_DMDRESDATA3 0xf2cc
1548#define F0900_P2_DMDRES_DATA3 0xf2cc00ff
1549
1550/*P2_DMDRESDATA2*/
1551#define R0900_P2_DMDRESDATA2 0xf2cd
1552#define F0900_P2_DMDRES_DATA2 0xf2cd00ff
1553
1554/*P2_DMDRESDATA1*/
1555#define R0900_P2_DMDRESDATA1 0xf2ce
1556#define F0900_P2_DMDRES_DATA1 0xf2ce00ff
1557
1558/*P2_DMDRESDATA0*/
1559#define R0900_P2_DMDRESDATA0 0xf2cf
1560#define F0900_P2_DMDRES_DATA0 0xf2cf00ff
1561
1562/*P2_FFEI1*/
1563#define R0900_P2_FFEI1 0xf2d0
1564#define F0900_P2_FFE_ACCI1 0xf2d001ff
1565
1566/*P2_FFEQ1*/
1567#define R0900_P2_FFEQ1 0xf2d1
1568#define F0900_P2_FFE_ACCQ1 0xf2d101ff
1569
1570/*P2_FFEI2*/
1571#define R0900_P2_FFEI2 0xf2d2
1572#define F0900_P2_FFE_ACCI2 0xf2d201ff
1573
1574/*P2_FFEQ2*/
1575#define R0900_P2_FFEQ2 0xf2d3
1576#define F0900_P2_FFE_ACCQ2 0xf2d301ff
1577
1578/*P2_FFEI3*/
1579#define R0900_P2_FFEI3 0xf2d4
1580#define F0900_P2_FFE_ACCI3 0xf2d401ff
1581
1582/*P2_FFEQ3*/
1583#define R0900_P2_FFEQ3 0xf2d5
1584#define F0900_P2_FFE_ACCQ3 0xf2d501ff
1585
1586/*P2_FFEI4*/
1587#define R0900_P2_FFEI4 0xf2d6
1588#define F0900_P2_FFE_ACCI4 0xf2d601ff
1589
1590/*P2_FFEQ4*/
1591#define R0900_P2_FFEQ4 0xf2d7
1592#define F0900_P2_FFE_ACCQ4 0xf2d701ff
1593
1594/*P2_FFECFG*/
1595#define R0900_P2_FFECFG 0xf2d8
1596#define F0900_P2_EQUALFFE_ON 0xf2d80040
1597#define F0900_P2_MU_EQUALFFE 0xf2d80007
1598
1599/*P2_TNRCFG*/
1600#define R0900_P2_TNRCFG 0xf2e0
1601#define F0900_P2_TUN_ACKFAIL 0xf2e00080
1602#define F0900_P2_TUN_TYPE 0xf2e00070
1603#define F0900_P2_TUN_SECSTOP 0xf2e00008
1604#define F0900_P2_TUN_VCOSRCH 0xf2e00004
1605#define F0900_P2_TUN_MADDRESS 0xf2e00003
1606
1607/*P2_TNRCFG2*/
1608#define R0900_P2_TNRCFG2 0xf2e1
1609#define F0900_P2_TUN_IQSWAP 0xf2e10080
1610#define F0900_P2_DIS_BWCALC 0xf2e10004
1611#define F0900_P2_SHORT_WAITSTATES 0xf2e10002
1612
1613/*P2_TNRXTAL*/
1614#define R0900_P2_TNRXTAL 0xf2e4
1615#define F0900_P2_TUN_XTALFREQ 0xf2e4001f
1616
1617/*P2_TNRSTEPS*/
1618#define R0900_P2_TNRSTEPS 0xf2e7
1619#define F0900_P2_TUNER_BW0P125 0xf2e70080
1620#define F0900_P2_BWINC_OFFSET 0xf2e70170
1621#define F0900_P2_SOFTSTEP_RNG 0xf2e70008
1622#define F0900_P2_TUN_BWOFFSET 0xf2e70007
1623
1624/*P2_TNRGAIN*/
1625#define R0900_P2_TNRGAIN 0xf2e8
1626#define F0900_P2_TUN_KDIVEN 0xf2e800c0
1627#define F0900_P2_STB6X00_OCK 0xf2e80030
1628#define F0900_P2_TUN_GAIN 0xf2e8000f
1629
1630/*P2_TNRRF1*/
1631#define R0900_P2_TNRRF1 0xf2e9
1632#define F0900_P2_TUN_RFFREQ2 0xf2e900ff
1633
1634/*P2_TNRRF0*/
1635#define R0900_P2_TNRRF0 0xf2ea
1636#define F0900_P2_TUN_RFFREQ1 0xf2ea00ff
1637
1638/*P2_TNRBW*/
1639#define R0900_P2_TNRBW 0xf2eb
1640#define F0900_P2_TUN_RFFREQ0 0xf2eb00c0
1641#define F0900_P2_TUN_BW 0xf2eb003f
1642
1643/*P2_TNRADJ*/
1644#define R0900_P2_TNRADJ 0xf2ec
1645#define F0900_P2_STB61X0_CALTIME 0xf2ec0040
1646
1647/*P2_TNRCTL2*/
1648#define R0900_P2_TNRCTL2 0xf2ed
1649#define F0900_P2_STB61X0_RCCKOFF 0xf2ed0080
1650#define F0900_P2_STB61X0_ICP_SDOFF 0xf2ed0040
1651#define F0900_P2_STB61X0_DCLOOPOFF 0xf2ed0020
1652#define F0900_P2_STB61X0_REFOUTSEL 0xf2ed0010
1653#define F0900_P2_STB61X0_CALOFF 0xf2ed0008
1654#define F0900_P2_STB6XX0_LPT_BEN 0xf2ed0004
1655#define F0900_P2_STB6XX0_RX_OSCP 0xf2ed0002
1656#define F0900_P2_STB6XX0_SYN 0xf2ed0001
1657
1658/*P2_TNRCFG3*/
1659#define R0900_P2_TNRCFG3 0xf2ee
1660#define F0900_P2_TUN_PLLFREQ 0xf2ee001c
1661#define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003
1662
1663/*P2_TNRLAUNCH*/
1664#define R0900_P2_TNRLAUNCH 0xf2f0
1665
1666/*P2_TNRLD*/
1667#define R0900_P2_TNRLD 0xf2f0
1668#define F0900_P2_TUNLD_VCOING 0xf2f00080
1669#define F0900_P2_TUN_REG1FAIL 0xf2f00040
1670#define F0900_P2_TUN_REG2FAIL 0xf2f00020
1671#define F0900_P2_TUN_REG3FAIL 0xf2f00010
1672#define F0900_P2_TUN_REG4FAIL 0xf2f00008
1673#define F0900_P2_TUN_REG5FAIL 0xf2f00004
1674#define F0900_P2_TUN_BWING 0xf2f00002
1675#define F0900_P2_TUN_LOCKED 0xf2f00001
1676
1677/*P2_TNROBSL*/
1678#define R0900_P2_TNROBSL 0xf2f6
1679#define F0900_P2_TUN_I2CABORTED 0xf2f60080
1680#define F0900_P2_TUN_LPEN 0xf2f60040
1681#define F0900_P2_TUN_FCCK 0xf2f60020
1682#define F0900_P2_TUN_I2CLOCKED 0xf2f60010
1683#define F0900_P2_TUN_PROGDONE 0xf2f6000c
1684#define F0900_P2_TUN_RFRESTE1 0xf2f60003
1685
1686/*P2_TNRRESTE*/
1687#define R0900_P2_TNRRESTE 0xf2f7
1688#define F0900_P2_TUN_RFRESTE0 0xf2f700ff
1689
1690/*P2_SMAPCOEF7*/
1691#define R0900_P2_SMAPCOEF7 0xf300
1692#define F0900_P2_DIS_QSCALE 0xf3000080
1693#define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f
1694
1695/*P2_SMAPCOEF6*/
1696#define R0900_P2_SMAPCOEF6 0xf301
1697#define F0900_P2_ADJ_8PSKLLR1 0xf3010004
1698#define F0900_P2_OLD_8PSKLLR1 0xf3010002
1699#define F0900_P2_DIS_AB8PSK 0xf3010001
1700
1701/*P2_SMAPCOEF5*/
1702#define R0900_P2_SMAPCOEF5 0xf302
1703#define F0900_P2_DIS_8SCALE 0xf3020080
1704#define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f
1705
1706/*P2_NCO2MAX1*/
1707#define R0900_P2_NCO2MAX1 0xf314
1708#define F0900_P2_TETA2_MAXVABS1 0xf31400ff
1709
1710/*P2_NCO2MAX0*/
1711#define R0900_P2_NCO2MAX0 0xf315
1712#define F0900_P2_TETA2_MAXVABS0 0xf31500ff
1713
1714/*P2_NCO2FR1*/
1715#define R0900_P2_NCO2FR1 0xf316
1716#define F0900_P2_NCO2FINAL_ANGLE1 0xf31600ff
1717
1718/*P2_NCO2FR0*/
1719#define R0900_P2_NCO2FR0 0xf317
1720#define F0900_P2_NCO2FINAL_ANGLE0 0xf31700ff
1721
1722/*P2_CFR2AVRGE1*/
1723#define R0900_P2_CFR2AVRGE1 0xf318
1724#define F0900_P2_I2C_CFR2AVERAGE1 0xf31800ff
1725
1726/*P2_CFR2AVRGE0*/
1727#define R0900_P2_CFR2AVRGE0 0xf319
1728#define F0900_P2_I2C_CFR2AVERAGE0 0xf31900ff
1729
1730/*P2_DMDPLHSTAT*/
1731#define R0900_P2_DMDPLHSTAT 0xf320
1732#define F0900_P2_PLH_STATISTIC 0xf32000ff
1733
1734/*P2_LOCKTIME3*/
1735#define R0900_P2_LOCKTIME3 0xf322
1736#define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff
1737
1738/*P2_LOCKTIME2*/
1739#define R0900_P2_LOCKTIME2 0xf323
1740#define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff
1741
1742/*P2_LOCKTIME1*/
1743#define R0900_P2_LOCKTIME1 0xf324
1744#define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff
1745
1746/*P2_LOCKTIME0*/
1747#define R0900_P2_LOCKTIME0 0xf325
1748#define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff
1749
1750/*P2_VITSCALE*/
1751#define R0900_P2_VITSCALE 0xf332
1752#define F0900_P2_NVTH_NOSRANGE 0xf3320080
1753#define F0900_P2_VERROR_MAXMODE 0xf3320040
1754#define F0900_P2_NSLOWSN_LOCKED 0xf3320008
1755#define F0900_P2_DIS_RSFLOCK 0xf3320002
1756
1757/*P2_FECM*/
1758#define R0900_P2_FECM 0xf333
1759#define F0900_P2_DSS_DVB 0xf3330080
1760#define F0900_P2_DSS_SRCH 0xf3330010
1761#define F0900_P2_SYNCVIT 0xf3330002
1762#define F0900_P2_IQINV 0xf3330001
1763
1764/*P2_VTH12*/
1765#define R0900_P2_VTH12 0xf334
1766#define F0900_P2_VTH12 0xf33400ff
1767
1768/*P2_VTH23*/
1769#define R0900_P2_VTH23 0xf335
1770#define F0900_P2_VTH23 0xf33500ff
1771
1772/*P2_VTH34*/
1773#define R0900_P2_VTH34 0xf336
1774#define F0900_P2_VTH34 0xf33600ff
1775
1776/*P2_VTH56*/
1777#define R0900_P2_VTH56 0xf337
1778#define F0900_P2_VTH56 0xf33700ff
1779
1780/*P2_VTH67*/
1781#define R0900_P2_VTH67 0xf338
1782#define F0900_P2_VTH67 0xf33800ff
1783
1784/*P2_VTH78*/
1785#define R0900_P2_VTH78 0xf339
1786#define F0900_P2_VTH78 0xf33900ff
1787
1788/*P2_VITCURPUN*/
1789#define R0900_P2_VITCURPUN 0xf33a
1790#define F0900_P2_VIT_CURPUN 0xf33a001f
1791
1792/*P2_VERROR*/
1793#define R0900_P2_VERROR 0xf33b
1794#define F0900_P2_REGERR_VIT 0xf33b00ff
1795
1796/*P2_PRVIT*/
1797#define R0900_P2_PRVIT 0xf33c
1798#define F0900_P2_DIS_VTHLOCK 0xf33c0040
1799#define F0900_P2_E7_8VIT 0xf33c0020
1800#define F0900_P2_E6_7VIT 0xf33c0010
1801#define F0900_P2_E5_6VIT 0xf33c0008
1802#define F0900_P2_E3_4VIT 0xf33c0004
1803#define F0900_P2_E2_3VIT 0xf33c0002
1804#define F0900_P2_E1_2VIT 0xf33c0001
1805
1806/*P2_VAVSRVIT*/
1807#define R0900_P2_VAVSRVIT 0xf33d
1808#define F0900_P2_AMVIT 0xf33d0080
1809#define F0900_P2_FROZENVIT 0xf33d0040
1810#define F0900_P2_SNVIT 0xf33d0030
1811#define F0900_P2_TOVVIT 0xf33d000c
1812#define F0900_P2_HYPVIT 0xf33d0003
1813
1814/*P2_VSTATUSVIT*/
1815#define R0900_P2_VSTATUSVIT 0xf33e
1816#define F0900_P2_PRFVIT 0xf33e0010
1817#define F0900_P2_LOCKEDVIT 0xf33e0008
1818
1819/*P2_VTHINUSE*/
1820#define R0900_P2_VTHINUSE 0xf33f
1821#define F0900_P2_VIT_INUSE 0xf33f00ff
1822
1823/*P2_KDIV12*/
1824#define R0900_P2_KDIV12 0xf340
1825#define F0900_P2_K_DIVIDER_12 0xf340007f
1826
1827/*P2_KDIV23*/
1828#define R0900_P2_KDIV23 0xf341
1829#define F0900_P2_K_DIVIDER_23 0xf341007f
1830
1831/*P2_KDIV34*/
1832#define R0900_P2_KDIV34 0xf342
1833#define F0900_P2_K_DIVIDER_34 0xf342007f
1834
1835/*P2_KDIV56*/
1836#define R0900_P2_KDIV56 0xf343
1837#define F0900_P2_K_DIVIDER_56 0xf343007f
1838
1839/*P2_KDIV67*/
1840#define R0900_P2_KDIV67 0xf344
1841#define F0900_P2_K_DIVIDER_67 0xf344007f
1842
1843/*P2_KDIV78*/
1844#define R0900_P2_KDIV78 0xf345
1845#define F0900_P2_K_DIVIDER_78 0xf345007f
1846
1847/*P2_PDELCTRL1*/
1848#define R0900_P2_PDELCTRL1 0xf350
1849#define F0900_P2_INV_MISMASK 0xf3500080
1850#define F0900_P2_FILTER_EN 0xf3500020
1851#define F0900_P2_EN_MIS00 0xf3500002
1852#define F0900_P2_ALGOSWRST 0xf3500001
1853
1854/*P2_PDELCTRL2*/
1855#define R0900_P2_PDELCTRL2 0xf351
1856#define F0900_P2_RESET_UPKO_COUNT 0xf3510040
1857#define F0900_P2_FRAME_MODE 0xf3510002
1858#define F0900_P2_NOBCHERRFLG_USE 0xf3510001
1859
1860/*P2_HYSTTHRESH*/
1861#define R0900_P2_HYSTTHRESH 0xf354
1862#define F0900_P2_UNLCK_THRESH 0xf35400f0
1863#define F0900_P2_DELIN_LCK_THRESH 0xf354000f
1864
1865/*P2_ISIENTRY*/
1866#define R0900_P2_ISIENTRY 0xf35e
1867#define F0900_P2_ISI_ENTRY 0xf35e00ff
1868
1869/*P2_ISIBITENA*/
1870#define R0900_P2_ISIBITENA 0xf35f
1871#define F0900_P2_ISI_BIT_EN 0xf35f00ff
1872
1873/*P2_MATSTR1*/
1874#define R0900_P2_MATSTR1 0xf360
1875#define F0900_P2_MATYPE_CURRENT1 0xf36000ff
1876
1877/*P2_MATSTR0*/
1878#define R0900_P2_MATSTR0 0xf361
1879#define F0900_P2_MATYPE_CURRENT0 0xf36100ff
1880
1881/*P2_UPLSTR1*/
1882#define R0900_P2_UPLSTR1 0xf362
1883#define F0900_P2_UPL_CURRENT1 0xf36200ff
1884
1885/*P2_UPLSTR0*/
1886#define R0900_P2_UPLSTR0 0xf363
1887#define F0900_P2_UPL_CURRENT0 0xf36300ff
1888
1889/*P2_DFLSTR1*/
1890#define R0900_P2_DFLSTR1 0xf364
1891#define F0900_P2_DFL_CURRENT1 0xf36400ff
1892
1893/*P2_DFLSTR0*/
1894#define R0900_P2_DFLSTR0 0xf365
1895#define F0900_P2_DFL_CURRENT0 0xf36500ff
1896
1897/*P2_SYNCSTR*/
1898#define R0900_P2_SYNCSTR 0xf366
1899#define F0900_P2_SYNC_CURRENT 0xf36600ff
1900
1901/*P2_SYNCDSTR1*/
1902#define R0900_P2_SYNCDSTR1 0xf367
1903#define F0900_P2_SYNCD_CURRENT1 0xf36700ff
1904
1905/*P2_SYNCDSTR0*/
1906#define R0900_P2_SYNCDSTR0 0xf368
1907#define F0900_P2_SYNCD_CURRENT0 0xf36800ff
1908
1909/*P2_PDELSTATUS1*/
1910#define R0900_P2_PDELSTATUS1 0xf369
1911#define F0900_P2_PKTDELIN_DELOCK 0xf3690080
1912#define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040
1913#define F0900_P2_CONTINUOUS_STREAM 0xf3690020
1914#define F0900_P2_UNACCEPTED_STREAM 0xf3690010
1915#define F0900_P2_BCH_ERROR_FLAG 0xf3690008
1916#define F0900_P2_PKTDELIN_LOCK 0xf3690002
1917#define F0900_P2_FIRST_LOCK 0xf3690001
1918
1919/*P2_PDELSTATUS2*/
1920#define R0900_P2_PDELSTATUS2 0xf36a
1921#define F0900_P2_FRAME_MODCOD 0xf36a007c
1922#define F0900_P2_FRAME_TYPE 0xf36a0003
1923
1924/*P2_BBFCRCKO1*/
1925#define R0900_P2_BBFCRCKO1 0xf36b
1926#define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff
1927
1928/*P2_BBFCRCKO0*/
1929#define R0900_P2_BBFCRCKO0 0xf36c
1930#define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff
1931
1932/*P2_UPCRCKO1*/
1933#define R0900_P2_UPCRCKO1 0xf36d
1934#define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff
1935
1936/*P2_UPCRCKO0*/
1937#define R0900_P2_UPCRCKO0 0xf36e
1938#define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff
1939
1940/*P2_PDELCTRL3*/
1941#define R0900_P2_PDELCTRL3 0xf36f
1942#define F0900_P2_PKTDEL_CONTFAIL 0xf36f0080
1943#define F0900_P2_NOFIFO_BCHERR 0xf36f0020
1944
1945/*P2_TSSTATEM*/
1946#define R0900_P2_TSSTATEM 0xf370
1947#define F0900_P2_TSDIL_ON 0xf3700080
1948#define F0900_P2_TSRS_ON 0xf3700020
1949#define F0900_P2_TSDESCRAMB_ON 0xf3700010
1950#define F0900_P2_TSFRAME_MODE 0xf3700008
1951#define F0900_P2_TS_DISABLE 0xf3700004
1952#define F0900_P2_TSOUT_NOSYNC 0xf3700001
1953
1954/*P2_TSCFGH*/
1955#define R0900_P2_TSCFGH 0xf372
1956#define F0900_P2_TSFIFO_DVBCI 0xf3720080
1957#define F0900_P2_TSFIFO_SERIAL 0xf3720040
1958#define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020
1959#define F0900_P2_TSFIFO_DUTY50 0xf3720010
1960#define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008
1961#define F0900_P2_TSFIFO_ERRMODE 0xf3720006
1962#define F0900_P2_RST_HWARE 0xf3720001
1963
1964/*P2_TSCFGM*/
1965#define R0900_P2_TSCFGM 0xf373
1966#define F0900_P2_TSFIFO_MANSPEED 0xf37300c0
1967#define F0900_P2_TSFIFO_PERMDATA 0xf3730020
1968#define F0900_P2_TSFIFO_DPUNACT 0xf3730002
1969#define F0900_P2_TSFIFO_INVDATA 0xf3730001
1970
1971/*P2_TSCFGL*/
1972#define R0900_P2_TSCFGL 0xf374
1973#define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0
1974#define F0900_P2_BCHERROR_MODE 0xf3740030
1975#define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008
1976#define F0900_P2_TSFIFO_EMBINDVB 0xf3740004
1977#define F0900_P2_TSFIFO_BITSPEED 0xf3740003
1978
1979/*P2_TSINSDELH*/
1980#define R0900_P2_TSINSDELH 0xf376
1981#define F0900_P2_TSDEL_SYNCBYTE 0xf3760080
1982#define F0900_P2_TSDEL_XXHEADER 0xf3760040
1983#define F0900_P2_TSDEL_BBHEADER 0xf3760020
1984#define F0900_P2_TSDEL_DATAFIELD 0xf3760010
1985#define F0900_P2_TSINSDEL_ISCR 0xf3760008
1986#define F0900_P2_TSINSDEL_NPD 0xf3760004
1987#define F0900_P2_TSINSDEL_RSPARITY 0xf3760002
1988#define F0900_P2_TSINSDEL_CRC8 0xf3760001
1989
1990/*P2_TSDIVN*/
1991#define R0900_P2_TSDIVN 0xf379
1992#define F0900_P2_TSFIFO_SPEEDMODE 0xf37900c0
1993
1994/*P2_TSCFG4*/
1995#define R0900_P2_TSCFG4 0xf37a
1996#define F0900_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0
1997
1998/*P2_TSSPEED*/
1999#define R0900_P2_TSSPEED 0xf380
2000#define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff
2001
2002/*P2_TSSTATUS*/
2003#define R0900_P2_TSSTATUS 0xf381
2004#define F0900_P2_TSFIFO_LINEOK 0xf3810080
2005#define F0900_P2_TSFIFO_ERROR 0xf3810040
2006#define F0900_P2_DIL_READY 0xf3810001
2007
2008/*P2_TSSTATUS2*/
2009#define R0900_P2_TSSTATUS2 0xf382
2010#define F0900_P2_TSFIFO_DEMODSEL 0xf3820080
2011#define F0900_P2_TSFIFOSPEED_STORE 0xf3820040
2012#define F0900_P2_DILXX_RESET 0xf3820020
2013#define F0900_P2_TSSERIAL_IMPOS 0xf3820010
2014#define F0900_P2_SCRAMBDETECT 0xf3820002
2015
2016/*P2_TSBITRATE1*/
2017#define R0900_P2_TSBITRATE1 0xf383
2018#define F0900_P2_TSFIFO_BITRATE1 0xf38300ff
2019
2020/*P2_TSBITRATE0*/
2021#define R0900_P2_TSBITRATE0 0xf384
2022#define F0900_P2_TSFIFO_BITRATE0 0xf38400ff
2023
2024/*P2_ERRCTRL1*/
2025#define R0900_P2_ERRCTRL1 0xf398
2026#define F0900_P2_ERR_SOURCE1 0xf39800f0
2027#define F0900_P2_NUM_EVENT1 0xf3980007
2028
2029/*P2_ERRCNT12*/
2030#define R0900_P2_ERRCNT12 0xf399
2031#define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080
2032#define F0900_P2_ERR_CNT12 0xf399007f
2033
2034/*P2_ERRCNT11*/
2035#define R0900_P2_ERRCNT11 0xf39a
2036#define F0900_P2_ERR_CNT11 0xf39a00ff
2037
2038/*P2_ERRCNT10*/
2039#define R0900_P2_ERRCNT10 0xf39b
2040#define F0900_P2_ERR_CNT10 0xf39b00ff
2041
2042/*P2_ERRCTRL2*/
2043#define R0900_P2_ERRCTRL2 0xf39c
2044#define F0900_P2_ERR_SOURCE2 0xf39c00f0
2045#define F0900_P2_NUM_EVENT2 0xf39c0007
2046
2047/*P2_ERRCNT22*/
2048#define R0900_P2_ERRCNT22 0xf39d
2049#define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080
2050#define F0900_P2_ERR_CNT22 0xf39d007f
2051
2052/*P2_ERRCNT21*/
2053#define R0900_P2_ERRCNT21 0xf39e
2054#define F0900_P2_ERR_CNT21 0xf39e00ff
2055
2056/*P2_ERRCNT20*/
2057#define R0900_P2_ERRCNT20 0xf39f
2058#define F0900_P2_ERR_CNT20 0xf39f00ff
2059
2060/*P2_FECSPY*/
2061#define R0900_P2_FECSPY 0xf3a0
2062#define F0900_P2_SPY_ENABLE 0xf3a00080
2063#define F0900_P2_NO_SYNCBYTE 0xf3a00040
2064#define F0900_P2_SERIAL_MODE 0xf3a00020
2065#define F0900_P2_UNUSUAL_PACKET 0xf3a00010
2066#define F0900_P2_BERMETER_DATAMODE 0xf3a00008
2067#define F0900_P2_BERMETER_LMODE 0xf3a00002
2068#define F0900_P2_BERMETER_RESET 0xf3a00001
2069
2070/*P2_FSPYCFG*/
2071#define R0900_P2_FSPYCFG 0xf3a1
2072#define F0900_P2_FECSPY_INPUT 0xf3a100c0
2073#define F0900_P2_RST_ON_ERROR 0xf3a10020
2074#define F0900_P2_ONE_SHOT 0xf3a10010
2075#define F0900_P2_I2C_MODE 0xf3a1000c
2076#define F0900_P2_SPY_HYSTERESIS 0xf3a10003
2077
2078/*P2_FSPYDATA*/
2079#define R0900_P2_FSPYDATA 0xf3a2
2080#define F0900_P2_SPY_STUFFING 0xf3a20080
2081#define F0900_P2_SPY_CNULLPKT 0xf3a20020
2082#define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f
2083
2084/*P2_FSPYOUT*/
2085#define R0900_P2_FSPYOUT 0xf3a3
2086#define F0900_P2_FSPY_DIRECT 0xf3a30080
2087#define F0900_P2_STUFF_MODE 0xf3a30007
2088
2089/*P2_FSTATUS*/
2090#define R0900_P2_FSTATUS 0xf3a4
2091#define F0900_P2_SPY_ENDSIM 0xf3a40080
2092#define F0900_P2_VALID_SIM 0xf3a40040
2093#define F0900_P2_FOUND_SIGNAL 0xf3a40020
2094#define F0900_P2_DSS_SYNCBYTE 0xf3a40010
2095#define F0900_P2_RESULT_STATE 0xf3a4000f
2096
2097/*P2_FBERCPT4*/
2098#define R0900_P2_FBERCPT4 0xf3a8
2099#define F0900_P2_FBERMETER_CPT4 0xf3a800ff
2100
2101/*P2_FBERCPT3*/
2102#define R0900_P2_FBERCPT3 0xf3a9
2103#define F0900_P2_FBERMETER_CPT3 0xf3a900ff
2104
2105/*P2_FBERCPT2*/
2106#define R0900_P2_FBERCPT2 0xf3aa
2107#define F0900_P2_FBERMETER_CPT2 0xf3aa00ff
2108
2109/*P2_FBERCPT1*/
2110#define R0900_P2_FBERCPT1 0xf3ab
2111#define F0900_P2_FBERMETER_CPT1 0xf3ab00ff
2112
2113/*P2_FBERCPT0*/
2114#define R0900_P2_FBERCPT0 0xf3ac
2115#define F0900_P2_FBERMETER_CPT0 0xf3ac00ff
2116
2117/*P2_FBERERR2*/
2118#define R0900_P2_FBERERR2 0xf3ad
2119#define F0900_P2_FBERMETER_ERR2 0xf3ad00ff
2120
2121/*P2_FBERERR1*/
2122#define R0900_P2_FBERERR1 0xf3ae
2123#define F0900_P2_FBERMETER_ERR1 0xf3ae00ff
2124
2125/*P2_FBERERR0*/
2126#define R0900_P2_FBERERR0 0xf3af
2127#define F0900_P2_FBERMETER_ERR0 0xf3af00ff
2128
2129/*P2_FSPYBER*/
2130#define R0900_P2_FSPYBER 0xf3b2
2131#define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010
2132#define F0900_P2_FSPYBER_UNSYNC 0xf3b20008
2133#define F0900_P2_FSPYBER_CTIME 0xf3b20007
2134
2135/*P1_IQCONST*/
2136#define R0900_P1_IQCONST 0xf400
2137#define IQCONST REGx(R0900_P1_IQCONST)
2138#define F0900_P1_CONSTEL_SELECT 0xf4000060
2139#define F0900_P1_IQSYMB_SEL 0xf400001f
2140
2141/*P1_NOSCFG*/
2142#define R0900_P1_NOSCFG 0xf401
2143#define NOSCFG REGx(R0900_P1_NOSCFG)
2144#define F0900_P1_DUMMYPL_NOSDATA 0xf4010020
2145#define F0900_P1_NOSPLH_BETA 0xf4010018
2146#define F0900_P1_NOSDATA_BETA 0xf4010007
2147
2148/*P1_ISYMB*/
2149#define R0900_P1_ISYMB 0xf402
2150#define ISYMB REGx(R0900_P1_ISYMB)
2151#define F0900_P1_I_SYMBOL 0xf40201ff
2152
2153/*P1_QSYMB*/
2154#define R0900_P1_QSYMB 0xf403
2155#define QSYMB REGx(R0900_P1_QSYMB)
2156#define F0900_P1_Q_SYMBOL 0xf40301ff
2157
2158/*P1_AGC1CFG*/
2159#define R0900_P1_AGC1CFG 0xf404
2160#define AGC1CFG REGx(R0900_P1_AGC1CFG)
2161#define F0900_P1_DC_FROZEN 0xf4040080
2162#define F0900_P1_DC_CORRECT 0xf4040040
2163#define F0900_P1_AMM_FROZEN 0xf4040020
2164#define F0900_P1_AMM_CORRECT 0xf4040010
2165#define F0900_P1_QUAD_FROZEN 0xf4040008
2166#define F0900_P1_QUAD_CORRECT 0xf4040004
2167
2168/*P1_AGC1CN*/
2169#define R0900_P1_AGC1CN 0xf406
2170#define AGC1CN REGx(R0900_P1_AGC1CN)
2171#define F0900_P1_AGC1_LOCKED 0xf4060080
2172#define F0900_P1_AGC1_MINPOWER 0xf4060010
2173#define F0900_P1_AGCOUT_FAST 0xf4060008
2174#define F0900_P1_AGCIQ_BETA 0xf4060007
2175
2176/*P1_AGC1REF*/
2177#define R0900_P1_AGC1REF 0xf407
2178#define AGC1REF REGx(R0900_P1_AGC1REF)
2179#define F0900_P1_AGCIQ_REF 0xf40700ff
2180
2181/*P1_IDCCOMP*/
2182#define R0900_P1_IDCCOMP 0xf408
2183#define IDCCOMP REGx(R0900_P1_IDCCOMP)
2184#define F0900_P1_IAVERAGE_ADJ 0xf40801ff
2185
2186/*P1_QDCCOMP*/
2187#define R0900_P1_QDCCOMP 0xf409
2188#define QDCCOMP REGx(R0900_P1_QDCCOMP)
2189#define F0900_P1_QAVERAGE_ADJ 0xf40901ff
2190
2191/*P1_POWERI*/
2192#define R0900_P1_POWERI 0xf40a
2193#define POWERI REGx(R0900_P1_POWERI)
2194#define F0900_P1_POWER_I 0xf40a00ff
2195#define POWER_I FLDx(F0900_P1_POWER_I)
2196
2197/*P1_POWERQ*/
2198#define R0900_P1_POWERQ 0xf40b
2199#define POWERQ REGx(R0900_P1_POWERQ)
2200#define F0900_P1_POWER_Q 0xf40b00ff
2201#define POWER_Q FLDx(F0900_P1_POWER_Q)
2202
2203/*P1_AGC1AMM*/
2204#define R0900_P1_AGC1AMM 0xf40c
2205#define AGC1AMM REGx(R0900_P1_AGC1AMM)
2206#define F0900_P1_AMM_VALUE 0xf40c00ff
2207
2208/*P1_AGC1QUAD*/
2209#define R0900_P1_AGC1QUAD 0xf40d
2210#define AGC1QUAD REGx(R0900_P1_AGC1QUAD)
2211#define F0900_P1_QUAD_VALUE 0xf40d01ff
2212
2213/*P1_AGCIQIN1*/
2214#define R0900_P1_AGCIQIN1 0xf40e
2215#define AGCIQIN1 REGx(R0900_P1_AGCIQIN1)
2216#define F0900_P1_AGCIQ_VALUE1 0xf40e00ff
2217#define AGCIQ_VALUE1 FLDx(F0900_P1_AGCIQ_VALUE1)
2218
2219/*P1_AGCIQIN0*/
2220#define R0900_P1_AGCIQIN0 0xf40f
2221#define AGCIQIN0 REGx(R0900_P1_AGCIQIN0)
2222#define F0900_P1_AGCIQ_VALUE0 0xf40f00ff
2223#define AGCIQ_VALUE0 FLDx(F0900_P1_AGCIQ_VALUE0)
2224
2225/*P1_DEMOD*/
2226#define R0900_P1_DEMOD 0xf410
2227#define DEMOD REGx(R0900_P1_DEMOD)
2228#define F0900_P1_MANUALS2_ROLLOFF 0xf4100080
2229#define MANUALS2_ROLLOFF FLDx(F0900_P1_MANUALS2_ROLLOFF)
2230
2231#define F0900_P1_SPECINV_CONTROL 0xf4100030
2232#define SPECINV_CONTROL FLDx(F0900_P1_SPECINV_CONTROL)
2233#define F0900_P1_FORCE_ENASAMP 0xf4100008
2234#define F0900_P1_MANUALSX_ROLLOFF 0xf4100004
2235#define MANUALSX_ROLLOFF FLDx(F0900_P1_MANUALSX_ROLLOFF)
2236#define F0900_P1_ROLLOFF_CONTROL 0xf4100003
2237#define ROLLOFF_CONTROL FLDx(F0900_P1_ROLLOFF_CONTROL)
2238
2239/*P1_DMDMODCOD*/
2240#define R0900_P1_DMDMODCOD 0xf411
2241#define DMDMODCOD REGx(R0900_P1_DMDMODCOD)
2242#define F0900_P1_MANUAL_MODCOD 0xf4110080
2243#define F0900_P1_DEMOD_MODCOD 0xf411007c
2244#define DEMOD_MODCOD FLDx(F0900_P1_DEMOD_MODCOD)
2245#define F0900_P1_DEMOD_TYPE 0xf4110003
2246#define DEMOD_TYPE FLDx(F0900_P1_DEMOD_TYPE)
2247
2248/*P1_DSTATUS*/
2249#define R0900_P1_DSTATUS 0xf412
2250#define DSTATUS REGx(R0900_P1_DSTATUS)
2251#define F0900_P1_CAR_LOCK 0xf4120080
2252#define F0900_P1_TMGLOCK_QUALITY 0xf4120060
2253#define TMGLOCK_QUALITY FLDx(F0900_P1_TMGLOCK_QUALITY)
2254#define F0900_P1_LOCK_DEFINITIF 0xf4120008
2255#define LOCK_DEFINITIF FLDx(F0900_P1_LOCK_DEFINITIF)
2256#define F0900_P1_OVADC_DETECT 0xf4120001
2257
2258/*P1_DSTATUS2*/
2259#define R0900_P1_DSTATUS2 0xf413
2260#define DSTATUS2 REGx(R0900_P1_DSTATUS2)
2261#define F0900_P1_DEMOD_DELOCK 0xf4130080
2262#define F0900_P1_AGC1_NOSIGNALACK 0xf4130008
2263#define F0900_P1_AGC2_OVERFLOW 0xf4130004
2264#define F0900_P1_CFR_OVERFLOW 0xf4130002
2265#define F0900_P1_GAMMA_OVERUNDER 0xf4130001
2266
2267/*P1_DMDCFGMD*/
2268#define R0900_P1_DMDCFGMD 0xf414
2269#define DMDCFGMD REGx(R0900_P1_DMDCFGMD)
2270#define F0900_P1_DVBS2_ENABLE 0xf4140080
2271#define DVBS2_ENABLE FLDx(F0900_P1_DVBS2_ENABLE)
2272#define F0900_P1_DVBS1_ENABLE 0xf4140040
2273#define DVBS1_ENABLE FLDx(F0900_P1_DVBS1_ENABLE)
2274#define F0900_P1_SCAN_ENABLE 0xf4140010
2275#define SCAN_ENABLE FLDx(F0900_P1_SCAN_ENABLE)
2276#define F0900_P1_CFR_AUTOSCAN 0xf4140008
2277#define CFR_AUTOSCAN FLDx(F0900_P1_CFR_AUTOSCAN)
2278#define F0900_P1_TUN_RNG 0xf4140003
2279
2280/*P1_DMDCFG2*/
2281#define R0900_P1_DMDCFG2 0xf415
2282#define DMDCFG2 REGx(R0900_P1_DMDCFG2)
2283#define F0900_P1_S1S2_SEQUENTIAL 0xf4150040
2284#define S1S2_SEQUENTIAL FLDx(F0900_P1_S1S2_SEQUENTIAL)
2285#define F0900_P1_INFINITE_RELOCK 0xf4150010
2286
2287/*P1_DMDISTATE*/
2288#define R0900_P1_DMDISTATE 0xf416
2289#define DMDISTATE REGx(R0900_P1_DMDISTATE)
2290#define F0900_P1_I2C_DEMOD_MODE 0xf416001f
2291#define DEMOD_MODE FLDx(F0900_P1_I2C_DEMOD_MODE)
2292
2293/*P1_DMDT0M*/
2294#define R0900_P1_DMDT0M 0xf417
2295#define DMDT0M REGx(R0900_P1_DMDT0M)
2296#define F0900_P1_DMDT0_MIN 0xf41700ff
2297
2298/*P1_DMDSTATE*/
2299#define R0900_P1_DMDSTATE 0xf41b
2300#define DMDSTATE REGx(R0900_P1_DMDSTATE)
2301#define F0900_P1_HEADER_MODE 0xf41b0060
2302#define HEADER_MODE FLDx(F0900_P1_HEADER_MODE)
2303
2304/*P1_DMDFLYW*/
2305#define R0900_P1_DMDFLYW 0xf41c
2306#define DMDFLYW REGx(R0900_P1_DMDFLYW)
2307#define F0900_P1_I2C_IRQVAL 0xf41c00f0
2308#define F0900_P1_FLYWHEEL_CPT 0xf41c000f
2309#define FLYWHEEL_CPT FLDx(F0900_P1_FLYWHEEL_CPT)
2310
2311/*P1_DSTATUS3*/
2312#define R0900_P1_DSTATUS3 0xf41d
2313#define DSTATUS3 REGx(R0900_P1_DSTATUS3)
2314#define F0900_P1_DEMOD_CFGMODE 0xf41d0060
2315
2316/*P1_DMDCFG3*/
2317#define R0900_P1_DMDCFG3 0xf41e
2318#define DMDCFG3 REGx(R0900_P1_DMDCFG3)
2319#define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008
2320
2321/*P1_DMDCFG4*/
2322#define R0900_P1_DMDCFG4 0xf41f
2323#define DMDCFG4 REGx(R0900_P1_DMDCFG4)
2324#define F0900_P1_TUNER_NRELAUNCH 0xf41f0008
2325
2326/*P1_CORRELMANT*/
2327#define R0900_P1_CORRELMANT 0xf420
2328#define CORRELMANT REGx(R0900_P1_CORRELMANT)
2329#define F0900_P1_CORREL_MANT 0xf42000ff
2330
2331/*P1_CORRELABS*/
2332#define R0900_P1_CORRELABS 0xf421
2333#define CORRELABS REGx(R0900_P1_CORRELABS)
2334#define F0900_P1_CORREL_ABS 0xf42100ff
2335
2336/*P1_CORRELEXP*/
2337#define R0900_P1_CORRELEXP 0xf422
2338#define CORRELEXP REGx(R0900_P1_CORRELEXP)
2339#define F0900_P1_CORREL_ABSEXP 0xf42200f0
2340#define F0900_P1_CORREL_EXP 0xf422000f
2341
2342/*P1_PLHMODCOD*/
2343#define R0900_P1_PLHMODCOD 0xf424
2344#define PLHMODCOD REGx(R0900_P1_PLHMODCOD)
2345#define F0900_P1_SPECINV_DEMOD 0xf4240080
2346#define SPECINV_DEMOD FLDx(F0900_P1_SPECINV_DEMOD)
2347#define F0900_P1_PLH_MODCOD 0xf424007c
2348#define F0900_P1_PLH_TYPE 0xf4240003
2349
2350/*P1_DMDREG*/
2351#define R0900_P1_DMDREG 0xf425
2352#define DMDREG REGx(R0900_P1_DMDREG)
2353#define F0900_P1_DECIM_PLFRAMES 0xf4250001
2354
2355/*P1_AGC2O*/
2356#define R0900_P1_AGC2O 0xf42c
2357#define AGC2O REGx(R0900_P1_AGC2O)
2358#define F0900_P1_AGC2_COEF 0xf42c0007
2359
2360/*P1_AGC2REF*/
2361#define R0900_P1_AGC2REF 0xf42d
2362#define AGC2REF REGx(R0900_P1_AGC2REF)
2363#define F0900_P1_AGC2_REF 0xf42d00ff
2364
2365/*P1_AGC1ADJ*/
2366#define R0900_P1_AGC1ADJ 0xf42e
2367#define AGC1ADJ REGx(R0900_P1_AGC1ADJ)
2368#define F0900_P1_AGC1_ADJUSTED 0xf42e007f
2369
2370/*P1_AGC2I1*/
2371#define R0900_P1_AGC2I1 0xf436
2372#define AGC2I1 REGx(R0900_P1_AGC2I1)
2373#define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff
2374
2375/*P1_AGC2I0*/
2376#define R0900_P1_AGC2I0 0xf437
2377#define AGC2I0 REGx(R0900_P1_AGC2I0)
2378#define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff
2379
2380/*P1_CARCFG*/
2381#define R0900_P1_CARCFG 0xf438
2382#define CARCFG REGx(R0900_P1_CARCFG)
2383#define F0900_P1_CFRUPLOW_AUTO 0xf4380080
2384#define F0900_P1_CFRUPLOW_TEST 0xf4380040
2385#define F0900_P1_ROTAON 0xf4380004
2386#define F0900_P1_PH_DET_ALGO 0xf4380003
2387
2388/*P1_ACLC*/
2389#define R0900_P1_ACLC 0xf439
2390#define ACLC REGx(R0900_P1_ACLC)
2391#define F0900_P1_CAR_ALPHA_MANT 0xf4390030
2392#define F0900_P1_CAR_ALPHA_EXP 0xf439000f
2393
2394/*P1_BCLC*/
2395#define R0900_P1_BCLC 0xf43a
2396#define BCLC REGx(R0900_P1_BCLC)
2397#define F0900_P1_CAR_BETA_MANT 0xf43a0030
2398#define F0900_P1_CAR_BETA_EXP 0xf43a000f
2399
2400/*P1_CARFREQ*/
2401#define R0900_P1_CARFREQ 0xf43d
2402#define CARFREQ REGx(R0900_P1_CARFREQ)
2403#define F0900_P1_KC_COARSE_EXP 0xf43d00f0
2404#define F0900_P1_BETA_FREQ 0xf43d000f
2405
2406/*P1_CARHDR*/
2407#define R0900_P1_CARHDR 0xf43e
2408#define CARHDR REGx(R0900_P1_CARHDR)
2409#define F0900_P1_K_FREQ_HDR 0xf43e00ff
2410
2411/*P1_LDT*/
2412#define R0900_P1_LDT 0xf43f
2413#define LDT REGx(R0900_P1_LDT)
2414#define F0900_P1_CARLOCK_THRES 0xf43f01ff
2415
2416/*P1_LDT2*/
2417#define R0900_P1_LDT2 0xf440
2418#define LDT2 REGx(R0900_P1_LDT2)
2419#define F0900_P1_CARLOCK_THRES2 0xf44001ff
2420
2421/*P1_CFRICFG*/
2422#define R0900_P1_CFRICFG 0xf441
2423#define CFRICFG REGx(R0900_P1_CFRICFG)
2424#define F0900_P1_NEG_CFRSTEP 0xf4410001
2425
2426/*P1_CFRUP1*/
2427#define R0900_P1_CFRUP1 0xf442
2428#define CFRUP1 REGx(R0900_P1_CFRUP1)
2429#define F0900_P1_CFR_UP1 0xf44201ff
2430#define CFR_UP1 FLDx(F0900_P1_CFR_UP1)
2431
2432/*P1_CFRUP0*/
2433#define R0900_P1_CFRUP0 0xf443
2434#define CFRUP0 REGx(R0900_P1_CFRUP0)
2435#define F0900_P1_CFR_UP0 0xf44300ff
2436#define CFR_UP0 FLDx(F0900_P1_CFR_UP0)
2437
2438/*P1_CFRLOW1*/
2439#define R0900_P1_CFRLOW1 0xf446
2440#define CFRLOW1 REGx(R0900_P1_CFRLOW1)
2441#define F0900_P1_CFR_LOW1 0xf44601ff
2442#define CFR_LOW1 FLDx(F0900_P1_CFR_LOW1)
2443
2444/*P1_CFRLOW0*/
2445#define R0900_P1_CFRLOW0 0xf447
2446#define CFRLOW0 REGx(R0900_P1_CFRLOW0)
2447#define F0900_P1_CFR_LOW0 0xf44700ff
2448#define CFR_LOW0 FLDx(F0900_P1_CFR_LOW0)
2449
2450/*P1_CFRINIT1*/
2451#define R0900_P1_CFRINIT1 0xf448
2452#define CFRINIT1 REGx(R0900_P1_CFRINIT1)
2453#define F0900_P1_CFR_INIT1 0xf44801ff
2454#define CFR_INIT1 FLDx(F0900_P1_CFR_INIT1)
2455
2456/*P1_CFRINIT0*/
2457#define R0900_P1_CFRINIT0 0xf449
2458#define CFRINIT0 REGx(R0900_P1_CFRINIT0)
2459#define F0900_P1_CFR_INIT0 0xf44900ff
2460#define CFR_INIT0 FLDx(F0900_P1_CFR_INIT0)
2461
2462/*P1_CFRINC1*/
2463#define R0900_P1_CFRINC1 0xf44a
2464#define CFRINC1 REGx(R0900_P1_CFRINC1)
2465#define F0900_P1_MANUAL_CFRINC 0xf44a0080
2466#define F0900_P1_CFR_INC1 0xf44a003f
2467
2468/*P1_CFRINC0*/
2469#define R0900_P1_CFRINC0 0xf44b
2470#define CFRINC0 REGx(R0900_P1_CFRINC0)
2471#define F0900_P1_CFR_INC0 0xf44b00f8
2472
2473/*P1_CFR2*/
2474#define R0900_P1_CFR2 0xf44c
2475#define CFR2 REGx(R0900_P1_CFR2)
2476#define F0900_P1_CAR_FREQ2 0xf44c01ff
2477#define CAR_FREQ2 FLDx(F0900_P1_CAR_FREQ2)
2478
2479/*P1_CFR1*/
2480#define R0900_P1_CFR1 0xf44d
2481#define CFR1 REGx(R0900_P1_CFR1)
2482#define F0900_P1_CAR_FREQ1 0xf44d00ff
2483#define CAR_FREQ1 FLDx(F0900_P1_CAR_FREQ1)
2484
2485/*P1_CFR0*/
2486#define R0900_P1_CFR0 0xf44e
2487#define CFR0 REGx(R0900_P1_CFR0)
2488#define F0900_P1_CAR_FREQ0 0xf44e00ff
2489#define CAR_FREQ0 FLDx(F0900_P1_CAR_FREQ0)
2490
2491/*P1_LDI*/
2492#define R0900_P1_LDI 0xf44f
2493#define LDI REGx(R0900_P1_LDI)
2494#define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff
2495
2496/*P1_TMGCFG*/
2497#define R0900_P1_TMGCFG 0xf450
2498#define TMGCFG REGx(R0900_P1_TMGCFG)
2499#define F0900_P1_TMGLOCK_BETA 0xf45000c0
2500#define F0900_P1_DO_TIMING_CORR 0xf4500010
2501#define F0900_P1_TMG_MINFREQ 0xf4500003
2502
2503/*P1_RTC*/
2504#define R0900_P1_RTC 0xf451
2505#define RTC REGx(R0900_P1_RTC)
2506#define F0900_P1_TMGALPHA_EXP 0xf45100f0
2507#define F0900_P1_TMGBETA_EXP 0xf451000f
2508
2509/*P1_RTCS2*/
2510#define R0900_P1_RTCS2 0xf452
2511#define RTCS2 REGx(R0900_P1_RTCS2)
2512#define F0900_P1_TMGALPHAS2_EXP 0xf45200f0
2513#define F0900_P1_TMGBETAS2_EXP 0xf452000f
2514
2515/*P1_TMGTHRISE*/
2516#define R0900_P1_TMGTHRISE 0xf453
2517#define TMGTHRISE REGx(R0900_P1_TMGTHRISE)
2518#define F0900_P1_TMGLOCK_THRISE 0xf45300ff
2519
2520/*P1_TMGTHFALL*/
2521#define R0900_P1_TMGTHFALL 0xf454
2522#define TMGTHFALL REGx(R0900_P1_TMGTHFALL)
2523#define F0900_P1_TMGLOCK_THFALL 0xf45400ff
2524
2525/*P1_SFRUPRATIO*/
2526#define R0900_P1_SFRUPRATIO 0xf455
2527#define SFRUPRATIO REGx(R0900_P1_SFRUPRATIO)
2528#define F0900_P1_SFR_UPRATIO 0xf45500ff
2529
2530/*P1_SFRLOWRATIO*/
2531#define R0900_P1_SFRLOWRATIO 0xf456
2532#define F0900_P1_SFR_LOWRATIO 0xf45600ff
2533
2534/*P1_KREFTMG*/
2535#define R0900_P1_KREFTMG 0xf458
2536#define KREFTMG REGx(R0900_P1_KREFTMG)
2537#define F0900_P1_KREF_TMG 0xf45800ff
2538
2539/*P1_SFRSTEP*/
2540#define R0900_P1_SFRSTEP 0xf459
2541#define SFRSTEP REGx(R0900_P1_SFRSTEP)
2542#define F0900_P1_SFR_SCANSTEP 0xf45900f0
2543#define F0900_P1_SFR_CENTERSTEP 0xf459000f
2544
2545/*P1_TMGCFG2*/
2546#define R0900_P1_TMGCFG2 0xf45a
2547#define TMGCFG2 REGx(R0900_P1_TMGCFG2)
2548#define F0900_P1_SFRRATIO_FINE 0xf45a0001
2549
2550/*P1_KREFTMG2*/
2551#define R0900_P1_KREFTMG2 0xf45b
2552#define KREFTMG2 REGx(R0900_P1_KREFTMG2)
2553#define F0900_P1_KREF_TMG2 0xf45b00ff
2554
2555/*P1_SFRINIT1*/
2556#define R0900_P1_SFRINIT1 0xf45e
2557#define SFRINIT1 REGx(R0900_P1_SFRINIT1)
2558#define F0900_P1_SFR_INIT1 0xf45e007f
2559
2560/*P1_SFRINIT0*/
2561#define R0900_P1_SFRINIT0 0xf45f
2562#define SFRINIT0 REGx(R0900_P1_SFRINIT0)
2563#define F0900_P1_SFR_INIT0 0xf45f00ff
2564
2565/*P1_SFRUP1*/
2566#define R0900_P1_SFRUP1 0xf460
2567#define SFRUP1 REGx(R0900_P1_SFRUP1)
2568#define F0900_P1_AUTO_GUP 0xf4600080
2569#define AUTO_GUP FLDx(F0900_P1_AUTO_GUP)
2570#define F0900_P1_SYMB_FREQ_UP1 0xf460007f
2571
2572/*P1_SFRUP0*/
2573#define R0900_P1_SFRUP0 0xf461
2574#define SFRUP0 REGx(R0900_P1_SFRUP0)
2575#define F0900_P1_SYMB_FREQ_UP0 0xf46100ff
2576
2577/*P1_SFRLOW1*/
2578#define R0900_P1_SFRLOW1 0xf462
2579#define SFRLOW1 REGx(R0900_P1_SFRLOW1)
2580#define F0900_P1_AUTO_GLOW 0xf4620080
2581#define AUTO_GLOW FLDx(F0900_P1_AUTO_GLOW)
2582#define F0900_P1_SYMB_FREQ_LOW1 0xf462007f
2583
2584/*P1_SFRLOW0*/
2585#define R0900_P1_SFRLOW0 0xf463
2586#define SFRLOW0 REGx(R0900_P1_SFRLOW0)
2587#define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff
2588
2589/*P1_SFR3*/
2590#define R0900_P1_SFR3 0xf464
2591#define SFR3 REGx(R0900_P1_SFR3)
2592#define F0900_P1_SYMB_FREQ3 0xf46400ff
2593#define SYMB_FREQ3 FLDx(F0900_P1_SYMB_FREQ3)
2594
2595/*P1_SFR2*/
2596#define R0900_P1_SFR2 0xf465
2597#define SFR2 REGx(R0900_P1_SFR2)
2598#define F0900_P1_SYMB_FREQ2 0xf46500ff
2599#define SYMB_FREQ2 FLDx(F0900_P1_SYMB_FREQ2)
2600
2601/*P1_SFR1*/
2602#define R0900_P1_SFR1 0xf466
2603#define SFR1 REGx(R0900_P1_SFR1)
2604#define F0900_P1_SYMB_FREQ1 0xf46600ff
2605#define SYMB_FREQ1 FLDx(F0900_P1_SYMB_FREQ1)
2606
2607/*P1_SFR0*/
2608#define R0900_P1_SFR0 0xf467
2609#define SFR0 REGx(R0900_P1_SFR0)
2610#define F0900_P1_SYMB_FREQ0 0xf46700ff
2611#define SYMB_FREQ0 FLDx(F0900_P1_SYMB_FREQ0)
2612
2613/*P1_TMGREG2*/
2614#define R0900_P1_TMGREG2 0xf468
2615#define TMGREG2 REGx(R0900_P1_TMGREG2)
2616#define F0900_P1_TMGREG2 0xf46800ff
2617
2618/*P1_TMGREG1*/
2619#define R0900_P1_TMGREG1 0xf469
2620#define TMGREG1 REGx(R0900_P1_TMGREG1)
2621#define F0900_P1_TMGREG1 0xf46900ff
2622
2623/*P1_TMGREG0*/
2624#define R0900_P1_TMGREG0 0xf46a
2625#define TMGREG0 REGx(R0900_P1_TMGREG0)
2626#define F0900_P1_TMGREG0 0xf46a00ff
2627
2628/*P1_TMGLOCK1*/
2629#define R0900_P1_TMGLOCK1 0xf46b
2630#define TMGLOCK1 REGx(R0900_P1_TMGLOCK1)
2631#define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff
2632
2633/*P1_TMGLOCK0*/
2634#define R0900_P1_TMGLOCK0 0xf46c
2635#define TMGLOCK0 REGx(R0900_P1_TMGLOCK0)
2636#define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff
2637
2638/*P1_TMGOBS*/
2639#define R0900_P1_TMGOBS 0xf46d
2640#define TMGOBS REGx(R0900_P1_TMGOBS)
2641#define F0900_P1_ROLLOFF_STATUS 0xf46d00c0
2642#define ROLLOFF_STATUS FLDx(F0900_P1_ROLLOFF_STATUS)
2643
2644/*P1_EQUALCFG*/
2645#define R0900_P1_EQUALCFG 0xf46f
2646#define EQUALCFG REGx(R0900_P1_EQUALCFG)
2647#define F0900_P1_EQUAL_ON 0xf46f0040
2648#define F0900_P1_MU_EQUALDFE 0xf46f0007
2649
2650/*P1_EQUAI1*/
2651#define R0900_P1_EQUAI1 0xf470
2652#define EQUAI1 REGx(R0900_P1_EQUAI1)
2653#define F0900_P1_EQUA_ACCI1 0xf47001ff
2654
2655/*P1_EQUAQ1*/
2656#define R0900_P1_EQUAQ1 0xf471
2657#define EQUAQ1 REGx(R0900_P1_EQUAQ1)
2658#define F0900_P1_EQUA_ACCQ1 0xf47101ff
2659
2660/*P1_EQUAI2*/
2661#define R0900_P1_EQUAI2 0xf472
2662#define EQUAI2 REGx(R0900_P1_EQUAI2)
2663#define F0900_P1_EQUA_ACCI2 0xf47201ff
2664
2665/*P1_EQUAQ2*/
2666#define R0900_P1_EQUAQ2 0xf473
2667#define EQUAQ2 REGx(R0900_P1_EQUAQ2)
2668#define F0900_P1_EQUA_ACCQ2 0xf47301ff
2669
2670/*P1_EQUAI3*/
2671#define R0900_P1_EQUAI3 0xf474
2672#define EQUAI3 REGx(R0900_P1_EQUAI3)
2673#define F0900_P1_EQUA_ACCI3 0xf47401ff
2674
2675/*P1_EQUAQ3*/
2676#define R0900_P1_EQUAQ3 0xf475
2677#define EQUAQ3 REGx(R0900_P1_EQUAQ3)
2678#define F0900_P1_EQUA_ACCQ3 0xf47501ff
2679
2680/*P1_EQUAI4*/
2681#define R0900_P1_EQUAI4 0xf476
2682#define EQUAI4 REGx(R0900_P1_EQUAI4)
2683#define F0900_P1_EQUA_ACCI4 0xf47601ff
2684
2685/*P1_EQUAQ4*/
2686#define R0900_P1_EQUAQ4 0xf477
2687#define EQUAQ4 REGx(R0900_P1_EQUAQ4)
2688#define F0900_P1_EQUA_ACCQ4 0xf47701ff
2689
2690/*P1_EQUAI5*/
2691#define R0900_P1_EQUAI5 0xf478
2692#define EQUAI5 REGx(R0900_P1_EQUAI5)
2693#define F0900_P1_EQUA_ACCI5 0xf47801ff
2694
2695/*P1_EQUAQ5*/
2696#define R0900_P1_EQUAQ5 0xf479
2697#define EQUAQ5 REGx(R0900_P1_EQUAQ5)
2698#define F0900_P1_EQUA_ACCQ5 0xf47901ff
2699
2700/*P1_EQUAI6*/
2701#define R0900_P1_EQUAI6 0xf47a
2702#define EQUAI6 REGx(R0900_P1_EQUAI6)
2703#define F0900_P1_EQUA_ACCI6 0xf47a01ff
2704
2705/*P1_EQUAQ6*/
2706#define R0900_P1_EQUAQ6 0xf47b
2707#define EQUAQ6 REGx(R0900_P1_EQUAQ6)
2708#define F0900_P1_EQUA_ACCQ6 0xf47b01ff
2709
2710/*P1_EQUAI7*/
2711#define R0900_P1_EQUAI7 0xf47c
2712#define EQUAI7 REGx(R0900_P1_EQUAI7)
2713#define F0900_P1_EQUA_ACCI7 0xf47c01ff
2714
2715/*P1_EQUAQ7*/
2716#define R0900_P1_EQUAQ7 0xf47d
2717#define EQUAQ7 REGx(R0900_P1_EQUAQ7)
2718#define F0900_P1_EQUA_ACCQ7 0xf47d01ff
2719
2720/*P1_EQUAI8*/
2721#define R0900_P1_EQUAI8 0xf47e
2722#define EQUAI8 REGx(R0900_P1_EQUAI8)
2723#define F0900_P1_EQUA_ACCI8 0xf47e01ff
2724
2725/*P1_EQUAQ8*/
2726#define R0900_P1_EQUAQ8 0xf47f
2727#define EQUAQ8 REGx(R0900_P1_EQUAQ8)
2728#define F0900_P1_EQUA_ACCQ8 0xf47f01ff
2729
2730/*P1_NNOSDATAT1*/
2731#define R0900_P1_NNOSDATAT1 0xf480
2732#define NNOSDATAT1 REGx(R0900_P1_NNOSDATAT1)
2733#define F0900_P1_NOSDATAT_NORMED1 0xf48000ff
2734#define NOSDATAT_NORMED1 FLDx(F0900_P1_NOSDATAT_NORMED1)
2735
2736/*P1_NNOSDATAT0*/
2737#define R0900_P1_NNOSDATAT0 0xf481
2738#define NNOSDATAT0 REGx(R0900_P1_NNOSDATAT0)
2739#define F0900_P1_NOSDATAT_NORMED0 0xf48100ff
2740#define NOSDATAT_NORMED0 FLDx(F0900_P1_NOSDATAT_NORMED0)
2741
2742/*P1_NNOSDATA1*/
2743#define R0900_P1_NNOSDATA1 0xf482
2744#define NNOSDATA1 REGx(R0900_P1_NNOSDATA1)
2745#define F0900_P1_NOSDATA_NORMED1 0xf48200ff
2746
2747/*P1_NNOSDATA0*/
2748#define R0900_P1_NNOSDATA0 0xf483
2749#define NNOSDATA0 REGx(R0900_P1_NNOSDATA0)
2750#define F0900_P1_NOSDATA_NORMED0 0xf48300ff
2751
2752/*P1_NNOSPLHT1*/
2753#define R0900_P1_NNOSPLHT1 0xf484
2754#define NNOSPLHT1 REGx(R0900_P1_NNOSPLHT1)
2755#define F0900_P1_NOSPLHT_NORMED1 0xf48400ff
2756#define NOSPLHT_NORMED1 FLDx(F0900_P1_NOSPLHT_NORMED1)
2757
2758/*P1_NNOSPLHT0*/
2759#define R0900_P1_NNOSPLHT0 0xf485
2760#define NNOSPLHT0 REGx(R0900_P1_NNOSPLHT0)
2761#define F0900_P1_NOSPLHT_NORMED0 0xf48500ff
2762#define NOSPLHT_NORMED0 FLDx(F0900_P1_NOSPLHT_NORMED0)
2763
2764/*P1_NNOSPLH1*/
2765#define R0900_P1_NNOSPLH1 0xf486
2766#define NNOSPLH1 REGx(R0900_P1_NNOSPLH1)
2767#define F0900_P1_NOSPLH_NORMED1 0xf48600ff
2768
2769/*P1_NNOSPLH0*/
2770#define R0900_P1_NNOSPLH0 0xf487
2771#define NNOSPLH0 REGx(R0900_P1_NNOSPLH0)
2772#define F0900_P1_NOSPLH_NORMED0 0xf48700ff
2773
2774/*P1_NOSDATAT1*/
2775#define R0900_P1_NOSDATAT1 0xf488
2776#define NOSDATAT1 REGx(R0900_P1_NOSDATAT1)
2777#define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff
2778
2779/*P1_NOSDATAT0*/
2780#define R0900_P1_NOSDATAT0 0xf489
2781#define NOSDATAT0 REGx(R0900_P1_NOSDATAT0)
2782#define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff
2783
2784/*P1_NOSDATA1*/
2785#define R0900_P1_NOSDATA1 0xf48a
2786#define NOSDATA1 REGx(R0900_P1_NOSDATA1)
2787#define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff
2788
2789/*P1_NOSDATA0*/
2790#define R0900_P1_NOSDATA0 0xf48b
2791#define NOSDATA0 REGx(R0900_P1_NOSDATA0)
2792#define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff
2793
2794/*P1_NOSPLHT1*/
2795#define R0900_P1_NOSPLHT1 0xf48c
2796#define NOSPLHT1 REGx(R0900_P1_NOSPLHT1)
2797#define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff
2798
2799/*P1_NOSPLHT0*/
2800#define R0900_P1_NOSPLHT0 0xf48d
2801#define NOSPLHT0 REGx(R0900_P1_NOSPLHT0)
2802#define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff
2803
2804/*P1_NOSPLH1*/
2805#define R0900_P1_NOSPLH1 0xf48e
2806#define NOSPLH1 REGx(R0900_P1_NOSPLH1)
2807#define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff
2808
2809/*P1_NOSPLH0*/
2810#define R0900_P1_NOSPLH0 0xf48f
2811#define NOSPLH0 REGx(R0900_P1_NOSPLH0)
2812#define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff
2813
2814/*P1_CAR2CFG*/
2815#define R0900_P1_CAR2CFG 0xf490
2816#define CAR2CFG REGx(R0900_P1_CAR2CFG)
2817#define F0900_P1_CARRIER3_DISABLE 0xf4900040
2818#define F0900_P1_ROTA2ON 0xf4900004
2819#define F0900_P1_PH_DET_ALGO2 0xf4900003
2820
2821/*P1_CFR2CFR1*/
2822#define R0900_P1_CFR2CFR1 0xf491
2823#define CFR2CFR1 REGx(R0900_P1_CFR2CFR1)
2824#define F0900_P1_CFR2TOCFR1_DVBS1 0xf49100c0
2825#define F0900_P1_EN_S2CAR2CENTER 0xf4910020
2826#define F0900_P1_DIS_BCHERRCFR2 0xf4910010
2827#define F0900_P1_CFR2TOCFR1_BETA 0xf4910007
2828
2829/*P1_CFR22*/
2830#define R0900_P1_CFR22 0xf493
2831#define CFR22 REGx(R0900_P1_CFR22)
2832#define F0900_P1_CAR2_FREQ2 0xf49301ff
2833
2834/*P1_CFR21*/
2835#define R0900_P1_CFR21 0xf494
2836#define CFR21 REGx(R0900_P1_CFR21)
2837#define F0900_P1_CAR2_FREQ1 0xf49400ff
2838
2839/*P1_CFR20*/
2840#define R0900_P1_CFR20 0xf495
2841#define CFR20 REGx(R0900_P1_CFR20)
2842#define F0900_P1_CAR2_FREQ0 0xf49500ff
2843
2844/*P1_ACLC2S2Q*/
2845#define R0900_P1_ACLC2S2Q 0xf497
2846#define ACLC2S2Q REGx(R0900_P1_ACLC2S2Q)
2847#define F0900_P1_ENAB_SPSKSYMB 0xf4970080
2848#define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030
2849#define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f
2850
2851/*P1_ACLC2S28*/
2852#define R0900_P1_ACLC2S28 0xf498
2853#define ACLC2S28 REGx(R0900_P1_ACLC2S28)
2854#define F0900_P1_OLDI3Q_MODE 0xf4980080
2855#define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030
2856#define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f
2857
2858/*P1_ACLC2S216A*/
2859#define R0900_P1_ACLC2S216A 0xf499
2860#define ACLC2S216A REGx(R0900_P1_ACLC2S216A)
2861#define F0900_P1_DIS_C3STOPA2 0xf4990080
2862#define F0900_P1_CAR2S2_16ADERAT 0xf4990040
2863#define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030
2864#define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f
2865
2866/*P1_ACLC2S232A*/
2867#define R0900_P1_ACLC2S232A 0xf49a
2868#define ACLC2S232A REGx(R0900_P1_ACLC2S232A)
2869#define F0900_P1_CAR2S2_32ADERAT 0xf49a0040
2870#define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030
2871#define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f
2872
2873/*P1_BCLC2S2Q*/
2874#define R0900_P1_BCLC2S2Q 0xf49c
2875#define BCLC2S2Q REGx(R0900_P1_BCLC2S2Q)
2876#define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030
2877#define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f
2878
2879/*P1_BCLC2S28*/
2880#define R0900_P1_BCLC2S28 0xf49d
2881#define BCLC2S28 REGx(R0900_P1_BCLC2S28)
2882#define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030
2883#define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f
2884
2885/*P1_BCLC2S216A*/
2886#define R0900_P1_BCLC2S216A 0xf49e
2887#define BCLC2S216A REGx(R0900_P1_BCLC2S216A)
2888
2889/*P1_BCLC2S232A*/
2890#define R0900_P1_BCLC2S232A 0xf49f
2891#define BCLC2S232A REGx(R0900_P1_BCLC2S232A)
2892
2893/*P1_PLROOT2*/
2894#define R0900_P1_PLROOT2 0xf4ac
2895#define PLROOT2 REGx(R0900_P1_PLROOT2)
2896#define F0900_P1_PLSCRAMB_MODE 0xf4ac000c
2897#define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003
2898
2899/*P1_PLROOT1*/
2900#define R0900_P1_PLROOT1 0xf4ad
2901#define PLROOT1 REGx(R0900_P1_PLROOT1)
2902#define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff
2903
2904/*P1_PLROOT0*/
2905#define R0900_P1_PLROOT0 0xf4ae
2906#define PLROOT0 REGx(R0900_P1_PLROOT0)
2907#define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff
2908
2909/*P1_MODCODLST0*/
2910#define R0900_P1_MODCODLST0 0xf4b0
2911#define MODCODLST0 REGx(R0900_P1_MODCODLST0)
2912
2913/*P1_MODCODLST1*/
2914#define R0900_P1_MODCODLST1 0xf4b1
2915#define MODCODLST1 REGx(R0900_P1_MODCODLST1)
2916#define F0900_P1_DIS_MODCOD29 0xf4b100f0
2917#define F0900_P1_DIS_32PSK_9_10 0xf4b1000f
2918
2919/*P1_MODCODLST2*/
2920#define R0900_P1_MODCODLST2 0xf4b2
2921#define MODCODLST2 REGx(R0900_P1_MODCODLST2)
2922#define F0900_P1_DIS_32PSK_8_9 0xf4b200f0
2923#define F0900_P1_DIS_32PSK_5_6 0xf4b2000f
2924
2925/*P1_MODCODLST3*/
2926#define R0900_P1_MODCODLST3 0xf4b3
2927#define MODCODLST3 REGx(R0900_P1_MODCODLST3)
2928#define F0900_P1_DIS_32PSK_4_5 0xf4b300f0
2929#define F0900_P1_DIS_32PSK_3_4 0xf4b3000f
2930
2931/*P1_MODCODLST4*/
2932#define R0900_P1_MODCODLST4 0xf4b4
2933#define MODCODLST4 REGx(R0900_P1_MODCODLST4)
2934#define F0900_P1_DIS_16PSK_9_10 0xf4b400f0
2935#define F0900_P1_DIS_16PSK_8_9 0xf4b4000f
2936
2937/*P1_MODCODLST5*/
2938#define R0900_P1_MODCODLST5 0xf4b5
2939#define MODCODLST5 REGx(R0900_P1_MODCODLST5)
2940#define F0900_P1_DIS_16PSK_5_6 0xf4b500f0
2941#define F0900_P1_DIS_16PSK_4_5 0xf4b5000f
2942
2943/*P1_MODCODLST6*/
2944#define R0900_P1_MODCODLST6 0xf4b6
2945#define MODCODLST6 REGx(R0900_P1_MODCODLST6)
2946#define F0900_P1_DIS_16PSK_3_4 0xf4b600f0
2947#define F0900_P1_DIS_16PSK_2_3 0xf4b6000f
2948
2949/*P1_MODCODLST7*/
2950#define R0900_P1_MODCODLST7 0xf4b7
2951#define MODCODLST7 REGx(R0900_P1_MODCODLST7)
2952#define F0900_P1_DIS_8P_9_10 0xf4b700f0
2953#define F0900_P1_DIS_8P_8_9 0xf4b7000f
2954
2955/*P1_MODCODLST8*/
2956#define R0900_P1_MODCODLST8 0xf4b8
2957#define MODCODLST8 REGx(R0900_P1_MODCODLST8)
2958#define F0900_P1_DIS_8P_5_6 0xf4b800f0
2959#define F0900_P1_DIS_8P_3_4 0xf4b8000f
2960
2961/*P1_MODCODLST9*/
2962#define R0900_P1_MODCODLST9 0xf4b9
2963#define MODCODLST9 REGx(R0900_P1_MODCODLST9)
2964#define F0900_P1_DIS_8P_2_3 0xf4b900f0
2965#define F0900_P1_DIS_8P_3_5 0xf4b9000f
2966
2967/*P1_MODCODLSTA*/
2968#define R0900_P1_MODCODLSTA 0xf4ba
2969#define MODCODLSTA REGx(R0900_P1_MODCODLSTA)
2970#define F0900_P1_DIS_QP_9_10 0xf4ba00f0
2971#define F0900_P1_DIS_QP_8_9 0xf4ba000f
2972
2973/*P1_MODCODLSTB*/
2974#define R0900_P1_MODCODLSTB 0xf4bb
2975#define MODCODLSTB REGx(R0900_P1_MODCODLSTB)
2976#define F0900_P1_DIS_QP_5_6 0xf4bb00f0
2977#define F0900_P1_DIS_QP_4_5 0xf4bb000f
2978
2979/*P1_MODCODLSTC*/
2980#define R0900_P1_MODCODLSTC 0xf4bc
2981#define MODCODLSTC REGx(R0900_P1_MODCODLSTC)
2982#define F0900_P1_DIS_QP_3_4 0xf4bc00f0
2983#define F0900_P1_DIS_QP_2_3 0xf4bc000f
2984
2985/*P1_MODCODLSTD*/
2986#define R0900_P1_MODCODLSTD 0xf4bd
2987#define MODCODLSTD REGx(R0900_P1_MODCODLSTD)
2988#define F0900_P1_DIS_QP_3_5 0xf4bd00f0
2989#define F0900_P1_DIS_QP_1_2 0xf4bd000f
2990
2991/*P1_MODCODLSTE*/
2992#define R0900_P1_MODCODLSTE 0xf4be
2993#define MODCODLSTE REGx(R0900_P1_MODCODLSTE)
2994#define F0900_P1_DIS_QP_2_5 0xf4be00f0
2995#define F0900_P1_DIS_QP_1_3 0xf4be000f
2996
2997/*P1_MODCODLSTF*/
2998#define R0900_P1_MODCODLSTF 0xf4bf
2999#define MODCODLSTF REGx(R0900_P1_MODCODLSTF)
3000#define F0900_P1_DIS_QP_1_4 0xf4bf00f0
3001
3002/*P1_GAUSSR0*/
3003#define R0900_P1_GAUSSR0 0xf4c0
3004#define GAUSSR0 REGx(R0900_P1_GAUSSR0)
3005#define F0900_P1_EN_CCIMODE 0xf4c00080
3006#define F0900_P1_R0_GAUSSIEN 0xf4c0007f
3007
3008/*P1_CCIR0*/
3009#define R0900_P1_CCIR0 0xf4c1
3010#define CCIR0 REGx(R0900_P1_CCIR0)
3011#define F0900_P1_CCIDETECT_PLHONLY 0xf4c10080
3012#define F0900_P1_R0_CCI 0xf4c1007f
3013
3014/*P1_CCIQUANT*/
3015#define R0900_P1_CCIQUANT 0xf4c2
3016#define CCIQUANT REGx(R0900_P1_CCIQUANT)
3017#define F0900_P1_CCI_BETA 0xf4c200e0
3018#define F0900_P1_CCI_QUANT 0xf4c2001f
3019
3020/*P1_CCITHRES*/
3021#define R0900_P1_CCITHRES 0xf4c3
3022#define CCITHRES REGx(R0900_P1_CCITHRES)
3023#define F0900_P1_CCI_THRESHOLD 0xf4c300ff
3024
3025/*P1_CCIACC*/
3026#define R0900_P1_CCIACC 0xf4c4
3027#define CCIACC REGx(R0900_P1_CCIACC)
3028#define F0900_P1_CCI_VALUE 0xf4c400ff
3029
3030/*P1_DMDRESCFG*/
3031#define R0900_P1_DMDRESCFG 0xf4c6
3032#define DMDRESCFG REGx(R0900_P1_DMDRESCFG)
3033#define F0900_P1_DMDRES_RESET 0xf4c60080
3034#define F0900_P1_DMDRES_STRALL 0xf4c60008
3035#define F0900_P1_DMDRES_NEWONLY 0xf4c60004
3036#define F0900_P1_DMDRES_NOSTORE 0xf4c60002
3037
3038/*P1_DMDRESADR*/
3039#define R0900_P1_DMDRESADR 0xf4c7
3040#define DMDRESADR REGx(R0900_P1_DMDRESADR)
3041#define F0900_P1_DMDRES_VALIDCFR 0xf4c70040
3042#define F0900_P1_DMDRES_MEMFULL 0xf4c70030
3043#define F0900_P1_DMDRES_RESNBR 0xf4c7000f
3044
3045/*P1_DMDRESDATA7*/
3046#define R0900_P1_DMDRESDATA7 0xf4c8
3047#define F0900_P1_DMDRES_DATA7 0xf4c800ff
3048
3049/*P1_DMDRESDATA6*/
3050#define R0900_P1_DMDRESDATA6 0xf4c9
3051#define F0900_P1_DMDRES_DATA6 0xf4c900ff
3052
3053/*P1_DMDRESDATA5*/
3054#define R0900_P1_DMDRESDATA5 0xf4ca
3055#define F0900_P1_DMDRES_DATA5 0xf4ca00ff
3056
3057/*P1_DMDRESDATA4*/
3058#define R0900_P1_DMDRESDATA4 0xf4cb
3059#define F0900_P1_DMDRES_DATA4 0xf4cb00ff
3060
3061/*P1_DMDRESDATA3*/
3062#define R0900_P1_DMDRESDATA3 0xf4cc
3063#define F0900_P1_DMDRES_DATA3 0xf4cc00ff
3064
3065/*P1_DMDRESDATA2*/
3066#define R0900_P1_DMDRESDATA2 0xf4cd
3067#define F0900_P1_DMDRES_DATA2 0xf4cd00ff
3068
3069/*P1_DMDRESDATA1*/
3070#define R0900_P1_DMDRESDATA1 0xf4ce
3071#define F0900_P1_DMDRES_DATA1 0xf4ce00ff
3072
3073/*P1_DMDRESDATA0*/
3074#define R0900_P1_DMDRESDATA0 0xf4cf
3075#define F0900_P1_DMDRES_DATA0 0xf4cf00ff
3076
3077/*P1_FFEI1*/
3078#define R0900_P1_FFEI1 0xf4d0
3079#define FFEI1 REGx(R0900_P1_FFEI1)
3080#define F0900_P1_FFE_ACCI1 0xf4d001ff
3081
3082/*P1_FFEQ1*/
3083#define R0900_P1_FFEQ1 0xf4d1
3084#define FFEQ1 REGx(R0900_P1_FFEQ1)
3085#define F0900_P1_FFE_ACCQ1 0xf4d101ff
3086
3087/*P1_FFEI2*/
3088#define R0900_P1_FFEI2 0xf4d2
3089#define FFEI2 REGx(R0900_P1_FFEI2)
3090#define F0900_P1_FFE_ACCI2 0xf4d201ff
3091
3092/*P1_FFEQ2*/
3093#define R0900_P1_FFEQ2 0xf4d3
3094#define FFEQ2 REGx(R0900_P1_FFEQ2)
3095#define F0900_P1_FFE_ACCQ2 0xf4d301ff
3096
3097/*P1_FFEI3*/
3098#define R0900_P1_FFEI3 0xf4d4
3099#define FFEI3 REGx(R0900_P1_FFEI3)
3100#define F0900_P1_FFE_ACCI3 0xf4d401ff
3101
3102/*P1_FFEQ3*/
3103#define R0900_P1_FFEQ3 0xf4d5
3104#define FFEQ3 REGx(R0900_P1_FFEQ3)
3105#define F0900_P1_FFE_ACCQ3 0xf4d501ff
3106
3107/*P1_FFEI4*/
3108#define R0900_P1_FFEI4 0xf4d6
3109#define FFEI4 REGx(R0900_P1_FFEI4)
3110#define F0900_P1_FFE_ACCI4 0xf4d601ff
3111
3112/*P1_FFEQ4*/
3113#define R0900_P1_FFEQ4 0xf4d7
3114#define FFEQ4 REGx(R0900_P1_FFEQ4)
3115#define F0900_P1_FFE_ACCQ4 0xf4d701ff
3116
3117/*P1_FFECFG*/
3118#define R0900_P1_FFECFG 0xf4d8
3119#define FFECFG REGx(R0900_P1_FFECFG)
3120#define F0900_P1_EQUALFFE_ON 0xf4d80040
3121#define F0900_P1_MU_EQUALFFE 0xf4d80007
3122
3123/*P1_TNRCFG*/
3124#define R0900_P1_TNRCFG 0xf4e0
3125#define TNRCFG REGx(R0900_P1_TNRCFG)
3126#define F0900_P1_TUN_ACKFAIL 0xf4e00080
3127#define F0900_P1_TUN_TYPE 0xf4e00070
3128#define F0900_P1_TUN_SECSTOP 0xf4e00008
3129#define F0900_P1_TUN_VCOSRCH 0xf4e00004
3130#define F0900_P1_TUN_MADDRESS 0xf4e00003
3131
3132/*P1_TNRCFG2*/
3133#define R0900_P1_TNRCFG2 0xf4e1
3134#define TNRCFG2 REGx(R0900_P1_TNRCFG2)
3135#define F0900_P1_TUN_IQSWAP 0xf4e10080
3136#define F0900_P1_DIS_BWCALC 0xf4e10004
3137#define F0900_P1_SHORT_WAITSTATES 0xf4e10002
3138
3139/*P1_TNRXTAL*/
3140#define R0900_P1_TNRXTAL 0xf4e4
3141#define TNRXTAL REGx(R0900_P1_TNRXTAL)
3142#define F0900_P1_TUN_XTALFREQ 0xf4e4001f
3143
3144/*P1_TNRSTEPS*/
3145#define R0900_P1_TNRSTEPS 0xf4e7
3146#define TNRSTEPS REGx(R0900_P1_TNRSTEPS)
3147#define F0900_P1_TUNER_BW0P125 0xf4e70080
3148#define F0900_P1_BWINC_OFFSET 0xf4e70170
3149#define F0900_P1_SOFTSTEP_RNG 0xf4e70008
3150#define F0900_P1_TUN_BWOFFSET 0xf4e70007
3151
3152/*P1_TNRGAIN*/
3153#define R0900_P1_TNRGAIN 0xf4e8
3154#define TNRGAIN REGx(R0900_P1_TNRGAIN)
3155#define F0900_P1_TUN_KDIVEN 0xf4e800c0
3156#define F0900_P1_STB6X00_OCK 0xf4e80030
3157#define F0900_P1_TUN_GAIN 0xf4e8000f
3158
3159/*P1_TNRRF1*/
3160#define R0900_P1_TNRRF1 0xf4e9
3161#define TNRRF1 REGx(R0900_P1_TNRRF1)
3162#define F0900_P1_TUN_RFFREQ2 0xf4e900ff
3163#define TUN_RFFREQ2 FLDx(F0900_P1_TUN_RFFREQ2)
3164
3165/*P1_TNRRF0*/
3166#define R0900_P1_TNRRF0 0xf4ea
3167#define TNRRF0 REGx(R0900_P1_TNRRF0)
3168#define F0900_P1_TUN_RFFREQ1 0xf4ea00ff
3169#define TUN_RFFREQ1 FLDx(F0900_P1_TUN_RFFREQ1)
3170
3171/*P1_TNRBW*/
3172#define R0900_P1_TNRBW 0xf4eb
3173#define TNRBW REGx(R0900_P1_TNRBW)
3174#define F0900_P1_TUN_RFFREQ0 0xf4eb00c0
3175#define TUN_RFFREQ0 FLDx(F0900_P1_TUN_RFFREQ0)
3176#define F0900_P1_TUN_BW 0xf4eb003f
3177#define TUN_BW FLDx(F0900_P1_TUN_BW)
3178
3179/*P1_TNRADJ*/
3180#define R0900_P1_TNRADJ 0xf4ec
3181#define TNRADJ REGx(R0900_P1_TNRADJ)
3182#define F0900_P1_STB61X0_CALTIME 0xf4ec0040
3183
3184/*P1_TNRCTL2*/
3185#define R0900_P1_TNRCTL2 0xf4ed
3186#define TNRCTL2 REGx(R0900_P1_TNRCTL2)
3187#define F0900_P1_STB61X0_RCCKOFF 0xf4ed0080
3188#define F0900_P1_STB61X0_ICP_SDOFF 0xf4ed0040
3189#define F0900_P1_STB61X0_DCLOOPOFF 0xf4ed0020
3190#define F0900_P1_STB61X0_REFOUTSEL 0xf4ed0010
3191#define F0900_P1_STB61X0_CALOFF 0xf4ed0008
3192#define F0900_P1_STB6XX0_LPT_BEN 0xf4ed0004
3193#define F0900_P1_STB6XX0_RX_OSCP 0xf4ed0002
3194#define F0900_P1_STB6XX0_SYN 0xf4ed0001
3195
3196/*P1_TNRCFG3*/
3197#define R0900_P1_TNRCFG3 0xf4ee
3198#define TNRCFG3 REGx(R0900_P1_TNRCFG3)
3199#define F0900_P1_TUN_PLLFREQ 0xf4ee001c
3200#define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003
3201
3202/*P1_TNRLAUNCH*/
3203#define R0900_P1_TNRLAUNCH 0xf4f0
3204#define TNRLAUNCH REGx(R0900_P1_TNRLAUNCH)
3205
3206/*P1_TNRLD*/
3207#define R0900_P1_TNRLD 0xf4f0
3208#define TNRLD REGx(R0900_P1_TNRLD)
3209#define F0900_P1_TUNLD_VCOING 0xf4f00080
3210#define F0900_P1_TUN_REG1FAIL 0xf4f00040
3211#define F0900_P1_TUN_REG2FAIL 0xf4f00020
3212#define F0900_P1_TUN_REG3FAIL 0xf4f00010
3213#define F0900_P1_TUN_REG4FAIL 0xf4f00008
3214#define F0900_P1_TUN_REG5FAIL 0xf4f00004
3215#define F0900_P1_TUN_BWING 0xf4f00002
3216#define F0900_P1_TUN_LOCKED 0xf4f00001
3217
3218/*P1_TNROBSL*/
3219#define R0900_P1_TNROBSL 0xf4f6
3220#define TNROBSL REGx(R0900_P1_TNROBSL)
3221#define F0900_P1_TUN_I2CABORTED 0xf4f60080
3222#define F0900_P1_TUN_LPEN 0xf4f60040
3223#define F0900_P1_TUN_FCCK 0xf4f60020
3224#define F0900_P1_TUN_I2CLOCKED 0xf4f60010
3225#define F0900_P1_TUN_PROGDONE 0xf4f6000c
3226#define F0900_P1_TUN_RFRESTE1 0xf4f60003
3227#define TUN_RFRESTE1 FLDx(F0900_P1_TUN_RFRESTE1)
3228
3229/*P1_TNRRESTE*/
3230#define R0900_P1_TNRRESTE 0xf4f7
3231#define TNRRESTE REGx(R0900_P1_TNRRESTE)
3232#define F0900_P1_TUN_RFRESTE0 0xf4f700ff
3233#define TUN_RFRESTE0 FLDx(F0900_P1_TUN_RFRESTE0)
3234
3235/*P1_SMAPCOEF7*/
3236#define R0900_P1_SMAPCOEF7 0xf500
3237#define SMAPCOEF7 REGx(R0900_P1_SMAPCOEF7)
3238#define F0900_P1_DIS_QSCALE 0xf5000080
3239#define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f
3240
3241/*P1_SMAPCOEF6*/
3242#define R0900_P1_SMAPCOEF6 0xf501
3243#define SMAPCOEF6 REGx(R0900_P1_SMAPCOEF6)
3244#define F0900_P1_ADJ_8PSKLLR1 0xf5010004
3245#define F0900_P1_OLD_8PSKLLR1 0xf5010002
3246#define F0900_P1_DIS_AB8PSK 0xf5010001
3247
3248/*P1_SMAPCOEF5*/
3249#define R0900_P1_SMAPCOEF5 0xf502
3250#define SMAPCOEF5 REGx(R0900_P1_SMAPCOEF5)
3251#define F0900_P1_DIS_8SCALE 0xf5020080
3252#define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f
3253
3254/*P1_NCO2MAX1*/
3255#define R0900_P1_NCO2MAX1 0xf514
3256#define NCO2MAX1 REGx(R0900_P1_NCO2MAX1)
3257#define F0900_P1_TETA2_MAXVABS1 0xf51400ff
3258
3259/*P1_NCO2MAX0*/
3260#define R0900_P1_NCO2MAX0 0xf515
3261#define NCO2MAX0 REGx(R0900_P1_NCO2MAX0)
3262#define F0900_P1_TETA2_MAXVABS0 0xf51500ff
3263
3264/*P1_NCO2FR1*/
3265#define R0900_P1_NCO2FR1 0xf516
3266#define NCO2FR1 REGx(R0900_P1_NCO2FR1)
3267#define F0900_P1_NCO2FINAL_ANGLE1 0xf51600ff
3268
3269/*P1_NCO2FR0*/
3270#define R0900_P1_NCO2FR0 0xf517
3271#define NCO2FR0 REGx(R0900_P1_NCO2FR0)
3272#define F0900_P1_NCO2FINAL_ANGLE0 0xf51700ff
3273
3274/*P1_CFR2AVRGE1*/
3275#define R0900_P1_CFR2AVRGE1 0xf518
3276#define CFR2AVRGE1 REGx(R0900_P1_CFR2AVRGE1)
3277#define F0900_P1_I2C_CFR2AVERAGE1 0xf51800ff
3278
3279/*P1_CFR2AVRGE0*/
3280#define R0900_P1_CFR2AVRGE0 0xf519
3281#define CFR2AVRGE0 REGx(R0900_P1_CFR2AVRGE0)
3282#define F0900_P1_I2C_CFR2AVERAGE0 0xf51900ff
3283
3284/*P1_DMDPLHSTAT*/
3285#define R0900_P1_DMDPLHSTAT 0xf520
3286#define DMDPLHSTAT REGx(R0900_P1_DMDPLHSTAT)
3287#define F0900_P1_PLH_STATISTIC 0xf52000ff
3288
3289/*P1_LOCKTIME3*/
3290#define R0900_P1_LOCKTIME3 0xf522
3291#define LOCKTIME3 REGx(R0900_P1_LOCKTIME3)
3292#define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff
3293
3294/*P1_LOCKTIME2*/
3295#define R0900_P1_LOCKTIME2 0xf523
3296#define LOCKTIME2 REGx(R0900_P1_LOCKTIME2)
3297#define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff
3298
3299/*P1_LOCKTIME1*/
3300#define R0900_P1_LOCKTIME1 0xf524
3301#define LOCKTIME1 REGx(R0900_P1_LOCKTIME1)
3302#define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff
3303
3304/*P1_LOCKTIME0*/
3305#define R0900_P1_LOCKTIME0 0xf525
3306#define LOCKTIME0 REGx(R0900_P1_LOCKTIME0)
3307#define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff
3308
3309/*P1_VITSCALE*/
3310#define R0900_P1_VITSCALE 0xf532
3311#define VITSCALE REGx(R0900_P1_VITSCALE)
3312#define F0900_P1_NVTH_NOSRANGE 0xf5320080
3313#define F0900_P1_VERROR_MAXMODE 0xf5320040
3314#define F0900_P1_NSLOWSN_LOCKED 0xf5320008
3315#define F0900_P1_DIS_RSFLOCK 0xf5320002
3316
3317/*P1_FECM*/
3318#define R0900_P1_FECM 0xf533
3319#define FECM REGx(R0900_P1_FECM)
3320#define F0900_P1_DSS_DVB 0xf5330080
3321#define DSS_DVB FLDx(F0900_P1_DSS_DVB)
3322#define F0900_P1_DSS_SRCH 0xf5330010
3323#define F0900_P1_SYNCVIT 0xf5330002
3324#define F0900_P1_IQINV 0xf5330001
3325#define IQINV FLDx(F0900_P1_IQINV)
3326
3327/*P1_VTH12*/
3328#define R0900_P1_VTH12 0xf534
3329#define VTH12 REGx(R0900_P1_VTH12)
3330#define F0900_P1_VTH12 0xf53400ff
3331
3332/*P1_VTH23*/
3333#define R0900_P1_VTH23 0xf535
3334#define VTH23 REGx(R0900_P1_VTH23)
3335#define F0900_P1_VTH23 0xf53500ff
3336
3337/*P1_VTH34*/
3338#define R0900_P1_VTH34 0xf536
3339#define VTH34 REGx(R0900_P1_VTH34)
3340#define F0900_P1_VTH34 0xf53600ff
3341
3342/*P1_VTH56*/
3343#define R0900_P1_VTH56 0xf537
3344#define VTH56 REGx(R0900_P1_VTH56)
3345#define F0900_P1_VTH56 0xf53700ff
3346
3347/*P1_VTH67*/
3348#define R0900_P1_VTH67 0xf538
3349#define VTH67 REGx(R0900_P1_VTH67)
3350#define F0900_P1_VTH67 0xf53800ff
3351
3352/*P1_VTH78*/
3353#define R0900_P1_VTH78 0xf539
3354#define VTH78 REGx(R0900_P1_VTH78)
3355#define F0900_P1_VTH78 0xf53900ff
3356
3357/*P1_VITCURPUN*/
3358#define R0900_P1_VITCURPUN 0xf53a
3359#define VITCURPUN REGx(R0900_P1_VITCURPUN)
3360#define F0900_P1_VIT_CURPUN 0xf53a001f
3361#define VIT_CURPUN FLDx(F0900_P1_VIT_CURPUN)
3362
3363/*P1_VERROR*/
3364#define R0900_P1_VERROR 0xf53b
3365#define VERROR REGx(R0900_P1_VERROR)
3366#define F0900_P1_REGERR_VIT 0xf53b00ff
3367
3368/*P1_PRVIT*/
3369#define R0900_P1_PRVIT 0xf53c
3370#define PRVIT REGx(R0900_P1_PRVIT)
3371#define F0900_P1_DIS_VTHLOCK 0xf53c0040
3372#define F0900_P1_E7_8VIT 0xf53c0020
3373#define F0900_P1_E6_7VIT 0xf53c0010
3374#define F0900_P1_E5_6VIT 0xf53c0008
3375#define F0900_P1_E3_4VIT 0xf53c0004
3376#define F0900_P1_E2_3VIT 0xf53c0002
3377#define F0900_P1_E1_2VIT 0xf53c0001
3378
3379/*P1_VAVSRVIT*/
3380#define R0900_P1_VAVSRVIT 0xf53d
3381#define VAVSRVIT REGx(R0900_P1_VAVSRVIT)
3382#define F0900_P1_AMVIT 0xf53d0080
3383#define F0900_P1_FROZENVIT 0xf53d0040
3384#define F0900_P1_SNVIT 0xf53d0030
3385#define F0900_P1_TOVVIT 0xf53d000c
3386#define F0900_P1_HYPVIT 0xf53d0003
3387
3388/*P1_VSTATUSVIT*/
3389#define R0900_P1_VSTATUSVIT 0xf53e
3390#define VSTATUSVIT REGx(R0900_P1_VSTATUSVIT)
3391#define F0900_P1_PRFVIT 0xf53e0010
3392#define PRFVIT FLDx(F0900_P1_PRFVIT)
3393#define F0900_P1_LOCKEDVIT 0xf53e0008
3394#define LOCKEDVIT FLDx(F0900_P1_LOCKEDVIT)
3395
3396/*P1_VTHINUSE*/
3397#define R0900_P1_VTHINUSE 0xf53f
3398#define VTHINUSE REGx(R0900_P1_VTHINUSE)
3399#define F0900_P1_VIT_INUSE 0xf53f00ff
3400
3401/*P1_KDIV12*/
3402#define R0900_P1_KDIV12 0xf540
3403#define KDIV12 REGx(R0900_P1_KDIV12)
3404#define F0900_P1_K_DIVIDER_12 0xf540007f
3405
3406/*P1_KDIV23*/
3407#define R0900_P1_KDIV23 0xf541
3408#define KDIV23 REGx(R0900_P1_KDIV23)
3409#define F0900_P1_K_DIVIDER_23 0xf541007f
3410
3411/*P1_KDIV34*/
3412#define R0900_P1_KDIV34 0xf542
3413#define KDIV34 REGx(R0900_P1_KDIV34)
3414#define F0900_P1_K_DIVIDER_34 0xf542007f
3415
3416/*P1_KDIV56*/
3417#define R0900_P1_KDIV56 0xf543
3418#define KDIV56 REGx(R0900_P1_KDIV56)
3419#define F0900_P1_K_DIVIDER_56 0xf543007f
3420
3421/*P1_KDIV67*/
3422#define R0900_P1_KDIV67 0xf544
3423#define KDIV67 REGx(R0900_P1_KDIV67)
3424#define F0900_P1_K_DIVIDER_67 0xf544007f
3425
3426/*P1_KDIV78*/
3427#define R0900_P1_KDIV78 0xf545
3428#define KDIV78 REGx(R0900_P1_KDIV78)
3429#define F0900_P1_K_DIVIDER_78 0xf545007f
3430
3431/*P1_PDELCTRL1*/
3432#define R0900_P1_PDELCTRL1 0xf550
3433#define PDELCTRL1 REGx(R0900_P1_PDELCTRL1)
3434#define F0900_P1_INV_MISMASK 0xf5500080
3435#define INV_MISMASK FLDx(F0900_P1_INV_MISMASK)
3436#define F0900_P1_FILTER_EN 0xf5500020
3437#define FILTER_EN FLDx(F0900_P1_FILTER_EN)
3438#define F0900_P1_EN_MIS00 0xf5500002
3439#define EN_MIS00 FLDx(F0900_P1_EN_MIS00)
3440#define F0900_P1_ALGOSWRST 0xf5500001
3441#define ALGOSWRST FLDx(F0900_P1_ALGOSWRST)
3442
3443/*P1_PDELCTRL2*/
3444#define R0900_P1_PDELCTRL2 0xf551
3445#define PDELCTRL2 REGx(R0900_P1_PDELCTRL2)
3446#define F0900_P1_RESET_UPKO_COUNT 0xf5510040
3447#define RESET_UPKO_COUNT FLDx(F0900_P1_RESET_UPKO_COUNT)
3448#define F0900_P1_FRAME_MODE 0xf5510002
3449#define F0900_P1_NOBCHERRFLG_USE 0xf5510001
3450
3451/*P1_HYSTTHRESH*/
3452#define R0900_P1_HYSTTHRESH 0xf554
3453#define HYSTTHRESH REGx(R0900_P1_HYSTTHRESH)
3454#define F0900_P1_UNLCK_THRESH 0xf55400f0
3455#define F0900_P1_DELIN_LCK_THRESH 0xf554000f
3456
3457/*P1_ISIENTRY*/
3458#define R0900_P1_ISIENTRY 0xf55e
3459#define ISIENTRY REGx(R0900_P1_ISIENTRY)
3460#define F0900_P1_ISI_ENTRY 0xf55e00ff
3461
3462/*P1_ISIBITENA*/
3463#define R0900_P1_ISIBITENA 0xf55f
3464#define ISIBITENA REGx(R0900_P1_ISIBITENA)
3465#define F0900_P1_ISI_BIT_EN 0xf55f00ff
3466
3467/*P1_MATSTR1*/
3468#define R0900_P1_MATSTR1 0xf560
3469#define MATSTR1 REGx(R0900_P1_MATSTR1)
3470#define F0900_P1_MATYPE_CURRENT1 0xf56000ff
3471
3472/*P1_MATSTR0*/
3473#define R0900_P1_MATSTR0 0xf561
3474#define MATSTR0 REGx(R0900_P1_MATSTR0)
3475#define F0900_P1_MATYPE_CURRENT0 0xf56100ff
3476
3477/*P1_UPLSTR1*/
3478#define R0900_P1_UPLSTR1 0xf562
3479#define UPLSTR1 REGx(R0900_P1_UPLSTR1)
3480#define F0900_P1_UPL_CURRENT1 0xf56200ff
3481
3482/*P1_UPLSTR0*/
3483#define R0900_P1_UPLSTR0 0xf563
3484#define UPLSTR0 REGx(R0900_P1_UPLSTR0)
3485#define F0900_P1_UPL_CURRENT0 0xf56300ff
3486
3487/*P1_DFLSTR1*/
3488#define R0900_P1_DFLSTR1 0xf564
3489#define DFLSTR1 REGx(R0900_P1_DFLSTR1)
3490#define F0900_P1_DFL_CURRENT1 0xf56400ff
3491
3492/*P1_DFLSTR0*/
3493#define R0900_P1_DFLSTR0 0xf565
3494#define DFLSTR0 REGx(R0900_P1_DFLSTR0)
3495#define F0900_P1_DFL_CURRENT0 0xf56500ff
3496
3497/*P1_SYNCSTR*/
3498#define R0900_P1_SYNCSTR 0xf566
3499#define SYNCSTR REGx(R0900_P1_SYNCSTR)
3500#define F0900_P1_SYNC_CURRENT 0xf56600ff
3501
3502/*P1_SYNCDSTR1*/
3503#define R0900_P1_SYNCDSTR1 0xf567
3504#define SYNCDSTR1 REGx(R0900_P1_SYNCDSTR1)
3505#define F0900_P1_SYNCD_CURRENT1 0xf56700ff
3506
3507/*P1_SYNCDSTR0*/
3508#define R0900_P1_SYNCDSTR0 0xf568
3509#define SYNCDSTR0 REGx(R0900_P1_SYNCDSTR0)
3510#define F0900_P1_SYNCD_CURRENT0 0xf56800ff
3511
3512/*P1_PDELSTATUS1*/
3513#define R0900_P1_PDELSTATUS1 0xf569
3514#define F0900_P1_PKTDELIN_DELOCK 0xf5690080
3515#define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040
3516#define F0900_P1_CONTINUOUS_STREAM 0xf5690020
3517#define F0900_P1_UNACCEPTED_STREAM 0xf5690010
3518#define F0900_P1_BCH_ERROR_FLAG 0xf5690008
3519#define F0900_P1_PKTDELIN_LOCK 0xf5690002
3520#define PKTDELIN_LOCK FLDx(F0900_P1_PKTDELIN_LOCK)
3521#define F0900_P1_FIRST_LOCK 0xf5690001
3522
3523/*P1_PDELSTATUS2*/
3524#define R0900_P1_PDELSTATUS2 0xf56a
3525#define F0900_P1_FRAME_MODCOD 0xf56a007c
3526#define F0900_P1_FRAME_TYPE 0xf56a0003
3527
3528/*P1_BBFCRCKO1*/
3529#define R0900_P1_BBFCRCKO1 0xf56b
3530#define BBFCRCKO1 REGx(R0900_P1_BBFCRCKO1)
3531#define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff
3532
3533/*P1_BBFCRCKO0*/
3534#define R0900_P1_BBFCRCKO0 0xf56c
3535#define BBFCRCKO0 REGx(R0900_P1_BBFCRCKO0)
3536#define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff
3537
3538/*P1_UPCRCKO1*/
3539#define R0900_P1_UPCRCKO1 0xf56d
3540#define UPCRCKO1 REGx(R0900_P1_UPCRCKO1)
3541#define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff
3542
3543/*P1_UPCRCKO0*/
3544#define R0900_P1_UPCRCKO0 0xf56e
3545#define UPCRCKO0 REGx(R0900_P1_UPCRCKO0)
3546#define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff
3547
3548/*P1_PDELCTRL3*/
3549#define R0900_P1_PDELCTRL3 0xf56f
3550#define PDELCTRL3 REGx(R0900_P1_PDELCTRL3)
3551#define F0900_P1_PKTDEL_CONTFAIL 0xf56f0080
3552#define F0900_P1_NOFIFO_BCHERR 0xf56f0020
3553
3554/*P1_TSSTATEM*/
3555#define R0900_P1_TSSTATEM 0xf570
3556#define TSSTATEM REGx(R0900_P1_TSSTATEM)
3557#define F0900_P1_TSDIL_ON 0xf5700080
3558#define F0900_P1_TSRS_ON 0xf5700020
3559#define F0900_P1_TSDESCRAMB_ON 0xf5700010
3560#define F0900_P1_TSFRAME_MODE 0xf5700008
3561#define F0900_P1_TS_DISABLE 0xf5700004
3562#define F0900_P1_TSOUT_NOSYNC 0xf5700001
3563
3564/*P1_TSCFGH*/
3565#define R0900_P1_TSCFGH 0xf572
3566#define TSCFGH REGx(R0900_P1_TSCFGH)
3567#define F0900_P1_TSFIFO_DVBCI 0xf5720080
3568#define F0900_P1_TSFIFO_SERIAL 0xf5720040
3569#define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020
3570#define F0900_P1_TSFIFO_DUTY50 0xf5720010
3571#define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008
3572#define F0900_P1_TSFIFO_ERRMODE 0xf5720006
3573#define F0900_P1_RST_HWARE 0xf5720001
3574#define RST_HWARE FLDx(F0900_P1_RST_HWARE)
3575
3576/*P1_TSCFGM*/
3577#define R0900_P1_TSCFGM 0xf573
3578#define TSCFGM REGx(R0900_P1_TSCFGM)
3579#define F0900_P1_TSFIFO_MANSPEED 0xf57300c0
3580#define F0900_P1_TSFIFO_PERMDATA 0xf5730020
3581#define F0900_P1_TSFIFO_DPUNACT 0xf5730002
3582#define F0900_P1_TSFIFO_INVDATA 0xf5730001
3583
3584/*P1_TSCFGL*/
3585#define R0900_P1_TSCFGL 0xf574
3586#define TSCFGL REGx(R0900_P1_TSCFGL)
3587#define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0
3588#define F0900_P1_BCHERROR_MODE 0xf5740030
3589#define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008
3590#define F0900_P1_TSFIFO_EMBINDVB 0xf5740004
3591#define F0900_P1_TSFIFO_BITSPEED 0xf5740003
3592
3593/*P1_TSINSDELH*/
3594#define R0900_P1_TSINSDELH 0xf576
3595#define TSINSDELH REGx(R0900_P1_TSINSDELH)
3596#define F0900_P1_TSDEL_SYNCBYTE 0xf5760080
3597#define F0900_P1_TSDEL_XXHEADER 0xf5760040
3598#define F0900_P1_TSDEL_BBHEADER 0xf5760020
3599#define F0900_P1_TSDEL_DATAFIELD 0xf5760010
3600#define F0900_P1_TSINSDEL_ISCR 0xf5760008
3601#define F0900_P1_TSINSDEL_NPD 0xf5760004
3602#define F0900_P1_TSINSDEL_RSPARITY 0xf5760002
3603#define F0900_P1_TSINSDEL_CRC8 0xf5760001
3604
3605/*P1_TSDIVN*/
3606#define R0900_P1_TSDIVN 0xf579
3607#define TSDIVN REGx(R0900_P1_TSDIVN)
3608#define F0900_P1_TSFIFO_SPEEDMODE 0xf57900c0
3609
3610/*P1_TSCFG4*/
3611#define R0900_P1_TSCFG4 0xf57a
3612#define TSCFG4 REGx(R0900_P1_TSCFG4)
3613#define F0900_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0
3614
3615/*P1_TSSPEED*/
3616#define R0900_P1_TSSPEED 0xf580
3617#define TSSPEED REGx(R0900_P1_TSSPEED)
3618#define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff
3619
3620/*P1_TSSTATUS*/
3621#define R0900_P1_TSSTATUS 0xf581
3622#define TSSTATUS REGx(R0900_P1_TSSTATUS)
3623#define F0900_P1_TSFIFO_LINEOK 0xf5810080
3624#define TSFIFO_LINEOK FLDx(F0900_P1_TSFIFO_LINEOK)
3625#define F0900_P1_TSFIFO_ERROR 0xf5810040
3626#define F0900_P1_DIL_READY 0xf5810001
3627
3628/*P1_TSSTATUS2*/
3629#define R0900_P1_TSSTATUS2 0xf582
3630#define TSSTATUS2 REGx(R0900_P1_TSSTATUS2)
3631#define F0900_P1_TSFIFO_DEMODSEL 0xf5820080
3632#define F0900_P1_TSFIFOSPEED_STORE 0xf5820040
3633#define F0900_P1_DILXX_RESET 0xf5820020
3634#define F0900_P1_TSSERIAL_IMPOS 0xf5820010
3635#define F0900_P1_SCRAMBDETECT 0xf5820002
3636
3637/*P1_TSBITRATE1*/
3638#define R0900_P1_TSBITRATE1 0xf583
3639#define TSBITRATE1 REGx(R0900_P1_TSBITRATE1)
3640#define F0900_P1_TSFIFO_BITRATE1 0xf58300ff
3641
3642/*P1_TSBITRATE0*/
3643#define R0900_P1_TSBITRATE0 0xf584
3644#define TSBITRATE0 REGx(R0900_P1_TSBITRATE0)
3645#define F0900_P1_TSFIFO_BITRATE0 0xf58400ff
3646
3647/*P1_ERRCTRL1*/
3648#define R0900_P1_ERRCTRL1 0xf598
3649#define ERRCTRL1 REGx(R0900_P1_ERRCTRL1)
3650#define F0900_P1_ERR_SOURCE1 0xf59800f0
3651#define F0900_P1_NUM_EVENT1 0xf5980007
3652
3653/*P1_ERRCNT12*/
3654#define R0900_P1_ERRCNT12 0xf599
3655#define ERRCNT12 REGx(R0900_P1_ERRCNT12)
3656#define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080
3657#define F0900_P1_ERR_CNT12 0xf599007f
3658#define ERR_CNT12 FLDx(F0900_P1_ERR_CNT12)
3659
3660/*P1_ERRCNT11*/
3661#define R0900_P1_ERRCNT11 0xf59a
3662#define ERRCNT11 REGx(R0900_P1_ERRCNT11)
3663#define F0900_P1_ERR_CNT11 0xf59a00ff
3664#define ERR_CNT11 FLDx(F0900_P1_ERR_CNT11)
3665
3666/*P1_ERRCNT10*/
3667#define R0900_P1_ERRCNT10 0xf59b
3668#define ERRCNT10 REGx(R0900_P1_ERRCNT10)
3669#define F0900_P1_ERR_CNT10 0xf59b00ff
3670#define ERR_CNT10 FLDx(F0900_P1_ERR_CNT10)
3671
3672/*P1_ERRCTRL2*/
3673#define R0900_P1_ERRCTRL2 0xf59c
3674#define ERRCTRL2 REGx(R0900_P1_ERRCTRL2)
3675#define F0900_P1_ERR_SOURCE2 0xf59c00f0
3676#define F0900_P1_NUM_EVENT2 0xf59c0007
3677
3678/*P1_ERRCNT22*/
3679#define R0900_P1_ERRCNT22 0xf59d
3680#define ERRCNT22 REGx(R0900_P1_ERRCNT22)
3681#define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080
3682#define F0900_P1_ERR_CNT22 0xf59d007f
3683#define ERR_CNT22 FLDx(F0900_P1_ERR_CNT22)
3684
3685/*P1_ERRCNT21*/
3686#define R0900_P1_ERRCNT21 0xf59e
3687#define ERRCNT21 REGx(R0900_P1_ERRCNT21)
3688#define F0900_P1_ERR_CNT21 0xf59e00ff
3689#define ERR_CNT21 FLDx(F0900_P1_ERR_CNT21)
3690
3691/*P1_ERRCNT20*/
3692#define R0900_P1_ERRCNT20 0xf59f
3693#define ERRCNT20 REGx(R0900_P1_ERRCNT20)
3694#define F0900_P1_ERR_CNT20 0xf59f00ff
3695#define ERR_CNT20 FLDx(F0900_P1_ERR_CNT20)
3696
3697/*P1_FECSPY*/
3698#define R0900_P1_FECSPY 0xf5a0
3699#define FECSPY REGx(R0900_P1_FECSPY)
3700#define F0900_P1_SPY_ENABLE 0xf5a00080
3701#define F0900_P1_NO_SYNCBYTE 0xf5a00040
3702#define F0900_P1_SERIAL_MODE 0xf5a00020
3703#define F0900_P1_UNUSUAL_PACKET 0xf5a00010
3704#define F0900_P1_BERMETER_DATAMODE 0xf5a00008
3705#define F0900_P1_BERMETER_LMODE 0xf5a00002
3706#define F0900_P1_BERMETER_RESET 0xf5a00001
3707
3708/*P1_FSPYCFG*/
3709#define R0900_P1_FSPYCFG 0xf5a1
3710#define FSPYCFG REGx(R0900_P1_FSPYCFG)
3711#define F0900_P1_FECSPY_INPUT 0xf5a100c0
3712#define F0900_P1_RST_ON_ERROR 0xf5a10020
3713#define F0900_P1_ONE_SHOT 0xf5a10010
3714#define F0900_P1_I2C_MODE 0xf5a1000c
3715#define F0900_P1_SPY_HYSTERESIS 0xf5a10003
3716
3717/*P1_FSPYDATA*/
3718#define R0900_P1_FSPYDATA 0xf5a2
3719#define FSPYDATA REGx(R0900_P1_FSPYDATA)
3720#define F0900_P1_SPY_STUFFING 0xf5a20080
3721#define F0900_P1_SPY_CNULLPKT 0xf5a20020
3722#define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f
3723
3724/*P1_FSPYOUT*/
3725#define R0900_P1_FSPYOUT 0xf5a3
3726#define FSPYOUT REGx(R0900_P1_FSPYOUT)
3727#define F0900_P1_FSPY_DIRECT 0xf5a30080
3728#define F0900_P1_STUFF_MODE 0xf5a30007
3729
3730/*P1_FSTATUS*/
3731#define R0900_P1_FSTATUS 0xf5a4
3732#define FSTATUS REGx(R0900_P1_FSTATUS)
3733#define F0900_P1_SPY_ENDSIM 0xf5a40080
3734#define F0900_P1_VALID_SIM 0xf5a40040
3735#define F0900_P1_FOUND_SIGNAL 0xf5a40020
3736#define F0900_P1_DSS_SYNCBYTE 0xf5a40010
3737#define F0900_P1_RESULT_STATE 0xf5a4000f
3738
3739/*P1_FBERCPT4*/
3740#define R0900_P1_FBERCPT4 0xf5a8
3741#define FBERCPT4 REGx(R0900_P1_FBERCPT4)
3742#define F0900_P1_FBERMETER_CPT4 0xf5a800ff
3743
3744/*P1_FBERCPT3*/
3745#define R0900_P1_FBERCPT3 0xf5a9
3746#define FBERCPT3 REGx(R0900_P1_FBERCPT3)
3747#define F0900_P1_FBERMETER_CPT3 0xf5a900ff
3748
3749/*P1_FBERCPT2*/
3750#define R0900_P1_FBERCPT2 0xf5aa
3751#define FBERCPT2 REGx(R0900_P1_FBERCPT2)
3752#define F0900_P1_FBERMETER_CPT2 0xf5aa00ff
3753
3754/*P1_FBERCPT1*/
3755#define R0900_P1_FBERCPT1 0xf5ab
3756#define FBERCPT1 REGx(R0900_P1_FBERCPT1)
3757#define F0900_P1_FBERMETER_CPT1 0xf5ab00ff
3758
3759/*P1_FBERCPT0*/
3760#define R0900_P1_FBERCPT0 0xf5ac
3761#define FBERCPT0 REGx(R0900_P1_FBERCPT0)
3762#define F0900_P1_FBERMETER_CPT0 0xf5ac00ff
3763
3764/*P1_FBERERR2*/
3765#define R0900_P1_FBERERR2 0xf5ad
3766#define FBERERR2 REGx(R0900_P1_FBERERR2)
3767#define F0900_P1_FBERMETER_ERR2 0xf5ad00ff
3768
3769/*P1_FBERERR1*/
3770#define R0900_P1_FBERERR1 0xf5ae
3771#define FBERERR1 REGx(R0900_P1_FBERERR1)
3772#define F0900_P1_FBERMETER_ERR1 0xf5ae00ff
3773
3774/*P1_FBERERR0*/
3775#define R0900_P1_FBERERR0 0xf5af
3776#define FBERERR0 REGx(R0900_P1_FBERERR0)
3777#define F0900_P1_FBERMETER_ERR0 0xf5af00ff
3778
3779/*P1_FSPYBER*/
3780#define R0900_P1_FSPYBER 0xf5b2
3781#define FSPYBER REGx(R0900_P1_FSPYBER)
3782#define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010
3783#define F0900_P1_FSPYBER_UNSYNC 0xf5b20008
3784#define F0900_P1_FSPYBER_CTIME 0xf5b20007
3785
3786/*RCCFG2*/
3787#define R0900_RCCFG2 0xf600
3788
3789/*TSGENERAL*/
3790#define R0900_TSGENERAL 0xf630
3791#define F0900_TSFIFO_DISTS2PAR 0xf6300040
3792#define F0900_MUXSTREAM_OUTMODE 0xf6300008
3793#define F0900_TSFIFO_PERMPARAL 0xf6300006
3794
3795/*TSGENERAL1X*/
3796#define R0900_TSGENERAL1X 0xf670
3797
3798/*NBITER_NF4*/
3799#define R0900_NBITER_NF4 0xfa03
3800#define F0900_NBITER_NF_QP_1_2 0xfa0300ff
3801
3802/*NBITER_NF5*/
3803#define R0900_NBITER_NF5 0xfa04
3804#define F0900_NBITER_NF_QP_3_5 0xfa0400ff
3805
3806/*NBITER_NF6*/
3807#define R0900_NBITER_NF6 0xfa05
3808#define F0900_NBITER_NF_QP_2_3 0xfa0500ff
3809
3810/*NBITER_NF7*/
3811#define R0900_NBITER_NF7 0xfa06
3812#define F0900_NBITER_NF_QP_3_4 0xfa0600ff
3813
3814/*NBITER_NF8*/
3815#define R0900_NBITER_NF8 0xfa07
3816#define F0900_NBITER_NF_QP_4_5 0xfa0700ff
3817
3818/*NBITER_NF9*/
3819#define R0900_NBITER_NF9 0xfa08
3820#define F0900_NBITER_NF_QP_5_6 0xfa0800ff
3821
3822/*NBITER_NF10*/
3823#define R0900_NBITER_NF10 0xfa09
3824#define F0900_NBITER_NF_QP_8_9 0xfa0900ff
3825
3826/*NBITER_NF11*/
3827#define R0900_NBITER_NF11 0xfa0a
3828#define F0900_NBITER_NF_QP_9_10 0xfa0a00ff
3829
3830/*NBITER_NF12*/
3831#define R0900_NBITER_NF12 0xfa0b
3832#define F0900_NBITER_NF_8P_3_5 0xfa0b00ff
3833
3834/*NBITER_NF13*/
3835#define R0900_NBITER_NF13 0xfa0c
3836#define F0900_NBITER_NF_8P_2_3 0xfa0c00ff
3837
3838/*NBITER_NF14*/
3839#define R0900_NBITER_NF14 0xfa0d
3840#define F0900_NBITER_NF_8P_3_4 0xfa0d00ff
3841
3842/*NBITER_NF15*/
3843#define R0900_NBITER_NF15 0xfa0e
3844#define F0900_NBITER_NF_8P_5_6 0xfa0e00ff
3845
3846/*NBITER_NF16*/
3847#define R0900_NBITER_NF16 0xfa0f
3848#define F0900_NBITER_NF_8P_8_9 0xfa0f00ff
3849
3850/*NBITER_NF17*/
3851#define R0900_NBITER_NF17 0xfa10
3852#define F0900_NBITER_NF_8P_9_10 0xfa1000ff
3853
3854/*NBITERNOERR*/
3855#define R0900_NBITERNOERR 0xfa3f
3856#define F0900_NBITER_STOP_CRIT 0xfa3f000f
3857
3858/*GAINLLR_NF4*/
3859#define R0900_GAINLLR_NF4 0xfa43
3860#define F0900_GAINLLR_NF_QP_1_2 0xfa43007f
3861
3862/*GAINLLR_NF5*/
3863#define R0900_GAINLLR_NF5 0xfa44
3864#define F0900_GAINLLR_NF_QP_3_5 0xfa44007f
3865
3866/*GAINLLR_NF6*/
3867#define R0900_GAINLLR_NF6 0xfa45
3868#define F0900_GAINLLR_NF_QP_2_3 0xfa45007f
3869
3870/*GAINLLR_NF7*/
3871#define R0900_GAINLLR_NF7 0xfa46
3872#define F0900_GAINLLR_NF_QP_3_4 0xfa46007f
3873
3874/*GAINLLR_NF8*/
3875#define R0900_GAINLLR_NF8 0xfa47
3876#define F0900_GAINLLR_NF_QP_4_5 0xfa47007f
3877
3878/*GAINLLR_NF9*/
3879#define R0900_GAINLLR_NF9 0xfa48
3880#define F0900_GAINLLR_NF_QP_5_6 0xfa48007f
3881
3882/*GAINLLR_NF10*/
3883#define R0900_GAINLLR_NF10 0xfa49
3884#define F0900_GAINLLR_NF_QP_8_9 0xfa49007f
3885
3886/*GAINLLR_NF11*/
3887#define R0900_GAINLLR_NF11 0xfa4a
3888#define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f
3889
3890/*GAINLLR_NF12*/
3891#define R0900_GAINLLR_NF12 0xfa4b
3892#define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f
3893
3894/*GAINLLR_NF13*/
3895#define R0900_GAINLLR_NF13 0xfa4c
3896#define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f
3897
3898/*GAINLLR_NF14*/
3899#define R0900_GAINLLR_NF14 0xfa4d
3900#define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f
3901
3902/*GAINLLR_NF15*/
3903#define R0900_GAINLLR_NF15 0xfa4e
3904#define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f
3905
3906/*GAINLLR_NF16*/
3907#define R0900_GAINLLR_NF16 0xfa4f
3908#define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f
3909
3910/*GAINLLR_NF17*/
3911#define R0900_GAINLLR_NF17 0xfa50
3912#define F0900_GAINLLR_NF_8P_9_10 0xfa50007f
3913
3914/*CFGEXT*/
3915#define R0900_CFGEXT 0xfa80
3916#define F0900_STAGMODE 0xfa800080
3917#define F0900_BYPBCH 0xfa800040
3918#define F0900_BYPLDPC 0xfa800020
3919#define F0900_LDPCMODE 0xfa800010
3920#define F0900_INVLLRSIGN 0xfa800008
3921#define F0900_SHORTMULT 0xfa800004
3922#define F0900_EXTERNTX 0xfa800001
3923
3924/*GENCFG*/
3925#define R0900_GENCFG 0xfa86
3926#define F0900_BROADCAST 0xfa860010
3927#define F0900_PRIORITY 0xfa860002
3928#define F0900_DDEMOD 0xfa860001
3929
3930/*LDPCERR1*/
3931#define R0900_LDPCERR1 0xfa96
3932#define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff
3933
3934/*LDPCERR0*/
3935#define R0900_LDPCERR0 0xfa97
3936#define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff
3937
3938/*BCHERR*/
3939#define R0900_BCHERR 0xfa98
3940#define F0900_ERRORFLAG 0xfa980010
3941#define F0900_BCH_ERRORS_COUNTER 0xfa98000f
3942
3943/*TSTRES0*/
3944#define R0900_TSTRES0 0xff11
3945#define F0900_FRESFEC 0xff110080
3946
3947/*P2_TCTL4*/
3948#define R0900_P2_TCTL4 0xff28
3949#define F0900_P2_PN4_SELECT 0xff280020
3950
3951/*P1_TCTL4*/
3952#define R0900_P1_TCTL4 0xff48
3953#define TCTL4 shiftx(R0900_P1_TCTL4, demod, 0x20)
3954#define F0900_P1_PN4_SELECT 0xff480020
3955
3956/*P2_TSTDISRX*/
3957#define R0900_P2_TSTDISRX 0xff65
3958#define F0900_P2_PIN_SELECT1 0xff650008
3959
3960/*P1_TSTDISRX*/
3961#define R0900_P1_TSTDISRX 0xff67
3962#define TSTDISRX shiftx(R0900_P1_TSTDISRX, demod, 2)
3963#define F0900_P1_PIN_SELECT1 0xff670008
3964#define PIN_SELECT1 shiftx(F0900_P1_PIN_SELECT1, demod, 0x20000)
3965
3966#define STV0900_NBREGS 723
3967#define STV0900_NBFIELDS 1420
3968
3969#endif
3970
3971

source code of linux/drivers/media/dvb-frontends/stv0900_reg.h