1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Driver for Zarlink DVB-T ZL10353 demodulator |
4 | * |
5 | * Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au> |
6 | */ |
7 | |
8 | #include <linux/kernel.h> |
9 | #include <linux/module.h> |
10 | #include <linux/init.h> |
11 | #include <linux/delay.h> |
12 | #include <linux/string.h> |
13 | #include <linux/slab.h> |
14 | #include <asm/div64.h> |
15 | |
16 | #include <media/dvb_frontend.h> |
17 | #include "zl10353_priv.h" |
18 | #include "zl10353.h" |
19 | |
20 | struct zl10353_state { |
21 | struct i2c_adapter *i2c; |
22 | struct dvb_frontend frontend; |
23 | |
24 | struct zl10353_config config; |
25 | |
26 | u32 bandwidth; |
27 | u32 ucblocks; |
28 | u32 frequency; |
29 | }; |
30 | |
31 | static int debug; |
32 | #define dprintk(args...) \ |
33 | do { \ |
34 | if (debug) printk(KERN_DEBUG "zl10353: " args); \ |
35 | } while (0) |
36 | |
37 | static int debug_regs; |
38 | |
39 | static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val) |
40 | { |
41 | struct zl10353_state *state = fe->demodulator_priv; |
42 | u8 buf[2] = { reg, val }; |
43 | struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0, |
44 | .buf = buf, .len = 2 }; |
45 | int err = i2c_transfer(adap: state->i2c, msgs: &msg, num: 1); |
46 | if (err != 1) { |
47 | printk("zl10353: write to reg %x failed (err = %d)!\n" , reg, err); |
48 | return err; |
49 | } |
50 | return 0; |
51 | } |
52 | |
53 | static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen) |
54 | { |
55 | int err, i; |
56 | for (i = 0; i < ilen - 1; i++) |
57 | if ((err = zl10353_single_write(fe, reg: ibuf[0] + i, val: ibuf[i + 1]))) |
58 | return err; |
59 | |
60 | return 0; |
61 | } |
62 | |
63 | static int zl10353_read_register(struct zl10353_state *state, u8 reg) |
64 | { |
65 | int ret; |
66 | u8 b0[1] = { reg }; |
67 | u8 b1[1] = { 0 }; |
68 | struct i2c_msg msg[2] = { { .addr = state->config.demod_address, |
69 | .flags = 0, |
70 | .buf = b0, .len = 1 }, |
71 | { .addr = state->config.demod_address, |
72 | .flags = I2C_M_RD, |
73 | .buf = b1, .len = 1 } }; |
74 | |
75 | ret = i2c_transfer(adap: state->i2c, msgs: msg, num: 2); |
76 | |
77 | if (ret != 2) { |
78 | printk("%s: readreg error (reg=%d, ret==%i)\n" , |
79 | __func__, reg, ret); |
80 | return ret; |
81 | } |
82 | |
83 | return b1[0]; |
84 | } |
85 | |
86 | static void zl10353_dump_regs(struct dvb_frontend *fe) |
87 | { |
88 | struct zl10353_state *state = fe->demodulator_priv; |
89 | int ret; |
90 | u8 reg; |
91 | |
92 | /* Dump all registers. */ |
93 | for (reg = 0; ; reg++) { |
94 | if (reg % 16 == 0) { |
95 | if (reg) |
96 | printk(KERN_CONT "\n" ); |
97 | printk(KERN_DEBUG "%02x:" , reg); |
98 | } |
99 | ret = zl10353_read_register(state, reg); |
100 | if (ret >= 0) |
101 | printk(KERN_CONT " %02x" , (u8)ret); |
102 | else |
103 | printk(KERN_CONT " --" ); |
104 | if (reg == 0xff) |
105 | break; |
106 | } |
107 | printk(KERN_CONT "\n" ); |
108 | } |
109 | |
110 | static void zl10353_calc_nominal_rate(struct dvb_frontend *fe, |
111 | u32 bandwidth, |
112 | u16 *nominal_rate) |
113 | { |
114 | struct zl10353_state *state = fe->demodulator_priv; |
115 | u32 adc_clock = 450560; /* 45.056 MHz */ |
116 | u64 value; |
117 | u8 bw = bandwidth / 1000000; |
118 | |
119 | if (state->config.adc_clock) |
120 | adc_clock = state->config.adc_clock; |
121 | |
122 | value = (u64)10 * (1 << 23) / 7 * 125; |
123 | value = (bw * value) + adc_clock / 2; |
124 | *nominal_rate = div_u64(dividend: value, divisor: adc_clock); |
125 | |
126 | dprintk("%s: bw %d, adc_clock %d => 0x%x\n" , |
127 | __func__, bw, adc_clock, *nominal_rate); |
128 | } |
129 | |
130 | static void zl10353_calc_input_freq(struct dvb_frontend *fe, |
131 | u16 *input_freq) |
132 | { |
133 | struct zl10353_state *state = fe->demodulator_priv; |
134 | u32 adc_clock = 450560; /* 45.056 MHz */ |
135 | int if2 = 361667; /* 36.1667 MHz */ |
136 | int ife; |
137 | u64 value; |
138 | |
139 | if (state->config.adc_clock) |
140 | adc_clock = state->config.adc_clock; |
141 | if (state->config.if2) |
142 | if2 = state->config.if2; |
143 | |
144 | if (adc_clock >= if2 * 2) |
145 | ife = if2; |
146 | else { |
147 | ife = adc_clock - (if2 % adc_clock); |
148 | if (ife > adc_clock / 2) |
149 | ife = adc_clock - ife; |
150 | } |
151 | value = div_u64(dividend: (u64)65536 * ife + adc_clock / 2, divisor: adc_clock); |
152 | *input_freq = -value; |
153 | |
154 | dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n" , |
155 | __func__, if2, ife, adc_clock, -(int)value, *input_freq); |
156 | } |
157 | |
158 | static int zl10353_sleep(struct dvb_frontend *fe) |
159 | { |
160 | static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 }; |
161 | |
162 | zl10353_write(fe, ibuf: zl10353_softdown, ilen: sizeof(zl10353_softdown)); |
163 | return 0; |
164 | } |
165 | |
166 | static int zl10353_set_parameters(struct dvb_frontend *fe) |
167 | { |
168 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
169 | struct zl10353_state *state = fe->demodulator_priv; |
170 | u16 nominal_rate, input_freq; |
171 | u8 pllbuf[6] = { 0x67 }, acq_ctl = 0; |
172 | u16 tps = 0; |
173 | |
174 | state->frequency = c->frequency; |
175 | |
176 | zl10353_single_write(fe, reg: RESET, val: 0x80); |
177 | udelay(200); |
178 | zl10353_single_write(fe, reg: 0xEA, val: 0x01); |
179 | udelay(200); |
180 | zl10353_single_write(fe, reg: 0xEA, val: 0x00); |
181 | |
182 | zl10353_single_write(fe, reg: AGC_TARGET, val: 0x28); |
183 | |
184 | if (c->transmission_mode != TRANSMISSION_MODE_AUTO) |
185 | acq_ctl |= (1 << 0); |
186 | if (c->guard_interval != GUARD_INTERVAL_AUTO) |
187 | acq_ctl |= (1 << 1); |
188 | zl10353_single_write(fe, reg: ACQ_CTL, val: acq_ctl); |
189 | |
190 | switch (c->bandwidth_hz) { |
191 | case 6000000: |
192 | /* These are extrapolated from the 7 and 8MHz values */ |
193 | zl10353_single_write(fe, reg: MCLK_RATIO, val: 0x97); |
194 | zl10353_single_write(fe, reg: 0x64, val: 0x34); |
195 | zl10353_single_write(fe, reg: 0xcc, val: 0xdd); |
196 | break; |
197 | case 7000000: |
198 | zl10353_single_write(fe, reg: MCLK_RATIO, val: 0x86); |
199 | zl10353_single_write(fe, reg: 0x64, val: 0x35); |
200 | zl10353_single_write(fe, reg: 0xcc, val: 0x73); |
201 | break; |
202 | default: |
203 | c->bandwidth_hz = 8000000; |
204 | fallthrough; |
205 | case 8000000: |
206 | zl10353_single_write(fe, reg: MCLK_RATIO, val: 0x75); |
207 | zl10353_single_write(fe, reg: 0x64, val: 0x36); |
208 | zl10353_single_write(fe, reg: 0xcc, val: 0x73); |
209 | } |
210 | |
211 | zl10353_calc_nominal_rate(fe, bandwidth: c->bandwidth_hz, nominal_rate: &nominal_rate); |
212 | zl10353_single_write(fe, reg: TRL_NOMINAL_RATE_1, msb(nominal_rate)); |
213 | zl10353_single_write(fe, reg: TRL_NOMINAL_RATE_0, lsb(nominal_rate)); |
214 | state->bandwidth = c->bandwidth_hz; |
215 | |
216 | zl10353_calc_input_freq(fe, input_freq: &input_freq); |
217 | zl10353_single_write(fe, reg: INPUT_FREQ_1, msb(input_freq)); |
218 | zl10353_single_write(fe, reg: INPUT_FREQ_0, lsb(input_freq)); |
219 | |
220 | /* Hint at TPS settings */ |
221 | switch (c->code_rate_HP) { |
222 | case FEC_2_3: |
223 | tps |= (1 << 7); |
224 | break; |
225 | case FEC_3_4: |
226 | tps |= (2 << 7); |
227 | break; |
228 | case FEC_5_6: |
229 | tps |= (3 << 7); |
230 | break; |
231 | case FEC_7_8: |
232 | tps |= (4 << 7); |
233 | break; |
234 | case FEC_1_2: |
235 | case FEC_AUTO: |
236 | break; |
237 | default: |
238 | return -EINVAL; |
239 | } |
240 | |
241 | switch (c->code_rate_LP) { |
242 | case FEC_2_3: |
243 | tps |= (1 << 4); |
244 | break; |
245 | case FEC_3_4: |
246 | tps |= (2 << 4); |
247 | break; |
248 | case FEC_5_6: |
249 | tps |= (3 << 4); |
250 | break; |
251 | case FEC_7_8: |
252 | tps |= (4 << 4); |
253 | break; |
254 | case FEC_1_2: |
255 | case FEC_AUTO: |
256 | break; |
257 | case FEC_NONE: |
258 | if (c->hierarchy == HIERARCHY_AUTO || |
259 | c->hierarchy == HIERARCHY_NONE) |
260 | break; |
261 | fallthrough; |
262 | default: |
263 | return -EINVAL; |
264 | } |
265 | |
266 | switch (c->modulation) { |
267 | case QPSK: |
268 | break; |
269 | case QAM_AUTO: |
270 | case QAM_16: |
271 | tps |= (1 << 13); |
272 | break; |
273 | case QAM_64: |
274 | tps |= (2 << 13); |
275 | break; |
276 | default: |
277 | return -EINVAL; |
278 | } |
279 | |
280 | switch (c->transmission_mode) { |
281 | case TRANSMISSION_MODE_2K: |
282 | case TRANSMISSION_MODE_AUTO: |
283 | break; |
284 | case TRANSMISSION_MODE_8K: |
285 | tps |= (1 << 0); |
286 | break; |
287 | default: |
288 | return -EINVAL; |
289 | } |
290 | |
291 | switch (c->guard_interval) { |
292 | case GUARD_INTERVAL_1_32: |
293 | case GUARD_INTERVAL_AUTO: |
294 | break; |
295 | case GUARD_INTERVAL_1_16: |
296 | tps |= (1 << 2); |
297 | break; |
298 | case GUARD_INTERVAL_1_8: |
299 | tps |= (2 << 2); |
300 | break; |
301 | case GUARD_INTERVAL_1_4: |
302 | tps |= (3 << 2); |
303 | break; |
304 | default: |
305 | return -EINVAL; |
306 | } |
307 | |
308 | switch (c->hierarchy) { |
309 | case HIERARCHY_AUTO: |
310 | case HIERARCHY_NONE: |
311 | break; |
312 | case HIERARCHY_1: |
313 | tps |= (1 << 10); |
314 | break; |
315 | case HIERARCHY_2: |
316 | tps |= (2 << 10); |
317 | break; |
318 | case HIERARCHY_4: |
319 | tps |= (3 << 10); |
320 | break; |
321 | default: |
322 | return -EINVAL; |
323 | } |
324 | |
325 | zl10353_single_write(fe, reg: TPS_GIVEN_1, msb(tps)); |
326 | zl10353_single_write(fe, reg: TPS_GIVEN_0, lsb(tps)); |
327 | |
328 | if (fe->ops.i2c_gate_ctrl) |
329 | fe->ops.i2c_gate_ctrl(fe, 0); |
330 | |
331 | /* |
332 | * If there is no tuner attached to the secondary I2C bus, we call |
333 | * set_params to program a potential tuner attached somewhere else. |
334 | * Otherwise, we update the PLL registers via calc_regs. |
335 | */ |
336 | if (state->config.no_tuner) { |
337 | if (fe->ops.tuner_ops.set_params) { |
338 | fe->ops.tuner_ops.set_params(fe); |
339 | if (fe->ops.i2c_gate_ctrl) |
340 | fe->ops.i2c_gate_ctrl(fe, 0); |
341 | } |
342 | } else if (fe->ops.tuner_ops.calc_regs) { |
343 | fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5); |
344 | pllbuf[1] <<= 1; |
345 | zl10353_write(fe, ibuf: pllbuf, ilen: sizeof(pllbuf)); |
346 | } |
347 | |
348 | zl10353_single_write(fe, reg: 0x5F, val: 0x13); |
349 | |
350 | /* If no attached tuner or invalid PLL registers, just start the FSM. */ |
351 | if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL) |
352 | zl10353_single_write(fe, reg: FSM_GO, val: 0x01); |
353 | else |
354 | zl10353_single_write(fe, reg: TUNER_GO, val: 0x01); |
355 | |
356 | return 0; |
357 | } |
358 | |
359 | static int zl10353_get_parameters(struct dvb_frontend *fe, |
360 | struct dtv_frontend_properties *c) |
361 | { |
362 | struct zl10353_state *state = fe->demodulator_priv; |
363 | int s6, s9; |
364 | u16 tps; |
365 | static const u8 tps_fec_to_api[8] = { |
366 | FEC_1_2, |
367 | FEC_2_3, |
368 | FEC_3_4, |
369 | FEC_5_6, |
370 | FEC_7_8, |
371 | FEC_AUTO, |
372 | FEC_AUTO, |
373 | FEC_AUTO |
374 | }; |
375 | |
376 | s6 = zl10353_read_register(state, reg: STATUS_6); |
377 | s9 = zl10353_read_register(state, reg: STATUS_9); |
378 | if (s6 < 0 || s9 < 0) |
379 | return -EREMOTEIO; |
380 | if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0) |
381 | return -EINVAL; /* no FE or TPS lock */ |
382 | |
383 | tps = zl10353_read_register(state, reg: TPS_RECEIVED_1) << 8 | |
384 | zl10353_read_register(state, reg: TPS_RECEIVED_0); |
385 | |
386 | c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7]; |
387 | c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7]; |
388 | |
389 | switch ((tps >> 13) & 3) { |
390 | case 0: |
391 | c->modulation = QPSK; |
392 | break; |
393 | case 1: |
394 | c->modulation = QAM_16; |
395 | break; |
396 | case 2: |
397 | c->modulation = QAM_64; |
398 | break; |
399 | default: |
400 | c->modulation = QAM_AUTO; |
401 | break; |
402 | } |
403 | |
404 | c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : |
405 | TRANSMISSION_MODE_2K; |
406 | |
407 | switch ((tps >> 2) & 3) { |
408 | case 0: |
409 | c->guard_interval = GUARD_INTERVAL_1_32; |
410 | break; |
411 | case 1: |
412 | c->guard_interval = GUARD_INTERVAL_1_16; |
413 | break; |
414 | case 2: |
415 | c->guard_interval = GUARD_INTERVAL_1_8; |
416 | break; |
417 | case 3: |
418 | c->guard_interval = GUARD_INTERVAL_1_4; |
419 | break; |
420 | default: |
421 | c->guard_interval = GUARD_INTERVAL_AUTO; |
422 | break; |
423 | } |
424 | |
425 | switch ((tps >> 10) & 7) { |
426 | case 0: |
427 | c->hierarchy = HIERARCHY_NONE; |
428 | break; |
429 | case 1: |
430 | c->hierarchy = HIERARCHY_1; |
431 | break; |
432 | case 2: |
433 | c->hierarchy = HIERARCHY_2; |
434 | break; |
435 | case 3: |
436 | c->hierarchy = HIERARCHY_4; |
437 | break; |
438 | default: |
439 | c->hierarchy = HIERARCHY_AUTO; |
440 | break; |
441 | } |
442 | |
443 | c->frequency = state->frequency; |
444 | c->bandwidth_hz = state->bandwidth; |
445 | c->inversion = INVERSION_AUTO; |
446 | |
447 | return 0; |
448 | } |
449 | |
450 | static int zl10353_read_status(struct dvb_frontend *fe, enum fe_status *status) |
451 | { |
452 | struct zl10353_state *state = fe->demodulator_priv; |
453 | int s6, s7, s8; |
454 | |
455 | if ((s6 = zl10353_read_register(state, reg: STATUS_6)) < 0) |
456 | return -EREMOTEIO; |
457 | if ((s7 = zl10353_read_register(state, reg: STATUS_7)) < 0) |
458 | return -EREMOTEIO; |
459 | if ((s8 = zl10353_read_register(state, reg: STATUS_8)) < 0) |
460 | return -EREMOTEIO; |
461 | |
462 | *status = 0; |
463 | if (s6 & (1 << 2)) |
464 | *status |= FE_HAS_CARRIER; |
465 | if (s6 & (1 << 1)) |
466 | *status |= FE_HAS_VITERBI; |
467 | if (s6 & (1 << 5)) |
468 | *status |= FE_HAS_LOCK; |
469 | if (s7 & (1 << 4)) |
470 | *status |= FE_HAS_SYNC; |
471 | if (s8 & (1 << 6)) |
472 | *status |= FE_HAS_SIGNAL; |
473 | |
474 | if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) != |
475 | (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) |
476 | *status &= ~FE_HAS_LOCK; |
477 | |
478 | return 0; |
479 | } |
480 | |
481 | static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber) |
482 | { |
483 | struct zl10353_state *state = fe->demodulator_priv; |
484 | |
485 | *ber = zl10353_read_register(state, reg: RS_ERR_CNT_2) << 16 | |
486 | zl10353_read_register(state, reg: RS_ERR_CNT_1) << 8 | |
487 | zl10353_read_register(state, reg: RS_ERR_CNT_0); |
488 | |
489 | return 0; |
490 | } |
491 | |
492 | static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength) |
493 | { |
494 | struct zl10353_state *state = fe->demodulator_priv; |
495 | |
496 | u16 signal = zl10353_read_register(state, reg: AGC_GAIN_1) << 10 | |
497 | zl10353_read_register(state, reg: AGC_GAIN_0) << 2 | 3; |
498 | |
499 | *strength = ~signal; |
500 | |
501 | return 0; |
502 | } |
503 | |
504 | static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr) |
505 | { |
506 | struct zl10353_state *state = fe->demodulator_priv; |
507 | u8 _snr; |
508 | |
509 | if (debug_regs) |
510 | zl10353_dump_regs(fe); |
511 | |
512 | _snr = zl10353_read_register(state, reg: SNR); |
513 | *snr = 10 * _snr / 8; |
514 | |
515 | return 0; |
516 | } |
517 | |
518 | static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) |
519 | { |
520 | struct zl10353_state *state = fe->demodulator_priv; |
521 | u32 ubl = 0; |
522 | |
523 | ubl = zl10353_read_register(state, reg: RS_UBC_1) << 8 | |
524 | zl10353_read_register(state, reg: RS_UBC_0); |
525 | |
526 | state->ucblocks += ubl; |
527 | *ucblocks = state->ucblocks; |
528 | |
529 | return 0; |
530 | } |
531 | |
532 | static int zl10353_get_tune_settings(struct dvb_frontend *fe, |
533 | struct dvb_frontend_tune_settings |
534 | *fe_tune_settings) |
535 | { |
536 | fe_tune_settings->min_delay_ms = 1000; |
537 | fe_tune_settings->step_size = 0; |
538 | fe_tune_settings->max_drift = 0; |
539 | |
540 | return 0; |
541 | } |
542 | |
543 | static int zl10353_init(struct dvb_frontend *fe) |
544 | { |
545 | struct zl10353_state *state = fe->demodulator_priv; |
546 | u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F }; |
547 | |
548 | if (debug_regs) |
549 | zl10353_dump_regs(fe); |
550 | if (state->config.parallel_ts) |
551 | zl10353_reset_attach[2] &= ~0x20; |
552 | if (state->config.clock_ctl_1) |
553 | zl10353_reset_attach[3] = state->config.clock_ctl_1; |
554 | if (state->config.pll_0) |
555 | zl10353_reset_attach[4] = state->config.pll_0; |
556 | |
557 | /* Do a "hard" reset if not already done */ |
558 | if (zl10353_read_register(state, reg: 0x50) != zl10353_reset_attach[1] || |
559 | zl10353_read_register(state, reg: 0x51) != zl10353_reset_attach[2]) { |
560 | zl10353_write(fe, ibuf: zl10353_reset_attach, |
561 | ilen: sizeof(zl10353_reset_attach)); |
562 | if (debug_regs) |
563 | zl10353_dump_regs(fe); |
564 | } |
565 | |
566 | return 0; |
567 | } |
568 | |
569 | static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) |
570 | { |
571 | struct zl10353_state *state = fe->demodulator_priv; |
572 | u8 val = 0x0a; |
573 | |
574 | if (state->config.disable_i2c_gate_ctrl) { |
575 | /* No tuner attached to the internal I2C bus */ |
576 | /* If set enable I2C bridge, the main I2C bus stopped hardly */ |
577 | return 0; |
578 | } |
579 | |
580 | if (enable) |
581 | val |= 0x10; |
582 | |
583 | return zl10353_single_write(fe, reg: 0x62, val); |
584 | } |
585 | |
586 | static void zl10353_release(struct dvb_frontend *fe) |
587 | { |
588 | struct zl10353_state *state = fe->demodulator_priv; |
589 | kfree(objp: state); |
590 | } |
591 | |
592 | static const struct dvb_frontend_ops zl10353_ops; |
593 | |
594 | struct dvb_frontend *zl10353_attach(const struct zl10353_config *config, |
595 | struct i2c_adapter *i2c) |
596 | { |
597 | struct zl10353_state *state = NULL; |
598 | int id; |
599 | |
600 | /* allocate memory for the internal state */ |
601 | state = kzalloc(size: sizeof(struct zl10353_state), GFP_KERNEL); |
602 | if (state == NULL) |
603 | goto error; |
604 | |
605 | /* setup the state */ |
606 | state->i2c = i2c; |
607 | memcpy(&state->config, config, sizeof(struct zl10353_config)); |
608 | |
609 | /* check if the demod is there */ |
610 | id = zl10353_read_register(state, reg: CHIP_ID); |
611 | if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231)) |
612 | goto error; |
613 | |
614 | /* create dvb_frontend */ |
615 | memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops)); |
616 | state->frontend.demodulator_priv = state; |
617 | |
618 | return &state->frontend; |
619 | error: |
620 | kfree(objp: state); |
621 | return NULL; |
622 | } |
623 | |
624 | static const struct dvb_frontend_ops zl10353_ops = { |
625 | .delsys = { SYS_DVBT }, |
626 | .info = { |
627 | .name = "Zarlink ZL10353 DVB-T" , |
628 | .frequency_min_hz = 174 * MHz, |
629 | .frequency_max_hz = 862 * MHz, |
630 | .frequency_stepsize_hz = 166667, |
631 | .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | |
632 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | |
633 | FE_CAN_FEC_AUTO | |
634 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | |
635 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | |
636 | FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | |
637 | FE_CAN_MUTE_TS |
638 | }, |
639 | |
640 | .release = zl10353_release, |
641 | |
642 | .init = zl10353_init, |
643 | .sleep = zl10353_sleep, |
644 | .i2c_gate_ctrl = zl10353_i2c_gate_ctrl, |
645 | .write = zl10353_write, |
646 | |
647 | .set_frontend = zl10353_set_parameters, |
648 | .get_frontend = zl10353_get_parameters, |
649 | .get_tune_settings = zl10353_get_tune_settings, |
650 | |
651 | .read_status = zl10353_read_status, |
652 | .read_ber = zl10353_read_ber, |
653 | .read_signal_strength = zl10353_read_signal_strength, |
654 | .read_snr = zl10353_read_snr, |
655 | .read_ucblocks = zl10353_read_ucblocks, |
656 | }; |
657 | |
658 | module_param(debug, int, 0644); |
659 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)." ); |
660 | |
661 | module_param(debug_regs, int, 0644); |
662 | MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off)." ); |
663 | |
664 | MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver" ); |
665 | MODULE_AUTHOR("Chris Pascoe" ); |
666 | MODULE_LICENSE("GPL" ); |
667 | |
668 | EXPORT_SYMBOL_GPL(zl10353_attach); |
669 | |