1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * adv7842 - Analog Devices ADV7842 video decoder driver |
4 | * |
5 | * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. |
6 | */ |
7 | |
8 | /* |
9 | * References (c = chapter, p = page): |
10 | * REF_01 - Analog devices, ADV7842, |
11 | * Register Settings Recommendations, Rev. 1.9, April 2011 |
12 | * REF_02 - Analog devices, Software User Guide, UG-206, |
13 | * ADV7842 I2C Register Maps, Rev. 0, November 2010 |
14 | * REF_03 - Analog devices, Hardware User Guide, UG-214, |
15 | * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb |
16 | * Decoder and Digitizer , Rev. 0, January 2011 |
17 | */ |
18 | |
19 | |
20 | #include <linux/kernel.h> |
21 | #include <linux/module.h> |
22 | #include <linux/slab.h> |
23 | #include <linux/i2c.h> |
24 | #include <linux/delay.h> |
25 | #include <linux/videodev2.h> |
26 | #include <linux/workqueue.h> |
27 | #include <linux/v4l2-dv-timings.h> |
28 | #include <linux/hdmi.h> |
29 | #include <media/cec.h> |
30 | #include <media/v4l2-device.h> |
31 | #include <media/v4l2-event.h> |
32 | #include <media/v4l2-ctrls.h> |
33 | #include <media/v4l2-dv-timings.h> |
34 | #include <media/i2c/adv7842.h> |
35 | |
36 | static int debug; |
37 | module_param(debug, int, 0644); |
38 | MODULE_PARM_DESC(debug, "debug level (0-2)" ); |
39 | |
40 | MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver" ); |
41 | MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>" ); |
42 | MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>" ); |
43 | MODULE_LICENSE("GPL" ); |
44 | |
45 | /* ADV7842 system clock frequency */ |
46 | #define ADV7842_fsc (28636360) |
47 | |
48 | #define ADV7842_RGB_OUT (1 << 1) |
49 | |
50 | #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0) |
51 | #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0) |
52 | #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0) |
53 | |
54 | #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5) |
55 | #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5) |
56 | #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5) |
57 | #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5) |
58 | #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5) |
59 | #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5) |
60 | |
61 | #define ADV7842_OP_CH_SEL_GBR (0 << 5) |
62 | #define ADV7842_OP_CH_SEL_GRB (1 << 5) |
63 | #define ADV7842_OP_CH_SEL_BGR (2 << 5) |
64 | #define ADV7842_OP_CH_SEL_RGB (3 << 5) |
65 | #define ADV7842_OP_CH_SEL_BRG (4 << 5) |
66 | #define ADV7842_OP_CH_SEL_RBG (5 << 5) |
67 | |
68 | #define ADV7842_OP_SWAP_CB_CR (1 << 0) |
69 | |
70 | #define ADV7842_MAX_ADDRS (3) |
71 | |
72 | /* |
73 | ********************************************************************** |
74 | * |
75 | * Arrays with configuration parameters for the ADV7842 |
76 | * |
77 | ********************************************************************** |
78 | */ |
79 | |
80 | struct adv7842_format_info { |
81 | u32 code; |
82 | u8 op_ch_sel; |
83 | bool rgb_out; |
84 | bool swap_cb_cr; |
85 | u8 op_format_sel; |
86 | }; |
87 | |
88 | struct adv7842_state { |
89 | struct adv7842_platform_data pdata; |
90 | struct v4l2_subdev sd; |
91 | struct media_pad pads[ADV7842_PAD_SOURCE + 1]; |
92 | struct v4l2_ctrl_handler hdl; |
93 | enum adv7842_mode mode; |
94 | struct v4l2_dv_timings timings; |
95 | enum adv7842_vid_std_select vid_std_select; |
96 | |
97 | const struct adv7842_format_info *format; |
98 | |
99 | v4l2_std_id norm; |
100 | struct { |
101 | u8 edid[512]; |
102 | u32 blocks; |
103 | u32 present; |
104 | } hdmi_edid; |
105 | struct { |
106 | u8 edid[128]; |
107 | u32 blocks; |
108 | u32 present; |
109 | } vga_edid; |
110 | struct v4l2_fract aspect_ratio; |
111 | u32 rgb_quantization_range; |
112 | bool is_cea_format; |
113 | struct delayed_work delayed_work_enable_hotplug; |
114 | bool restart_stdi_once; |
115 | bool hdmi_port_a; |
116 | |
117 | /* i2c clients */ |
118 | struct i2c_client *i2c_sdp_io; |
119 | struct i2c_client *i2c_sdp; |
120 | struct i2c_client *i2c_cp; |
121 | struct i2c_client *i2c_vdp; |
122 | struct i2c_client *i2c_afe; |
123 | struct i2c_client *i2c_hdmi; |
124 | struct i2c_client *i2c_repeater; |
125 | struct i2c_client *i2c_edid; |
126 | struct i2c_client *i2c_infoframe; |
127 | struct i2c_client *i2c_cec; |
128 | struct i2c_client *i2c_avlink; |
129 | |
130 | /* controls */ |
131 | struct v4l2_ctrl *detect_tx_5v_ctrl; |
132 | struct v4l2_ctrl *analog_sampling_phase_ctrl; |
133 | struct v4l2_ctrl *free_run_color_ctrl_manual; |
134 | struct v4l2_ctrl *free_run_color_ctrl; |
135 | struct v4l2_ctrl *rgb_quantization_range_ctrl; |
136 | |
137 | struct cec_adapter *cec_adap; |
138 | u8 cec_addr[ADV7842_MAX_ADDRS]; |
139 | u8 cec_valid_addrs; |
140 | bool cec_enabled_adap; |
141 | }; |
142 | |
143 | /* Unsupported timings. This device cannot support 720p30. */ |
144 | static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { |
145 | V4L2_DV_BT_CEA_1280X720P30, |
146 | { } |
147 | }; |
148 | |
149 | static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) |
150 | { |
151 | int i; |
152 | |
153 | for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) |
154 | if (v4l2_match_dv_timings(measured: t, standard: adv7842_timings_exceptions + i, pclock_delta: 0, match_reduced_fps: false)) |
155 | return false; |
156 | return true; |
157 | } |
158 | |
159 | struct adv7842_video_standards { |
160 | struct v4l2_dv_timings timings; |
161 | u8 vid_std; |
162 | u8 v_freq; |
163 | }; |
164 | |
165 | /* sorted by number of lines */ |
166 | static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { |
167 | /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ |
168 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, |
169 | { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, |
170 | { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, |
171 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, |
172 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, |
173 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, |
174 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, |
175 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, |
176 | /* TODO add 1920x1080P60_RB (CVT timing) */ |
177 | { }, |
178 | }; |
179 | |
180 | /* sorted by number of lines */ |
181 | static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { |
182 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, |
183 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, |
184 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, |
185 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, |
186 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, |
187 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, |
188 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, |
189 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, |
190 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, |
191 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, |
192 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, |
193 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, |
194 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, |
195 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, |
196 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, |
197 | { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, |
198 | { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, |
199 | { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, |
200 | { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, |
201 | { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ |
202 | /* TODO add 1600X1200P60_RB (not a DMT timing) */ |
203 | { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, |
204 | { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ |
205 | { }, |
206 | }; |
207 | |
208 | /* sorted by number of lines */ |
209 | static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { |
210 | { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, |
211 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, |
212 | { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, |
213 | { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, |
214 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, |
215 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, |
216 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, |
217 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, |
218 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, |
219 | { }, |
220 | }; |
221 | |
222 | /* sorted by number of lines */ |
223 | static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { |
224 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, |
225 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, |
226 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, |
227 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, |
228 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, |
229 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, |
230 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, |
231 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, |
232 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, |
233 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, |
234 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, |
235 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, |
236 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, |
237 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, |
238 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, |
239 | { }, |
240 | }; |
241 | |
242 | static const struct v4l2_event adv7842_ev_fmt = { |
243 | .type = V4L2_EVENT_SOURCE_CHANGE, |
244 | .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, |
245 | }; |
246 | |
247 | /* ----------------------------------------------------------------------- */ |
248 | |
249 | static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) |
250 | { |
251 | return container_of(sd, struct adv7842_state, sd); |
252 | } |
253 | |
254 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) |
255 | { |
256 | return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; |
257 | } |
258 | |
259 | static inline unsigned htotal(const struct v4l2_bt_timings *t) |
260 | { |
261 | return V4L2_DV_BT_FRAME_WIDTH(t); |
262 | } |
263 | |
264 | static inline unsigned vtotal(const struct v4l2_bt_timings *t) |
265 | { |
266 | return V4L2_DV_BT_FRAME_HEIGHT(t); |
267 | } |
268 | |
269 | |
270 | /* ----------------------------------------------------------------------- */ |
271 | |
272 | static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, |
273 | u8 command, bool check) |
274 | { |
275 | union i2c_smbus_data data; |
276 | |
277 | if (!i2c_smbus_xfer(adapter: client->adapter, addr: client->addr, flags: client->flags, |
278 | I2C_SMBUS_READ, command, |
279 | I2C_SMBUS_BYTE_DATA, data: &data)) |
280 | return data.byte; |
281 | if (check) |
282 | v4l_err(client, "error reading %02x, %02x\n" , |
283 | client->addr, command); |
284 | return -EIO; |
285 | } |
286 | |
287 | static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) |
288 | { |
289 | int i; |
290 | |
291 | for (i = 0; i < 3; i++) { |
292 | int ret = adv_smbus_read_byte_data_check(client, command, check: true); |
293 | |
294 | if (ret >= 0) { |
295 | if (i) |
296 | v4l_err(client, "read ok after %d retries\n" , i); |
297 | return ret; |
298 | } |
299 | } |
300 | v4l_err(client, "read failed\n" ); |
301 | return -EIO; |
302 | } |
303 | |
304 | static s32 adv_smbus_write_byte_data(struct i2c_client *client, |
305 | u8 command, u8 value) |
306 | { |
307 | union i2c_smbus_data data; |
308 | int err; |
309 | int i; |
310 | |
311 | data.byte = value; |
312 | for (i = 0; i < 3; i++) { |
313 | err = i2c_smbus_xfer(adapter: client->adapter, addr: client->addr, |
314 | flags: client->flags, |
315 | I2C_SMBUS_WRITE, command, |
316 | I2C_SMBUS_BYTE_DATA, data: &data); |
317 | if (!err) |
318 | break; |
319 | } |
320 | if (err < 0) |
321 | v4l_err(client, "error writing %02x, %02x, %02x\n" , |
322 | client->addr, command, value); |
323 | return err; |
324 | } |
325 | |
326 | static void adv_smbus_write_byte_no_check(struct i2c_client *client, |
327 | u8 command, u8 value) |
328 | { |
329 | union i2c_smbus_data data; |
330 | data.byte = value; |
331 | |
332 | i2c_smbus_xfer(adapter: client->adapter, addr: client->addr, |
333 | flags: client->flags, |
334 | I2C_SMBUS_WRITE, command, |
335 | I2C_SMBUS_BYTE_DATA, data: &data); |
336 | } |
337 | |
338 | /* ----------------------------------------------------------------------- */ |
339 | |
340 | static inline int io_read(struct v4l2_subdev *sd, u8 reg) |
341 | { |
342 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
343 | |
344 | return adv_smbus_read_byte_data(client, command: reg); |
345 | } |
346 | |
347 | static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
348 | { |
349 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
350 | |
351 | return adv_smbus_write_byte_data(client, command: reg, value: val); |
352 | } |
353 | |
354 | static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
355 | { |
356 | return io_write(sd, reg, val: (io_read(sd, reg) & mask) | val); |
357 | } |
358 | |
359 | static inline int io_write_clr_set(struct v4l2_subdev *sd, |
360 | u8 reg, u8 mask, u8 val) |
361 | { |
362 | return io_write(sd, reg, val: (io_read(sd, reg) & ~mask) | val); |
363 | } |
364 | |
365 | static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) |
366 | { |
367 | struct adv7842_state *state = to_state(sd); |
368 | |
369 | return adv_smbus_read_byte_data(client: state->i2c_avlink, command: reg); |
370 | } |
371 | |
372 | static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
373 | { |
374 | struct adv7842_state *state = to_state(sd); |
375 | |
376 | return adv_smbus_write_byte_data(client: state->i2c_avlink, command: reg, value: val); |
377 | } |
378 | |
379 | static inline int cec_read(struct v4l2_subdev *sd, u8 reg) |
380 | { |
381 | struct adv7842_state *state = to_state(sd); |
382 | |
383 | return adv_smbus_read_byte_data(client: state->i2c_cec, command: reg); |
384 | } |
385 | |
386 | static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
387 | { |
388 | struct adv7842_state *state = to_state(sd); |
389 | |
390 | return adv_smbus_write_byte_data(client: state->i2c_cec, command: reg, value: val); |
391 | } |
392 | |
393 | static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
394 | { |
395 | return cec_write(sd, reg, val: (cec_read(sd, reg) & ~mask) | val); |
396 | } |
397 | |
398 | static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) |
399 | { |
400 | struct adv7842_state *state = to_state(sd); |
401 | |
402 | return adv_smbus_read_byte_data(client: state->i2c_infoframe, command: reg); |
403 | } |
404 | |
405 | static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
406 | { |
407 | struct adv7842_state *state = to_state(sd); |
408 | |
409 | return adv_smbus_write_byte_data(client: state->i2c_infoframe, command: reg, value: val); |
410 | } |
411 | |
412 | static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) |
413 | { |
414 | struct adv7842_state *state = to_state(sd); |
415 | |
416 | return adv_smbus_read_byte_data(client: state->i2c_sdp_io, command: reg); |
417 | } |
418 | |
419 | static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
420 | { |
421 | struct adv7842_state *state = to_state(sd); |
422 | |
423 | return adv_smbus_write_byte_data(client: state->i2c_sdp_io, command: reg, value: val); |
424 | } |
425 | |
426 | static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
427 | { |
428 | return sdp_io_write(sd, reg, val: (sdp_io_read(sd, reg) & mask) | val); |
429 | } |
430 | |
431 | static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) |
432 | { |
433 | struct adv7842_state *state = to_state(sd); |
434 | |
435 | return adv_smbus_read_byte_data(client: state->i2c_sdp, command: reg); |
436 | } |
437 | |
438 | static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
439 | { |
440 | struct adv7842_state *state = to_state(sd); |
441 | |
442 | return adv_smbus_write_byte_data(client: state->i2c_sdp, command: reg, value: val); |
443 | } |
444 | |
445 | static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
446 | { |
447 | return sdp_write(sd, reg, val: (sdp_read(sd, reg) & mask) | val); |
448 | } |
449 | |
450 | static inline int afe_read(struct v4l2_subdev *sd, u8 reg) |
451 | { |
452 | struct adv7842_state *state = to_state(sd); |
453 | |
454 | return adv_smbus_read_byte_data(client: state->i2c_afe, command: reg); |
455 | } |
456 | |
457 | static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
458 | { |
459 | struct adv7842_state *state = to_state(sd); |
460 | |
461 | return adv_smbus_write_byte_data(client: state->i2c_afe, command: reg, value: val); |
462 | } |
463 | |
464 | static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
465 | { |
466 | return afe_write(sd, reg, val: (afe_read(sd, reg) & mask) | val); |
467 | } |
468 | |
469 | static inline int rep_read(struct v4l2_subdev *sd, u8 reg) |
470 | { |
471 | struct adv7842_state *state = to_state(sd); |
472 | |
473 | return adv_smbus_read_byte_data(client: state->i2c_repeater, command: reg); |
474 | } |
475 | |
476 | static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
477 | { |
478 | struct adv7842_state *state = to_state(sd); |
479 | |
480 | return adv_smbus_write_byte_data(client: state->i2c_repeater, command: reg, value: val); |
481 | } |
482 | |
483 | static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
484 | { |
485 | return rep_write(sd, reg, val: (rep_read(sd, reg) & mask) | val); |
486 | } |
487 | |
488 | static inline int edid_read(struct v4l2_subdev *sd, u8 reg) |
489 | { |
490 | struct adv7842_state *state = to_state(sd); |
491 | |
492 | return adv_smbus_read_byte_data(client: state->i2c_edid, command: reg); |
493 | } |
494 | |
495 | static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
496 | { |
497 | struct adv7842_state *state = to_state(sd); |
498 | |
499 | return adv_smbus_write_byte_data(client: state->i2c_edid, command: reg, value: val); |
500 | } |
501 | |
502 | static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) |
503 | { |
504 | struct adv7842_state *state = to_state(sd); |
505 | |
506 | return adv_smbus_read_byte_data(client: state->i2c_hdmi, command: reg); |
507 | } |
508 | |
509 | static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
510 | { |
511 | struct adv7842_state *state = to_state(sd); |
512 | |
513 | return adv_smbus_write_byte_data(client: state->i2c_hdmi, command: reg, value: val); |
514 | } |
515 | |
516 | static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
517 | { |
518 | return hdmi_write(sd, reg, val: (hdmi_read(sd, reg) & mask) | val); |
519 | } |
520 | |
521 | static inline int cp_read(struct v4l2_subdev *sd, u8 reg) |
522 | { |
523 | struct adv7842_state *state = to_state(sd); |
524 | |
525 | return adv_smbus_read_byte_data(client: state->i2c_cp, command: reg); |
526 | } |
527 | |
528 | static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
529 | { |
530 | struct adv7842_state *state = to_state(sd); |
531 | |
532 | return adv_smbus_write_byte_data(client: state->i2c_cp, command: reg, value: val); |
533 | } |
534 | |
535 | static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
536 | { |
537 | return cp_write(sd, reg, val: (cp_read(sd, reg) & mask) | val); |
538 | } |
539 | |
540 | static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) |
541 | { |
542 | struct adv7842_state *state = to_state(sd); |
543 | |
544 | return adv_smbus_read_byte_data(client: state->i2c_vdp, command: reg); |
545 | } |
546 | |
547 | static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
548 | { |
549 | struct adv7842_state *state = to_state(sd); |
550 | |
551 | return adv_smbus_write_byte_data(client: state->i2c_vdp, command: reg, value: val); |
552 | } |
553 | |
554 | static void main_reset(struct v4l2_subdev *sd) |
555 | { |
556 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
557 | |
558 | v4l2_dbg(1, debug, sd, "%s:\n" , __func__); |
559 | |
560 | adv_smbus_write_byte_no_check(client, command: 0xff, value: 0x80); |
561 | |
562 | mdelay(5); |
563 | } |
564 | |
565 | /* ----------------------------------------------------------------------------- |
566 | * Format helpers |
567 | */ |
568 | |
569 | static const struct adv7842_format_info adv7842_formats[] = { |
570 | { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false, |
571 | ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT }, |
572 | { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false, |
573 | ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, |
574 | { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true, |
575 | ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, |
576 | { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false, |
577 | ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, |
578 | { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true, |
579 | ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, |
580 | { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false, |
581 | ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, |
582 | { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true, |
583 | ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, |
584 | { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false, |
585 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, |
586 | { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true, |
587 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, |
588 | { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false, |
589 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, |
590 | { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true, |
591 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, |
592 | { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false, |
593 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, |
594 | { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true, |
595 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, |
596 | { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false, |
597 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, |
598 | { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true, |
599 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, |
600 | { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false, |
601 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, |
602 | { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true, |
603 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, |
604 | { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false, |
605 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, |
606 | { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true, |
607 | ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, |
608 | }; |
609 | |
610 | static const struct adv7842_format_info * |
611 | adv7842_format_info(struct adv7842_state *state, u32 code) |
612 | { |
613 | unsigned int i; |
614 | |
615 | for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) { |
616 | if (adv7842_formats[i].code == code) |
617 | return &adv7842_formats[i]; |
618 | } |
619 | |
620 | return NULL; |
621 | } |
622 | |
623 | /* ----------------------------------------------------------------------- */ |
624 | |
625 | static inline bool is_analog_input(struct v4l2_subdev *sd) |
626 | { |
627 | struct adv7842_state *state = to_state(sd); |
628 | |
629 | return ((state->mode == ADV7842_MODE_RGB) || |
630 | (state->mode == ADV7842_MODE_COMP)); |
631 | } |
632 | |
633 | static inline bool is_digital_input(struct v4l2_subdev *sd) |
634 | { |
635 | struct adv7842_state *state = to_state(sd); |
636 | |
637 | return state->mode == ADV7842_MODE_HDMI; |
638 | } |
639 | |
640 | static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { |
641 | .type = V4L2_DV_BT_656_1120, |
642 | /* keep this initialization for compatibility with GCC < 4.4.6 */ |
643 | .reserved = { 0 }, |
644 | V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, |
645 | V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
646 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, |
647 | V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | |
648 | V4L2_DV_BT_CAP_CUSTOM) |
649 | }; |
650 | |
651 | static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { |
652 | .type = V4L2_DV_BT_656_1120, |
653 | /* keep this initialization for compatibility with GCC < 4.4.6 */ |
654 | .reserved = { 0 }, |
655 | V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, |
656 | V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
657 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, |
658 | V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | |
659 | V4L2_DV_BT_CAP_CUSTOM) |
660 | }; |
661 | |
662 | static inline const struct v4l2_dv_timings_cap * |
663 | adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) |
664 | { |
665 | return is_digital_input(sd) ? &adv7842_timings_cap_digital : |
666 | &adv7842_timings_cap_analog; |
667 | } |
668 | |
669 | /* ----------------------------------------------------------------------- */ |
670 | |
671 | static u16 adv7842_read_cable_det(struct v4l2_subdev *sd) |
672 | { |
673 | u8 reg = io_read(sd, reg: 0x6f); |
674 | u16 val = 0; |
675 | |
676 | if (reg & 0x02) |
677 | val |= 1; /* port A */ |
678 | if (reg & 0x01) |
679 | val |= 2; /* port B */ |
680 | return val; |
681 | } |
682 | |
683 | static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) |
684 | { |
685 | struct delayed_work *dwork = to_delayed_work(work); |
686 | struct adv7842_state *state = container_of(dwork, |
687 | struct adv7842_state, delayed_work_enable_hotplug); |
688 | struct v4l2_subdev *sd = &state->sd; |
689 | int present = state->hdmi_edid.present; |
690 | u8 mask = 0; |
691 | |
692 | v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n" , |
693 | __func__, present); |
694 | |
695 | if (present & (0x04 << ADV7842_EDID_PORT_A)) |
696 | mask |= 0x20; |
697 | if (present & (0x04 << ADV7842_EDID_PORT_B)) |
698 | mask |= 0x10; |
699 | io_write_and_or(sd, reg: 0x20, mask: 0xcf, val: mask); |
700 | } |
701 | |
702 | static int edid_write_vga_segment(struct v4l2_subdev *sd) |
703 | { |
704 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
705 | struct adv7842_state *state = to_state(sd); |
706 | const u8 *edid = state->vga_edid.edid; |
707 | u32 blocks = state->vga_edid.blocks; |
708 | int err = 0; |
709 | int i; |
710 | |
711 | v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n" , __func__); |
712 | |
713 | if (!state->vga_edid.present) |
714 | return 0; |
715 | |
716 | /* HPA disable on port A and B */ |
717 | io_write_and_or(sd, reg: 0x20, mask: 0xcf, val: 0x00); |
718 | |
719 | /* Disable I2C access to internal EDID ram from VGA DDC port */ |
720 | rep_write_and_or(sd, reg: 0x7f, mask: 0x7f, val: 0x00); |
721 | |
722 | /* edid segment pointer '1' for VGA port */ |
723 | rep_write_and_or(sd, reg: 0x77, mask: 0xef, val: 0x10); |
724 | |
725 | for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) |
726 | err = i2c_smbus_write_i2c_block_data(client: state->i2c_edid, command: i, |
727 | I2C_SMBUS_BLOCK_MAX, |
728 | values: edid + i); |
729 | if (err) |
730 | return err; |
731 | |
732 | /* Calculates the checksums and enables I2C access |
733 | * to internal EDID ram from VGA DDC port. |
734 | */ |
735 | rep_write_and_or(sd, reg: 0x7f, mask: 0x7f, val: 0x80); |
736 | |
737 | for (i = 0; i < 1000; i++) { |
738 | if (rep_read(sd, reg: 0x79) & 0x20) |
739 | break; |
740 | mdelay(1); |
741 | } |
742 | if (i == 1000) { |
743 | v4l_err(client, "error enabling edid on VGA port\n" ); |
744 | return -EIO; |
745 | } |
746 | |
747 | /* enable hotplug after 200 ms */ |
748 | schedule_delayed_work(dwork: &state->delayed_work_enable_hotplug, HZ / 5); |
749 | |
750 | return 0; |
751 | } |
752 | |
753 | static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) |
754 | { |
755 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
756 | struct adv7842_state *state = to_state(sd); |
757 | const u8 *edid = state->hdmi_edid.edid; |
758 | u32 blocks = state->hdmi_edid.blocks; |
759 | unsigned int spa_loc; |
760 | u16 pa, parent_pa; |
761 | int err = 0; |
762 | int i; |
763 | |
764 | v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n" , |
765 | __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); |
766 | |
767 | /* HPA disable on port A and B */ |
768 | io_write_and_or(sd, reg: 0x20, mask: 0xcf, val: 0x00); |
769 | |
770 | /* Disable I2C access to internal EDID ram from HDMI DDC ports */ |
771 | rep_write_and_or(sd, reg: 0x77, mask: 0xf3, val: 0x00); |
772 | |
773 | if (!state->hdmi_edid.present) { |
774 | cec_phys_addr_invalidate(adap: state->cec_adap); |
775 | return 0; |
776 | } |
777 | |
778 | pa = v4l2_get_edid_phys_addr(edid, size: blocks * 128, offset: &spa_loc); |
779 | err = v4l2_phys_addr_validate(phys_addr: pa, parent: &parent_pa, NULL); |
780 | if (err) |
781 | return err; |
782 | |
783 | if (!spa_loc) { |
784 | /* |
785 | * There is no SPA, so just set spa_loc to 128 and pa to whatever |
786 | * data is there. |
787 | */ |
788 | spa_loc = 128; |
789 | pa = (edid[spa_loc] << 8) | edid[spa_loc + 1]; |
790 | } |
791 | |
792 | |
793 | for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) { |
794 | /* set edid segment pointer for HDMI ports */ |
795 | if (i % 256 == 0) |
796 | rep_write_and_or(sd, reg: 0x77, mask: 0xef, val: i >= 256 ? 0x10 : 0x00); |
797 | err = i2c_smbus_write_i2c_block_data(client: state->i2c_edid, command: i, |
798 | I2C_SMBUS_BLOCK_MAX, values: edid + i); |
799 | } |
800 | if (err) |
801 | return err; |
802 | |
803 | if (port == ADV7842_EDID_PORT_A) { |
804 | rep_write(sd, reg: 0x72, val: pa >> 8); |
805 | rep_write(sd, reg: 0x73, val: pa & 0xff); |
806 | } else { |
807 | rep_write(sd, reg: 0x74, val: pa >> 8); |
808 | rep_write(sd, reg: 0x75, val: pa & 0xff); |
809 | } |
810 | rep_write(sd, reg: 0x76, val: spa_loc & 0xff); |
811 | rep_write_and_or(sd, reg: 0x77, mask: 0xbf, val: (spa_loc >> 2) & 0x40); |
812 | |
813 | /* Calculates the checksums and enables I2C access to internal |
814 | * EDID ram from HDMI DDC ports |
815 | */ |
816 | rep_write_and_or(sd, reg: 0x77, mask: 0xf3, val: state->hdmi_edid.present); |
817 | |
818 | for (i = 0; i < 1000; i++) { |
819 | if (rep_read(sd, reg: 0x7d) & state->hdmi_edid.present) |
820 | break; |
821 | mdelay(1); |
822 | } |
823 | if (i == 1000) { |
824 | v4l_err(client, "error enabling edid on port %c\n" , |
825 | (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); |
826 | return -EIO; |
827 | } |
828 | cec_s_phys_addr(adap: state->cec_adap, phys_addr: parent_pa, block: false); |
829 | |
830 | /* enable hotplug after 200 ms */ |
831 | schedule_delayed_work(dwork: &state->delayed_work_enable_hotplug, HZ / 5); |
832 | |
833 | return 0; |
834 | } |
835 | |
836 | /* ----------------------------------------------------------------------- */ |
837 | |
838 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
839 | static void adv7842_inv_register(struct v4l2_subdev *sd) |
840 | { |
841 | v4l2_info(sd, "0x000-0x0ff: IO Map\n" ); |
842 | v4l2_info(sd, "0x100-0x1ff: AVLink Map\n" ); |
843 | v4l2_info(sd, "0x200-0x2ff: CEC Map\n" ); |
844 | v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n" ); |
845 | v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n" ); |
846 | v4l2_info(sd, "0x500-0x5ff: SDP Map\n" ); |
847 | v4l2_info(sd, "0x600-0x6ff: AFE Map\n" ); |
848 | v4l2_info(sd, "0x700-0x7ff: Repeater Map\n" ); |
849 | v4l2_info(sd, "0x800-0x8ff: EDID Map\n" ); |
850 | v4l2_info(sd, "0x900-0x9ff: HDMI Map\n" ); |
851 | v4l2_info(sd, "0xa00-0xaff: CP Map\n" ); |
852 | v4l2_info(sd, "0xb00-0xbff: VDP Map\n" ); |
853 | } |
854 | |
855 | static int adv7842_g_register(struct v4l2_subdev *sd, |
856 | struct v4l2_dbg_register *reg) |
857 | { |
858 | reg->size = 1; |
859 | switch (reg->reg >> 8) { |
860 | case 0: |
861 | reg->val = io_read(sd, reg: reg->reg & 0xff); |
862 | break; |
863 | case 1: |
864 | reg->val = avlink_read(sd, reg: reg->reg & 0xff); |
865 | break; |
866 | case 2: |
867 | reg->val = cec_read(sd, reg: reg->reg & 0xff); |
868 | break; |
869 | case 3: |
870 | reg->val = infoframe_read(sd, reg: reg->reg & 0xff); |
871 | break; |
872 | case 4: |
873 | reg->val = sdp_io_read(sd, reg: reg->reg & 0xff); |
874 | break; |
875 | case 5: |
876 | reg->val = sdp_read(sd, reg: reg->reg & 0xff); |
877 | break; |
878 | case 6: |
879 | reg->val = afe_read(sd, reg: reg->reg & 0xff); |
880 | break; |
881 | case 7: |
882 | reg->val = rep_read(sd, reg: reg->reg & 0xff); |
883 | break; |
884 | case 8: |
885 | reg->val = edid_read(sd, reg: reg->reg & 0xff); |
886 | break; |
887 | case 9: |
888 | reg->val = hdmi_read(sd, reg: reg->reg & 0xff); |
889 | break; |
890 | case 0xa: |
891 | reg->val = cp_read(sd, reg: reg->reg & 0xff); |
892 | break; |
893 | case 0xb: |
894 | reg->val = vdp_read(sd, reg: reg->reg & 0xff); |
895 | break; |
896 | default: |
897 | v4l2_info(sd, "Register %03llx not supported\n" , reg->reg); |
898 | adv7842_inv_register(sd); |
899 | break; |
900 | } |
901 | return 0; |
902 | } |
903 | |
904 | static int adv7842_s_register(struct v4l2_subdev *sd, |
905 | const struct v4l2_dbg_register *reg) |
906 | { |
907 | u8 val = reg->val & 0xff; |
908 | |
909 | switch (reg->reg >> 8) { |
910 | case 0: |
911 | io_write(sd, reg: reg->reg & 0xff, val); |
912 | break; |
913 | case 1: |
914 | avlink_write(sd, reg: reg->reg & 0xff, val); |
915 | break; |
916 | case 2: |
917 | cec_write(sd, reg: reg->reg & 0xff, val); |
918 | break; |
919 | case 3: |
920 | infoframe_write(sd, reg: reg->reg & 0xff, val); |
921 | break; |
922 | case 4: |
923 | sdp_io_write(sd, reg: reg->reg & 0xff, val); |
924 | break; |
925 | case 5: |
926 | sdp_write(sd, reg: reg->reg & 0xff, val); |
927 | break; |
928 | case 6: |
929 | afe_write(sd, reg: reg->reg & 0xff, val); |
930 | break; |
931 | case 7: |
932 | rep_write(sd, reg: reg->reg & 0xff, val); |
933 | break; |
934 | case 8: |
935 | edid_write(sd, reg: reg->reg & 0xff, val); |
936 | break; |
937 | case 9: |
938 | hdmi_write(sd, reg: reg->reg & 0xff, val); |
939 | break; |
940 | case 0xa: |
941 | cp_write(sd, reg: reg->reg & 0xff, val); |
942 | break; |
943 | case 0xb: |
944 | vdp_write(sd, reg: reg->reg & 0xff, val); |
945 | break; |
946 | default: |
947 | v4l2_info(sd, "Register %03llx not supported\n" , reg->reg); |
948 | adv7842_inv_register(sd); |
949 | break; |
950 | } |
951 | return 0; |
952 | } |
953 | #endif |
954 | |
955 | static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) |
956 | { |
957 | struct adv7842_state *state = to_state(sd); |
958 | u16 cable_det = adv7842_read_cable_det(sd); |
959 | |
960 | v4l2_dbg(1, debug, sd, "%s: 0x%x\n" , __func__, cable_det); |
961 | |
962 | return v4l2_ctrl_s_ctrl(ctrl: state->detect_tx_5v_ctrl, val: cable_det); |
963 | } |
964 | |
965 | static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, |
966 | u8 prim_mode, |
967 | const struct adv7842_video_standards *predef_vid_timings, |
968 | const struct v4l2_dv_timings *timings) |
969 | { |
970 | int i; |
971 | |
972 | for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { |
973 | if (!v4l2_match_dv_timings(measured: timings, standard: &predef_vid_timings[i].timings, |
974 | pclock_delta: is_digital_input(sd) ? 250000 : 1000000, match_reduced_fps: false)) |
975 | continue; |
976 | /* video std */ |
977 | io_write(sd, reg: 0x00, val: predef_vid_timings[i].vid_std); |
978 | /* v_freq and prim mode */ |
979 | io_write(sd, reg: 0x01, val: (predef_vid_timings[i].v_freq << 4) + prim_mode); |
980 | return 0; |
981 | } |
982 | |
983 | return -1; |
984 | } |
985 | |
986 | static int configure_predefined_video_timings(struct v4l2_subdev *sd, |
987 | struct v4l2_dv_timings *timings) |
988 | { |
989 | struct adv7842_state *state = to_state(sd); |
990 | int err; |
991 | |
992 | v4l2_dbg(1, debug, sd, "%s\n" , __func__); |
993 | |
994 | /* reset to default values */ |
995 | io_write(sd, reg: 0x16, val: 0x43); |
996 | io_write(sd, reg: 0x17, val: 0x5a); |
997 | /* disable embedded syncs for auto graphics mode */ |
998 | cp_write_and_or(sd, reg: 0x81, mask: 0xef, val: 0x00); |
999 | cp_write(sd, reg: 0x26, val: 0x00); |
1000 | cp_write(sd, reg: 0x27, val: 0x00); |
1001 | cp_write(sd, reg: 0x28, val: 0x00); |
1002 | cp_write(sd, reg: 0x29, val: 0x00); |
1003 | cp_write(sd, reg: 0x8f, val: 0x40); |
1004 | cp_write(sd, reg: 0x90, val: 0x00); |
1005 | cp_write(sd, reg: 0xa5, val: 0x00); |
1006 | cp_write(sd, reg: 0xa6, val: 0x00); |
1007 | cp_write(sd, reg: 0xa7, val: 0x00); |
1008 | cp_write(sd, reg: 0xab, val: 0x00); |
1009 | cp_write(sd, reg: 0xac, val: 0x00); |
1010 | |
1011 | switch (state->mode) { |
1012 | case ADV7842_MODE_COMP: |
1013 | case ADV7842_MODE_RGB: |
1014 | err = find_and_set_predefined_video_timings(sd, |
1015 | prim_mode: 0x01, predef_vid_timings: adv7842_prim_mode_comp, timings); |
1016 | if (err) |
1017 | err = find_and_set_predefined_video_timings(sd, |
1018 | prim_mode: 0x02, predef_vid_timings: adv7842_prim_mode_gr, timings); |
1019 | break; |
1020 | case ADV7842_MODE_HDMI: |
1021 | err = find_and_set_predefined_video_timings(sd, |
1022 | prim_mode: 0x05, predef_vid_timings: adv7842_prim_mode_hdmi_comp, timings); |
1023 | if (err) |
1024 | err = find_and_set_predefined_video_timings(sd, |
1025 | prim_mode: 0x06, predef_vid_timings: adv7842_prim_mode_hdmi_gr, timings); |
1026 | break; |
1027 | default: |
1028 | v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n" , |
1029 | __func__, state->mode); |
1030 | err = -1; |
1031 | break; |
1032 | } |
1033 | |
1034 | |
1035 | return err; |
1036 | } |
1037 | |
1038 | static void configure_custom_video_timings(struct v4l2_subdev *sd, |
1039 | const struct v4l2_bt_timings *bt) |
1040 | { |
1041 | struct adv7842_state *state = to_state(sd); |
1042 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
1043 | u32 width = htotal(t: bt); |
1044 | u32 height = vtotal(t: bt); |
1045 | u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; |
1046 | u16 cp_start_eav = width - bt->hfrontporch; |
1047 | u16 cp_start_vbi = height - bt->vfrontporch + 1; |
1048 | u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; |
1049 | u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? |
1050 | ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; |
1051 | const u8 pll[2] = { |
1052 | 0xc0 | ((width >> 8) & 0x1f), |
1053 | width & 0xff |
1054 | }; |
1055 | |
1056 | v4l2_dbg(2, debug, sd, "%s\n" , __func__); |
1057 | |
1058 | switch (state->mode) { |
1059 | case ADV7842_MODE_COMP: |
1060 | case ADV7842_MODE_RGB: |
1061 | /* auto graphics */ |
1062 | io_write(sd, reg: 0x00, val: 0x07); /* video std */ |
1063 | io_write(sd, reg: 0x01, val: 0x02); /* prim mode */ |
1064 | /* enable embedded syncs for auto graphics mode */ |
1065 | cp_write_and_or(sd, reg: 0x81, mask: 0xef, val: 0x10); |
1066 | |
1067 | /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ |
1068 | /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ |
1069 | /* IO-map reg. 0x16 and 0x17 should be written in sequence */ |
1070 | if (i2c_smbus_write_i2c_block_data(client, command: 0x16, length: 2, values: pll)) { |
1071 | v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n" ); |
1072 | break; |
1073 | } |
1074 | |
1075 | /* active video - horizontal timing */ |
1076 | cp_write(sd, reg: 0x26, val: (cp_start_sav >> 8) & 0xf); |
1077 | cp_write(sd, reg: 0x27, val: (cp_start_sav & 0xff)); |
1078 | cp_write(sd, reg: 0x28, val: (cp_start_eav >> 8) & 0xf); |
1079 | cp_write(sd, reg: 0x29, val: (cp_start_eav & 0xff)); |
1080 | |
1081 | /* active video - vertical timing */ |
1082 | cp_write(sd, reg: 0xa5, val: (cp_start_vbi >> 4) & 0xff); |
1083 | cp_write(sd, reg: 0xa6, val: ((cp_start_vbi & 0xf) << 4) | |
1084 | ((cp_end_vbi >> 8) & 0xf)); |
1085 | cp_write(sd, reg: 0xa7, val: cp_end_vbi & 0xff); |
1086 | break; |
1087 | case ADV7842_MODE_HDMI: |
1088 | /* set default prim_mode/vid_std for HDMI |
1089 | according to [REF_03, c. 4.2] */ |
1090 | io_write(sd, reg: 0x00, val: 0x02); /* video std */ |
1091 | io_write(sd, reg: 0x01, val: 0x06); /* prim mode */ |
1092 | break; |
1093 | default: |
1094 | v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n" , |
1095 | __func__, state->mode); |
1096 | break; |
1097 | } |
1098 | |
1099 | cp_write(sd, reg: 0x8f, val: (ch1_fr_ll >> 8) & 0x7); |
1100 | cp_write(sd, reg: 0x90, val: ch1_fr_ll & 0xff); |
1101 | cp_write(sd, reg: 0xab, val: (height >> 4) & 0xff); |
1102 | cp_write(sd, reg: 0xac, val: (height & 0x0f) << 4); |
1103 | } |
1104 | |
1105 | static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) |
1106 | { |
1107 | struct adv7842_state *state = to_state(sd); |
1108 | u8 offset_buf[4]; |
1109 | |
1110 | if (auto_offset) { |
1111 | offset_a = 0x3ff; |
1112 | offset_b = 0x3ff; |
1113 | offset_c = 0x3ff; |
1114 | } |
1115 | |
1116 | v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n" , |
1117 | __func__, auto_offset ? "Auto" : "Manual" , |
1118 | offset_a, offset_b, offset_c); |
1119 | |
1120 | offset_buf[0]= (cp_read(sd, reg: 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); |
1121 | offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); |
1122 | offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); |
1123 | offset_buf[3] = offset_c & 0x0ff; |
1124 | |
1125 | /* Registers must be written in this order with no i2c access in between */ |
1126 | if (i2c_smbus_write_i2c_block_data(client: state->i2c_cp, command: 0x77, length: 4, values: offset_buf)) |
1127 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n" , __func__); |
1128 | } |
1129 | |
1130 | static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) |
1131 | { |
1132 | struct adv7842_state *state = to_state(sd); |
1133 | u8 gain_buf[4]; |
1134 | u8 gain_man = 1; |
1135 | u8 agc_mode_man = 1; |
1136 | |
1137 | if (auto_gain) { |
1138 | gain_man = 0; |
1139 | agc_mode_man = 0; |
1140 | gain_a = 0x100; |
1141 | gain_b = 0x100; |
1142 | gain_c = 0x100; |
1143 | } |
1144 | |
1145 | v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n" , |
1146 | __func__, auto_gain ? "Auto" : "Manual" , |
1147 | gain_a, gain_b, gain_c); |
1148 | |
1149 | gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); |
1150 | gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); |
1151 | gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); |
1152 | gain_buf[3] = ((gain_c & 0x0ff)); |
1153 | |
1154 | /* Registers must be written in this order with no i2c access in between */ |
1155 | if (i2c_smbus_write_i2c_block_data(client: state->i2c_cp, command: 0x73, length: 4, values: gain_buf)) |
1156 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n" , __func__); |
1157 | } |
1158 | |
1159 | static void set_rgb_quantization_range(struct v4l2_subdev *sd) |
1160 | { |
1161 | struct adv7842_state *state = to_state(sd); |
1162 | bool rgb_output = io_read(sd, reg: 0x02) & 0x02; |
1163 | bool hdmi_signal = hdmi_read(sd, reg: 0x05) & 0x80; |
1164 | u8 y = HDMI_COLORSPACE_RGB; |
1165 | |
1166 | if (hdmi_signal && (io_read(sd, reg: 0x60) & 1)) |
1167 | y = infoframe_read(sd, reg: 0x01) >> 5; |
1168 | |
1169 | v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n" , |
1170 | __func__, state->rgb_quantization_range, |
1171 | rgb_output, hdmi_signal); |
1172 | |
1173 | adv7842_set_gain(sd, auto_gain: true, gain_a: 0x0, gain_b: 0x0, gain_c: 0x0); |
1174 | adv7842_set_offset(sd, auto_offset: true, offset_a: 0x0, offset_b: 0x0, offset_c: 0x0); |
1175 | io_write_clr_set(sd, reg: 0x02, mask: 0x04, val: rgb_output ? 0 : 4); |
1176 | |
1177 | switch (state->rgb_quantization_range) { |
1178 | case V4L2_DV_RGB_RANGE_AUTO: |
1179 | if (state->mode == ADV7842_MODE_RGB) { |
1180 | /* Receiving analog RGB signal |
1181 | * Set RGB full range (0-255) */ |
1182 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0x10); |
1183 | break; |
1184 | } |
1185 | |
1186 | if (state->mode == ADV7842_MODE_COMP) { |
1187 | /* Receiving analog YPbPr signal |
1188 | * Set automode */ |
1189 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0xf0); |
1190 | break; |
1191 | } |
1192 | |
1193 | if (hdmi_signal) { |
1194 | /* Receiving HDMI signal |
1195 | * Set automode */ |
1196 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0xf0); |
1197 | break; |
1198 | } |
1199 | |
1200 | /* Receiving DVI-D signal |
1201 | * ADV7842 selects RGB limited range regardless of |
1202 | * input format (CE/IT) in automatic mode */ |
1203 | if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { |
1204 | /* RGB limited range (16-235) */ |
1205 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0x00); |
1206 | } else { |
1207 | /* RGB full range (0-255) */ |
1208 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0x10); |
1209 | |
1210 | if (is_digital_input(sd) && rgb_output) { |
1211 | adv7842_set_offset(sd, auto_offset: false, offset_a: 0x40, offset_b: 0x40, offset_c: 0x40); |
1212 | } else { |
1213 | adv7842_set_gain(sd, auto_gain: false, gain_a: 0xe0, gain_b: 0xe0, gain_c: 0xe0); |
1214 | adv7842_set_offset(sd, auto_offset: false, offset_a: 0x70, offset_b: 0x70, offset_c: 0x70); |
1215 | } |
1216 | } |
1217 | break; |
1218 | case V4L2_DV_RGB_RANGE_LIMITED: |
1219 | if (state->mode == ADV7842_MODE_COMP) { |
1220 | /* YCrCb limited range (16-235) */ |
1221 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0x20); |
1222 | break; |
1223 | } |
1224 | |
1225 | if (y != HDMI_COLORSPACE_RGB) |
1226 | break; |
1227 | |
1228 | /* RGB limited range (16-235) */ |
1229 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0x00); |
1230 | |
1231 | break; |
1232 | case V4L2_DV_RGB_RANGE_FULL: |
1233 | if (state->mode == ADV7842_MODE_COMP) { |
1234 | /* YCrCb full range (0-255) */ |
1235 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0x60); |
1236 | break; |
1237 | } |
1238 | |
1239 | if (y != HDMI_COLORSPACE_RGB) |
1240 | break; |
1241 | |
1242 | /* RGB full range (0-255) */ |
1243 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0x10); |
1244 | |
1245 | if (is_analog_input(sd) || hdmi_signal) |
1246 | break; |
1247 | |
1248 | /* Adjust gain/offset for DVI-D signals only */ |
1249 | if (rgb_output) { |
1250 | adv7842_set_offset(sd, auto_offset: false, offset_a: 0x40, offset_b: 0x40, offset_c: 0x40); |
1251 | } else { |
1252 | adv7842_set_gain(sd, auto_gain: false, gain_a: 0xe0, gain_b: 0xe0, gain_c: 0xe0); |
1253 | adv7842_set_offset(sd, auto_offset: false, offset_a: 0x70, offset_b: 0x70, offset_c: 0x70); |
1254 | } |
1255 | break; |
1256 | } |
1257 | } |
1258 | |
1259 | static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) |
1260 | { |
1261 | struct v4l2_subdev *sd = to_sd(ctrl); |
1262 | struct adv7842_state *state = to_state(sd); |
1263 | |
1264 | /* TODO SDP ctrls |
1265 | contrast/brightness/hue/free run is acting a bit strange, |
1266 | not sure if sdp csc is correct. |
1267 | */ |
1268 | switch (ctrl->id) { |
1269 | /* standard ctrls */ |
1270 | case V4L2_CID_BRIGHTNESS: |
1271 | cp_write(sd, reg: 0x3c, val: ctrl->val); |
1272 | sdp_write(sd, reg: 0x14, val: ctrl->val); |
1273 | /* ignore lsb sdp 0x17[3:2] */ |
1274 | return 0; |
1275 | case V4L2_CID_CONTRAST: |
1276 | cp_write(sd, reg: 0x3a, val: ctrl->val); |
1277 | sdp_write(sd, reg: 0x13, val: ctrl->val); |
1278 | /* ignore lsb sdp 0x17[1:0] */ |
1279 | return 0; |
1280 | case V4L2_CID_SATURATION: |
1281 | cp_write(sd, reg: 0x3b, val: ctrl->val); |
1282 | sdp_write(sd, reg: 0x15, val: ctrl->val); |
1283 | /* ignore lsb sdp 0x17[5:4] */ |
1284 | return 0; |
1285 | case V4L2_CID_HUE: |
1286 | cp_write(sd, reg: 0x3d, val: ctrl->val); |
1287 | sdp_write(sd, reg: 0x16, val: ctrl->val); |
1288 | /* ignore lsb sdp 0x17[7:6] */ |
1289 | return 0; |
1290 | /* custom ctrls */ |
1291 | case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: |
1292 | afe_write(sd, reg: 0xc8, val: ctrl->val); |
1293 | return 0; |
1294 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: |
1295 | cp_write_and_or(sd, reg: 0xbf, mask: ~0x04, val: (ctrl->val << 2)); |
1296 | sdp_write_and_or(sd, reg: 0xdd, mask: ~0x04, val: (ctrl->val << 2)); |
1297 | return 0; |
1298 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { |
1299 | u8 R = (ctrl->val & 0xff0000) >> 16; |
1300 | u8 G = (ctrl->val & 0x00ff00) >> 8; |
1301 | u8 B = (ctrl->val & 0x0000ff); |
1302 | /* RGB -> YUV, numerical approximation */ |
1303 | int Y = 66 * R + 129 * G + 25 * B; |
1304 | int U = -38 * R - 74 * G + 112 * B; |
1305 | int V = 112 * R - 94 * G - 18 * B; |
1306 | |
1307 | /* Scale down to 8 bits with rounding */ |
1308 | Y = (Y + 128) >> 8; |
1309 | U = (U + 128) >> 8; |
1310 | V = (V + 128) >> 8; |
1311 | /* make U,V positive */ |
1312 | Y += 16; |
1313 | U += 128; |
1314 | V += 128; |
1315 | |
1316 | v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n" , R, G, B); |
1317 | v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n" , Y, U, V); |
1318 | |
1319 | /* CP */ |
1320 | cp_write(sd, reg: 0xc1, val: R); |
1321 | cp_write(sd, reg: 0xc0, val: G); |
1322 | cp_write(sd, reg: 0xc2, val: B); |
1323 | /* SDP */ |
1324 | sdp_write(sd, reg: 0xde, val: Y); |
1325 | sdp_write(sd, reg: 0xdf, val: (V & 0xf0) | ((U >> 4) & 0x0f)); |
1326 | return 0; |
1327 | } |
1328 | case V4L2_CID_DV_RX_RGB_RANGE: |
1329 | state->rgb_quantization_range = ctrl->val; |
1330 | set_rgb_quantization_range(sd); |
1331 | return 0; |
1332 | } |
1333 | return -EINVAL; |
1334 | } |
1335 | |
1336 | static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
1337 | { |
1338 | struct v4l2_subdev *sd = to_sd(ctrl); |
1339 | |
1340 | if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { |
1341 | ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; |
1342 | if ((io_read(sd, reg: 0x60) & 1) && (infoframe_read(sd, reg: 0x03) & 0x80)) |
1343 | ctrl->val = (infoframe_read(sd, reg: 0x05) >> 4) & 3; |
1344 | return 0; |
1345 | } |
1346 | return -EINVAL; |
1347 | } |
1348 | |
1349 | static inline bool no_power(struct v4l2_subdev *sd) |
1350 | { |
1351 | return io_read(sd, reg: 0x0c) & 0x24; |
1352 | } |
1353 | |
1354 | static inline bool no_cp_signal(struct v4l2_subdev *sd) |
1355 | { |
1356 | return ((cp_read(sd, reg: 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, reg: 0xb1) & 0x80); |
1357 | } |
1358 | |
1359 | static inline bool is_hdmi(struct v4l2_subdev *sd) |
1360 | { |
1361 | return hdmi_read(sd, reg: 0x05) & 0x80; |
1362 | } |
1363 | |
1364 | static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) |
1365 | { |
1366 | struct adv7842_state *state = to_state(sd); |
1367 | |
1368 | *status = 0; |
1369 | |
1370 | if (io_read(sd, reg: 0x0c) & 0x24) |
1371 | *status |= V4L2_IN_ST_NO_POWER; |
1372 | |
1373 | if (state->mode == ADV7842_MODE_SDP) { |
1374 | /* status from SDP block */ |
1375 | if (!(sdp_read(sd, reg: 0x5A) & 0x01)) |
1376 | *status |= V4L2_IN_ST_NO_SIGNAL; |
1377 | |
1378 | v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n" , |
1379 | __func__, *status); |
1380 | return 0; |
1381 | } |
1382 | /* status from CP block */ |
1383 | if ((cp_read(sd, reg: 0xb5) & 0xd0) != 0xd0 || |
1384 | !(cp_read(sd, reg: 0xb1) & 0x80)) |
1385 | /* TODO channel 2 */ |
1386 | *status |= V4L2_IN_ST_NO_SIGNAL; |
1387 | |
1388 | if (is_digital_input(sd) && ((io_read(sd, reg: 0x74) & 0x03) != 0x03)) |
1389 | *status |= V4L2_IN_ST_NO_SIGNAL; |
1390 | |
1391 | v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n" , |
1392 | __func__, *status); |
1393 | |
1394 | return 0; |
1395 | } |
1396 | |
1397 | struct stdi_readback { |
1398 | u16 bl, lcf, lcvs; |
1399 | u8 hs_pol, vs_pol; |
1400 | bool interlaced; |
1401 | }; |
1402 | |
1403 | static int stdi2dv_timings(struct v4l2_subdev *sd, |
1404 | struct stdi_readback *stdi, |
1405 | struct v4l2_dv_timings *timings) |
1406 | { |
1407 | struct adv7842_state *state = to_state(sd); |
1408 | u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; |
1409 | u32 pix_clk; |
1410 | int i; |
1411 | |
1412 | for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { |
1413 | const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; |
1414 | |
1415 | if (!v4l2_valid_dv_timings(t: &v4l2_dv_timings_presets[i], |
1416 | cap: adv7842_get_dv_timings_cap(sd), |
1417 | fnc: adv7842_check_dv_timings, NULL)) |
1418 | continue; |
1419 | if (vtotal(t: bt) != stdi->lcf + 1) |
1420 | continue; |
1421 | if (bt->vsync != stdi->lcvs) |
1422 | continue; |
1423 | |
1424 | pix_clk = hfreq * htotal(t: bt); |
1425 | |
1426 | if ((pix_clk < bt->pixelclock + 1000000) && |
1427 | (pix_clk > bt->pixelclock - 1000000)) { |
1428 | *timings = v4l2_dv_timings_presets[i]; |
1429 | return 0; |
1430 | } |
1431 | } |
1432 | |
1433 | if (v4l2_detect_cvt(frame_height: stdi->lcf + 1, hfreq, vsync: stdi->lcvs, active_width: 0, |
1434 | polarities: (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | |
1435 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), |
1436 | interlaced: false, fmt: timings)) |
1437 | return 0; |
1438 | if (v4l2_detect_gtf(frame_height: stdi->lcf + 1, hfreq, vsync: stdi->lcvs, |
1439 | polarities: (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | |
1440 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), |
1441 | interlaced: false, aspect: state->aspect_ratio, fmt: timings)) |
1442 | return 0; |
1443 | |
1444 | v4l2_dbg(2, debug, sd, |
1445 | "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n" , |
1446 | __func__, stdi->lcvs, stdi->lcf, stdi->bl, |
1447 | stdi->hs_pol, stdi->vs_pol); |
1448 | return -1; |
1449 | } |
1450 | |
1451 | static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) |
1452 | { |
1453 | u32 status; |
1454 | |
1455 | adv7842_g_input_status(sd, status: &status); |
1456 | if (status & V4L2_IN_ST_NO_SIGNAL) { |
1457 | v4l2_dbg(2, debug, sd, "%s: no signal\n" , __func__); |
1458 | return -ENOLINK; |
1459 | } |
1460 | |
1461 | stdi->bl = ((cp_read(sd, reg: 0xb1) & 0x3f) << 8) | cp_read(sd, reg: 0xb2); |
1462 | stdi->lcf = ((cp_read(sd, reg: 0xb3) & 0x7) << 8) | cp_read(sd, reg: 0xb4); |
1463 | stdi->lcvs = cp_read(sd, reg: 0xb3) >> 3; |
1464 | |
1465 | if ((cp_read(sd, reg: 0xb5) & 0x80) && ((cp_read(sd, reg: 0xb5) & 0x03) == 0x01)) { |
1466 | stdi->hs_pol = ((cp_read(sd, reg: 0xb5) & 0x10) ? |
1467 | ((cp_read(sd, reg: 0xb5) & 0x08) ? '+' : '-') : 'x'); |
1468 | stdi->vs_pol = ((cp_read(sd, reg: 0xb5) & 0x40) ? |
1469 | ((cp_read(sd, reg: 0xb5) & 0x20) ? '+' : '-') : 'x'); |
1470 | } else { |
1471 | stdi->hs_pol = 'x'; |
1472 | stdi->vs_pol = 'x'; |
1473 | } |
1474 | stdi->interlaced = (cp_read(sd, reg: 0xb1) & 0x40) ? true : false; |
1475 | |
1476 | if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { |
1477 | v4l2_dbg(2, debug, sd, "%s: invalid signal\n" , __func__); |
1478 | return -ENOLINK; |
1479 | } |
1480 | |
1481 | v4l2_dbg(2, debug, sd, |
1482 | "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n" , |
1483 | __func__, stdi->lcf, stdi->bl, stdi->lcvs, |
1484 | stdi->hs_pol, stdi->vs_pol, |
1485 | stdi->interlaced ? "interlaced" : "progressive" ); |
1486 | |
1487 | return 0; |
1488 | } |
1489 | |
1490 | static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, |
1491 | struct v4l2_enum_dv_timings *timings) |
1492 | { |
1493 | if (timings->pad != 0) |
1494 | return -EINVAL; |
1495 | |
1496 | return v4l2_enum_dv_timings_cap(t: timings, |
1497 | cap: adv7842_get_dv_timings_cap(sd), fnc: adv7842_check_dv_timings, NULL); |
1498 | } |
1499 | |
1500 | static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, |
1501 | struct v4l2_dv_timings_cap *cap) |
1502 | { |
1503 | if (cap->pad != 0) |
1504 | return -EINVAL; |
1505 | |
1506 | *cap = *adv7842_get_dv_timings_cap(sd); |
1507 | return 0; |
1508 | } |
1509 | |
1510 | /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings |
1511 | if the format is listed in adv7842_timings[] */ |
1512 | static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, |
1513 | struct v4l2_dv_timings *timings) |
1514 | { |
1515 | v4l2_find_dv_timings_cap(t: timings, cap: adv7842_get_dv_timings_cap(sd), |
1516 | pclock_delta: is_digital_input(sd) ? 250000 : 1000000, |
1517 | fnc: adv7842_check_dv_timings, NULL); |
1518 | timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS; |
1519 | } |
1520 | |
1521 | static int adv7842_query_dv_timings(struct v4l2_subdev *sd, |
1522 | struct v4l2_dv_timings *timings) |
1523 | { |
1524 | struct adv7842_state *state = to_state(sd); |
1525 | struct v4l2_bt_timings *bt = &timings->bt; |
1526 | struct stdi_readback stdi = { 0 }; |
1527 | |
1528 | v4l2_dbg(1, debug, sd, "%s:\n" , __func__); |
1529 | |
1530 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); |
1531 | |
1532 | /* SDP block */ |
1533 | if (state->mode == ADV7842_MODE_SDP) |
1534 | return -ENODATA; |
1535 | |
1536 | /* read STDI */ |
1537 | if (read_stdi(sd, stdi: &stdi)) { |
1538 | state->restart_stdi_once = true; |
1539 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n" , __func__); |
1540 | return -ENOLINK; |
1541 | } |
1542 | bt->interlaced = stdi.interlaced ? |
1543 | V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; |
1544 | bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
1545 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; |
1546 | |
1547 | if (is_digital_input(sd)) { |
1548 | u32 freq; |
1549 | |
1550 | timings->type = V4L2_DV_BT_656_1120; |
1551 | |
1552 | bt->width = (hdmi_read(sd, reg: 0x07) & 0x0f) * 256 + hdmi_read(sd, reg: 0x08); |
1553 | bt->height = (hdmi_read(sd, reg: 0x09) & 0x0f) * 256 + hdmi_read(sd, reg: 0x0a); |
1554 | freq = ((hdmi_read(sd, reg: 0x51) << 1) + (hdmi_read(sd, reg: 0x52) >> 7)) * 1000000; |
1555 | freq += ((hdmi_read(sd, reg: 0x52) & 0x7f) * 7813); |
1556 | if (is_hdmi(sd)) { |
1557 | /* adjust for deep color mode */ |
1558 | freq = freq * 8 / (((hdmi_read(sd, reg: 0x0b) & 0xc0) >> 6) * 2 + 8); |
1559 | } |
1560 | bt->pixelclock = freq; |
1561 | bt->hfrontporch = (hdmi_read(sd, reg: 0x20) & 0x03) * 256 + |
1562 | hdmi_read(sd, reg: 0x21); |
1563 | bt->hsync = (hdmi_read(sd, reg: 0x22) & 0x03) * 256 + |
1564 | hdmi_read(sd, reg: 0x23); |
1565 | bt->hbackporch = (hdmi_read(sd, reg: 0x24) & 0x03) * 256 + |
1566 | hdmi_read(sd, reg: 0x25); |
1567 | bt->vfrontporch = ((hdmi_read(sd, reg: 0x2a) & 0x1f) * 256 + |
1568 | hdmi_read(sd, reg: 0x2b)) / 2; |
1569 | bt->vsync = ((hdmi_read(sd, reg: 0x2e) & 0x1f) * 256 + |
1570 | hdmi_read(sd, reg: 0x2f)) / 2; |
1571 | bt->vbackporch = ((hdmi_read(sd, reg: 0x32) & 0x1f) * 256 + |
1572 | hdmi_read(sd, reg: 0x33)) / 2; |
1573 | bt->polarities = ((hdmi_read(sd, reg: 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | |
1574 | ((hdmi_read(sd, reg: 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); |
1575 | if (bt->interlaced == V4L2_DV_INTERLACED) { |
1576 | bt->height += (hdmi_read(sd, reg: 0x0b) & 0x0f) * 256 + |
1577 | hdmi_read(sd, reg: 0x0c); |
1578 | bt->il_vfrontporch = ((hdmi_read(sd, reg: 0x2c) & 0x1f) * 256 + |
1579 | hdmi_read(sd, reg: 0x2d)) / 2; |
1580 | bt->il_vsync = ((hdmi_read(sd, reg: 0x30) & 0x1f) * 256 + |
1581 | hdmi_read(sd, reg: 0x31)) / 2; |
1582 | bt->il_vbackporch = ((hdmi_read(sd, reg: 0x34) & 0x1f) * 256 + |
1583 | hdmi_read(sd, reg: 0x35)) / 2; |
1584 | } else { |
1585 | bt->il_vfrontporch = 0; |
1586 | bt->il_vsync = 0; |
1587 | bt->il_vbackporch = 0; |
1588 | } |
1589 | adv7842_fill_optional_dv_timings_fields(sd, timings); |
1590 | if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) && |
1591 | freq < bt->pixelclock) { |
1592 | u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000; |
1593 | u32 delta_freq = abs(freq - reduced_freq); |
1594 | |
1595 | if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2) |
1596 | timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS; |
1597 | } |
1598 | } else { |
1599 | /* find format |
1600 | * Since LCVS values are inaccurate [REF_03, p. 339-340], |
1601 | * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. |
1602 | */ |
1603 | if (!stdi2dv_timings(sd, stdi: &stdi, timings)) |
1604 | goto found; |
1605 | stdi.lcvs += 1; |
1606 | v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n" , __func__, stdi.lcvs); |
1607 | if (!stdi2dv_timings(sd, stdi: &stdi, timings)) |
1608 | goto found; |
1609 | stdi.lcvs -= 2; |
1610 | v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n" , __func__, stdi.lcvs); |
1611 | if (stdi2dv_timings(sd, stdi: &stdi, timings)) { |
1612 | /* |
1613 | * The STDI block may measure wrong values, especially |
1614 | * for lcvs and lcf. If the driver can not find any |
1615 | * valid timing, the STDI block is restarted to measure |
1616 | * the video timings again. The function will return an |
1617 | * error, but the restart of STDI will generate a new |
1618 | * STDI interrupt and the format detection process will |
1619 | * restart. |
1620 | */ |
1621 | if (state->restart_stdi_once) { |
1622 | v4l2_dbg(1, debug, sd, "%s: restart STDI\n" , __func__); |
1623 | /* TODO restart STDI for Sync Channel 2 */ |
1624 | /* enter one-shot mode */ |
1625 | cp_write_and_or(sd, reg: 0x86, mask: 0xf9, val: 0x00); |
1626 | /* trigger STDI restart */ |
1627 | cp_write_and_or(sd, reg: 0x86, mask: 0xf9, val: 0x04); |
1628 | /* reset to continuous mode */ |
1629 | cp_write_and_or(sd, reg: 0x86, mask: 0xf9, val: 0x02); |
1630 | state->restart_stdi_once = false; |
1631 | return -ENOLINK; |
1632 | } |
1633 | v4l2_dbg(1, debug, sd, "%s: format not supported\n" , __func__); |
1634 | return -ERANGE; |
1635 | } |
1636 | state->restart_stdi_once = true; |
1637 | } |
1638 | found: |
1639 | |
1640 | if (debug > 1) |
1641 | v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "adv7842_query_dv_timings:" , |
1642 | t: timings, detailed: true); |
1643 | return 0; |
1644 | } |
1645 | |
1646 | static int adv7842_s_dv_timings(struct v4l2_subdev *sd, |
1647 | struct v4l2_dv_timings *timings) |
1648 | { |
1649 | struct adv7842_state *state = to_state(sd); |
1650 | struct v4l2_bt_timings *bt; |
1651 | int err; |
1652 | |
1653 | v4l2_dbg(1, debug, sd, "%s:\n" , __func__); |
1654 | |
1655 | if (state->mode == ADV7842_MODE_SDP) |
1656 | return -ENODATA; |
1657 | |
1658 | if (v4l2_match_dv_timings(measured: &state->timings, standard: timings, pclock_delta: 0, match_reduced_fps: false)) { |
1659 | v4l2_dbg(1, debug, sd, "%s: no change\n" , __func__); |
1660 | return 0; |
1661 | } |
1662 | |
1663 | bt = &timings->bt; |
1664 | |
1665 | if (!v4l2_valid_dv_timings(t: timings, cap: adv7842_get_dv_timings_cap(sd), |
1666 | fnc: adv7842_check_dv_timings, NULL)) |
1667 | return -ERANGE; |
1668 | |
1669 | adv7842_fill_optional_dv_timings_fields(sd, timings); |
1670 | |
1671 | state->timings = *timings; |
1672 | |
1673 | cp_write(sd, reg: 0x91, val: bt->interlaced ? 0x40 : 0x00); |
1674 | |
1675 | /* Use prim_mode and vid_std when available */ |
1676 | err = configure_predefined_video_timings(sd, timings); |
1677 | if (err) { |
1678 | /* custom settings when the video format |
1679 | does not have prim_mode/vid_std */ |
1680 | configure_custom_video_timings(sd, bt); |
1681 | } |
1682 | |
1683 | set_rgb_quantization_range(sd); |
1684 | |
1685 | |
1686 | if (debug > 1) |
1687 | v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "adv7842_s_dv_timings: " , |
1688 | t: timings, detailed: true); |
1689 | return 0; |
1690 | } |
1691 | |
1692 | static int adv7842_g_dv_timings(struct v4l2_subdev *sd, |
1693 | struct v4l2_dv_timings *timings) |
1694 | { |
1695 | struct adv7842_state *state = to_state(sd); |
1696 | |
1697 | if (state->mode == ADV7842_MODE_SDP) |
1698 | return -ENODATA; |
1699 | *timings = state->timings; |
1700 | return 0; |
1701 | } |
1702 | |
1703 | static void enable_input(struct v4l2_subdev *sd) |
1704 | { |
1705 | struct adv7842_state *state = to_state(sd); |
1706 | |
1707 | set_rgb_quantization_range(sd); |
1708 | switch (state->mode) { |
1709 | case ADV7842_MODE_SDP: |
1710 | case ADV7842_MODE_COMP: |
1711 | case ADV7842_MODE_RGB: |
1712 | io_write(sd, reg: 0x15, val: 0xb0); /* Disable Tristate of Pins (no audio) */ |
1713 | break; |
1714 | case ADV7842_MODE_HDMI: |
1715 | hdmi_write(sd, reg: 0x01, val: 0x00); /* Enable HDMI clock terminators */ |
1716 | io_write(sd, reg: 0x15, val: 0xa0); /* Disable Tristate of Pins */ |
1717 | hdmi_write_and_or(sd, reg: 0x1a, mask: 0xef, val: 0x00); /* Unmute audio */ |
1718 | break; |
1719 | default: |
1720 | v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n" , |
1721 | __func__, state->mode); |
1722 | break; |
1723 | } |
1724 | } |
1725 | |
1726 | static void disable_input(struct v4l2_subdev *sd) |
1727 | { |
1728 | hdmi_write_and_or(sd, reg: 0x1a, mask: 0xef, val: 0x10); /* Mute audio [REF_01, c. 2.2.2] */ |
1729 | msleep(msecs: 16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */ |
1730 | io_write(sd, reg: 0x15, val: 0xbe); /* Tristate all outputs from video core */ |
1731 | hdmi_write(sd, reg: 0x01, val: 0x78); /* Disable HDMI clock terminators */ |
1732 | } |
1733 | |
1734 | static void sdp_csc_coeff(struct v4l2_subdev *sd, |
1735 | const struct adv7842_sdp_csc_coeff *c) |
1736 | { |
1737 | /* csc auto/manual */ |
1738 | sdp_io_write_and_or(sd, reg: 0xe0, mask: 0xbf, val: c->manual ? 0x00 : 0x40); |
1739 | |
1740 | if (!c->manual) |
1741 | return; |
1742 | |
1743 | /* csc scaling */ |
1744 | sdp_io_write_and_or(sd, reg: 0xe0, mask: 0x7f, val: c->scaling == 2 ? 0x80 : 0x00); |
1745 | |
1746 | /* A coeff */ |
1747 | sdp_io_write_and_or(sd, reg: 0xe0, mask: 0xe0, val: c->A1 >> 8); |
1748 | sdp_io_write(sd, reg: 0xe1, val: c->A1); |
1749 | sdp_io_write_and_or(sd, reg: 0xe2, mask: 0xe0, val: c->A2 >> 8); |
1750 | sdp_io_write(sd, reg: 0xe3, val: c->A2); |
1751 | sdp_io_write_and_or(sd, reg: 0xe4, mask: 0xe0, val: c->A3 >> 8); |
1752 | sdp_io_write(sd, reg: 0xe5, val: c->A3); |
1753 | |
1754 | /* A scale */ |
1755 | sdp_io_write_and_or(sd, reg: 0xe6, mask: 0x80, val: c->A4 >> 8); |
1756 | sdp_io_write(sd, reg: 0xe7, val: c->A4); |
1757 | |
1758 | /* B coeff */ |
1759 | sdp_io_write_and_or(sd, reg: 0xe8, mask: 0xe0, val: c->B1 >> 8); |
1760 | sdp_io_write(sd, reg: 0xe9, val: c->B1); |
1761 | sdp_io_write_and_or(sd, reg: 0xea, mask: 0xe0, val: c->B2 >> 8); |
1762 | sdp_io_write(sd, reg: 0xeb, val: c->B2); |
1763 | sdp_io_write_and_or(sd, reg: 0xec, mask: 0xe0, val: c->B3 >> 8); |
1764 | sdp_io_write(sd, reg: 0xed, val: c->B3); |
1765 | |
1766 | /* B scale */ |
1767 | sdp_io_write_and_or(sd, reg: 0xee, mask: 0x80, val: c->B4 >> 8); |
1768 | sdp_io_write(sd, reg: 0xef, val: c->B4); |
1769 | |
1770 | /* C coeff */ |
1771 | sdp_io_write_and_or(sd, reg: 0xf0, mask: 0xe0, val: c->C1 >> 8); |
1772 | sdp_io_write(sd, reg: 0xf1, val: c->C1); |
1773 | sdp_io_write_and_or(sd, reg: 0xf2, mask: 0xe0, val: c->C2 >> 8); |
1774 | sdp_io_write(sd, reg: 0xf3, val: c->C2); |
1775 | sdp_io_write_and_or(sd, reg: 0xf4, mask: 0xe0, val: c->C3 >> 8); |
1776 | sdp_io_write(sd, reg: 0xf5, val: c->C3); |
1777 | |
1778 | /* C scale */ |
1779 | sdp_io_write_and_or(sd, reg: 0xf6, mask: 0x80, val: c->C4 >> 8); |
1780 | sdp_io_write(sd, reg: 0xf7, val: c->C4); |
1781 | } |
1782 | |
1783 | static void select_input(struct v4l2_subdev *sd, |
1784 | enum adv7842_vid_std_select vid_std_select) |
1785 | { |
1786 | struct adv7842_state *state = to_state(sd); |
1787 | |
1788 | switch (state->mode) { |
1789 | case ADV7842_MODE_SDP: |
1790 | io_write(sd, reg: 0x00, val: vid_std_select); /* video std: CVBS or YC mode */ |
1791 | io_write(sd, reg: 0x01, val: 0); /* prim mode */ |
1792 | /* enable embedded syncs for auto graphics mode */ |
1793 | cp_write_and_or(sd, reg: 0x81, mask: 0xef, val: 0x10); |
1794 | |
1795 | afe_write(sd, reg: 0x00, val: 0x00); /* power up ADC */ |
1796 | afe_write(sd, reg: 0xc8, val: 0x00); /* phase control */ |
1797 | |
1798 | io_write(sd, reg: 0xdd, val: 0x90); /* Manual 2x output clock */ |
1799 | /* script says register 0xde, which don't exist in manual */ |
1800 | |
1801 | /* Manual analog input muxing mode, CVBS (6.4)*/ |
1802 | afe_write_and_or(sd, reg: 0x02, mask: 0x7f, val: 0x80); |
1803 | if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { |
1804 | afe_write(sd, reg: 0x03, val: 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ |
1805 | afe_write(sd, reg: 0x04, val: 0x00); /* ADC2 N/C,ADC3 N/C*/ |
1806 | } else { |
1807 | afe_write(sd, reg: 0x03, val: 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ |
1808 | afe_write(sd, reg: 0x04, val: 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ |
1809 | } |
1810 | afe_write(sd, reg: 0x0c, val: 0x1f); /* ADI recommend write */ |
1811 | afe_write(sd, reg: 0x12, val: 0x63); /* ADI recommend write */ |
1812 | |
1813 | sdp_io_write(sd, reg: 0xb2, val: 0x60); /* Disable AV codes */ |
1814 | sdp_io_write(sd, reg: 0xc8, val: 0xe3); /* Disable Ancillary data */ |
1815 | |
1816 | /* SDP recommended settings */ |
1817 | sdp_write(sd, reg: 0x00, val: 0x3F); /* Autodetect PAL NTSC (not SECAM) */ |
1818 | sdp_write(sd, reg: 0x01, val: 0x00); /* Pedestal Off */ |
1819 | |
1820 | sdp_write(sd, reg: 0x03, val: 0xE4); /* Manual VCR Gain Luma 0x40B */ |
1821 | sdp_write(sd, reg: 0x04, val: 0x0B); /* Manual Luma setting */ |
1822 | sdp_write(sd, reg: 0x05, val: 0xC3); /* Manual Chroma setting 0x3FE */ |
1823 | sdp_write(sd, reg: 0x06, val: 0xFE); /* Manual Chroma setting */ |
1824 | sdp_write(sd, reg: 0x12, val: 0x0D); /* Frame TBC,I_P, 3D comb enabled */ |
1825 | sdp_write(sd, reg: 0xA7, val: 0x00); /* ADI Recommended Write */ |
1826 | sdp_io_write(sd, reg: 0xB0, val: 0x00); /* Disable H and v blanking */ |
1827 | |
1828 | /* deinterlacer enabled and 3D comb */ |
1829 | sdp_write_and_or(sd, reg: 0x12, mask: 0xf6, val: 0x09); |
1830 | |
1831 | break; |
1832 | |
1833 | case ADV7842_MODE_COMP: |
1834 | case ADV7842_MODE_RGB: |
1835 | /* Automatic analog input muxing mode */ |
1836 | afe_write_and_or(sd, reg: 0x02, mask: 0x7f, val: 0x00); |
1837 | /* set mode and select free run resolution */ |
1838 | io_write(sd, reg: 0x00, val: vid_std_select); /* video std */ |
1839 | io_write(sd, reg: 0x01, val: 0x02); /* prim mode */ |
1840 | cp_write_and_or(sd, reg: 0x81, mask: 0xef, val: 0x10); /* enable embedded syncs |
1841 | for auto graphics mode */ |
1842 | |
1843 | afe_write(sd, reg: 0x00, val: 0x00); /* power up ADC */ |
1844 | afe_write(sd, reg: 0xc8, val: 0x00); /* phase control */ |
1845 | if (state->mode == ADV7842_MODE_COMP) { |
1846 | /* force to YCrCb */ |
1847 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0x60); |
1848 | } else { |
1849 | /* force to RGB */ |
1850 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0x10); |
1851 | } |
1852 | |
1853 | /* set ADI recommended settings for digitizer */ |
1854 | /* "ADV7842 Register Settings Recommendations |
1855 | * (rev. 1.8, November 2010)" p. 9. */ |
1856 | afe_write(sd, reg: 0x0c, val: 0x1f); /* ADC Range improvement */ |
1857 | afe_write(sd, reg: 0x12, val: 0x63); /* ADC Range improvement */ |
1858 | |
1859 | /* set to default gain for RGB */ |
1860 | cp_write(sd, reg: 0x73, val: 0x10); |
1861 | cp_write(sd, reg: 0x74, val: 0x04); |
1862 | cp_write(sd, reg: 0x75, val: 0x01); |
1863 | cp_write(sd, reg: 0x76, val: 0x00); |
1864 | |
1865 | cp_write(sd, reg: 0x3e, val: 0x04); /* CP core pre-gain control */ |
1866 | cp_write(sd, reg: 0xc3, val: 0x39); /* CP coast control. Graphics mode */ |
1867 | cp_write(sd, reg: 0x40, val: 0x5c); /* CP core pre-gain control. Graphics mode */ |
1868 | break; |
1869 | |
1870 | case ADV7842_MODE_HDMI: |
1871 | /* Automatic analog input muxing mode */ |
1872 | afe_write_and_or(sd, reg: 0x02, mask: 0x7f, val: 0x00); |
1873 | /* set mode and select free run resolution */ |
1874 | if (state->hdmi_port_a) |
1875 | hdmi_write(sd, reg: 0x00, val: 0x02); /* select port A */ |
1876 | else |
1877 | hdmi_write(sd, reg: 0x00, val: 0x03); /* select port B */ |
1878 | io_write(sd, reg: 0x00, val: vid_std_select); /* video std */ |
1879 | io_write(sd, reg: 0x01, val: 5); /* prim mode */ |
1880 | cp_write_and_or(sd, reg: 0x81, mask: 0xef, val: 0x00); /* disable embedded syncs |
1881 | for auto graphics mode */ |
1882 | |
1883 | /* set ADI recommended settings for HDMI: */ |
1884 | /* "ADV7842 Register Settings Recommendations |
1885 | * (rev. 1.8, November 2010)" p. 3. */ |
1886 | hdmi_write(sd, reg: 0xc0, val: 0x00); |
1887 | hdmi_write(sd, reg: 0x0d, val: 0x34); /* ADI recommended write */ |
1888 | hdmi_write(sd, reg: 0x3d, val: 0x10); /* ADI recommended write */ |
1889 | hdmi_write(sd, reg: 0x44, val: 0x85); /* TMDS PLL optimization */ |
1890 | hdmi_write(sd, reg: 0x46, val: 0x1f); /* ADI recommended write */ |
1891 | hdmi_write(sd, reg: 0x57, val: 0xb6); /* TMDS PLL optimization */ |
1892 | hdmi_write(sd, reg: 0x58, val: 0x03); /* TMDS PLL optimization */ |
1893 | hdmi_write(sd, reg: 0x60, val: 0x88); /* TMDS PLL optimization */ |
1894 | hdmi_write(sd, reg: 0x61, val: 0x88); /* TMDS PLL optimization */ |
1895 | hdmi_write(sd, reg: 0x6c, val: 0x18); /* Disable ISRC clearing bit, |
1896 | Improve robustness */ |
1897 | hdmi_write(sd, reg: 0x75, val: 0x10); /* DDC drive strength */ |
1898 | hdmi_write(sd, reg: 0x85, val: 0x1f); /* equaliser */ |
1899 | hdmi_write(sd, reg: 0x87, val: 0x70); /* ADI recommended write */ |
1900 | hdmi_write(sd, reg: 0x89, val: 0x04); /* equaliser */ |
1901 | hdmi_write(sd, reg: 0x8a, val: 0x1e); /* equaliser */ |
1902 | hdmi_write(sd, reg: 0x93, val: 0x04); /* equaliser */ |
1903 | hdmi_write(sd, reg: 0x94, val: 0x1e); /* equaliser */ |
1904 | hdmi_write(sd, reg: 0x99, val: 0xa1); /* ADI recommended write */ |
1905 | hdmi_write(sd, reg: 0x9b, val: 0x09); /* ADI recommended write */ |
1906 | hdmi_write(sd, reg: 0x9d, val: 0x02); /* equaliser */ |
1907 | |
1908 | afe_write(sd, reg: 0x00, val: 0xff); /* power down ADC */ |
1909 | afe_write(sd, reg: 0xc8, val: 0x40); /* phase control */ |
1910 | |
1911 | /* set to default gain for HDMI */ |
1912 | cp_write(sd, reg: 0x73, val: 0x10); |
1913 | cp_write(sd, reg: 0x74, val: 0x04); |
1914 | cp_write(sd, reg: 0x75, val: 0x01); |
1915 | cp_write(sd, reg: 0x76, val: 0x00); |
1916 | |
1917 | /* reset ADI recommended settings for digitizer */ |
1918 | /* "ADV7842 Register Settings Recommendations |
1919 | * (rev. 2.5, June 2010)" p. 17. */ |
1920 | afe_write(sd, reg: 0x12, val: 0xfb); /* ADC noise shaping filter controls */ |
1921 | afe_write(sd, reg: 0x0c, val: 0x0d); /* CP core gain controls */ |
1922 | cp_write(sd, reg: 0x3e, val: 0x00); /* CP core pre-gain control */ |
1923 | |
1924 | /* CP coast control */ |
1925 | cp_write(sd, reg: 0xc3, val: 0x33); /* Component mode */ |
1926 | |
1927 | /* color space conversion, autodetect color space */ |
1928 | io_write_and_or(sd, reg: 0x02, mask: 0x0f, val: 0xf0); |
1929 | break; |
1930 | |
1931 | default: |
1932 | v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n" , |
1933 | __func__, state->mode); |
1934 | break; |
1935 | } |
1936 | } |
1937 | |
1938 | static int adv7842_s_routing(struct v4l2_subdev *sd, |
1939 | u32 input, u32 output, u32 config) |
1940 | { |
1941 | struct adv7842_state *state = to_state(sd); |
1942 | |
1943 | v4l2_dbg(2, debug, sd, "%s: input %d\n" , __func__, input); |
1944 | |
1945 | switch (input) { |
1946 | case ADV7842_SELECT_HDMI_PORT_A: |
1947 | state->mode = ADV7842_MODE_HDMI; |
1948 | state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; |
1949 | state->hdmi_port_a = true; |
1950 | break; |
1951 | case ADV7842_SELECT_HDMI_PORT_B: |
1952 | state->mode = ADV7842_MODE_HDMI; |
1953 | state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; |
1954 | state->hdmi_port_a = false; |
1955 | break; |
1956 | case ADV7842_SELECT_VGA_COMP: |
1957 | state->mode = ADV7842_MODE_COMP; |
1958 | state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; |
1959 | break; |
1960 | case ADV7842_SELECT_VGA_RGB: |
1961 | state->mode = ADV7842_MODE_RGB; |
1962 | state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; |
1963 | break; |
1964 | case ADV7842_SELECT_SDP_CVBS: |
1965 | state->mode = ADV7842_MODE_SDP; |
1966 | state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; |
1967 | break; |
1968 | case ADV7842_SELECT_SDP_YC: |
1969 | state->mode = ADV7842_MODE_SDP; |
1970 | state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; |
1971 | break; |
1972 | default: |
1973 | return -EINVAL; |
1974 | } |
1975 | |
1976 | disable_input(sd); |
1977 | select_input(sd, vid_std_select: state->vid_std_select); |
1978 | enable_input(sd); |
1979 | |
1980 | v4l2_subdev_notify_event(sd, ev: &adv7842_ev_fmt); |
1981 | |
1982 | return 0; |
1983 | } |
1984 | |
1985 | static int adv7842_enum_mbus_code(struct v4l2_subdev *sd, |
1986 | struct v4l2_subdev_state *sd_state, |
1987 | struct v4l2_subdev_mbus_code_enum *code) |
1988 | { |
1989 | if (code->index >= ARRAY_SIZE(adv7842_formats)) |
1990 | return -EINVAL; |
1991 | code->code = adv7842_formats[code->index].code; |
1992 | return 0; |
1993 | } |
1994 | |
1995 | static void adv7842_fill_format(struct adv7842_state *state, |
1996 | struct v4l2_mbus_framefmt *format) |
1997 | { |
1998 | memset(format, 0, sizeof(*format)); |
1999 | |
2000 | format->width = state->timings.bt.width; |
2001 | format->height = state->timings.bt.height; |
2002 | format->field = V4L2_FIELD_NONE; |
2003 | format->colorspace = V4L2_COLORSPACE_SRGB; |
2004 | |
2005 | if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) |
2006 | format->colorspace = (state->timings.bt.height <= 576) ? |
2007 | V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; |
2008 | } |
2009 | |
2010 | /* |
2011 | * Compute the op_ch_sel value required to obtain on the bus the component order |
2012 | * corresponding to the selected format taking into account bus reordering |
2013 | * applied by the board at the output of the device. |
2014 | * |
2015 | * The following table gives the op_ch_value from the format component order |
2016 | * (expressed as op_ch_sel value in column) and the bus reordering (expressed as |
2017 | * adv7842_bus_order value in row). |
2018 | * |
2019 | * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) |
2020 | * ----------+------------------------------------------------- |
2021 | * RGB (NOP) | GBR GRB BGR RGB BRG RBG |
2022 | * GRB (1-2) | BGR RGB GBR GRB RBG BRG |
2023 | * RBG (2-3) | GRB GBR BRG RBG BGR RGB |
2024 | * BGR (1-3) | RBG BRG RGB BGR GRB GBR |
2025 | * BRG (ROR) | BRG RBG GRB GBR RGB BGR |
2026 | * GBR (ROL) | RGB BGR RBG BRG GBR GRB |
2027 | */ |
2028 | static unsigned int adv7842_op_ch_sel(struct adv7842_state *state) |
2029 | { |
2030 | #define _SEL(a, b, c, d, e, f) { \ |
2031 | ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \ |
2032 | ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f } |
2033 | #define _BUS(x) [ADV7842_BUS_ORDER_##x] |
2034 | |
2035 | static const unsigned int op_ch_sel[6][6] = { |
2036 | _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), |
2037 | _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), |
2038 | _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), |
2039 | _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), |
2040 | _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), |
2041 | _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), |
2042 | }; |
2043 | |
2044 | return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; |
2045 | } |
2046 | |
2047 | static void adv7842_setup_format(struct adv7842_state *state) |
2048 | { |
2049 | struct v4l2_subdev *sd = &state->sd; |
2050 | |
2051 | io_write_clr_set(sd, reg: 0x02, mask: 0x02, |
2052 | val: state->format->rgb_out ? ADV7842_RGB_OUT : 0); |
2053 | io_write(sd, reg: 0x03, val: state->format->op_format_sel | |
2054 | state->pdata.op_format_mode_sel); |
2055 | io_write_clr_set(sd, reg: 0x04, mask: 0xe0, val: adv7842_op_ch_sel(state)); |
2056 | io_write_clr_set(sd, reg: 0x05, mask: 0x01, |
2057 | val: state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0); |
2058 | set_rgb_quantization_range(sd); |
2059 | } |
2060 | |
2061 | static int adv7842_get_format(struct v4l2_subdev *sd, |
2062 | struct v4l2_subdev_state *sd_state, |
2063 | struct v4l2_subdev_format *format) |
2064 | { |
2065 | struct adv7842_state *state = to_state(sd); |
2066 | |
2067 | if (format->pad != ADV7842_PAD_SOURCE) |
2068 | return -EINVAL; |
2069 | |
2070 | if (state->mode == ADV7842_MODE_SDP) { |
2071 | /* SPD block */ |
2072 | if (!(sdp_read(sd, reg: 0x5a) & 0x01)) |
2073 | return -EINVAL; |
2074 | format->format.code = MEDIA_BUS_FMT_YUYV8_2X8; |
2075 | format->format.width = 720; |
2076 | /* valid signal */ |
2077 | if (state->norm & V4L2_STD_525_60) |
2078 | format->format.height = 480; |
2079 | else |
2080 | format->format.height = 576; |
2081 | format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; |
2082 | return 0; |
2083 | } |
2084 | |
2085 | adv7842_fill_format(state, format: &format->format); |
2086 | |
2087 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { |
2088 | struct v4l2_mbus_framefmt *fmt; |
2089 | |
2090 | fmt = v4l2_subdev_state_get_format(sd_state, format->pad); |
2091 | format->format.code = fmt->code; |
2092 | } else { |
2093 | format->format.code = state->format->code; |
2094 | } |
2095 | |
2096 | return 0; |
2097 | } |
2098 | |
2099 | static int adv7842_set_format(struct v4l2_subdev *sd, |
2100 | struct v4l2_subdev_state *sd_state, |
2101 | struct v4l2_subdev_format *format) |
2102 | { |
2103 | struct adv7842_state *state = to_state(sd); |
2104 | const struct adv7842_format_info *info; |
2105 | |
2106 | if (format->pad != ADV7842_PAD_SOURCE) |
2107 | return -EINVAL; |
2108 | |
2109 | if (state->mode == ADV7842_MODE_SDP) |
2110 | return adv7842_get_format(sd, sd_state, format); |
2111 | |
2112 | info = adv7842_format_info(state, code: format->format.code); |
2113 | if (info == NULL) |
2114 | info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); |
2115 | |
2116 | adv7842_fill_format(state, format: &format->format); |
2117 | format->format.code = info->code; |
2118 | |
2119 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { |
2120 | struct v4l2_mbus_framefmt *fmt; |
2121 | |
2122 | fmt = v4l2_subdev_state_get_format(sd_state, format->pad); |
2123 | fmt->code = format->format.code; |
2124 | } else { |
2125 | state->format = info; |
2126 | adv7842_setup_format(state); |
2127 | } |
2128 | |
2129 | return 0; |
2130 | } |
2131 | |
2132 | static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) |
2133 | { |
2134 | if (enable) { |
2135 | /* Enable SSPD, STDI and CP locked/unlocked interrupts */ |
2136 | io_write(sd, reg: 0x46, val: 0x9c); |
2137 | /* ESDP_50HZ_DET interrupt */ |
2138 | io_write(sd, reg: 0x5a, val: 0x10); |
2139 | /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ |
2140 | io_write(sd, reg: 0x73, val: 0x03); |
2141 | /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ |
2142 | io_write(sd, reg: 0x78, val: 0x03); |
2143 | /* Enable SDP Standard Detection Change and SDP Video Detected */ |
2144 | io_write(sd, reg: 0xa0, val: 0x09); |
2145 | /* Enable HDMI_MODE interrupt */ |
2146 | io_write(sd, reg: 0x69, val: 0x08); |
2147 | } else { |
2148 | io_write(sd, reg: 0x46, val: 0x0); |
2149 | io_write(sd, reg: 0x5a, val: 0x0); |
2150 | io_write(sd, reg: 0x73, val: 0x0); |
2151 | io_write(sd, reg: 0x78, val: 0x0); |
2152 | io_write(sd, reg: 0xa0, val: 0x0); |
2153 | io_write(sd, reg: 0x69, val: 0x0); |
2154 | } |
2155 | } |
2156 | |
2157 | #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) |
2158 | static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) |
2159 | { |
2160 | struct adv7842_state *state = to_state(sd); |
2161 | |
2162 | if ((cec_read(sd, reg: 0x11) & 0x01) == 0) { |
2163 | v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n" , __func__); |
2164 | return; |
2165 | } |
2166 | |
2167 | if (tx_raw_status & 0x02) { |
2168 | v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n" , |
2169 | __func__); |
2170 | cec_transmit_done(adap: state->cec_adap, CEC_TX_STATUS_ARB_LOST, |
2171 | arb_lost_cnt: 1, nack_cnt: 0, low_drive_cnt: 0, error_cnt: 0); |
2172 | return; |
2173 | } |
2174 | if (tx_raw_status & 0x04) { |
2175 | u8 status; |
2176 | u8 nack_cnt; |
2177 | u8 low_drive_cnt; |
2178 | |
2179 | v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n" , __func__); |
2180 | /* |
2181 | * We set this status bit since this hardware performs |
2182 | * retransmissions. |
2183 | */ |
2184 | status = CEC_TX_STATUS_MAX_RETRIES; |
2185 | nack_cnt = cec_read(sd, reg: 0x14) & 0xf; |
2186 | if (nack_cnt) |
2187 | status |= CEC_TX_STATUS_NACK; |
2188 | low_drive_cnt = cec_read(sd, reg: 0x14) >> 4; |
2189 | if (low_drive_cnt) |
2190 | status |= CEC_TX_STATUS_LOW_DRIVE; |
2191 | cec_transmit_done(adap: state->cec_adap, status, |
2192 | arb_lost_cnt: 0, nack_cnt, low_drive_cnt, error_cnt: 0); |
2193 | return; |
2194 | } |
2195 | if (tx_raw_status & 0x01) { |
2196 | v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n" , __func__); |
2197 | cec_transmit_done(adap: state->cec_adap, CEC_TX_STATUS_OK, arb_lost_cnt: 0, nack_cnt: 0, low_drive_cnt: 0, error_cnt: 0); |
2198 | return; |
2199 | } |
2200 | } |
2201 | |
2202 | static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled) |
2203 | { |
2204 | u8 cec_irq; |
2205 | |
2206 | /* cec controller */ |
2207 | cec_irq = io_read(sd, reg: 0x93) & 0x0f; |
2208 | if (!cec_irq) |
2209 | return; |
2210 | |
2211 | v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n" , __func__, cec_irq); |
2212 | adv7842_cec_tx_raw_status(sd, tx_raw_status: cec_irq); |
2213 | if (cec_irq & 0x08) { |
2214 | struct adv7842_state *state = to_state(sd); |
2215 | struct cec_msg msg; |
2216 | |
2217 | msg.len = cec_read(sd, reg: 0x25) & 0x1f; |
2218 | if (msg.len > CEC_MAX_MSG_SIZE) |
2219 | msg.len = CEC_MAX_MSG_SIZE; |
2220 | |
2221 | if (msg.len) { |
2222 | u8 i; |
2223 | |
2224 | for (i = 0; i < msg.len; i++) |
2225 | msg.msg[i] = cec_read(sd, reg: i + 0x15); |
2226 | cec_write(sd, reg: 0x26, val: 0x01); /* re-enable rx */ |
2227 | cec_received_msg(adap: state->cec_adap, msg: &msg); |
2228 | } |
2229 | } |
2230 | |
2231 | io_write(sd, reg: 0x94, val: cec_irq); |
2232 | |
2233 | if (handled) |
2234 | *handled = true; |
2235 | } |
2236 | |
2237 | static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable) |
2238 | { |
2239 | struct adv7842_state *state = cec_get_drvdata(adap); |
2240 | struct v4l2_subdev *sd = &state->sd; |
2241 | |
2242 | if (!state->cec_enabled_adap && enable) { |
2243 | cec_write_clr_set(sd, reg: 0x2a, mask: 0x01, val: 0x01); /* power up cec */ |
2244 | cec_write(sd, reg: 0x2c, val: 0x01); /* cec soft reset */ |
2245 | cec_write_clr_set(sd, reg: 0x11, mask: 0x01, val: 0); /* initially disable tx */ |
2246 | /* enabled irqs: */ |
2247 | /* tx: ready */ |
2248 | /* tx: arbitration lost */ |
2249 | /* tx: retry timeout */ |
2250 | /* rx: ready */ |
2251 | io_write_clr_set(sd, reg: 0x96, mask: 0x0f, val: 0x0f); |
2252 | cec_write(sd, reg: 0x26, val: 0x01); /* enable rx */ |
2253 | } else if (state->cec_enabled_adap && !enable) { |
2254 | /* disable cec interrupts */ |
2255 | io_write_clr_set(sd, reg: 0x96, mask: 0x0f, val: 0x00); |
2256 | /* disable address mask 1-3 */ |
2257 | cec_write_clr_set(sd, reg: 0x27, mask: 0x70, val: 0x00); |
2258 | /* power down cec section */ |
2259 | cec_write_clr_set(sd, reg: 0x2a, mask: 0x01, val: 0x00); |
2260 | state->cec_valid_addrs = 0; |
2261 | } |
2262 | state->cec_enabled_adap = enable; |
2263 | return 0; |
2264 | } |
2265 | |
2266 | static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) |
2267 | { |
2268 | struct adv7842_state *state = cec_get_drvdata(adap); |
2269 | struct v4l2_subdev *sd = &state->sd; |
2270 | unsigned int i, free_idx = ADV7842_MAX_ADDRS; |
2271 | |
2272 | if (!state->cec_enabled_adap) |
2273 | return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; |
2274 | |
2275 | if (addr == CEC_LOG_ADDR_INVALID) { |
2276 | cec_write_clr_set(sd, reg: 0x27, mask: 0x70, val: 0); |
2277 | state->cec_valid_addrs = 0; |
2278 | return 0; |
2279 | } |
2280 | |
2281 | for (i = 0; i < ADV7842_MAX_ADDRS; i++) { |
2282 | bool is_valid = state->cec_valid_addrs & (1 << i); |
2283 | |
2284 | if (free_idx == ADV7842_MAX_ADDRS && !is_valid) |
2285 | free_idx = i; |
2286 | if (is_valid && state->cec_addr[i] == addr) |
2287 | return 0; |
2288 | } |
2289 | if (i == ADV7842_MAX_ADDRS) { |
2290 | i = free_idx; |
2291 | if (i == ADV7842_MAX_ADDRS) |
2292 | return -ENXIO; |
2293 | } |
2294 | state->cec_addr[i] = addr; |
2295 | state->cec_valid_addrs |= 1 << i; |
2296 | |
2297 | switch (i) { |
2298 | case 0: |
2299 | /* enable address mask 0 */ |
2300 | cec_write_clr_set(sd, reg: 0x27, mask: 0x10, val: 0x10); |
2301 | /* set address for mask 0 */ |
2302 | cec_write_clr_set(sd, reg: 0x28, mask: 0x0f, val: addr); |
2303 | break; |
2304 | case 1: |
2305 | /* enable address mask 1 */ |
2306 | cec_write_clr_set(sd, reg: 0x27, mask: 0x20, val: 0x20); |
2307 | /* set address for mask 1 */ |
2308 | cec_write_clr_set(sd, reg: 0x28, mask: 0xf0, val: addr << 4); |
2309 | break; |
2310 | case 2: |
2311 | /* enable address mask 2 */ |
2312 | cec_write_clr_set(sd, reg: 0x27, mask: 0x40, val: 0x40); |
2313 | /* set address for mask 1 */ |
2314 | cec_write_clr_set(sd, reg: 0x29, mask: 0x0f, val: addr); |
2315 | break; |
2316 | } |
2317 | return 0; |
2318 | } |
2319 | |
2320 | static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, |
2321 | u32 signal_free_time, struct cec_msg *msg) |
2322 | { |
2323 | struct adv7842_state *state = cec_get_drvdata(adap); |
2324 | struct v4l2_subdev *sd = &state->sd; |
2325 | u8 len = msg->len; |
2326 | unsigned int i; |
2327 | |
2328 | /* |
2329 | * The number of retries is the number of attempts - 1, but retry |
2330 | * at least once. It's not clear if a value of 0 is allowed, so |
2331 | * let's do at least one retry. |
2332 | */ |
2333 | cec_write_clr_set(sd, reg: 0x12, mask: 0x70, max(1, attempts - 1) << 4); |
2334 | |
2335 | if (len > 16) { |
2336 | v4l2_err(sd, "%s: len exceeded 16 (%d)\n" , __func__, len); |
2337 | return -EINVAL; |
2338 | } |
2339 | |
2340 | /* write data */ |
2341 | for (i = 0; i < len; i++) |
2342 | cec_write(sd, reg: i, val: msg->msg[i]); |
2343 | |
2344 | /* set length (data + header) */ |
2345 | cec_write(sd, reg: 0x10, val: len); |
2346 | /* start transmit, enable tx */ |
2347 | cec_write(sd, reg: 0x11, val: 0x01); |
2348 | return 0; |
2349 | } |
2350 | |
2351 | static const struct cec_adap_ops adv7842_cec_adap_ops = { |
2352 | .adap_enable = adv7842_cec_adap_enable, |
2353 | .adap_log_addr = adv7842_cec_adap_log_addr, |
2354 | .adap_transmit = adv7842_cec_adap_transmit, |
2355 | }; |
2356 | #endif |
2357 | |
2358 | static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) |
2359 | { |
2360 | struct adv7842_state *state = to_state(sd); |
2361 | u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; |
2362 | u8 irq_status[6]; |
2363 | |
2364 | adv7842_irq_enable(sd, enable: false); |
2365 | |
2366 | /* read status */ |
2367 | irq_status[0] = io_read(sd, reg: 0x43); |
2368 | irq_status[1] = io_read(sd, reg: 0x57); |
2369 | irq_status[2] = io_read(sd, reg: 0x70); |
2370 | irq_status[3] = io_read(sd, reg: 0x75); |
2371 | irq_status[4] = io_read(sd, reg: 0x9d); |
2372 | irq_status[5] = io_read(sd, reg: 0x66); |
2373 | |
2374 | /* and clear */ |
2375 | if (irq_status[0]) |
2376 | io_write(sd, reg: 0x44, val: irq_status[0]); |
2377 | if (irq_status[1]) |
2378 | io_write(sd, reg: 0x58, val: irq_status[1]); |
2379 | if (irq_status[2]) |
2380 | io_write(sd, reg: 0x71, val: irq_status[2]); |
2381 | if (irq_status[3]) |
2382 | io_write(sd, reg: 0x76, val: irq_status[3]); |
2383 | if (irq_status[4]) |
2384 | io_write(sd, reg: 0x9e, val: irq_status[4]); |
2385 | if (irq_status[5]) |
2386 | io_write(sd, reg: 0x67, val: irq_status[5]); |
2387 | |
2388 | adv7842_irq_enable(sd, enable: true); |
2389 | |
2390 | v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n" , __func__, |
2391 | irq_status[0], irq_status[1], irq_status[2], |
2392 | irq_status[3], irq_status[4], irq_status[5]); |
2393 | |
2394 | /* format change CP */ |
2395 | fmt_change_cp = irq_status[0] & 0x9c; |
2396 | |
2397 | /* format change SDP */ |
2398 | if (state->mode == ADV7842_MODE_SDP) |
2399 | fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); |
2400 | else |
2401 | fmt_change_sdp = 0; |
2402 | |
2403 | /* digital format CP */ |
2404 | if (is_digital_input(sd)) |
2405 | fmt_change_digital = irq_status[3] & 0x03; |
2406 | else |
2407 | fmt_change_digital = 0; |
2408 | |
2409 | /* format change */ |
2410 | if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { |
2411 | v4l2_dbg(1, debug, sd, |
2412 | "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n" , |
2413 | __func__, fmt_change_cp, fmt_change_digital, |
2414 | fmt_change_sdp); |
2415 | v4l2_subdev_notify_event(sd, ev: &adv7842_ev_fmt); |
2416 | if (handled) |
2417 | *handled = true; |
2418 | } |
2419 | |
2420 | /* HDMI/DVI mode */ |
2421 | if (irq_status[5] & 0x08) { |
2422 | v4l2_dbg(1, debug, sd, "%s: irq %s mode\n" , __func__, |
2423 | (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI" ); |
2424 | set_rgb_quantization_range(sd); |
2425 | if (handled) |
2426 | *handled = true; |
2427 | } |
2428 | |
2429 | #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) |
2430 | /* cec */ |
2431 | adv7842_cec_isr(sd, handled); |
2432 | #endif |
2433 | |
2434 | /* tx 5v detect */ |
2435 | if (irq_status[2] & 0x3) { |
2436 | v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n" , __func__); |
2437 | adv7842_s_detect_tx_5v_ctrl(sd); |
2438 | if (handled) |
2439 | *handled = true; |
2440 | } |
2441 | return 0; |
2442 | } |
2443 | |
2444 | static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) |
2445 | { |
2446 | struct adv7842_state *state = to_state(sd); |
2447 | u32 blocks = 0; |
2448 | u8 *data = NULL; |
2449 | |
2450 | memset(edid->reserved, 0, sizeof(edid->reserved)); |
2451 | |
2452 | switch (edid->pad) { |
2453 | case ADV7842_EDID_PORT_A: |
2454 | case ADV7842_EDID_PORT_B: |
2455 | if (state->hdmi_edid.present & (0x04 << edid->pad)) { |
2456 | data = state->hdmi_edid.edid; |
2457 | blocks = state->hdmi_edid.blocks; |
2458 | } |
2459 | break; |
2460 | case ADV7842_EDID_PORT_VGA: |
2461 | if (state->vga_edid.present) { |
2462 | data = state->vga_edid.edid; |
2463 | blocks = state->vga_edid.blocks; |
2464 | } |
2465 | break; |
2466 | default: |
2467 | return -EINVAL; |
2468 | } |
2469 | |
2470 | if (edid->start_block == 0 && edid->blocks == 0) { |
2471 | edid->blocks = blocks; |
2472 | return 0; |
2473 | } |
2474 | |
2475 | if (!data) |
2476 | return -ENODATA; |
2477 | |
2478 | if (edid->start_block >= blocks) |
2479 | return -EINVAL; |
2480 | |
2481 | if (edid->start_block + edid->blocks > blocks) |
2482 | edid->blocks = blocks - edid->start_block; |
2483 | |
2484 | memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); |
2485 | |
2486 | return 0; |
2487 | } |
2488 | |
2489 | /* |
2490 | * If the VGA_EDID_ENABLE bit is set (Repeater Map 0x7f, bit 7), then |
2491 | * the first two blocks of the EDID are for the HDMI, and the first block |
2492 | * of segment 1 (i.e. the third block of the EDID) is for VGA. |
2493 | * So if a VGA EDID is installed, then the maximum size of the HDMI EDID |
2494 | * is 2 blocks. |
2495 | */ |
2496 | static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) |
2497 | { |
2498 | struct adv7842_state *state = to_state(sd); |
2499 | unsigned int max_blocks = e->pad == ADV7842_EDID_PORT_VGA ? 1 : 4; |
2500 | int err = 0; |
2501 | |
2502 | memset(e->reserved, 0, sizeof(e->reserved)); |
2503 | |
2504 | if (e->pad > ADV7842_EDID_PORT_VGA) |
2505 | return -EINVAL; |
2506 | if (e->start_block != 0) |
2507 | return -EINVAL; |
2508 | if (e->pad < ADV7842_EDID_PORT_VGA && state->vga_edid.blocks) |
2509 | max_blocks = 2; |
2510 | if (e->pad == ADV7842_EDID_PORT_VGA && state->hdmi_edid.blocks > 2) |
2511 | return -EBUSY; |
2512 | if (e->blocks > max_blocks) { |
2513 | e->blocks = max_blocks; |
2514 | return -E2BIG; |
2515 | } |
2516 | |
2517 | /* todo, per edid */ |
2518 | if (e->blocks) |
2519 | state->aspect_ratio = v4l2_calc_aspect_ratio(hor_landscape: e->edid[0x15], |
2520 | vert_portrait: e->edid[0x16]); |
2521 | |
2522 | switch (e->pad) { |
2523 | case ADV7842_EDID_PORT_VGA: |
2524 | memset(state->vga_edid.edid, 0, sizeof(state->vga_edid.edid)); |
2525 | state->vga_edid.blocks = e->blocks; |
2526 | state->vga_edid.present = e->blocks ? 0x1 : 0x0; |
2527 | if (e->blocks) |
2528 | memcpy(state->vga_edid.edid, e->edid, 128); |
2529 | err = edid_write_vga_segment(sd); |
2530 | break; |
2531 | case ADV7842_EDID_PORT_A: |
2532 | case ADV7842_EDID_PORT_B: |
2533 | memset(state->hdmi_edid.edid, 0, sizeof(state->hdmi_edid.edid)); |
2534 | state->hdmi_edid.blocks = e->blocks; |
2535 | if (e->blocks) { |
2536 | state->hdmi_edid.present |= 0x04 << e->pad; |
2537 | memcpy(state->hdmi_edid.edid, e->edid, 128 * e->blocks); |
2538 | } else { |
2539 | state->hdmi_edid.present &= ~(0x04 << e->pad); |
2540 | adv7842_s_detect_tx_5v_ctrl(sd); |
2541 | } |
2542 | err = edid_write_hdmi_segment(sd, port: e->pad); |
2543 | break; |
2544 | default: |
2545 | return -EINVAL; |
2546 | } |
2547 | if (err < 0) |
2548 | v4l2_err(sd, "error %d writing edid on port %d\n" , err, e->pad); |
2549 | return err; |
2550 | } |
2551 | |
2552 | struct adv7842_cfg_read_infoframe { |
2553 | const char *desc; |
2554 | u8 present_mask; |
2555 | u8 head_addr; |
2556 | u8 payload_addr; |
2557 | }; |
2558 | |
2559 | static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri) |
2560 | { |
2561 | int i; |
2562 | u8 buffer[32]; |
2563 | union hdmi_infoframe frame; |
2564 | u8 len; |
2565 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2566 | struct device *dev = &client->dev; |
2567 | |
2568 | if (!(io_read(sd, reg: 0x60) & cri->present_mask)) { |
2569 | v4l2_info(sd, "%s infoframe not received\n" , cri->desc); |
2570 | return; |
2571 | } |
2572 | |
2573 | for (i = 0; i < 3; i++) |
2574 | buffer[i] = infoframe_read(sd, reg: cri->head_addr + i); |
2575 | |
2576 | len = buffer[2] + 1; |
2577 | |
2578 | if (len + 3 > sizeof(buffer)) { |
2579 | v4l2_err(sd, "%s: invalid %s infoframe length %d\n" , __func__, cri->desc, len); |
2580 | return; |
2581 | } |
2582 | |
2583 | for (i = 0; i < len; i++) |
2584 | buffer[i + 3] = infoframe_read(sd, reg: cri->payload_addr + i); |
2585 | |
2586 | if (hdmi_infoframe_unpack(frame: &frame, buffer, size: len + 3) < 0) { |
2587 | v4l2_err(sd, "%s: unpack of %s infoframe failed\n" , __func__, cri->desc); |
2588 | return; |
2589 | } |
2590 | |
2591 | hdmi_infoframe_log(KERN_INFO, dev, frame: &frame); |
2592 | } |
2593 | |
2594 | static void adv7842_log_infoframes(struct v4l2_subdev *sd) |
2595 | { |
2596 | int i; |
2597 | static const struct adv7842_cfg_read_infoframe cri[] = { |
2598 | { "AVI" , 0x01, 0xe0, 0x00 }, |
2599 | { "Audio" , 0x02, 0xe3, 0x1c }, |
2600 | { "SDP" , 0x04, 0xe6, 0x2a }, |
2601 | { "Vendor" , 0x10, 0xec, 0x54 } |
2602 | }; |
2603 | |
2604 | if (!(hdmi_read(sd, reg: 0x05) & 0x80)) { |
2605 | v4l2_info(sd, "receive DVI-D signal, no infoframes\n" ); |
2606 | return; |
2607 | } |
2608 | |
2609 | for (i = 0; i < ARRAY_SIZE(cri); i++) |
2610 | log_infoframe(sd, cri: &cri[i]); |
2611 | } |
2612 | |
2613 | #if 0 |
2614 | /* Let's keep it here for now, as it could be useful for debug */ |
2615 | static const char * const prim_mode_txt[] = { |
2616 | "SDP" , |
2617 | "Component" , |
2618 | "Graphics" , |
2619 | "Reserved" , |
2620 | "CVBS & HDMI AUDIO" , |
2621 | "HDMI-Comp" , |
2622 | "HDMI-GR" , |
2623 | "Reserved" , |
2624 | "Reserved" , |
2625 | "Reserved" , |
2626 | "Reserved" , |
2627 | "Reserved" , |
2628 | "Reserved" , |
2629 | "Reserved" , |
2630 | "Reserved" , |
2631 | "Reserved" , |
2632 | }; |
2633 | #endif |
2634 | |
2635 | static int adv7842_sdp_log_status(struct v4l2_subdev *sd) |
2636 | { |
2637 | /* SDP (Standard definition processor) block */ |
2638 | u8 sdp_signal_detected = sdp_read(sd, reg: 0x5A) & 0x01; |
2639 | |
2640 | v4l2_info(sd, "Chip powered %s\n" , no_power(sd) ? "off" : "on" ); |
2641 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n" , |
2642 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); |
2643 | |
2644 | v4l2_info(sd, "SDP: free run: %s\n" , |
2645 | (sdp_read(sd, 0x56) & 0x01) ? "on" : "off" ); |
2646 | v4l2_info(sd, "SDP: %s\n" , sdp_signal_detected ? |
2647 | "valid SD/PR signal detected" : "invalid/no signal" ); |
2648 | if (sdp_signal_detected) { |
2649 | static const char * const sdp_std_txt[] = { |
2650 | "NTSC-M/J" , |
2651 | "1?" , |
2652 | "NTSC-443" , |
2653 | "60HzSECAM" , |
2654 | "PAL-M" , |
2655 | "5?" , |
2656 | "PAL-60" , |
2657 | "7?" , "8?" , "9?" , "a?" , "b?" , |
2658 | "PAL-CombN" , |
2659 | "d?" , |
2660 | "PAL-BGHID" , |
2661 | "SECAM" |
2662 | }; |
2663 | v4l2_info(sd, "SDP: standard %s\n" , |
2664 | sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); |
2665 | v4l2_info(sd, "SDP: %s\n" , |
2666 | (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz" ); |
2667 | v4l2_info(sd, "SDP: %s\n" , |
2668 | (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive" ); |
2669 | v4l2_info(sd, "SDP: deinterlacer %s\n" , |
2670 | (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled" ); |
2671 | v4l2_info(sd, "SDP: csc %s mode\n" , |
2672 | (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual" ); |
2673 | } |
2674 | return 0; |
2675 | } |
2676 | |
2677 | static int adv7842_cp_log_status(struct v4l2_subdev *sd) |
2678 | { |
2679 | /* CP block */ |
2680 | struct adv7842_state *state = to_state(sd); |
2681 | struct v4l2_dv_timings timings; |
2682 | u8 reg_io_0x02 = io_read(sd, reg: 0x02); |
2683 | u8 reg_io_0x21 = io_read(sd, reg: 0x21); |
2684 | u8 reg_rep_0x77 = rep_read(sd, reg: 0x77); |
2685 | u8 reg_rep_0x7d = rep_read(sd, reg: 0x7d); |
2686 | bool audio_pll_locked = hdmi_read(sd, reg: 0x04) & 0x01; |
2687 | bool audio_sample_packet_detect = hdmi_read(sd, reg: 0x18) & 0x01; |
2688 | bool audio_mute = io_read(sd, reg: 0x65) & 0x40; |
2689 | |
2690 | static const char * const csc_coeff_sel_rb[16] = { |
2691 | "bypassed" , "YPbPr601 -> RGB" , "reserved" , "YPbPr709 -> RGB" , |
2692 | "reserved" , "RGB -> YPbPr601" , "reserved" , "RGB -> YPbPr709" , |
2693 | "reserved" , "YPbPr709 -> YPbPr601" , "YPbPr601 -> YPbPr709" , |
2694 | "reserved" , "reserved" , "reserved" , "reserved" , "manual" |
2695 | }; |
2696 | static const char * const input_color_space_txt[16] = { |
2697 | "RGB limited range (16-235)" , "RGB full range (0-255)" , |
2698 | "YCbCr Bt.601 (16-235)" , "YCbCr Bt.709 (16-235)" , |
2699 | "xvYCC Bt.601" , "xvYCC Bt.709" , |
2700 | "YCbCr Bt.601 (0-255)" , "YCbCr Bt.709 (0-255)" , |
2701 | "invalid" , "invalid" , "invalid" , "invalid" , "invalid" , |
2702 | "invalid" , "invalid" , "automatic" |
2703 | }; |
2704 | static const char * const rgb_quantization_range_txt[] = { |
2705 | "Automatic" , |
2706 | "RGB limited range (16-235)" , |
2707 | "RGB full range (0-255)" , |
2708 | }; |
2709 | static const char * const deep_color_mode_txt[4] = { |
2710 | "8-bits per channel" , |
2711 | "10-bits per channel" , |
2712 | "12-bits per channel" , |
2713 | "16-bits per channel (not supported)" |
2714 | }; |
2715 | |
2716 | v4l2_info(sd, "-----Chip status-----\n" ); |
2717 | v4l2_info(sd, "Chip power: %s\n" , no_power(sd) ? "off" : "on" ); |
2718 | v4l2_info(sd, "HDMI/DVI-D port selected: %s\n" , |
2719 | state->hdmi_port_a ? "A" : "B" ); |
2720 | v4l2_info(sd, "EDID A %s, B %s\n" , |
2721 | ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? |
2722 | "enabled" : "disabled" , |
2723 | ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? |
2724 | "enabled" : "disabled" ); |
2725 | v4l2_info(sd, "HPD A %s, B %s\n" , |
2726 | reg_io_0x21 & 0x02 ? "enabled" : "disabled" , |
2727 | reg_io_0x21 & 0x01 ? "enabled" : "disabled" ); |
2728 | v4l2_info(sd, "CEC: %s\n" , state->cec_enabled_adap ? |
2729 | "enabled" : "disabled" ); |
2730 | if (state->cec_enabled_adap) { |
2731 | int i; |
2732 | |
2733 | for (i = 0; i < ADV7842_MAX_ADDRS; i++) { |
2734 | bool is_valid = state->cec_valid_addrs & (1 << i); |
2735 | |
2736 | if (is_valid) |
2737 | v4l2_info(sd, "CEC Logical Address: 0x%x\n" , |
2738 | state->cec_addr[i]); |
2739 | } |
2740 | } |
2741 | |
2742 | v4l2_info(sd, "-----Signal status-----\n" ); |
2743 | if (state->hdmi_port_a) { |
2744 | v4l2_info(sd, "Cable detected (+5V power): %s\n" , |
2745 | io_read(sd, 0x6f) & 0x02 ? "true" : "false" ); |
2746 | v4l2_info(sd, "TMDS signal detected: %s\n" , |
2747 | (io_read(sd, 0x6a) & 0x02) ? "true" : "false" ); |
2748 | v4l2_info(sd, "TMDS signal locked: %s\n" , |
2749 | (io_read(sd, 0x6a) & 0x20) ? "true" : "false" ); |
2750 | } else { |
2751 | v4l2_info(sd, "Cable detected (+5V power):%s\n" , |
2752 | io_read(sd, 0x6f) & 0x01 ? "true" : "false" ); |
2753 | v4l2_info(sd, "TMDS signal detected: %s\n" , |
2754 | (io_read(sd, 0x6a) & 0x01) ? "true" : "false" ); |
2755 | v4l2_info(sd, "TMDS signal locked: %s\n" , |
2756 | (io_read(sd, 0x6a) & 0x10) ? "true" : "false" ); |
2757 | } |
2758 | v4l2_info(sd, "CP free run: %s\n" , |
2759 | (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off" )); |
2760 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n" , |
2761 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, |
2762 | (io_read(sd, 0x01) & 0x70) >> 4); |
2763 | |
2764 | v4l2_info(sd, "-----Video Timings-----\n" ); |
2765 | if (no_cp_signal(sd)) { |
2766 | v4l2_info(sd, "STDI: not locked\n" ); |
2767 | } else { |
2768 | u32 bl = ((cp_read(sd, reg: 0xb1) & 0x3f) << 8) | cp_read(sd, reg: 0xb2); |
2769 | u32 lcf = ((cp_read(sd, reg: 0xb3) & 0x7) << 8) | cp_read(sd, reg: 0xb4); |
2770 | u32 lcvs = cp_read(sd, reg: 0xb3) >> 3; |
2771 | u32 fcl = ((cp_read(sd, reg: 0xb8) & 0x1f) << 8) | cp_read(sd, reg: 0xb9); |
2772 | char hs_pol = ((cp_read(sd, reg: 0xb5) & 0x10) ? |
2773 | ((cp_read(sd, reg: 0xb5) & 0x08) ? '+' : '-') : 'x'); |
2774 | char vs_pol = ((cp_read(sd, reg: 0xb5) & 0x40) ? |
2775 | ((cp_read(sd, reg: 0xb5) & 0x20) ? '+' : '-') : 'x'); |
2776 | v4l2_info(sd, |
2777 | "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n" , |
2778 | lcf, bl, lcvs, fcl, |
2779 | (cp_read(sd, 0xb1) & 0x40) ? |
2780 | "interlaced" : "progressive" , |
2781 | hs_pol, vs_pol); |
2782 | } |
2783 | if (adv7842_query_dv_timings(sd, timings: &timings)) |
2784 | v4l2_info(sd, "No video detected\n" ); |
2785 | else |
2786 | v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "Detected format: " , |
2787 | t: &timings, detailed: true); |
2788 | v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "Configured format: " , |
2789 | t: &state->timings, detailed: true); |
2790 | |
2791 | if (no_cp_signal(sd)) |
2792 | return 0; |
2793 | |
2794 | v4l2_info(sd, "-----Color space-----\n" ); |
2795 | v4l2_info(sd, "RGB quantization range ctrl: %s\n" , |
2796 | rgb_quantization_range_txt[state->rgb_quantization_range]); |
2797 | v4l2_info(sd, "Input color space: %s\n" , |
2798 | input_color_space_txt[reg_io_0x02 >> 4]); |
2799 | v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n" , |
2800 | (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr" , |
2801 | (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? |
2802 | "(16-235)" : "(0-255)" , |
2803 | (reg_io_0x02 & 0x08) ? "enabled" : "disabled" ); |
2804 | v4l2_info(sd, "Color space conversion: %s\n" , |
2805 | csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); |
2806 | |
2807 | if (!is_digital_input(sd)) |
2808 | return 0; |
2809 | |
2810 | v4l2_info(sd, "-----%s status-----\n" , is_hdmi(sd) ? "HDMI" : "DVI-D" ); |
2811 | v4l2_info(sd, "HDCP encrypted content: %s\n" , |
2812 | (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false" ); |
2813 | v4l2_info(sd, "HDCP keys read: %s%s\n" , |
2814 | (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no" , |
2815 | (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "" ); |
2816 | if (!is_hdmi(sd)) |
2817 | return 0; |
2818 | |
2819 | v4l2_info(sd, "Audio: pll %s, samples %s, %s\n" , |
2820 | audio_pll_locked ? "locked" : "not locked" , |
2821 | audio_sample_packet_detect ? "detected" : "not detected" , |
2822 | audio_mute ? "muted" : "enabled" ); |
2823 | if (audio_pll_locked && audio_sample_packet_detect) { |
2824 | v4l2_info(sd, "Audio format: %s\n" , |
2825 | (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo" ); |
2826 | } |
2827 | v4l2_info(sd, "Audio CTS: %u\n" , (hdmi_read(sd, 0x5b) << 12) + |
2828 | (hdmi_read(sd, 0x5c) << 8) + |
2829 | (hdmi_read(sd, 0x5d) & 0xf0)); |
2830 | v4l2_info(sd, "Audio N: %u\n" , ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + |
2831 | (hdmi_read(sd, 0x5e) << 8) + |
2832 | hdmi_read(sd, 0x5f)); |
2833 | v4l2_info(sd, "AV Mute: %s\n" , |
2834 | (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off" ); |
2835 | v4l2_info(sd, "Deep color mode: %s\n" , |
2836 | deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); |
2837 | |
2838 | adv7842_log_infoframes(sd); |
2839 | |
2840 | return 0; |
2841 | } |
2842 | |
2843 | static int adv7842_log_status(struct v4l2_subdev *sd) |
2844 | { |
2845 | struct adv7842_state *state = to_state(sd); |
2846 | |
2847 | if (state->mode == ADV7842_MODE_SDP) |
2848 | return adv7842_sdp_log_status(sd); |
2849 | return adv7842_cp_log_status(sd); |
2850 | } |
2851 | |
2852 | static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) |
2853 | { |
2854 | struct adv7842_state *state = to_state(sd); |
2855 | |
2856 | v4l2_dbg(1, debug, sd, "%s:\n" , __func__); |
2857 | |
2858 | if (state->mode != ADV7842_MODE_SDP) |
2859 | return -ENODATA; |
2860 | |
2861 | if (!(sdp_read(sd, reg: 0x5A) & 0x01)) { |
2862 | *std = 0; |
2863 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n" , __func__); |
2864 | return 0; |
2865 | } |
2866 | |
2867 | switch (sdp_read(sd, reg: 0x52) & 0x0f) { |
2868 | case 0: |
2869 | /* NTSC-M/J */ |
2870 | *std &= V4L2_STD_NTSC; |
2871 | break; |
2872 | case 2: |
2873 | /* NTSC-443 */ |
2874 | *std &= V4L2_STD_NTSC_443; |
2875 | break; |
2876 | case 3: |
2877 | /* 60HzSECAM */ |
2878 | *std &= V4L2_STD_SECAM; |
2879 | break; |
2880 | case 4: |
2881 | /* PAL-M */ |
2882 | *std &= V4L2_STD_PAL_M; |
2883 | break; |
2884 | case 6: |
2885 | /* PAL-60 */ |
2886 | *std &= V4L2_STD_PAL_60; |
2887 | break; |
2888 | case 0xc: |
2889 | /* PAL-CombN */ |
2890 | *std &= V4L2_STD_PAL_Nc; |
2891 | break; |
2892 | case 0xe: |
2893 | /* PAL-BGHID */ |
2894 | *std &= V4L2_STD_PAL; |
2895 | break; |
2896 | case 0xf: |
2897 | /* SECAM */ |
2898 | *std &= V4L2_STD_SECAM; |
2899 | break; |
2900 | default: |
2901 | *std &= V4L2_STD_ALL; |
2902 | break; |
2903 | } |
2904 | return 0; |
2905 | } |
2906 | |
2907 | static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) |
2908 | { |
2909 | if (s && s->adjust) { |
2910 | sdp_io_write(sd, reg: 0x94, val: (s->hs_beg >> 8) & 0xf); |
2911 | sdp_io_write(sd, reg: 0x95, val: s->hs_beg & 0xff); |
2912 | sdp_io_write(sd, reg: 0x96, val: (s->hs_width >> 8) & 0xf); |
2913 | sdp_io_write(sd, reg: 0x97, val: s->hs_width & 0xff); |
2914 | sdp_io_write(sd, reg: 0x98, val: (s->de_beg >> 8) & 0xf); |
2915 | sdp_io_write(sd, reg: 0x99, val: s->de_beg & 0xff); |
2916 | sdp_io_write(sd, reg: 0x9a, val: (s->de_end >> 8) & 0xf); |
2917 | sdp_io_write(sd, reg: 0x9b, val: s->de_end & 0xff); |
2918 | sdp_io_write(sd, reg: 0xa8, val: s->vs_beg_o); |
2919 | sdp_io_write(sd, reg: 0xa9, val: s->vs_beg_e); |
2920 | sdp_io_write(sd, reg: 0xaa, val: s->vs_end_o); |
2921 | sdp_io_write(sd, reg: 0xab, val: s->vs_end_e); |
2922 | sdp_io_write(sd, reg: 0xac, val: s->de_v_beg_o); |
2923 | sdp_io_write(sd, reg: 0xad, val: s->de_v_beg_e); |
2924 | sdp_io_write(sd, reg: 0xae, val: s->de_v_end_o); |
2925 | sdp_io_write(sd, reg: 0xaf, val: s->de_v_end_e); |
2926 | } else { |
2927 | /* set to default */ |
2928 | sdp_io_write(sd, reg: 0x94, val: 0x00); |
2929 | sdp_io_write(sd, reg: 0x95, val: 0x00); |
2930 | sdp_io_write(sd, reg: 0x96, val: 0x00); |
2931 | sdp_io_write(sd, reg: 0x97, val: 0x20); |
2932 | sdp_io_write(sd, reg: 0x98, val: 0x00); |
2933 | sdp_io_write(sd, reg: 0x99, val: 0x00); |
2934 | sdp_io_write(sd, reg: 0x9a, val: 0x00); |
2935 | sdp_io_write(sd, reg: 0x9b, val: 0x00); |
2936 | sdp_io_write(sd, reg: 0xa8, val: 0x04); |
2937 | sdp_io_write(sd, reg: 0xa9, val: 0x04); |
2938 | sdp_io_write(sd, reg: 0xaa, val: 0x04); |
2939 | sdp_io_write(sd, reg: 0xab, val: 0x04); |
2940 | sdp_io_write(sd, reg: 0xac, val: 0x04); |
2941 | sdp_io_write(sd, reg: 0xad, val: 0x04); |
2942 | sdp_io_write(sd, reg: 0xae, val: 0x04); |
2943 | sdp_io_write(sd, reg: 0xaf, val: 0x04); |
2944 | } |
2945 | } |
2946 | |
2947 | static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) |
2948 | { |
2949 | struct adv7842_state *state = to_state(sd); |
2950 | struct adv7842_platform_data *pdata = &state->pdata; |
2951 | |
2952 | v4l2_dbg(1, debug, sd, "%s:\n" , __func__); |
2953 | |
2954 | if (state->mode != ADV7842_MODE_SDP) |
2955 | return -ENODATA; |
2956 | |
2957 | if (norm & V4L2_STD_625_50) |
2958 | adv7842_s_sdp_io(sd, s: &pdata->sdp_io_sync_625); |
2959 | else if (norm & V4L2_STD_525_60) |
2960 | adv7842_s_sdp_io(sd, s: &pdata->sdp_io_sync_525); |
2961 | else |
2962 | adv7842_s_sdp_io(sd, NULL); |
2963 | |
2964 | if (norm & V4L2_STD_ALL) { |
2965 | state->norm = norm; |
2966 | return 0; |
2967 | } |
2968 | return -EINVAL; |
2969 | } |
2970 | |
2971 | static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) |
2972 | { |
2973 | struct adv7842_state *state = to_state(sd); |
2974 | |
2975 | v4l2_dbg(1, debug, sd, "%s:\n" , __func__); |
2976 | |
2977 | if (state->mode != ADV7842_MODE_SDP) |
2978 | return -ENODATA; |
2979 | |
2980 | *norm = state->norm; |
2981 | return 0; |
2982 | } |
2983 | |
2984 | /* ----------------------------------------------------------------------- */ |
2985 | |
2986 | static int adv7842_core_init(struct v4l2_subdev *sd) |
2987 | { |
2988 | struct adv7842_state *state = to_state(sd); |
2989 | struct adv7842_platform_data *pdata = &state->pdata; |
2990 | hdmi_write(sd, reg: 0x48, |
2991 | val: (pdata->disable_pwrdnb ? 0x80 : 0) | |
2992 | (pdata->disable_cable_det_rst ? 0x40 : 0)); |
2993 | |
2994 | disable_input(sd); |
2995 | |
2996 | /* |
2997 | * Disable I2C access to internal EDID ram from HDMI DDC ports |
2998 | * Disable auto edid enable when leaving powerdown mode |
2999 | */ |
3000 | rep_write_and_or(sd, reg: 0x77, mask: 0xd3, val: 0x20); |
3001 | |
3002 | /* power */ |
3003 | io_write(sd, reg: 0x0c, val: 0x42); /* Power up part and power down VDP */ |
3004 | io_write(sd, reg: 0x15, val: 0x80); /* Power up pads */ |
3005 | |
3006 | /* video format */ |
3007 | io_write(sd, reg: 0x02, val: 0xf0 | pdata->alt_gamma << 3); |
3008 | io_write_and_or(sd, reg: 0x05, mask: 0xf0, val: pdata->blank_data << 3 | |
3009 | pdata->insert_av_codes << 2 | |
3010 | pdata->replicate_av_codes << 1); |
3011 | adv7842_setup_format(state); |
3012 | |
3013 | /* HDMI audio */ |
3014 | hdmi_write_and_or(sd, reg: 0x1a, mask: 0xf1, val: 0x08); /* Wait 1 s before unmute */ |
3015 | |
3016 | /* Drive strength */ |
3017 | io_write_and_or(sd, reg: 0x14, mask: 0xc0, |
3018 | val: pdata->dr_str_data << 4 | |
3019 | pdata->dr_str_clk << 2 | |
3020 | pdata->dr_str_sync); |
3021 | |
3022 | /* HDMI free run */ |
3023 | cp_write_and_or(sd, reg: 0xba, mask: 0xfc, val: pdata->hdmi_free_run_enable | |
3024 | (pdata->hdmi_free_run_mode << 1)); |
3025 | |
3026 | /* SPD free run */ |
3027 | sdp_write_and_or(sd, reg: 0xdd, mask: 0xf0, val: pdata->sdp_free_run_force | |
3028 | (pdata->sdp_free_run_cbar_en << 1) | |
3029 | (pdata->sdp_free_run_man_col_en << 2) | |
3030 | (pdata->sdp_free_run_auto << 3)); |
3031 | |
3032 | /* TODO from platform data */ |
3033 | cp_write(sd, reg: 0x69, val: 0x14); /* Enable CP CSC */ |
3034 | io_write(sd, reg: 0x06, val: 0xa6); /* positive VS and HS and DE */ |
3035 | cp_write(sd, reg: 0xf3, val: 0xdc); /* Low threshold to enter/exit free run mode */ |
3036 | afe_write(sd, reg: 0xb5, val: 0x01); /* Setting MCLK to 256Fs */ |
3037 | |
3038 | afe_write(sd, reg: 0x02, val: pdata->ain_sel); /* Select analog input muxing mode */ |
3039 | io_write_and_or(sd, reg: 0x30, mask: ~(1 << 4), val: pdata->output_bus_lsb_to_msb << 4); |
3040 | |
3041 | sdp_csc_coeff(sd, c: &pdata->sdp_csc_coeff); |
3042 | |
3043 | /* todo, improve settings for sdram */ |
3044 | if (pdata->sd_ram_size >= 128) { |
3045 | sdp_write(sd, reg: 0x12, val: 0x0d); /* Frame TBC,3D comb enabled */ |
3046 | if (pdata->sd_ram_ddr) { |
3047 | /* SDP setup for the AD eval board */ |
3048 | sdp_io_write(sd, reg: 0x6f, val: 0x00); /* DDR mode */ |
3049 | sdp_io_write(sd, reg: 0x75, val: 0x0a); /* 128 MB memory size */ |
3050 | sdp_io_write(sd, reg: 0x7a, val: 0xa5); /* Timing Adjustment */ |
3051 | sdp_io_write(sd, reg: 0x7b, val: 0x8f); /* Timing Adjustment */ |
3052 | sdp_io_write(sd, reg: 0x60, val: 0x01); /* SDRAM reset */ |
3053 | } else { |
3054 | sdp_io_write(sd, reg: 0x75, val: 0x0a); /* 64 MB memory size ?*/ |
3055 | sdp_io_write(sd, reg: 0x74, val: 0x00); /* must be zero for sdr sdram */ |
3056 | sdp_io_write(sd, reg: 0x79, val: 0x33); /* CAS latency to 3, |
3057 | depends on memory */ |
3058 | sdp_io_write(sd, reg: 0x6f, val: 0x01); /* SDR mode */ |
3059 | sdp_io_write(sd, reg: 0x7a, val: 0xa5); /* Timing Adjustment */ |
3060 | sdp_io_write(sd, reg: 0x7b, val: 0x8f); /* Timing Adjustment */ |
3061 | sdp_io_write(sd, reg: 0x60, val: 0x01); /* SDRAM reset */ |
3062 | } |
3063 | } else { |
3064 | /* |
3065 | * Manual UG-214, rev 0 is bit confusing on this bit |
3066 | * but a '1' disables any signal if the Ram is active. |
3067 | */ |
3068 | sdp_io_write(sd, reg: 0x29, val: 0x10); /* Tristate memory interface */ |
3069 | } |
3070 | |
3071 | select_input(sd, vid_std_select: pdata->vid_std_select); |
3072 | |
3073 | enable_input(sd); |
3074 | |
3075 | if (pdata->hpa_auto) { |
3076 | /* HPA auto, HPA 0.5s after Edid set and Cable detect */ |
3077 | hdmi_write(sd, reg: 0x69, val: 0x5c); |
3078 | } else { |
3079 | /* HPA manual */ |
3080 | hdmi_write(sd, reg: 0x69, val: 0xa3); |
3081 | /* HPA disable on port A and B */ |
3082 | io_write_and_or(sd, reg: 0x20, mask: 0xcf, val: 0x00); |
3083 | } |
3084 | |
3085 | /* LLC */ |
3086 | io_write(sd, reg: 0x19, val: 0x80 | pdata->llc_dll_phase); |
3087 | io_write(sd, reg: 0x33, val: 0x40); |
3088 | |
3089 | /* interrupts */ |
3090 | io_write(sd, reg: 0x40, val: 0xf2); /* Configure INT1 */ |
3091 | |
3092 | adv7842_irq_enable(sd, enable: true); |
3093 | |
3094 | return v4l2_ctrl_handler_setup(hdl: sd->ctrl_handler); |
3095 | } |
3096 | |
3097 | /* ----------------------------------------------------------------------- */ |
3098 | |
3099 | static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) |
3100 | { |
3101 | /* |
3102 | * From ADV784x external Memory test.pdf |
3103 | * |
3104 | * Reset must just been performed before running test. |
3105 | * Recommended to reset after test. |
3106 | */ |
3107 | int i; |
3108 | int pass = 0; |
3109 | int fail = 0; |
3110 | int complete = 0; |
3111 | |
3112 | io_write(sd, reg: 0x00, val: 0x01); /* Program SDP 4x1 */ |
3113 | io_write(sd, reg: 0x01, val: 0x00); /* Program SDP mode */ |
3114 | afe_write(sd, reg: 0x80, val: 0x92); /* SDP Recommended Write */ |
3115 | afe_write(sd, reg: 0x9B, val: 0x01); /* SDP Recommended Write ADV7844ES1 */ |
3116 | afe_write(sd, reg: 0x9C, val: 0x60); /* SDP Recommended Write ADV7844ES1 */ |
3117 | afe_write(sd, reg: 0x9E, val: 0x02); /* SDP Recommended Write ADV7844ES1 */ |
3118 | afe_write(sd, reg: 0xA0, val: 0x0B); /* SDP Recommended Write ADV7844ES1 */ |
3119 | afe_write(sd, reg: 0xC3, val: 0x02); /* Memory BIST Initialisation */ |
3120 | io_write(sd, reg: 0x0C, val: 0x40); /* Power up ADV7844 */ |
3121 | io_write(sd, reg: 0x15, val: 0xBA); /* Enable outputs */ |
3122 | sdp_write(sd, reg: 0x12, val: 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ |
3123 | io_write(sd, reg: 0xFF, val: 0x04); /* Reset memory controller */ |
3124 | |
3125 | usleep_range(min: 5000, max: 6000); |
3126 | |
3127 | sdp_write(sd, reg: 0x12, val: 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ |
3128 | sdp_io_write(sd, reg: 0x2A, val: 0x01); /* Memory BIST Initialisation */ |
3129 | sdp_io_write(sd, reg: 0x7c, val: 0x19); /* Memory BIST Initialisation */ |
3130 | sdp_io_write(sd, reg: 0x80, val: 0x87); /* Memory BIST Initialisation */ |
3131 | sdp_io_write(sd, reg: 0x81, val: 0x4a); /* Memory BIST Initialisation */ |
3132 | sdp_io_write(sd, reg: 0x82, val: 0x2c); /* Memory BIST Initialisation */ |
3133 | sdp_io_write(sd, reg: 0x83, val: 0x0e); /* Memory BIST Initialisation */ |
3134 | sdp_io_write(sd, reg: 0x84, val: 0x94); /* Memory BIST Initialisation */ |
3135 | sdp_io_write(sd, reg: 0x85, val: 0x62); /* Memory BIST Initialisation */ |
3136 | sdp_io_write(sd, reg: 0x7d, val: 0x00); /* Memory BIST Initialisation */ |
3137 | sdp_io_write(sd, reg: 0x7e, val: 0x1a); /* Memory BIST Initialisation */ |
3138 | |
3139 | usleep_range(min: 5000, max: 6000); |
3140 | |
3141 | sdp_io_write(sd, reg: 0xd9, val: 0xd5); /* Enable BIST Test */ |
3142 | sdp_write(sd, reg: 0x12, val: 0x05); /* Enable FRAME TBC & 3D COMB */ |
3143 | |
3144 | msleep(msecs: 20); |
3145 | |
3146 | for (i = 0; i < 10; i++) { |
3147 | u8 result = sdp_io_read(sd, reg: 0xdb); |
3148 | if (result & 0x10) { |
3149 | complete++; |
3150 | if (result & 0x20) |
3151 | fail++; |
3152 | else |
3153 | pass++; |
3154 | } |
3155 | msleep(msecs: 20); |
3156 | } |
3157 | |
3158 | v4l2_dbg(1, debug, sd, |
3159 | "Ram Test: completed %d of %d: pass %d, fail %d\n" , |
3160 | complete, i, pass, fail); |
3161 | |
3162 | if (!complete || fail) |
3163 | return -EIO; |
3164 | return 0; |
3165 | } |
3166 | |
3167 | static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, |
3168 | struct adv7842_platform_data *pdata) |
3169 | { |
3170 | io_write(sd, reg: 0xf1, val: pdata->i2c_sdp << 1); |
3171 | io_write(sd, reg: 0xf2, val: pdata->i2c_sdp_io << 1); |
3172 | io_write(sd, reg: 0xf3, val: pdata->i2c_avlink << 1); |
3173 | io_write(sd, reg: 0xf4, val: pdata->i2c_cec << 1); |
3174 | io_write(sd, reg: 0xf5, val: pdata->i2c_infoframe << 1); |
3175 | |
3176 | io_write(sd, reg: 0xf8, val: pdata->i2c_afe << 1); |
3177 | io_write(sd, reg: 0xf9, val: pdata->i2c_repeater << 1); |
3178 | io_write(sd, reg: 0xfa, val: pdata->i2c_edid << 1); |
3179 | io_write(sd, reg: 0xfb, val: pdata->i2c_hdmi << 1); |
3180 | |
3181 | io_write(sd, reg: 0xfd, val: pdata->i2c_cp << 1); |
3182 | io_write(sd, reg: 0xfe, val: pdata->i2c_vdp << 1); |
3183 | } |
3184 | |
3185 | static int adv7842_command_ram_test(struct v4l2_subdev *sd) |
3186 | { |
3187 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
3188 | struct adv7842_state *state = to_state(sd); |
3189 | struct adv7842_platform_data *pdata = client->dev.platform_data; |
3190 | struct v4l2_dv_timings timings; |
3191 | int ret = 0; |
3192 | |
3193 | if (!pdata) |
3194 | return -ENODEV; |
3195 | |
3196 | if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { |
3197 | v4l2_info(sd, "no sdram or no ddr sdram\n" ); |
3198 | return -EINVAL; |
3199 | } |
3200 | |
3201 | main_reset(sd); |
3202 | |
3203 | adv7842_rewrite_i2c_addresses(sd, pdata); |
3204 | |
3205 | /* run ram test */ |
3206 | ret = adv7842_ddr_ram_test(sd); |
3207 | |
3208 | main_reset(sd); |
3209 | |
3210 | adv7842_rewrite_i2c_addresses(sd, pdata); |
3211 | |
3212 | /* and re-init chip and state */ |
3213 | adv7842_core_init(sd); |
3214 | |
3215 | disable_input(sd); |
3216 | |
3217 | select_input(sd, vid_std_select: state->vid_std_select); |
3218 | |
3219 | enable_input(sd); |
3220 | |
3221 | edid_write_vga_segment(sd); |
3222 | edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); |
3223 | edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); |
3224 | |
3225 | timings = state->timings; |
3226 | |
3227 | memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); |
3228 | |
3229 | adv7842_s_dv_timings(sd, timings: &timings); |
3230 | |
3231 | return ret; |
3232 | } |
3233 | |
3234 | static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) |
3235 | { |
3236 | switch (cmd) { |
3237 | case ADV7842_CMD_RAM_TEST: |
3238 | return adv7842_command_ram_test(sd); |
3239 | } |
3240 | return -ENOTTY; |
3241 | } |
3242 | |
3243 | static int adv7842_subscribe_event(struct v4l2_subdev *sd, |
3244 | struct v4l2_fh *fh, |
3245 | struct v4l2_event_subscription *sub) |
3246 | { |
3247 | switch (sub->type) { |
3248 | case V4L2_EVENT_SOURCE_CHANGE: |
3249 | return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); |
3250 | case V4L2_EVENT_CTRL: |
3251 | return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); |
3252 | default: |
3253 | return -EINVAL; |
3254 | } |
3255 | } |
3256 | |
3257 | static int adv7842_registered(struct v4l2_subdev *sd) |
3258 | { |
3259 | struct adv7842_state *state = to_state(sd); |
3260 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
3261 | int err; |
3262 | |
3263 | err = cec_register_adapter(adap: state->cec_adap, parent: &client->dev); |
3264 | if (err) |
3265 | cec_delete_adapter(adap: state->cec_adap); |
3266 | return err; |
3267 | } |
3268 | |
3269 | static void adv7842_unregistered(struct v4l2_subdev *sd) |
3270 | { |
3271 | struct adv7842_state *state = to_state(sd); |
3272 | |
3273 | cec_unregister_adapter(adap: state->cec_adap); |
3274 | } |
3275 | |
3276 | /* ----------------------------------------------------------------------- */ |
3277 | |
3278 | static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { |
3279 | .s_ctrl = adv7842_s_ctrl, |
3280 | .g_volatile_ctrl = adv7842_g_volatile_ctrl, |
3281 | }; |
3282 | |
3283 | static const struct v4l2_subdev_core_ops adv7842_core_ops = { |
3284 | .log_status = adv7842_log_status, |
3285 | .ioctl = adv7842_ioctl, |
3286 | .interrupt_service_routine = adv7842_isr, |
3287 | .subscribe_event = adv7842_subscribe_event, |
3288 | .unsubscribe_event = v4l2_event_subdev_unsubscribe, |
3289 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
3290 | .g_register = adv7842_g_register, |
3291 | .s_register = adv7842_s_register, |
3292 | #endif |
3293 | }; |
3294 | |
3295 | static const struct v4l2_subdev_video_ops adv7842_video_ops = { |
3296 | .g_std = adv7842_g_std, |
3297 | .s_std = adv7842_s_std, |
3298 | .s_routing = adv7842_s_routing, |
3299 | .querystd = adv7842_querystd, |
3300 | .g_input_status = adv7842_g_input_status, |
3301 | .s_dv_timings = adv7842_s_dv_timings, |
3302 | .g_dv_timings = adv7842_g_dv_timings, |
3303 | .query_dv_timings = adv7842_query_dv_timings, |
3304 | }; |
3305 | |
3306 | static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { |
3307 | .enum_mbus_code = adv7842_enum_mbus_code, |
3308 | .get_fmt = adv7842_get_format, |
3309 | .set_fmt = adv7842_set_format, |
3310 | .get_edid = adv7842_get_edid, |
3311 | .set_edid = adv7842_set_edid, |
3312 | .enum_dv_timings = adv7842_enum_dv_timings, |
3313 | .dv_timings_cap = adv7842_dv_timings_cap, |
3314 | }; |
3315 | |
3316 | static const struct v4l2_subdev_ops adv7842_ops = { |
3317 | .core = &adv7842_core_ops, |
3318 | .video = &adv7842_video_ops, |
3319 | .pad = &adv7842_pad_ops, |
3320 | }; |
3321 | |
3322 | static const struct v4l2_subdev_internal_ops adv7842_int_ops = { |
3323 | .registered = adv7842_registered, |
3324 | .unregistered = adv7842_unregistered, |
3325 | }; |
3326 | |
3327 | /* -------------------------- custom ctrls ---------------------------------- */ |
3328 | |
3329 | static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { |
3330 | .ops = &adv7842_ctrl_ops, |
3331 | .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, |
3332 | .name = "Analog Sampling Phase" , |
3333 | .type = V4L2_CTRL_TYPE_INTEGER, |
3334 | .min = 0, |
3335 | .max = 0x1f, |
3336 | .step = 1, |
3337 | .def = 0, |
3338 | }; |
3339 | |
3340 | static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { |
3341 | .ops = &adv7842_ctrl_ops, |
3342 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, |
3343 | .name = "Free Running Color, Manual" , |
3344 | .type = V4L2_CTRL_TYPE_BOOLEAN, |
3345 | .max = 1, |
3346 | .step = 1, |
3347 | .def = 1, |
3348 | }; |
3349 | |
3350 | static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { |
3351 | .ops = &adv7842_ctrl_ops, |
3352 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, |
3353 | .name = "Free Running Color" , |
3354 | .type = V4L2_CTRL_TYPE_INTEGER, |
3355 | .max = 0xffffff, |
3356 | .step = 0x1, |
3357 | }; |
3358 | |
3359 | |
3360 | static void adv7842_unregister_clients(struct v4l2_subdev *sd) |
3361 | { |
3362 | struct adv7842_state *state = to_state(sd); |
3363 | i2c_unregister_device(client: state->i2c_avlink); |
3364 | i2c_unregister_device(client: state->i2c_cec); |
3365 | i2c_unregister_device(client: state->i2c_infoframe); |
3366 | i2c_unregister_device(client: state->i2c_sdp_io); |
3367 | i2c_unregister_device(client: state->i2c_sdp); |
3368 | i2c_unregister_device(client: state->i2c_afe); |
3369 | i2c_unregister_device(client: state->i2c_repeater); |
3370 | i2c_unregister_device(client: state->i2c_edid); |
3371 | i2c_unregister_device(client: state->i2c_hdmi); |
3372 | i2c_unregister_device(client: state->i2c_cp); |
3373 | i2c_unregister_device(client: state->i2c_vdp); |
3374 | |
3375 | state->i2c_avlink = NULL; |
3376 | state->i2c_cec = NULL; |
3377 | state->i2c_infoframe = NULL; |
3378 | state->i2c_sdp_io = NULL; |
3379 | state->i2c_sdp = NULL; |
3380 | state->i2c_afe = NULL; |
3381 | state->i2c_repeater = NULL; |
3382 | state->i2c_edid = NULL; |
3383 | state->i2c_hdmi = NULL; |
3384 | state->i2c_cp = NULL; |
3385 | state->i2c_vdp = NULL; |
3386 | } |
3387 | |
3388 | static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, |
3389 | u8 addr, u8 io_reg) |
3390 | { |
3391 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
3392 | struct i2c_client *cp; |
3393 | |
3394 | io_write(sd, reg: io_reg, val: addr << 1); |
3395 | |
3396 | if (addr == 0) { |
3397 | v4l2_err(sd, "no %s i2c addr configured\n" , desc); |
3398 | return NULL; |
3399 | } |
3400 | |
3401 | cp = i2c_new_dummy_device(adapter: client->adapter, address: io_read(sd, reg: io_reg) >> 1); |
3402 | if (IS_ERR(ptr: cp)) { |
3403 | v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n" , |
3404 | desc, addr, PTR_ERR(cp)); |
3405 | cp = NULL; |
3406 | } |
3407 | |
3408 | return cp; |
3409 | } |
3410 | |
3411 | static int adv7842_register_clients(struct v4l2_subdev *sd) |
3412 | { |
3413 | struct adv7842_state *state = to_state(sd); |
3414 | struct adv7842_platform_data *pdata = &state->pdata; |
3415 | |
3416 | state->i2c_avlink = adv7842_dummy_client(sd, desc: "avlink" , addr: pdata->i2c_avlink, io_reg: 0xf3); |
3417 | state->i2c_cec = adv7842_dummy_client(sd, desc: "cec" , addr: pdata->i2c_cec, io_reg: 0xf4); |
3418 | state->i2c_infoframe = adv7842_dummy_client(sd, desc: "infoframe" , addr: pdata->i2c_infoframe, io_reg: 0xf5); |
3419 | state->i2c_sdp_io = adv7842_dummy_client(sd, desc: "sdp_io" , addr: pdata->i2c_sdp_io, io_reg: 0xf2); |
3420 | state->i2c_sdp = adv7842_dummy_client(sd, desc: "sdp" , addr: pdata->i2c_sdp, io_reg: 0xf1); |
3421 | state->i2c_afe = adv7842_dummy_client(sd, desc: "afe" , addr: pdata->i2c_afe, io_reg: 0xf8); |
3422 | state->i2c_repeater = adv7842_dummy_client(sd, desc: "repeater" , addr: pdata->i2c_repeater, io_reg: 0xf9); |
3423 | state->i2c_edid = adv7842_dummy_client(sd, desc: "edid" , addr: pdata->i2c_edid, io_reg: 0xfa); |
3424 | state->i2c_hdmi = adv7842_dummy_client(sd, desc: "hdmi" , addr: pdata->i2c_hdmi, io_reg: 0xfb); |
3425 | state->i2c_cp = adv7842_dummy_client(sd, desc: "cp" , addr: pdata->i2c_cp, io_reg: 0xfd); |
3426 | state->i2c_vdp = adv7842_dummy_client(sd, desc: "vdp" , addr: pdata->i2c_vdp, io_reg: 0xfe); |
3427 | |
3428 | if (!state->i2c_avlink || |
3429 | !state->i2c_cec || |
3430 | !state->i2c_infoframe || |
3431 | !state->i2c_sdp_io || |
3432 | !state->i2c_sdp || |
3433 | !state->i2c_afe || |
3434 | !state->i2c_repeater || |
3435 | !state->i2c_edid || |
3436 | !state->i2c_hdmi || |
3437 | !state->i2c_cp || |
3438 | !state->i2c_vdp) |
3439 | return -1; |
3440 | |
3441 | return 0; |
3442 | } |
3443 | |
3444 | static int adv7842_probe(struct i2c_client *client) |
3445 | { |
3446 | struct adv7842_state *state; |
3447 | static const struct v4l2_dv_timings cea640x480 = |
3448 | V4L2_DV_BT_CEA_640X480P59_94; |
3449 | struct adv7842_platform_data *pdata = client->dev.platform_data; |
3450 | struct v4l2_ctrl_handler *hdl; |
3451 | struct v4l2_ctrl *ctrl; |
3452 | struct v4l2_subdev *sd; |
3453 | unsigned int i; |
3454 | u16 rev; |
3455 | int err; |
3456 | |
3457 | /* Check if the adapter supports the needed features */ |
3458 | if (!i2c_check_functionality(adap: client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) |
3459 | return -EIO; |
3460 | |
3461 | v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n" , |
3462 | client->addr << 1); |
3463 | |
3464 | if (!pdata) { |
3465 | v4l_err(client, "No platform data!\n" ); |
3466 | return -ENODEV; |
3467 | } |
3468 | |
3469 | state = devm_kzalloc(dev: &client->dev, size: sizeof(*state), GFP_KERNEL); |
3470 | if (!state) |
3471 | return -ENOMEM; |
3472 | |
3473 | /* platform data */ |
3474 | state->pdata = *pdata; |
3475 | state->timings = cea640x480; |
3476 | state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); |
3477 | |
3478 | sd = &state->sd; |
3479 | v4l2_i2c_subdev_init(sd, client, ops: &adv7842_ops); |
3480 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; |
3481 | sd->internal_ops = &adv7842_int_ops; |
3482 | state->mode = pdata->mode; |
3483 | |
3484 | state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; |
3485 | state->restart_stdi_once = true; |
3486 | |
3487 | /* i2c access to adv7842? */ |
3488 | rev = adv_smbus_read_byte_data_check(client, command: 0xea, check: false) << 8 | |
3489 | adv_smbus_read_byte_data_check(client, command: 0xeb, check: false); |
3490 | if (rev != 0x2012) { |
3491 | v4l2_info(sd, "got rev=0x%04x on first read attempt\n" , rev); |
3492 | rev = adv_smbus_read_byte_data_check(client, command: 0xea, check: false) << 8 | |
3493 | adv_smbus_read_byte_data_check(client, command: 0xeb, check: false); |
3494 | } |
3495 | if (rev != 0x2012) { |
3496 | v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n" , |
3497 | client->addr << 1, rev); |
3498 | return -ENODEV; |
3499 | } |
3500 | |
3501 | if (pdata->chip_reset) |
3502 | main_reset(sd); |
3503 | |
3504 | /* control handlers */ |
3505 | hdl = &state->hdl; |
3506 | v4l2_ctrl_handler_init(hdl, 6); |
3507 | |
3508 | /* add in ascending ID order */ |
3509 | v4l2_ctrl_new_std(hdl, ops: &adv7842_ctrl_ops, |
3510 | V4L2_CID_BRIGHTNESS, min: -128, max: 127, step: 1, def: 0); |
3511 | v4l2_ctrl_new_std(hdl, ops: &adv7842_ctrl_ops, |
3512 | V4L2_CID_CONTRAST, min: 0, max: 255, step: 1, def: 128); |
3513 | v4l2_ctrl_new_std(hdl, ops: &adv7842_ctrl_ops, |
3514 | V4L2_CID_SATURATION, min: 0, max: 255, step: 1, def: 128); |
3515 | v4l2_ctrl_new_std(hdl, ops: &adv7842_ctrl_ops, |
3516 | V4L2_CID_HUE, min: 0, max: 128, step: 1, def: 0); |
3517 | ctrl = v4l2_ctrl_new_std_menu(hdl, ops: &adv7842_ctrl_ops, |
3518 | V4L2_CID_DV_RX_IT_CONTENT_TYPE, max: V4L2_DV_IT_CONTENT_TYPE_NO_ITC, |
3519 | mask: 0, def: V4L2_DV_IT_CONTENT_TYPE_NO_ITC); |
3520 | if (ctrl) |
3521 | ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; |
3522 | |
3523 | /* custom controls */ |
3524 | state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, |
3525 | V4L2_CID_DV_RX_POWER_PRESENT, min: 0, max: 3, step: 0, def: 0); |
3526 | state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, |
3527 | cfg: &adv7842_ctrl_analog_sampling_phase, NULL); |
3528 | state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, |
3529 | cfg: &adv7842_ctrl_free_run_color_manual, NULL); |
3530 | state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, |
3531 | cfg: &adv7842_ctrl_free_run_color, NULL); |
3532 | state->rgb_quantization_range_ctrl = |
3533 | v4l2_ctrl_new_std_menu(hdl, ops: &adv7842_ctrl_ops, |
3534 | V4L2_CID_DV_RX_RGB_RANGE, max: V4L2_DV_RGB_RANGE_FULL, |
3535 | mask: 0, def: V4L2_DV_RGB_RANGE_AUTO); |
3536 | sd->ctrl_handler = hdl; |
3537 | if (hdl->error) { |
3538 | err = hdl->error; |
3539 | goto err_hdl; |
3540 | } |
3541 | if (adv7842_s_detect_tx_5v_ctrl(sd)) { |
3542 | err = -ENODEV; |
3543 | goto err_hdl; |
3544 | } |
3545 | |
3546 | if (adv7842_register_clients(sd) < 0) { |
3547 | err = -ENOMEM; |
3548 | v4l2_err(sd, "failed to create all i2c clients\n" ); |
3549 | goto err_i2c; |
3550 | } |
3551 | |
3552 | |
3553 | INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, |
3554 | adv7842_delayed_work_enable_hotplug); |
3555 | |
3556 | sd->entity.function = MEDIA_ENT_F_DV_DECODER; |
3557 | for (i = 0; i < ADV7842_PAD_SOURCE; ++i) |
3558 | state->pads[i].flags = MEDIA_PAD_FL_SINK; |
3559 | state->pads[ADV7842_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; |
3560 | err = media_entity_pads_init(entity: &sd->entity, ADV7842_PAD_SOURCE + 1, |
3561 | pads: state->pads); |
3562 | if (err) |
3563 | goto err_work_queues; |
3564 | |
3565 | err = adv7842_core_init(sd); |
3566 | if (err) |
3567 | goto err_entity; |
3568 | |
3569 | #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) |
3570 | state->cec_adap = cec_allocate_adapter(ops: &adv7842_cec_adap_ops, |
3571 | priv: state, name: dev_name(dev: &client->dev), |
3572 | CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS); |
3573 | err = PTR_ERR_OR_ZERO(ptr: state->cec_adap); |
3574 | if (err) |
3575 | goto err_entity; |
3576 | #endif |
3577 | |
3578 | v4l2_info(sd, "%s found @ 0x%x (%s)\n" , client->name, |
3579 | client->addr << 1, client->adapter->name); |
3580 | return 0; |
3581 | |
3582 | err_entity: |
3583 | media_entity_cleanup(entity: &sd->entity); |
3584 | err_work_queues: |
3585 | cancel_delayed_work(dwork: &state->delayed_work_enable_hotplug); |
3586 | err_i2c: |
3587 | adv7842_unregister_clients(sd); |
3588 | err_hdl: |
3589 | v4l2_ctrl_handler_free(hdl); |
3590 | return err; |
3591 | } |
3592 | |
3593 | /* ----------------------------------------------------------------------- */ |
3594 | |
3595 | static void adv7842_remove(struct i2c_client *client) |
3596 | { |
3597 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
3598 | struct adv7842_state *state = to_state(sd); |
3599 | |
3600 | adv7842_irq_enable(sd, enable: false); |
3601 | cancel_delayed_work_sync(dwork: &state->delayed_work_enable_hotplug); |
3602 | v4l2_device_unregister_subdev(sd); |
3603 | media_entity_cleanup(entity: &sd->entity); |
3604 | adv7842_unregister_clients(sd); |
3605 | v4l2_ctrl_handler_free(hdl: sd->ctrl_handler); |
3606 | } |
3607 | |
3608 | /* ----------------------------------------------------------------------- */ |
3609 | |
3610 | static const struct i2c_device_id adv7842_id[] = { |
3611 | { "adv7842" , 0 }, |
3612 | { } |
3613 | }; |
3614 | MODULE_DEVICE_TABLE(i2c, adv7842_id); |
3615 | |
3616 | /* ----------------------------------------------------------------------- */ |
3617 | |
3618 | static struct i2c_driver adv7842_driver = { |
3619 | .driver = { |
3620 | .name = "adv7842" , |
3621 | }, |
3622 | .probe = adv7842_probe, |
3623 | .remove = adv7842_remove, |
3624 | .id_table = adv7842_id, |
3625 | }; |
3626 | |
3627 | module_i2c_driver(adv7842_driver); |
3628 | |