1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Allied Vision Technologies GmbH Alvium camera driver |
4 | * |
5 | * Copyright (C) 2023 Tommaso Merciai |
6 | * Copyright (C) 2023 Martin Hecht |
7 | * Copyright (C) 2023 Avnet EMG GmbH |
8 | */ |
9 | |
10 | #include <linux/i2c.h> |
11 | #include <linux/module.h> |
12 | #include <linux/pm_runtime.h> |
13 | #include <linux/regmap.h> |
14 | #include <linux/regulator/consumer.h> |
15 | #include <media/mipi-csi2.h> |
16 | #include <media/v4l2-async.h> |
17 | #include <media/v4l2-ctrls.h> |
18 | #include <media/v4l2-device.h> |
19 | #include <media/v4l2-event.h> |
20 | #include <media/v4l2-fwnode.h> |
21 | #include <media/v4l2-subdev.h> |
22 | |
23 | #include "alvium-csi2.h" |
24 | |
25 | static const struct v4l2_mbus_framefmt alvium_csi2_default_fmt = { |
26 | .code = MEDIA_BUS_FMT_UYVY8_1X16, |
27 | .width = 640, |
28 | .height = 480, |
29 | .colorspace = V4L2_COLORSPACE_SRGB, |
30 | .ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(V4L2_COLORSPACE_SRGB), |
31 | .quantization = V4L2_QUANTIZATION_FULL_RANGE, |
32 | .xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(V4L2_COLORSPACE_SRGB), |
33 | .field = V4L2_FIELD_NONE, |
34 | }; |
35 | |
36 | static const struct alvium_pixfmt alvium_csi2_fmts[] = { |
37 | { |
38 | /* UYVY8_2X8 */ |
39 | .id = ALVIUM_FMT_UYVY8_2X8, |
40 | .code = MEDIA_BUS_FMT_UYVY8_2X8, |
41 | .colorspace = V4L2_COLORSPACE_SRGB, |
42 | .fmt_av_bit = ALVIUM_BIT_YUV422_8, |
43 | .bay_av_bit = ALVIUM_BIT_BAY_NONE, |
44 | .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B, |
45 | .bay_fmt_regval = -1, |
46 | .is_raw = 0, |
47 | }, { |
48 | /* UYVY8_1X16 */ |
49 | .id = ALVIUM_FMT_UYVY8_1X16, |
50 | .code = MEDIA_BUS_FMT_UYVY8_1X16, |
51 | .colorspace = V4L2_COLORSPACE_SRGB, |
52 | .fmt_av_bit = ALVIUM_BIT_YUV422_8, |
53 | .bay_av_bit = ALVIUM_BIT_BAY_NONE, |
54 | .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B, |
55 | .bay_fmt_regval = -1, |
56 | .is_raw = 0, |
57 | }, { |
58 | /* YUYV8_1X16 */ |
59 | .id = ALVIUM_FMT_YUYV8_1X16, |
60 | .code = MEDIA_BUS_FMT_YUYV8_1X16, |
61 | .colorspace = V4L2_COLORSPACE_SRGB, |
62 | .fmt_av_bit = ALVIUM_BIT_YUV422_8, |
63 | .bay_av_bit = ALVIUM_BIT_BAY_NONE, |
64 | .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B, |
65 | .bay_fmt_regval = -1, |
66 | .is_raw = 0, |
67 | }, { |
68 | /* YUYV8_2X8 */ |
69 | .id = ALVIUM_FMT_YUYV8_2X8, |
70 | .code = MEDIA_BUS_FMT_YUYV8_2X8, |
71 | .colorspace = V4L2_COLORSPACE_SRGB, |
72 | .fmt_av_bit = ALVIUM_BIT_YUV422_8, |
73 | .bay_av_bit = ALVIUM_BIT_BAY_NONE, |
74 | .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B, |
75 | .bay_fmt_regval = -1, |
76 | .is_raw = 0, |
77 | }, { |
78 | /* YUYV10_1X20 */ |
79 | .id = ALVIUM_FMT_YUYV10_1X20, |
80 | .code = MEDIA_BUS_FMT_YUYV10_1X20, |
81 | .colorspace = V4L2_COLORSPACE_SRGB, |
82 | .fmt_av_bit = ALVIUM_BIT_YUV422_10, |
83 | .bay_av_bit = ALVIUM_BIT_BAY_NONE, |
84 | .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_10B, |
85 | .bay_fmt_regval = -1, |
86 | .is_raw = 0, |
87 | }, { |
88 | /* RGB888_1X24 */ |
89 | .id = ALVIUM_FMT_RGB888_1X24, |
90 | .code = MEDIA_BUS_FMT_RGB888_1X24, |
91 | .colorspace = V4L2_COLORSPACE_SRGB, |
92 | .fmt_av_bit = ALVIUM_BIT_RGB888, |
93 | .bay_av_bit = ALVIUM_BIT_BAY_NONE, |
94 | .mipi_fmt_regval = MIPI_CSI2_DT_RGB888, |
95 | .bay_fmt_regval = -1, |
96 | .is_raw = 0, |
97 | }, { |
98 | /* RBG888_1X24 */ |
99 | .id = ALVIUM_FMT_RBG888_1X24, |
100 | .code = MEDIA_BUS_FMT_RBG888_1X24, |
101 | .colorspace = V4L2_COLORSPACE_SRGB, |
102 | .fmt_av_bit = ALVIUM_BIT_RGB888, |
103 | .bay_av_bit = ALVIUM_BIT_BAY_NONE, |
104 | .mipi_fmt_regval = MIPI_CSI2_DT_RGB888, |
105 | .bay_fmt_regval = -1, |
106 | .is_raw = 0, |
107 | }, { |
108 | /* BGR888_1X24 */ |
109 | .id = ALVIUM_FMT_BGR888_1X24, |
110 | .code = MEDIA_BUS_FMT_BGR888_1X24, |
111 | .colorspace = V4L2_COLORSPACE_SRGB, |
112 | .fmt_av_bit = ALVIUM_BIT_RGB888, |
113 | .bay_av_bit = ALVIUM_BIT_BAY_NONE, |
114 | .mipi_fmt_regval = MIPI_CSI2_DT_RGB888, |
115 | .bay_fmt_regval = -1, |
116 | .is_raw = 0, |
117 | }, { |
118 | /* RGB888_3X8 */ |
119 | .id = ALVIUM_FMT_RGB888_3X8, |
120 | .code = MEDIA_BUS_FMT_RGB888_3X8, |
121 | .colorspace = V4L2_COLORSPACE_SRGB, |
122 | .fmt_av_bit = ALVIUM_BIT_RGB888, |
123 | .bay_av_bit = ALVIUM_BIT_BAY_NONE, |
124 | .mipi_fmt_regval = MIPI_CSI2_DT_RGB888, |
125 | .bay_fmt_regval = -1, |
126 | .is_raw = 0, |
127 | }, { |
128 | /* Y8_1X8 */ |
129 | .id = ALVIUM_FMT_Y8_1X8, |
130 | .code = MEDIA_BUS_FMT_Y8_1X8, |
131 | .colorspace = V4L2_COLORSPACE_RAW, |
132 | .fmt_av_bit = ALVIUM_BIT_RAW8, |
133 | .bay_av_bit = ALVIUM_BIT_BAY_MONO, |
134 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW8, |
135 | .bay_fmt_regval = 0x00, |
136 | .is_raw = 1, |
137 | }, { |
138 | /* SGRBG8_1X8 */ |
139 | .id = ALVIUM_FMT_SGRBG8_1X8, |
140 | .code = MEDIA_BUS_FMT_SGRBG8_1X8, |
141 | .colorspace = V4L2_COLORSPACE_RAW, |
142 | .fmt_av_bit = ALVIUM_BIT_RAW8, |
143 | .bay_av_bit = ALVIUM_BIT_BAY_GR, |
144 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW8, |
145 | .bay_fmt_regval = 0x01, |
146 | .is_raw = 1, |
147 | }, { |
148 | /* SRGGB8_1X8 */ |
149 | .id = ALVIUM_FMT_SRGGB8_1X8, |
150 | .code = MEDIA_BUS_FMT_SRGGB8_1X8, |
151 | .colorspace = V4L2_COLORSPACE_RAW, |
152 | .fmt_av_bit = ALVIUM_BIT_RAW8, |
153 | .bay_av_bit = ALVIUM_BIT_BAY_RG, |
154 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW8, |
155 | .bay_fmt_regval = 0x02, |
156 | .is_raw = 1, |
157 | }, { |
158 | /* SGBRG8_1X8 */ |
159 | .id = ALVIUM_FMT_SGBRG8_1X8, |
160 | .code = MEDIA_BUS_FMT_SGBRG8_1X8, |
161 | .colorspace = V4L2_COLORSPACE_RAW, |
162 | .fmt_av_bit = ALVIUM_BIT_RAW8, |
163 | .bay_av_bit = ALVIUM_BIT_BAY_GB, |
164 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW8, |
165 | .bay_fmt_regval = 0x03, |
166 | .is_raw = 1, |
167 | }, { |
168 | /* SBGGR8_1X8 */ |
169 | .id = ALVIUM_FMT_SBGGR8_1X8, |
170 | .code = MEDIA_BUS_FMT_SBGGR8_1X8, |
171 | .colorspace = V4L2_COLORSPACE_RAW, |
172 | .fmt_av_bit = ALVIUM_BIT_RAW8, |
173 | .bay_av_bit = ALVIUM_BIT_BAY_BG, |
174 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW8, |
175 | .bay_fmt_regval = 0x04, |
176 | .is_raw = 1, |
177 | }, { |
178 | /* Y10_1X10 */ |
179 | .id = ALVIUM_FMT_Y10_1X10, |
180 | .code = MEDIA_BUS_FMT_Y10_1X10, |
181 | .colorspace = V4L2_COLORSPACE_RAW, |
182 | .fmt_av_bit = ALVIUM_BIT_RAW10, |
183 | .bay_av_bit = ALVIUM_BIT_BAY_MONO, |
184 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW10, |
185 | .bay_fmt_regval = 0x00, |
186 | .is_raw = 1, |
187 | }, { |
188 | /* SGRBG10_1X10 */ |
189 | .id = ALVIUM_FMT_SGRBG10_1X10, |
190 | .code = MEDIA_BUS_FMT_SGRBG10_1X10, |
191 | .colorspace = V4L2_COLORSPACE_RAW, |
192 | .fmt_av_bit = ALVIUM_BIT_RAW10, |
193 | .bay_av_bit = ALVIUM_BIT_BAY_GR, |
194 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW10, |
195 | .bay_fmt_regval = 0x01, |
196 | .is_raw = 1, |
197 | }, { |
198 | /* SRGGB10_1X10 */ |
199 | .id = ALVIUM_FMT_SRGGB10_1X10, |
200 | .code = MEDIA_BUS_FMT_SRGGB10_1X10, |
201 | .colorspace = V4L2_COLORSPACE_RAW, |
202 | .fmt_av_bit = ALVIUM_BIT_RAW10, |
203 | .bay_av_bit = ALVIUM_BIT_BAY_RG, |
204 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW10, |
205 | .bay_fmt_regval = 0x02, |
206 | .is_raw = 1, |
207 | }, { |
208 | /* SGBRG10_1X10 */ |
209 | .id = ALVIUM_FMT_SGBRG10_1X10, |
210 | .code = MEDIA_BUS_FMT_SGBRG10_1X10, |
211 | .colorspace = V4L2_COLORSPACE_RAW, |
212 | .fmt_av_bit = ALVIUM_BIT_RAW10, |
213 | .bay_av_bit = ALVIUM_BIT_BAY_GB, |
214 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW10, |
215 | .bay_fmt_regval = 0x03, |
216 | .is_raw = 1, |
217 | }, { |
218 | /* SBGGR10_1X10 */ |
219 | .id = ALVIUM_FMT_SBGGR10_1X10, |
220 | .code = MEDIA_BUS_FMT_SBGGR10_1X10, |
221 | .colorspace = V4L2_COLORSPACE_RAW, |
222 | .fmt_av_bit = ALVIUM_BIT_RAW10, |
223 | .bay_av_bit = ALVIUM_BIT_BAY_BG, |
224 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW10, |
225 | .bay_fmt_regval = 0x04, |
226 | .is_raw = 1, |
227 | }, { |
228 | /* Y12_1X12 */ |
229 | .id = ALVIUM_FMT_Y12_1X12, |
230 | .code = MEDIA_BUS_FMT_Y12_1X12, |
231 | .colorspace = V4L2_COLORSPACE_RAW, |
232 | .fmt_av_bit = ALVIUM_BIT_RAW12, |
233 | .bay_av_bit = ALVIUM_BIT_BAY_MONO, |
234 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW12, |
235 | .bay_fmt_regval = 0x00, |
236 | .is_raw = 1, |
237 | }, { |
238 | /* SGRBG12_1X12 */ |
239 | .id = ALVIUM_FMT_SGRBG12_1X12, |
240 | .code = MEDIA_BUS_FMT_SGRBG12_1X12, |
241 | .colorspace = V4L2_COLORSPACE_RAW, |
242 | .fmt_av_bit = ALVIUM_BIT_RAW12, |
243 | .bay_av_bit = ALVIUM_BIT_BAY_GR, |
244 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW12, |
245 | .bay_fmt_regval = 0x01, |
246 | .is_raw = 1, |
247 | }, { |
248 | /* SRGGB12_1X12 */ |
249 | .id = ALVIUM_FMT_SRGGB12_1X12, |
250 | .code = MEDIA_BUS_FMT_SRGGB12_1X12, |
251 | .colorspace = V4L2_COLORSPACE_RAW, |
252 | .fmt_av_bit = ALVIUM_BIT_RAW12, |
253 | .bay_av_bit = ALVIUM_BIT_BAY_RG, |
254 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW12, |
255 | .bay_fmt_regval = 0x02, |
256 | .is_raw = 1, |
257 | }, { |
258 | /* SGBRG12_1X12 */ |
259 | .id = ALVIUM_FMT_SGBRG12_1X12, |
260 | .code = MEDIA_BUS_FMT_SGBRG12_1X12, |
261 | .colorspace = V4L2_COLORSPACE_RAW, |
262 | .fmt_av_bit = ALVIUM_BIT_RAW12, |
263 | .bay_av_bit = ALVIUM_BIT_BAY_GB, |
264 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW12, |
265 | .bay_fmt_regval = 0x03, |
266 | .is_raw = 1, |
267 | }, { |
268 | /* SBGGR12_1X12 */ |
269 | .id = ALVIUM_FMT_SBGGR12_1X12, |
270 | .code = MEDIA_BUS_FMT_SBGGR12_1X12, |
271 | .colorspace = V4L2_COLORSPACE_RAW, |
272 | .fmt_av_bit = ALVIUM_BIT_RAW12, |
273 | .bay_av_bit = ALVIUM_BIT_BAY_BG, |
274 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW12, |
275 | .bay_fmt_regval = 0x04, |
276 | .is_raw = 1, |
277 | }, { |
278 | /* SBGGR14_1X14 */ |
279 | .id = ALVIUM_FMT_SBGGR14_1X14, |
280 | .code = MEDIA_BUS_FMT_SBGGR14_1X14, |
281 | .colorspace = V4L2_COLORSPACE_RAW, |
282 | .fmt_av_bit = ALVIUM_BIT_RAW14, |
283 | .bay_av_bit = ALVIUM_BIT_BAY_GR, |
284 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW14, |
285 | .bay_fmt_regval = 0x01, |
286 | .is_raw = 1, |
287 | }, { |
288 | /* SGBRG14_1X14 */ |
289 | .id = ALVIUM_FMT_SGBRG14_1X14, |
290 | .code = MEDIA_BUS_FMT_SGBRG14_1X14, |
291 | .colorspace = V4L2_COLORSPACE_RAW, |
292 | .fmt_av_bit = ALVIUM_BIT_RAW14, |
293 | .bay_av_bit = ALVIUM_BIT_BAY_RG, |
294 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW14, |
295 | .bay_fmt_regval = 0x02, |
296 | .is_raw = 1, |
297 | }, { |
298 | /* SRGGB14_1X14 */ |
299 | .id = ALVIUM_FMT_SRGGB14_1X14, |
300 | .code = MEDIA_BUS_FMT_SRGGB14_1X14, |
301 | .colorspace = V4L2_COLORSPACE_RAW, |
302 | .fmt_av_bit = ALVIUM_BIT_RAW14, |
303 | .bay_av_bit = ALVIUM_BIT_BAY_GB, |
304 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW14, |
305 | .bay_fmt_regval = 0x03, |
306 | .is_raw = 1, |
307 | }, { |
308 | /* SGRBG14_1X14 */ |
309 | .id = ALVIUM_FMT_SGRBG14_1X14, |
310 | .code = MEDIA_BUS_FMT_SGRBG14_1X14, |
311 | .colorspace = V4L2_COLORSPACE_RAW, |
312 | .fmt_av_bit = ALVIUM_BIT_RAW14, |
313 | .bay_av_bit = ALVIUM_BIT_BAY_BG, |
314 | .mipi_fmt_regval = MIPI_CSI2_DT_RAW14, |
315 | .bay_fmt_regval = 0x04, |
316 | .is_raw = 1, |
317 | }, |
318 | { /* sentinel */ } |
319 | }; |
320 | |
321 | static int alvium_read(struct alvium_dev *alvium, u32 reg, u64 *val, int *err) |
322 | { |
323 | if (reg & REG_BCRM_V4L2) { |
324 | reg &= ~REG_BCRM_V4L2; |
325 | reg += alvium->bcrm_addr; |
326 | } |
327 | |
328 | return cci_read(map: alvium->regmap, reg, val, err); |
329 | } |
330 | |
331 | static int alvium_write(struct alvium_dev *alvium, u32 reg, u64 val, int *err) |
332 | { |
333 | if (reg & REG_BCRM_V4L2) { |
334 | reg &= ~REG_BCRM_V4L2; |
335 | reg += alvium->bcrm_addr; |
336 | } |
337 | |
338 | return cci_write(map: alvium->regmap, reg, val, err); |
339 | } |
340 | |
341 | static int alvium_write_hshake(struct alvium_dev *alvium, u32 reg, u64 val) |
342 | { |
343 | struct device *dev = &alvium->i2c_client->dev; |
344 | u64 hshake_bit; |
345 | int ret = 0; |
346 | |
347 | /* reset handshake bit and write alvium reg */ |
348 | alvium_write(alvium, REG_BCRM_WRITE_HANDSHAKE_RW, val: 0, err: &ret); |
349 | alvium_write(alvium, reg, val, err: &ret); |
350 | if (ret) { |
351 | dev_err(dev, "Fail to write reg\n" ); |
352 | return ret; |
353 | } |
354 | |
355 | /* poll handshake bit since bit0 = 1 */ |
356 | read_poll_timeout(alvium_read, hshake_bit, |
357 | ((hshake_bit & BCRM_HANDSHAKE_W_DONE_EN_BIT) == 1), |
358 | 15000, 45000, true, |
359 | alvium, REG_BCRM_WRITE_HANDSHAKE_RW, |
360 | &hshake_bit, &ret); |
361 | if (ret) { |
362 | dev_err(dev, "poll bit[0] = 1, hshake reg fail\n" ); |
363 | return ret; |
364 | } |
365 | |
366 | /* reset handshake bit, write 0 to bit0 */ |
367 | alvium_write(alvium, REG_BCRM_WRITE_HANDSHAKE_RW, val: 0, err: &ret); |
368 | if (ret) { |
369 | dev_err(dev, "Fail to reset hshake reg\n" ); |
370 | return ret; |
371 | } |
372 | |
373 | /* poll handshake bit since bit0 = 0 */ |
374 | read_poll_timeout(alvium_read, hshake_bit, |
375 | ((hshake_bit & BCRM_HANDSHAKE_W_DONE_EN_BIT) == 0), |
376 | 15000, 45000, true, |
377 | alvium, REG_BCRM_WRITE_HANDSHAKE_RW, |
378 | &hshake_bit, &ret); |
379 | if (ret) { |
380 | dev_err(dev, "poll bit[0] = 0, hshake reg fail\n" ); |
381 | return ret; |
382 | } |
383 | |
384 | return 0; |
385 | } |
386 | |
387 | static int alvium_get_bcrm_vers(struct alvium_dev *alvium) |
388 | { |
389 | struct device *dev = &alvium->i2c_client->dev; |
390 | u64 min, maj; |
391 | int ret = 0; |
392 | |
393 | ret = alvium_read(alvium, REG_BCRM_MINOR_VERSION_R, val: &min, err: &ret); |
394 | ret = alvium_read(alvium, REG_BCRM_MAJOR_VERSION_R, val: &maj, err: &ret); |
395 | if (ret) |
396 | return ret; |
397 | |
398 | dev_info(dev, "bcrm version: %llu.%llu\n" , min, maj); |
399 | |
400 | return 0; |
401 | } |
402 | |
403 | static int alvium_get_fw_version(struct alvium_dev *alvium) |
404 | { |
405 | struct device *dev = &alvium->i2c_client->dev; |
406 | u64 spec, maj, min, pat; |
407 | int ret = 0; |
408 | |
409 | ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_SPEC_VERSION_R, |
410 | val: &spec, err: &ret); |
411 | ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_MAJOR_VERSION_R, |
412 | val: &maj, err: &ret); |
413 | ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_MINOR_VERSION_R, |
414 | val: &min, err: &ret); |
415 | ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_PATCH_VERSION_R, |
416 | val: &pat, err: &ret); |
417 | if (ret) |
418 | return ret; |
419 | |
420 | dev_info(dev, "fw version: %llu.%llu.%llu.%llu\n" , spec, maj, min, pat); |
421 | |
422 | return 0; |
423 | } |
424 | |
425 | static int alvium_get_bcrm_addr(struct alvium_dev *alvium) |
426 | { |
427 | u64 val; |
428 | int ret; |
429 | |
430 | ret = alvium_read(alvium, REG_BCRM_REG_ADDR_R, val: &val, NULL); |
431 | if (ret) |
432 | return ret; |
433 | |
434 | alvium->bcrm_addr = val; |
435 | |
436 | return 0; |
437 | } |
438 | |
439 | static int alvium_is_alive(struct alvium_dev *alvium) |
440 | { |
441 | u64 bcrm, hbeat; |
442 | int ret = 0; |
443 | |
444 | alvium_read(alvium, REG_BCRM_MINOR_VERSION_R, val: &bcrm, err: &ret); |
445 | alvium_read(alvium, REG_BCRM_HEARTBEAT_RW, val: &hbeat, err: &ret); |
446 | if (ret) |
447 | return ret; |
448 | |
449 | return hbeat; |
450 | } |
451 | |
452 | static void alvium_print_avail_mipi_fmt(struct alvium_dev *alvium) |
453 | { |
454 | struct device *dev = &alvium->i2c_client->dev; |
455 | |
456 | dev_dbg(dev, "avail mipi_fmt yuv420_8_leg: %u\n" , |
457 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_LEG]); |
458 | dev_dbg(dev, "avail mipi_fmt yuv420_8: %u\n" , |
459 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8]); |
460 | dev_dbg(dev, "avail mipi_fmt yuv420_10: %u\n" , |
461 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10]); |
462 | dev_dbg(dev, "avail mipi_fmt yuv420_8_csps: %u\n" , |
463 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_CSPS]); |
464 | dev_dbg(dev, "avail mipi_fmt yuv420_10_csps: %u\n" , |
465 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10_CSPS]); |
466 | dev_dbg(dev, "avail mipi_fmt yuv422_8: %u\n" , |
467 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV422_8]); |
468 | dev_dbg(dev, "avail mipi_fmt yuv422_10: %u\n" , |
469 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV422_10]); |
470 | dev_dbg(dev, "avail mipi_fmt rgb888: %u\n" , |
471 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB888]); |
472 | dev_dbg(dev, "avail mipi_fmt rgb666: %u\n" , |
473 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB666]); |
474 | dev_dbg(dev, "avail mipi_fmt rgb565: %u\n" , |
475 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB565]); |
476 | dev_dbg(dev, "avail mipi_fmt rgb555: %u\n" , |
477 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB555]); |
478 | dev_dbg(dev, "avail mipi_fmt rgb444: %u\n" , |
479 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB444]); |
480 | dev_dbg(dev, "avail mipi_fmt raw6: %u\n" , |
481 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW6]); |
482 | dev_dbg(dev, "avail mipi_fmt raw7: %u\n" , |
483 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW7]); |
484 | dev_dbg(dev, "avail mipi_fmt raw8: %u\n" , |
485 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW8]); |
486 | dev_dbg(dev, "avail mipi_fmt raw10: %u\n" , |
487 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW10]); |
488 | dev_dbg(dev, "avail mipi_fmt raw12: %u\n" , |
489 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW12]); |
490 | dev_dbg(dev, "avail mipi_fmt raw14: %u\n" , |
491 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW14]); |
492 | dev_dbg(dev, "avail mipi_fmt jpeg: %u\n" , |
493 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_JPEG]); |
494 | } |
495 | |
496 | static void alvium_print_avail_feat(struct alvium_dev *alvium) |
497 | { |
498 | struct device *dev = &alvium->i2c_client->dev; |
499 | |
500 | dev_dbg(dev, "feature rev_x: %u\n" , alvium->avail_ft.rev_x); |
501 | dev_dbg(dev, "feature rev_y: %u\n" , alvium->avail_ft.rev_y); |
502 | dev_dbg(dev, "feature int_autop: %u\n" , alvium->avail_ft.int_autop); |
503 | dev_dbg(dev, "feature black_lvl: %u\n" , alvium->avail_ft.black_lvl); |
504 | dev_dbg(dev, "feature gain: %u\n" , alvium->avail_ft.gain); |
505 | dev_dbg(dev, "feature gamma: %u\n" , alvium->avail_ft.gamma); |
506 | dev_dbg(dev, "feature contrast: %u\n" , alvium->avail_ft.contrast); |
507 | dev_dbg(dev, "feature sat: %u\n" , alvium->avail_ft.sat); |
508 | dev_dbg(dev, "feature hue: %u\n" , alvium->avail_ft.hue); |
509 | dev_dbg(dev, "feature whiteb: %u\n" , alvium->avail_ft.whiteb); |
510 | dev_dbg(dev, "feature sharp: %u\n" , alvium->avail_ft.sharp); |
511 | dev_dbg(dev, "feature auto_exp: %u\n" , alvium->avail_ft.auto_exp); |
512 | dev_dbg(dev, "feature auto_gain: %u\n" , alvium->avail_ft.auto_gain); |
513 | dev_dbg(dev, "feature auto_whiteb: %u\n" , alvium->avail_ft.auto_whiteb); |
514 | dev_dbg(dev, "feature dev_temp: %u\n" , alvium->avail_ft.dev_temp); |
515 | dev_dbg(dev, "feature acq_abort: %u\n" , alvium->avail_ft.acq_abort); |
516 | dev_dbg(dev, "feature acq_fr: %u\n" , alvium->avail_ft.acq_fr); |
517 | dev_dbg(dev, "feature fr_trigger: %u\n" , alvium->avail_ft.fr_trigger); |
518 | dev_dbg(dev, "feature exp_acq_line: %u\n" , |
519 | alvium->avail_ft.exp_acq_line); |
520 | } |
521 | |
522 | static void alvium_print_avail_bayer(struct alvium_dev *alvium) |
523 | { |
524 | struct device *dev = &alvium->i2c_client->dev; |
525 | |
526 | dev_dbg(dev, "avail bayer mono: %u\n" , |
527 | alvium->is_bay_avail[ALVIUM_BIT_BAY_MONO]); |
528 | dev_dbg(dev, "avail bayer gr: %u\n" , |
529 | alvium->is_bay_avail[ALVIUM_BIT_BAY_GR]); |
530 | dev_dbg(dev, "avail bayer rg: %u\n" , |
531 | alvium->is_bay_avail[ALVIUM_BIT_BAY_RG]); |
532 | dev_dbg(dev, "avail bayer gb: %u\n" , |
533 | alvium->is_bay_avail[ALVIUM_BIT_BAY_GB]); |
534 | dev_dbg(dev, "avail bayer bg: %u\n" , |
535 | alvium->is_bay_avail[ALVIUM_BIT_BAY_BG]); |
536 | } |
537 | |
538 | static int alvium_get_feat_inq(struct alvium_dev *alvium) |
539 | { |
540 | struct alvium_avail_feat *f; |
541 | u64 val; |
542 | int ret; |
543 | |
544 | ret = alvium_read(alvium, REG_BCRM_FEATURE_INQUIRY_R, val: &val, NULL); |
545 | if (ret) |
546 | return ret; |
547 | |
548 | f = (struct alvium_avail_feat *)&val; |
549 | alvium->avail_ft = *f; |
550 | alvium_print_avail_feat(alvium); |
551 | |
552 | return 0; |
553 | } |
554 | |
555 | static int alvium_get_host_supp_csi_lanes(struct alvium_dev *alvium) |
556 | { |
557 | u64 val; |
558 | int ret; |
559 | |
560 | ret = alvium_read(alvium, REG_BCRM_CSI2_LANE_COUNT_RW, val: &val, NULL); |
561 | if (ret) |
562 | return ret; |
563 | |
564 | alvium->h_sup_csi_lanes = val; |
565 | |
566 | return 0; |
567 | } |
568 | |
569 | static int alvium_set_csi_lanes(struct alvium_dev *alvium) |
570 | { |
571 | struct device *dev = &alvium->i2c_client->dev; |
572 | u64 num_lanes; |
573 | int ret; |
574 | |
575 | num_lanes = alvium->ep.bus.mipi_csi2.num_data_lanes; |
576 | |
577 | if (num_lanes > alvium->h_sup_csi_lanes) |
578 | return -EINVAL; |
579 | |
580 | ret = alvium_write_hshake(alvium, REG_BCRM_CSI2_LANE_COUNT_RW, |
581 | val: num_lanes); |
582 | if (ret) { |
583 | dev_err(dev, "Fail to set csi lanes reg\n" ); |
584 | return ret; |
585 | } |
586 | |
587 | return 0; |
588 | } |
589 | |
590 | static int alvium_set_lp2hs_delay(struct alvium_dev *alvium) |
591 | { |
592 | struct device *dev = &alvium->i2c_client->dev; |
593 | int ret = 0; |
594 | |
595 | /* |
596 | * The purpose of this reg is force a DPhy reset |
597 | * for the period described by the millisecond on |
598 | * the reg, before it starts streaming. |
599 | * |
600 | * To be clear, with that value bigger than 0 the |
601 | * Alvium forces a dphy-reset on all lanes for that period. |
602 | * That means all lanes go up into low power state. |
603 | * |
604 | */ |
605 | alvium_write(alvium, REG_BCRM_LP2HS_DELAY_RW, |
606 | ALVIUM_LP2HS_DELAY_MS, err: &ret); |
607 | if (ret) { |
608 | dev_err(dev, "Fail to set lp2hs delay reg\n" ); |
609 | return ret; |
610 | } |
611 | |
612 | return 0; |
613 | } |
614 | |
615 | static int alvium_get_csi_clk_params(struct alvium_dev *alvium) |
616 | { |
617 | u64 min_csi_clk, max_csi_clk; |
618 | int ret = 0; |
619 | |
620 | alvium_read(alvium, REG_BCRM_CSI2_CLOCK_MIN_R, val: &min_csi_clk, err: &ret); |
621 | alvium_read(alvium, REG_BCRM_CSI2_CLOCK_MAX_R, val: &max_csi_clk, err: &ret); |
622 | if (ret) |
623 | return ret; |
624 | |
625 | alvium->min_csi_clk = min_csi_clk; |
626 | alvium->max_csi_clk = max_csi_clk; |
627 | |
628 | return 0; |
629 | } |
630 | |
631 | static int alvium_set_csi_clk(struct alvium_dev *alvium) |
632 | { |
633 | struct device *dev = &alvium->i2c_client->dev; |
634 | u64 csi_clk; |
635 | int ret; |
636 | |
637 | csi_clk = clamp(alvium->ep.link_frequencies[0], |
638 | (u64)alvium->min_csi_clk, (u64)alvium->max_csi_clk); |
639 | |
640 | if (alvium->ep.link_frequencies[0] != (u64)csi_clk) { |
641 | dev_warn(dev, |
642 | "requested csi clock (%llu MHz) out of range [%u, %u] Adjusted to %llu\n" , |
643 | alvium->ep.link_frequencies[0], |
644 | alvium->min_csi_clk, alvium->max_csi_clk, csi_clk); |
645 | } |
646 | |
647 | ret = alvium_write_hshake(alvium, REG_BCRM_CSI2_CLOCK_RW, val: csi_clk); |
648 | if (ret) { |
649 | dev_err(dev, "Fail to set csi clock reg\n" ); |
650 | return ret; |
651 | } |
652 | |
653 | alvium->link_freq = csi_clk; |
654 | |
655 | return 0; |
656 | } |
657 | |
658 | static int alvium_get_img_width_params(struct alvium_dev *alvium) |
659 | { |
660 | u64 imgw, imgw_min, imgw_max, imgw_inc; |
661 | int ret = 0; |
662 | |
663 | alvium_read(alvium, REG_BCRM_IMG_WIDTH_RW, val: &imgw, err: &ret); |
664 | alvium_read(alvium, REG_BCRM_IMG_WIDTH_MIN_R, val: &imgw_min, err: &ret); |
665 | alvium_read(alvium, REG_BCRM_IMG_WIDTH_MAX_R, val: &imgw_max, err: &ret); |
666 | alvium_read(alvium, REG_BCRM_IMG_WIDTH_INC_R, val: &imgw_inc, err: &ret); |
667 | if (ret) |
668 | return ret; |
669 | |
670 | alvium->dft_img_width = imgw; |
671 | alvium->img_min_width = imgw_min; |
672 | alvium->img_max_width = imgw_max; |
673 | alvium->img_inc_width = imgw_inc; |
674 | |
675 | return 0; |
676 | } |
677 | |
678 | static int alvium_get_img_height_params(struct alvium_dev *alvium) |
679 | { |
680 | u64 imgh, imgh_min, imgh_max, imgh_inc; |
681 | int ret = 0; |
682 | |
683 | alvium_read(alvium, REG_BCRM_IMG_HEIGHT_RW, val: &imgh, err: &ret); |
684 | alvium_read(alvium, REG_BCRM_IMG_HEIGHT_MIN_R, val: &imgh_min, err: &ret); |
685 | alvium_read(alvium, REG_BCRM_IMG_HEIGHT_MAX_R, val: &imgh_max, err: &ret); |
686 | alvium_read(alvium, REG_BCRM_IMG_HEIGHT_INC_R, val: &imgh_inc, err: &ret); |
687 | if (ret) |
688 | return ret; |
689 | |
690 | alvium->dft_img_height = imgh; |
691 | alvium->img_min_height = imgh_min; |
692 | alvium->img_max_height = imgh_max; |
693 | alvium->img_inc_height = imgh_inc; |
694 | |
695 | return 0; |
696 | } |
697 | |
698 | static int alvium_set_img_width(struct alvium_dev *alvium, u32 width) |
699 | { |
700 | struct device *dev = &alvium->i2c_client->dev; |
701 | int ret; |
702 | |
703 | ret = alvium_write_hshake(alvium, REG_BCRM_IMG_WIDTH_RW, val: width); |
704 | if (ret) { |
705 | dev_err(dev, "Fail to set img width\n" ); |
706 | return ret; |
707 | } |
708 | |
709 | return 0; |
710 | } |
711 | |
712 | static int alvium_set_img_height(struct alvium_dev *alvium, u32 height) |
713 | { |
714 | struct device *dev = &alvium->i2c_client->dev; |
715 | int ret; |
716 | |
717 | ret = alvium_write_hshake(alvium, REG_BCRM_IMG_HEIGHT_RW, val: height); |
718 | if (ret) { |
719 | dev_err(dev, "Fail to set img height\n" ); |
720 | return ret; |
721 | } |
722 | |
723 | return 0; |
724 | } |
725 | |
726 | static int alvium_set_img_offx(struct alvium_dev *alvium, u32 offx) |
727 | { |
728 | struct device *dev = &alvium->i2c_client->dev; |
729 | int ret; |
730 | |
731 | ret = alvium_write_hshake(alvium, REG_BCRM_IMG_OFFSET_X_RW, val: offx); |
732 | if (ret) { |
733 | dev_err(dev, "Fail to set img offx\n" ); |
734 | return ret; |
735 | } |
736 | |
737 | return 0; |
738 | } |
739 | |
740 | static int alvium_set_img_offy(struct alvium_dev *alvium, u32 offy) |
741 | { |
742 | struct device *dev = &alvium->i2c_client->dev; |
743 | int ret; |
744 | |
745 | ret = alvium_write_hshake(alvium, REG_BCRM_IMG_OFFSET_Y_RW, val: offy); |
746 | if (ret) { |
747 | dev_err(dev, "Fail to set img offy\n" ); |
748 | return ret; |
749 | } |
750 | |
751 | return 0; |
752 | } |
753 | |
754 | static int alvium_get_offx_params(struct alvium_dev *alvium) |
755 | { |
756 | u64 min_offx, max_offx, inc_offx; |
757 | int ret = 0; |
758 | |
759 | alvium_read(alvium, REG_BCRM_IMG_OFFSET_X_MIN_R, val: &min_offx, err: &ret); |
760 | alvium_read(alvium, REG_BCRM_IMG_OFFSET_X_MAX_R, val: &max_offx, err: &ret); |
761 | alvium_read(alvium, REG_BCRM_IMG_OFFSET_X_INC_R, val: &inc_offx, err: &ret); |
762 | if (ret) |
763 | return ret; |
764 | |
765 | alvium->min_offx = min_offx; |
766 | alvium->max_offx = max_offx; |
767 | alvium->inc_offx = inc_offx; |
768 | |
769 | return 0; |
770 | } |
771 | |
772 | static int alvium_get_offy_params(struct alvium_dev *alvium) |
773 | { |
774 | u64 min_offy, max_offy, inc_offy; |
775 | int ret = 0; |
776 | |
777 | alvium_read(alvium, REG_BCRM_IMG_OFFSET_Y_MIN_R, val: &min_offy, err: &ret); |
778 | alvium_read(alvium, REG_BCRM_IMG_OFFSET_Y_MAX_R, val: &max_offy, err: &ret); |
779 | alvium_read(alvium, REG_BCRM_IMG_OFFSET_Y_INC_R, val: &inc_offy, err: &ret); |
780 | if (ret) |
781 | return ret; |
782 | |
783 | alvium->min_offy = min_offy; |
784 | alvium->max_offy = max_offy; |
785 | alvium->inc_offy = inc_offy; |
786 | |
787 | return 0; |
788 | } |
789 | |
790 | static int alvium_get_gain_params(struct alvium_dev *alvium) |
791 | { |
792 | u64 dft_gain, min_gain, max_gain, inc_gain; |
793 | int ret = 0; |
794 | |
795 | alvium_read(alvium, REG_BCRM_GAIN_RW, val: &dft_gain, err: &ret); |
796 | alvium_read(alvium, REG_BCRM_GAIN_MIN_R, val: &min_gain, err: &ret); |
797 | alvium_read(alvium, REG_BCRM_GAIN_MAX_R, val: &max_gain, err: &ret); |
798 | alvium_read(alvium, REG_BCRM_GAIN_INC_R, val: &inc_gain, err: &ret); |
799 | if (ret) |
800 | return ret; |
801 | |
802 | alvium->dft_gain = dft_gain; |
803 | alvium->min_gain = min_gain; |
804 | alvium->max_gain = max_gain; |
805 | alvium->inc_gain = inc_gain; |
806 | |
807 | return 0; |
808 | } |
809 | |
810 | static int alvium_get_exposure_params(struct alvium_dev *alvium) |
811 | { |
812 | u64 dft_exp, min_exp, max_exp, inc_exp; |
813 | int ret = 0; |
814 | |
815 | alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_RW, val: &dft_exp, err: &ret); |
816 | alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_MIN_R, val: &min_exp, err: &ret); |
817 | alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_MAX_R, val: &max_exp, err: &ret); |
818 | alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_INC_R, val: &inc_exp, err: &ret); |
819 | if (ret) |
820 | return ret; |
821 | |
822 | alvium->dft_exp = dft_exp; |
823 | alvium->min_exp = min_exp; |
824 | alvium->max_exp = max_exp; |
825 | alvium->inc_exp = inc_exp; |
826 | |
827 | return 0; |
828 | } |
829 | |
830 | static int alvium_get_red_balance_ratio_params(struct alvium_dev *alvium) |
831 | { |
832 | u64 dft_rb, min_rb, max_rb, inc_rb; |
833 | int ret = 0; |
834 | |
835 | alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_RW, val: &dft_rb, err: &ret); |
836 | alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_MIN_R, val: &min_rb, err: &ret); |
837 | alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_MAX_R, val: &max_rb, err: &ret); |
838 | alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_INC_R, val: &inc_rb, err: &ret); |
839 | if (ret) |
840 | return ret; |
841 | |
842 | alvium->dft_rbalance = dft_rb; |
843 | alvium->min_rbalance = min_rb; |
844 | alvium->max_rbalance = max_rb; |
845 | alvium->inc_rbalance = inc_rb; |
846 | |
847 | return 0; |
848 | } |
849 | |
850 | static int alvium_get_blue_balance_ratio_params(struct alvium_dev *alvium) |
851 | { |
852 | u64 dft_bb, min_bb, max_bb, inc_bb; |
853 | int ret = 0; |
854 | |
855 | alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_RW, val: &dft_bb, err: &ret); |
856 | alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_MIN_R, val: &min_bb, err: &ret); |
857 | alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_MAX_R, val: &max_bb, err: &ret); |
858 | alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_INC_R, val: &inc_bb, err: &ret); |
859 | if (ret) |
860 | return ret; |
861 | |
862 | alvium->dft_bbalance = dft_bb; |
863 | alvium->min_bbalance = min_bb; |
864 | alvium->max_bbalance = max_bb; |
865 | alvium->inc_bbalance = inc_bb; |
866 | |
867 | return 0; |
868 | } |
869 | |
870 | static int alvium_get_hue_params(struct alvium_dev *alvium) |
871 | { |
872 | u64 dft_hue, min_hue, max_hue, inc_hue; |
873 | int ret = 0; |
874 | |
875 | alvium_read(alvium, REG_BCRM_HUE_RW, val: &dft_hue, err: &ret); |
876 | alvium_read(alvium, REG_BCRM_HUE_MIN_R, val: &min_hue, err: &ret); |
877 | alvium_read(alvium, REG_BCRM_HUE_MAX_R, val: &max_hue, err: &ret); |
878 | alvium_read(alvium, REG_BCRM_HUE_INC_R, val: &inc_hue, err: &ret); |
879 | if (ret) |
880 | return ret; |
881 | |
882 | alvium->dft_hue = (s32)dft_hue; |
883 | alvium->min_hue = (s32)min_hue; |
884 | alvium->max_hue = (s32)max_hue; |
885 | alvium->inc_hue = (s32)inc_hue; |
886 | |
887 | return 0; |
888 | } |
889 | |
890 | static int alvium_get_black_lvl_params(struct alvium_dev *alvium) |
891 | { |
892 | u64 dft_blvl, min_blvl, max_blvl, inc_blvl; |
893 | int ret = 0; |
894 | |
895 | alvium_read(alvium, REG_BCRM_BLACK_LEVEL_RW, val: &dft_blvl, err: &ret); |
896 | alvium_read(alvium, REG_BCRM_BLACK_LEVEL_MIN_R, val: &min_blvl, err: &ret); |
897 | alvium_read(alvium, REG_BCRM_BLACK_LEVEL_MAX_R, val: &max_blvl, err: &ret); |
898 | alvium_read(alvium, REG_BCRM_BLACK_LEVEL_INC_R, val: &inc_blvl, err: &ret); |
899 | if (ret) |
900 | return ret; |
901 | |
902 | alvium->dft_black_lvl = (s32)dft_blvl; |
903 | alvium->min_black_lvl = (s32)min_blvl; |
904 | alvium->max_black_lvl = (s32)max_blvl; |
905 | alvium->inc_black_lvl = (s32)inc_blvl; |
906 | |
907 | return 0; |
908 | } |
909 | |
910 | static int alvium_get_gamma_params(struct alvium_dev *alvium) |
911 | { |
912 | u64 dft_g, min_g, max_g, inc_g; |
913 | int ret = 0; |
914 | |
915 | alvium_read(alvium, REG_BCRM_GAMMA_RW, val: &dft_g, err: &ret); |
916 | alvium_read(alvium, REG_BCRM_GAMMA_MIN_R, val: &min_g, err: &ret); |
917 | alvium_read(alvium, REG_BCRM_GAMMA_MAX_R, val: &max_g, err: &ret); |
918 | alvium_read(alvium, REG_BCRM_GAMMA_INC_R, val: &inc_g, err: &ret); |
919 | if (ret) |
920 | return ret; |
921 | |
922 | alvium->dft_gamma = dft_g; |
923 | alvium->min_gamma = min_g; |
924 | alvium->max_gamma = max_g; |
925 | alvium->inc_gamma = inc_g; |
926 | |
927 | return 0; |
928 | } |
929 | |
930 | static int alvium_get_sharpness_params(struct alvium_dev *alvium) |
931 | { |
932 | u64 dft_sh, min_sh, max_sh, inc_sh; |
933 | int ret = 0; |
934 | |
935 | alvium_read(alvium, REG_BCRM_SHARPNESS_RW, val: &dft_sh, err: &ret); |
936 | alvium_read(alvium, REG_BCRM_SHARPNESS_MIN_R, val: &min_sh, err: &ret); |
937 | alvium_read(alvium, REG_BCRM_BLACK_LEVEL_MAX_R, val: &max_sh, err: &ret); |
938 | alvium_read(alvium, REG_BCRM_SHARPNESS_INC_R, val: &inc_sh, err: &ret); |
939 | if (ret) |
940 | return ret; |
941 | |
942 | alvium->dft_sharp = (s32)dft_sh; |
943 | alvium->min_sharp = (s32)min_sh; |
944 | alvium->max_sharp = (s32)max_sh; |
945 | alvium->inc_sharp = (s32)inc_sh; |
946 | |
947 | return 0; |
948 | } |
949 | |
950 | static int alvium_get_contrast_params(struct alvium_dev *alvium) |
951 | { |
952 | u64 dft_c, min_c, max_c, inc_c; |
953 | int ret = 0; |
954 | |
955 | alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_RW, val: &dft_c, err: &ret); |
956 | alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_MIN_R, val: &min_c, err: &ret); |
957 | alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_MAX_R, val: &max_c, err: &ret); |
958 | alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_INC_R, val: &inc_c, err: &ret); |
959 | if (ret) |
960 | return ret; |
961 | |
962 | alvium->dft_contrast = dft_c; |
963 | alvium->min_contrast = min_c; |
964 | alvium->max_contrast = max_c; |
965 | alvium->inc_contrast = inc_c; |
966 | |
967 | return 0; |
968 | } |
969 | |
970 | static int alvium_get_saturation_params(struct alvium_dev *alvium) |
971 | { |
972 | u64 dft_sat, min_sat, max_sat, inc_sat; |
973 | int ret = 0; |
974 | |
975 | alvium_read(alvium, REG_BCRM_SATURATION_RW, val: &dft_sat, err: &ret); |
976 | alvium_read(alvium, REG_BCRM_SATURATION_MIN_R, val: &min_sat, err: &ret); |
977 | alvium_read(alvium, REG_BCRM_SATURATION_MAX_R, val: &max_sat, err: &ret); |
978 | alvium_read(alvium, REG_BCRM_SATURATION_INC_R, val: &inc_sat, err: &ret); |
979 | if (ret) |
980 | return ret; |
981 | |
982 | alvium->dft_sat = dft_sat; |
983 | alvium->min_sat = min_sat; |
984 | alvium->max_sat = max_sat; |
985 | alvium->inc_sat = inc_sat; |
986 | |
987 | return 0; |
988 | } |
989 | |
990 | static int alvium_set_bcm_mode(struct alvium_dev *alvium) |
991 | { |
992 | int ret = 0; |
993 | |
994 | alvium_write(alvium, REG_GENCP_CHANGEMODE_W, val: ALVIUM_BCM_MODE, err: &ret); |
995 | alvium->bcrm_mode = ALVIUM_BCM_MODE; |
996 | |
997 | return ret; |
998 | } |
999 | |
1000 | static int alvium_get_mode(struct alvium_dev *alvium) |
1001 | { |
1002 | u64 bcrm_mode; |
1003 | int ret; |
1004 | |
1005 | ret = alvium_read(alvium, REG_GENCP_CURRENTMODE_R, val: &bcrm_mode, NULL); |
1006 | if (ret) |
1007 | return ret; |
1008 | |
1009 | switch (bcrm_mode) { |
1010 | case ALVIUM_BCM_MODE: |
1011 | alvium->bcrm_mode = ALVIUM_BCM_MODE; |
1012 | break; |
1013 | case ALVIUM_GENCP_MODE: |
1014 | alvium->bcrm_mode = ALVIUM_GENCP_MODE; |
1015 | break; |
1016 | } |
1017 | |
1018 | return 0; |
1019 | } |
1020 | |
1021 | static int alvium_get_avail_mipi_data_format(struct alvium_dev *alvium) |
1022 | { |
1023 | struct alvium_avail_mipi_fmt *avail_fmt; |
1024 | u64 val; |
1025 | int ret; |
1026 | |
1027 | ret = alvium_read(alvium, REG_BCRM_IMG_AVAILABLE_MIPI_DATA_FORMATS_R, |
1028 | val: &val, NULL); |
1029 | if (ret) |
1030 | return ret; |
1031 | |
1032 | avail_fmt = (struct alvium_avail_mipi_fmt *)&val; |
1033 | |
1034 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_LEG] = |
1035 | avail_fmt->yuv420_8_leg; |
1036 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8] = |
1037 | avail_fmt->yuv420_8; |
1038 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10] = |
1039 | avail_fmt->yuv420_10; |
1040 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_CSPS] = |
1041 | avail_fmt->yuv420_8_csps; |
1042 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10_CSPS] = |
1043 | avail_fmt->yuv420_10_csps; |
1044 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV422_8] = |
1045 | avail_fmt->yuv422_8; |
1046 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV422_10] = |
1047 | avail_fmt->yuv422_10; |
1048 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB888] = |
1049 | avail_fmt->rgb888; |
1050 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB666] = |
1051 | avail_fmt->rgb666; |
1052 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB565] = |
1053 | avail_fmt->rgb565; |
1054 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB555] = |
1055 | avail_fmt->rgb555; |
1056 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB444] = |
1057 | avail_fmt->rgb444; |
1058 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW6] = |
1059 | avail_fmt->raw6; |
1060 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW7] = |
1061 | avail_fmt->raw7; |
1062 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW8] = |
1063 | avail_fmt->raw8; |
1064 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW10] = |
1065 | avail_fmt->raw10; |
1066 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW12] = |
1067 | avail_fmt->raw12; |
1068 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW14] = |
1069 | avail_fmt->raw14; |
1070 | alvium->is_mipi_fmt_avail[ALVIUM_BIT_JPEG] = |
1071 | avail_fmt->jpeg; |
1072 | |
1073 | alvium_print_avail_mipi_fmt(alvium); |
1074 | |
1075 | return 0; |
1076 | } |
1077 | |
1078 | static int alvium_setup_mipi_fmt(struct alvium_dev *alvium) |
1079 | { |
1080 | unsigned int avail_fmt_cnt = 0; |
1081 | unsigned int fmt = 0; |
1082 | size_t sz = 0; |
1083 | |
1084 | /* calculate fmt array size */ |
1085 | for (fmt = 0; fmt < ALVIUM_NUM_SUPP_MIPI_DATA_FMT; fmt++) { |
1086 | if (!alvium->is_mipi_fmt_avail[alvium_csi2_fmts[fmt].fmt_av_bit]) |
1087 | continue; |
1088 | |
1089 | if (!alvium_csi2_fmts[fmt].is_raw || |
1090 | alvium->is_bay_avail[alvium_csi2_fmts[fmt].bay_av_bit]) |
1091 | sz++; |
1092 | } |
1093 | |
1094 | /* init alvium_csi2_fmt array */ |
1095 | alvium->alvium_csi2_fmt_n = sz; |
1096 | alvium->alvium_csi2_fmt = |
1097 | kmalloc_array(n: sz, size: sizeof(struct alvium_pixfmt), GFP_KERNEL); |
1098 | if (!alvium->alvium_csi2_fmt) |
1099 | return -ENOMEM; |
1100 | |
1101 | /* Create the alvium_csi2 fmt array from formats available */ |
1102 | for (fmt = 0; fmt < ALVIUM_NUM_SUPP_MIPI_DATA_FMT; fmt++) { |
1103 | if (!alvium->is_mipi_fmt_avail[alvium_csi2_fmts[fmt].fmt_av_bit]) |
1104 | continue; |
1105 | |
1106 | if (!alvium_csi2_fmts[fmt].is_raw || |
1107 | alvium->is_bay_avail[alvium_csi2_fmts[fmt].bay_av_bit]) { |
1108 | alvium->alvium_csi2_fmt[avail_fmt_cnt] = |
1109 | alvium_csi2_fmts[fmt]; |
1110 | avail_fmt_cnt++; |
1111 | } |
1112 | } |
1113 | |
1114 | return 0; |
1115 | } |
1116 | |
1117 | static int alvium_set_mipi_fmt(struct alvium_dev *alvium, |
1118 | const struct alvium_pixfmt *pixfmt) |
1119 | { |
1120 | struct device *dev = &alvium->i2c_client->dev; |
1121 | int ret; |
1122 | |
1123 | ret = alvium_write_hshake(alvium, REG_BCRM_IMG_MIPI_DATA_FORMAT_RW, |
1124 | val: pixfmt->mipi_fmt_regval); |
1125 | if (ret) { |
1126 | dev_err(dev, "Fail to set mipi fmt\n" ); |
1127 | return ret; |
1128 | } |
1129 | |
1130 | return 0; |
1131 | } |
1132 | |
1133 | static int alvium_get_avail_bayer(struct alvium_dev *alvium) |
1134 | { |
1135 | struct alvium_avail_bayer *avail_bay; |
1136 | u64 val; |
1137 | int ret; |
1138 | |
1139 | ret = alvium_read(alvium, REG_BCRM_IMG_BAYER_PATTERN_INQUIRY_R, |
1140 | val: &val, NULL); |
1141 | if (ret) |
1142 | return ret; |
1143 | |
1144 | avail_bay = (struct alvium_avail_bayer *)&val; |
1145 | |
1146 | alvium->is_bay_avail[ALVIUM_BIT_BAY_MONO] = avail_bay->mono; |
1147 | alvium->is_bay_avail[ALVIUM_BIT_BAY_GR] = avail_bay->gr; |
1148 | alvium->is_bay_avail[ALVIUM_BIT_BAY_RG] = avail_bay->rg; |
1149 | alvium->is_bay_avail[ALVIUM_BIT_BAY_GB] = avail_bay->gb; |
1150 | alvium->is_bay_avail[ALVIUM_BIT_BAY_BG] = avail_bay->bg; |
1151 | |
1152 | alvium_print_avail_bayer(alvium); |
1153 | |
1154 | return 0; |
1155 | } |
1156 | |
1157 | static int alvium_set_bayer_pattern(struct alvium_dev *alvium, |
1158 | const struct alvium_pixfmt *pixfmt) |
1159 | { |
1160 | struct device *dev = &alvium->i2c_client->dev; |
1161 | int ret; |
1162 | |
1163 | ret = alvium_write_hshake(alvium, REG_BCRM_IMG_BAYER_PATTERN_RW, |
1164 | val: pixfmt->bay_fmt_regval); |
1165 | if (ret) { |
1166 | dev_err(dev, "Fail to set bayer pattern\n" ); |
1167 | return ret; |
1168 | } |
1169 | |
1170 | return 0; |
1171 | } |
1172 | |
1173 | static int alvium_get_frame_interval(struct alvium_dev *alvium, |
1174 | u64 *min_fr, u64 *max_fr) |
1175 | { |
1176 | int ret = 0; |
1177 | |
1178 | alvium_read(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_MIN_R, |
1179 | val: min_fr, err: &ret); |
1180 | alvium_read(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_MAX_R, |
1181 | val: max_fr, err: &ret); |
1182 | |
1183 | return ret; |
1184 | } |
1185 | |
1186 | static int alvium_set_frame_rate(struct alvium_dev *alvium, u64 fr) |
1187 | { |
1188 | struct device *dev = &alvium->i2c_client->dev; |
1189 | int ret; |
1190 | |
1191 | ret = alvium_write_hshake(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_RW, |
1192 | val: fr); |
1193 | if (ret) { |
1194 | dev_err(dev, "Fail to set frame rate lanes reg\n" ); |
1195 | return ret; |
1196 | } |
1197 | |
1198 | dev_dbg(dev, "set frame rate: %llu us\n" , fr); |
1199 | |
1200 | return 0; |
1201 | } |
1202 | |
1203 | static int alvium_set_stream_mipi(struct alvium_dev *alvium, bool on) |
1204 | { |
1205 | struct device *dev = &alvium->i2c_client->dev; |
1206 | int ret; |
1207 | |
1208 | ret = alvium_write_hshake(alvium, reg: on ? REG_BCRM_ACQUISITION_START_RW : |
1209 | REG_BCRM_ACQUISITION_STOP_RW, val: 0x01); |
1210 | if (ret) { |
1211 | dev_err(dev, "Fail set_stream_mipi\n" ); |
1212 | return ret; |
1213 | } |
1214 | |
1215 | return 0; |
1216 | } |
1217 | |
1218 | static int alvium_get_gain(struct alvium_dev *alvium) |
1219 | { |
1220 | u64 gain; |
1221 | int ret; |
1222 | |
1223 | /* The unit is millibel (1 mB = 0.01 dB) */ |
1224 | ret = alvium_read(alvium, REG_BCRM_GAIN_RW, val: &gain, NULL); |
1225 | if (ret) |
1226 | return ret; |
1227 | |
1228 | return gain; |
1229 | } |
1230 | |
1231 | static int alvium_set_ctrl_gain(struct alvium_dev *alvium, int gain) |
1232 | { |
1233 | struct device *dev = &alvium->i2c_client->dev; |
1234 | int ret; |
1235 | |
1236 | /* The unit is millibel (1 mB = 0.01 dB) */ |
1237 | ret = alvium_write_hshake(alvium, REG_BCRM_GAIN_RW, val: (u64)gain); |
1238 | if (ret) { |
1239 | dev_err(dev, "Fail to set gain value reg\n" ); |
1240 | return ret; |
1241 | } |
1242 | |
1243 | return 0; |
1244 | } |
1245 | |
1246 | static int alvium_set_ctrl_auto_gain(struct alvium_dev *alvium, bool on) |
1247 | { |
1248 | struct device *dev = &alvium->i2c_client->dev; |
1249 | int ret; |
1250 | |
1251 | ret = alvium_write_hshake(alvium, REG_BCRM_GAIN_AUTO_RW, |
1252 | val: on ? 0x02 : 0x00); |
1253 | if (ret) { |
1254 | dev_err(dev, "Fail to set autogain reg\n" ); |
1255 | return ret; |
1256 | } |
1257 | |
1258 | return 0; |
1259 | } |
1260 | |
1261 | static int alvium_get_exposure(struct alvium_dev *alvium) |
1262 | { |
1263 | u64 exp; |
1264 | int ret; |
1265 | |
1266 | /* Exposure time in ns */ |
1267 | ret = alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_RW, val: &exp, NULL); |
1268 | if (ret) |
1269 | return ret; |
1270 | |
1271 | return exp; |
1272 | } |
1273 | |
1274 | static int alvium_set_ctrl_auto_exposure(struct alvium_dev *alvium, bool on) |
1275 | { |
1276 | struct device *dev = &alvium->i2c_client->dev; |
1277 | int ret; |
1278 | |
1279 | ret = alvium_write_hshake(alvium, REG_BCRM_WHITE_BALANCE_AUTO_RW, |
1280 | val: on ? 0x02 : 0x00); |
1281 | if (ret) { |
1282 | dev_err(dev, "Fail to set autoexposure reg\n" ); |
1283 | return ret; |
1284 | } |
1285 | |
1286 | return 0; |
1287 | } |
1288 | |
1289 | static int alvium_set_ctrl_exposure(struct alvium_dev *alvium, int exposure_ns) |
1290 | { |
1291 | struct device *dev = &alvium->i2c_client->dev; |
1292 | int ret; |
1293 | |
1294 | ret = alvium_write_hshake(alvium, REG_BCRM_EXPOSURE_TIME_RW, |
1295 | val: (u64)exposure_ns); |
1296 | if (ret) { |
1297 | dev_err(dev, "Fail to set exposure value reg\n" ); |
1298 | return ret; |
1299 | } |
1300 | |
1301 | return 0; |
1302 | } |
1303 | |
1304 | static int alvium_set_ctrl_blue_balance_ratio(struct alvium_dev *alvium, |
1305 | int blue) |
1306 | { |
1307 | struct device *dev = &alvium->i2c_client->dev; |
1308 | int ret; |
1309 | |
1310 | ret = alvium_write_hshake(alvium, REG_BCRM_BLUE_BALANCE_RATIO_RW, |
1311 | val: (u64)blue); |
1312 | if (ret) { |
1313 | dev_err(dev, "Fail to set blue ratio value reg\n" ); |
1314 | return ret; |
1315 | } |
1316 | |
1317 | return 0; |
1318 | } |
1319 | |
1320 | static int alvium_set_ctrl_red_balance_ratio(struct alvium_dev *alvium, int red) |
1321 | { |
1322 | struct device *dev = &alvium->i2c_client->dev; |
1323 | int ret; |
1324 | |
1325 | ret = alvium_write_hshake(alvium, REG_BCRM_RED_BALANCE_RATIO_RW, |
1326 | val: (u64)red); |
1327 | if (ret) { |
1328 | dev_err(dev, "Fail to set red ratio value reg\n" ); |
1329 | return ret; |
1330 | } |
1331 | |
1332 | return 0; |
1333 | } |
1334 | |
1335 | static int alvium_set_ctrl_awb(struct alvium_dev *alvium, bool on) |
1336 | { |
1337 | struct device *dev = &alvium->i2c_client->dev; |
1338 | int ret; |
1339 | |
1340 | ret = alvium_write_hshake(alvium, REG_BCRM_WHITE_BALANCE_AUTO_RW, |
1341 | val: on ? 0x02 : 0x00); |
1342 | if (ret) { |
1343 | dev_err(dev, "Fail to set awb reg\n" ); |
1344 | return ret; |
1345 | } |
1346 | |
1347 | return 0; |
1348 | } |
1349 | |
1350 | static int alvium_set_ctrl_hue(struct alvium_dev *alvium, int val) |
1351 | { |
1352 | struct device *dev = &alvium->i2c_client->dev; |
1353 | int ret; |
1354 | |
1355 | ret = alvium_write_hshake(alvium, REG_BCRM_HUE_RW, val: (u64)val); |
1356 | if (ret) { |
1357 | dev_err(dev, "Fail to set hue value reg\n" ); |
1358 | return ret; |
1359 | } |
1360 | |
1361 | return 0; |
1362 | } |
1363 | |
1364 | static int alvium_set_ctrl_contrast(struct alvium_dev *alvium, int val) |
1365 | { |
1366 | struct device *dev = &alvium->i2c_client->dev; |
1367 | int ret; |
1368 | |
1369 | ret = alvium_write_hshake(alvium, REG_BCRM_CONTRAST_VALUE_RW, val: (u64)val); |
1370 | if (ret) { |
1371 | dev_err(dev, "Fail to set contrast value reg\n" ); |
1372 | return ret; |
1373 | } |
1374 | |
1375 | return 0; |
1376 | } |
1377 | |
1378 | static int alvium_set_ctrl_saturation(struct alvium_dev *alvium, int val) |
1379 | { |
1380 | struct device *dev = &alvium->i2c_client->dev; |
1381 | int ret; |
1382 | |
1383 | ret = alvium_write_hshake(alvium, REG_BCRM_SATURATION_RW, val: (u64)val); |
1384 | if (ret) { |
1385 | dev_err(dev, "Fail to set contrast value reg\n" ); |
1386 | return ret; |
1387 | } |
1388 | |
1389 | return 0; |
1390 | } |
1391 | |
1392 | static int alvium_set_ctrl_gamma(struct alvium_dev *alvium, int val) |
1393 | { |
1394 | struct device *dev = &alvium->i2c_client->dev; |
1395 | int ret; |
1396 | |
1397 | ret = alvium_write_hshake(alvium, REG_BCRM_GAMMA_RW, val: (u64)val); |
1398 | if (ret) { |
1399 | dev_err(dev, "Fail to set gamma value reg\n" ); |
1400 | return ret; |
1401 | } |
1402 | |
1403 | return 0; |
1404 | } |
1405 | |
1406 | static int alvium_set_ctrl_sharpness(struct alvium_dev *alvium, int val) |
1407 | { |
1408 | struct device *dev = &alvium->i2c_client->dev; |
1409 | int ret; |
1410 | |
1411 | ret = alvium_write_hshake(alvium, REG_BCRM_SHARPNESS_RW, val: (u64)val); |
1412 | if (ret) { |
1413 | dev_err(dev, "Fail to set sharpness value reg\n" ); |
1414 | return ret; |
1415 | } |
1416 | |
1417 | return 0; |
1418 | } |
1419 | |
1420 | static int alvium_set_ctrl_hflip(struct alvium_dev *alvium, int val) |
1421 | { |
1422 | struct device *dev = &alvium->i2c_client->dev; |
1423 | int ret; |
1424 | |
1425 | ret = alvium_write_hshake(alvium, REG_BCRM_IMG_REVERSE_X_RW, val: (u64)val); |
1426 | if (ret) { |
1427 | dev_err(dev, "Fail to set reverse_x value reg\n" ); |
1428 | return ret; |
1429 | } |
1430 | |
1431 | return 0; |
1432 | } |
1433 | |
1434 | static int alvium_set_ctrl_vflip(struct alvium_dev *alvium, int val) |
1435 | { |
1436 | struct device *dev = &alvium->i2c_client->dev; |
1437 | int ret; |
1438 | |
1439 | ret = alvium_write_hshake(alvium, REG_BCRM_IMG_REVERSE_Y_RW, val: (u64)val); |
1440 | if (ret) { |
1441 | dev_err(dev, "Fail to set reverse_y value reg\n" ); |
1442 | return ret; |
1443 | } |
1444 | |
1445 | return 0; |
1446 | } |
1447 | |
1448 | static int alvium_get_hw_features_params(struct alvium_dev *alvium) |
1449 | { |
1450 | struct device *dev = &alvium->i2c_client->dev; |
1451 | int ret; |
1452 | |
1453 | ret = alvium_get_csi_clk_params(alvium); |
1454 | if (ret) { |
1455 | dev_err(dev, "Fail to read min/max csi clock regs\n" ); |
1456 | return ret; |
1457 | } |
1458 | |
1459 | ret = alvium_get_img_width_params(alvium); |
1460 | if (ret) { |
1461 | dev_err(dev, "Fail to read img width regs\n" ); |
1462 | return ret; |
1463 | } |
1464 | |
1465 | ret = alvium_get_img_height_params(alvium); |
1466 | if (ret) { |
1467 | dev_err(dev, "Fail to read img height regs\n" ); |
1468 | return ret; |
1469 | } |
1470 | |
1471 | ret = alvium_get_offx_params(alvium); |
1472 | if (ret) { |
1473 | dev_err(dev, "Fail to read offx regs\n" ); |
1474 | return ret; |
1475 | } |
1476 | |
1477 | ret = alvium_get_offy_params(alvium); |
1478 | if (ret) { |
1479 | dev_err(dev, "Fail to read offy regs\n" ); |
1480 | return ret; |
1481 | } |
1482 | |
1483 | ret = alvium_get_gain_params(alvium); |
1484 | if (ret) { |
1485 | dev_err(dev, "Fail to read gain regs\n" ); |
1486 | return ret; |
1487 | } |
1488 | |
1489 | ret = alvium_get_exposure_params(alvium); |
1490 | if (ret) { |
1491 | dev_err(dev, "Fail to read min/max exp regs\n" ); |
1492 | return ret; |
1493 | } |
1494 | |
1495 | ret = alvium_get_red_balance_ratio_params(alvium); |
1496 | if (ret) { |
1497 | dev_err(dev, "Fail to read red balance ratio regs\n" ); |
1498 | return ret; |
1499 | } |
1500 | |
1501 | ret = alvium_get_blue_balance_ratio_params(alvium); |
1502 | if (ret) { |
1503 | dev_err(dev, "Fail to read blue balance ratio regs\n" ); |
1504 | return ret; |
1505 | } |
1506 | |
1507 | ret = alvium_get_hue_params(alvium); |
1508 | if (ret) { |
1509 | dev_err(dev, "Fail to read hue regs\n" ); |
1510 | return ret; |
1511 | } |
1512 | |
1513 | ret = alvium_get_contrast_params(alvium); |
1514 | if (ret) { |
1515 | dev_err(dev, "Fail to read contrast regs\n" ); |
1516 | return ret; |
1517 | } |
1518 | |
1519 | ret = alvium_get_saturation_params(alvium); |
1520 | if (ret) { |
1521 | dev_err(dev, "Fail to read saturation regs\n" ); |
1522 | return ret; |
1523 | } |
1524 | |
1525 | ret = alvium_get_black_lvl_params(alvium); |
1526 | if (ret) { |
1527 | dev_err(dev, "Fail to read black lvl regs\n" ); |
1528 | return ret; |
1529 | } |
1530 | |
1531 | ret = alvium_get_gamma_params(alvium); |
1532 | if (ret) { |
1533 | dev_err(dev, "Fail to read gamma regs\n" ); |
1534 | return ret; |
1535 | } |
1536 | |
1537 | ret = alvium_get_sharpness_params(alvium); |
1538 | if (ret) { |
1539 | dev_err(dev, "Fail to read sharpness regs\n" ); |
1540 | return ret; |
1541 | } |
1542 | |
1543 | return 0; |
1544 | } |
1545 | |
1546 | static int alvium_get_hw_info(struct alvium_dev *alvium) |
1547 | { |
1548 | struct device *dev = &alvium->i2c_client->dev; |
1549 | int ret; |
1550 | |
1551 | ret = alvium_get_bcrm_vers(alvium); |
1552 | if (ret) { |
1553 | dev_err(dev, "Fail to read bcrm version reg\n" ); |
1554 | return ret; |
1555 | } |
1556 | |
1557 | ret = alvium_get_bcrm_addr(alvium); |
1558 | if (ret) { |
1559 | dev_err(dev, "Fail to bcrm address reg\n" ); |
1560 | return ret; |
1561 | } |
1562 | |
1563 | ret = alvium_get_fw_version(alvium); |
1564 | if (ret) { |
1565 | dev_err(dev, "Fail to read fw version reg\n" ); |
1566 | return ret; |
1567 | } |
1568 | |
1569 | ret = alvium_get_host_supp_csi_lanes(alvium); |
1570 | if (ret) { |
1571 | dev_err(dev, "Fail to read host supported csi lanes reg\n" ); |
1572 | return ret; |
1573 | } |
1574 | |
1575 | ret = alvium_get_feat_inq(alvium); |
1576 | if (ret) { |
1577 | dev_err(dev, "Fail to read bcrm feature inquiry reg\n" ); |
1578 | return ret; |
1579 | } |
1580 | |
1581 | ret = alvium_get_hw_features_params(alvium); |
1582 | if (ret) { |
1583 | dev_err(dev, "Fail to read features params regs\n" ); |
1584 | return ret; |
1585 | } |
1586 | |
1587 | ret = alvium_get_avail_mipi_data_format(alvium); |
1588 | if (ret) { |
1589 | dev_err(dev, "Fail to read available mipi data formats reg\n" ); |
1590 | return ret; |
1591 | } |
1592 | |
1593 | ret = alvium_get_avail_bayer(alvium); |
1594 | if (ret) { |
1595 | dev_err(dev, "Fail to read available Bayer patterns reg\n" ); |
1596 | return ret; |
1597 | } |
1598 | |
1599 | ret = alvium_get_mode(alvium); |
1600 | if (ret) { |
1601 | dev_err(dev, "Fail to get current mode reg\n" ); |
1602 | return ret; |
1603 | } |
1604 | |
1605 | return 0; |
1606 | } |
1607 | |
1608 | static int alvium_hw_init(struct alvium_dev *alvium) |
1609 | { |
1610 | struct device *dev = &alvium->i2c_client->dev; |
1611 | int ret; |
1612 | |
1613 | /* Set Alvium BCM mode*/ |
1614 | ret = alvium_set_bcm_mode(alvium); |
1615 | if (ret) { |
1616 | dev_err(dev, "Fail to set BCM mode\n" ); |
1617 | return ret; |
1618 | } |
1619 | |
1620 | ret = alvium_set_csi_lanes(alvium); |
1621 | if (ret) { |
1622 | dev_err(dev, "Fail to set csi lanes\n" ); |
1623 | return ret; |
1624 | } |
1625 | |
1626 | ret = alvium_set_csi_clk(alvium); |
1627 | if (ret) { |
1628 | dev_err(dev, "Fail to set csi clk\n" ); |
1629 | return ret; |
1630 | } |
1631 | |
1632 | ret = alvium_set_lp2hs_delay(alvium); |
1633 | if (ret) { |
1634 | dev_err(dev, "Fail to set lp2hs reg\n" ); |
1635 | return ret; |
1636 | } |
1637 | |
1638 | return 0; |
1639 | } |
1640 | |
1641 | /* --------------- Subdev Operations --------------- */ |
1642 | static int alvium_s_frame_interval(struct v4l2_subdev *sd, |
1643 | struct v4l2_subdev_state *sd_state, |
1644 | struct v4l2_subdev_frame_interval *fi) |
1645 | { |
1646 | struct alvium_dev *alvium = sd_to_alvium(sd); |
1647 | struct device *dev = &alvium->i2c_client->dev; |
1648 | u64 req_fr, min_fr, max_fr; |
1649 | struct v4l2_fract *interval; |
1650 | int ret; |
1651 | |
1652 | if (alvium->streaming) |
1653 | return -EBUSY; |
1654 | |
1655 | if (fi->interval.denominator == 0) |
1656 | return -EINVAL; |
1657 | |
1658 | ret = alvium_get_frame_interval(alvium, min_fr: &min_fr, max_fr: &max_fr); |
1659 | if (ret) { |
1660 | dev_err(dev, "Fail to get frame interval\n" ); |
1661 | return ret; |
1662 | } |
1663 | |
1664 | dev_dbg(dev, "fi->interval.numerator = %d\n" , |
1665 | fi->interval.numerator); |
1666 | dev_dbg(dev, "fi->interval.denominator = %d\n" , |
1667 | fi->interval.denominator); |
1668 | |
1669 | req_fr = (u64)((fi->interval.denominator * USEC_PER_SEC) / |
1670 | fi->interval.numerator); |
1671 | req_fr = clamp(req_fr, min_fr, max_fr); |
1672 | |
1673 | interval = v4l2_subdev_state_get_interval(sd_state, 0); |
1674 | |
1675 | interval->numerator = fi->interval.numerator; |
1676 | interval->denominator = fi->interval.denominator; |
1677 | |
1678 | if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE) |
1679 | return 0; |
1680 | |
1681 | return alvium_set_frame_rate(alvium, fr: req_fr); |
1682 | } |
1683 | |
1684 | static int alvium_enum_mbus_code(struct v4l2_subdev *sd, |
1685 | struct v4l2_subdev_state *sd_state, |
1686 | struct v4l2_subdev_mbus_code_enum *code) |
1687 | { |
1688 | struct alvium_dev *alvium = sd_to_alvium(sd); |
1689 | |
1690 | if (code->index >= alvium->alvium_csi2_fmt_n) |
1691 | return -EINVAL; |
1692 | |
1693 | code->code = alvium->alvium_csi2_fmt[code->index].code; |
1694 | |
1695 | return 0; |
1696 | } |
1697 | |
1698 | static const struct alvium_pixfmt * |
1699 | alvium_code_to_pixfmt(struct alvium_dev *alvium, u32 code) |
1700 | { |
1701 | unsigned int i; |
1702 | |
1703 | for (i = 0; alvium->alvium_csi2_fmt[i].code; ++i) |
1704 | if (alvium->alvium_csi2_fmt[i].code == code) |
1705 | return &alvium->alvium_csi2_fmt[i]; |
1706 | |
1707 | return &alvium->alvium_csi2_fmt[0]; |
1708 | } |
1709 | |
1710 | static int alvium_set_mode(struct alvium_dev *alvium, |
1711 | struct v4l2_subdev_state *state) |
1712 | { |
1713 | struct v4l2_mbus_framefmt *fmt; |
1714 | struct v4l2_rect *crop; |
1715 | int ret; |
1716 | |
1717 | crop = v4l2_subdev_state_get_crop(state, 0); |
1718 | fmt = v4l2_subdev_state_get_format(state, 0); |
1719 | |
1720 | v4l_bound_align_image(width: &fmt->width, wmin: alvium->img_min_width, |
1721 | wmax: alvium->img_max_width, walign: 0, |
1722 | height: &fmt->height, hmin: alvium->img_min_height, |
1723 | hmax: alvium->img_max_height, halign: 0, salign: 0); |
1724 | |
1725 | /* alvium don't accept negative crop left/top */ |
1726 | crop->left = clamp((u32)max(0, crop->left), alvium->min_offx, |
1727 | (u32)(alvium->img_max_width - fmt->width)); |
1728 | crop->top = clamp((u32)max(0, crop->top), alvium->min_offy, |
1729 | (u32)(alvium->img_max_height - fmt->height)); |
1730 | |
1731 | ret = alvium_set_img_width(alvium, width: fmt->width); |
1732 | if (ret) |
1733 | return ret; |
1734 | |
1735 | ret = alvium_set_img_height(alvium, height: fmt->height); |
1736 | if (ret) |
1737 | return ret; |
1738 | |
1739 | ret = alvium_set_img_offx(alvium, offx: crop->left); |
1740 | if (ret) |
1741 | return ret; |
1742 | |
1743 | ret = alvium_set_img_offy(alvium, offy: crop->top); |
1744 | if (ret) |
1745 | return ret; |
1746 | |
1747 | return 0; |
1748 | } |
1749 | |
1750 | static int alvium_set_framefmt(struct alvium_dev *alvium, |
1751 | struct v4l2_mbus_framefmt *format) |
1752 | { |
1753 | struct device *dev = &alvium->i2c_client->dev; |
1754 | const struct alvium_pixfmt *alvium_csi2_fmt; |
1755 | int ret = 0; |
1756 | |
1757 | alvium_csi2_fmt = alvium_code_to_pixfmt(alvium, code: format->code); |
1758 | |
1759 | ret = alvium_set_mipi_fmt(alvium, pixfmt: alvium_csi2_fmt); |
1760 | if (ret) |
1761 | return ret; |
1762 | |
1763 | if (alvium_csi2_fmt->is_raw) { |
1764 | ret = alvium_set_bayer_pattern(alvium, pixfmt: alvium_csi2_fmt); |
1765 | if (ret) |
1766 | return ret; |
1767 | } |
1768 | |
1769 | dev_dbg(dev, "start: %s, mipi_fmt_regval regval = 0x%llx" , |
1770 | __func__, alvium_csi2_fmt->mipi_fmt_regval); |
1771 | |
1772 | return ret; |
1773 | } |
1774 | |
1775 | static int alvium_s_stream(struct v4l2_subdev *sd, int enable) |
1776 | { |
1777 | struct alvium_dev *alvium = sd_to_alvium(sd); |
1778 | struct i2c_client *client = v4l2_get_subdevdata(sd: &alvium->sd); |
1779 | struct v4l2_mbus_framefmt *fmt; |
1780 | struct v4l2_subdev_state *state; |
1781 | int ret = 0; |
1782 | |
1783 | state = v4l2_subdev_lock_and_get_active_state(sd); |
1784 | |
1785 | if (enable) { |
1786 | ret = pm_runtime_resume_and_get(dev: &client->dev); |
1787 | if (ret < 0) |
1788 | goto out; |
1789 | |
1790 | ret = __v4l2_ctrl_handler_setup(hdl: &alvium->ctrls.handler); |
1791 | if (ret) |
1792 | goto out; |
1793 | |
1794 | ret = alvium_set_mode(alvium, state); |
1795 | if (ret) |
1796 | goto out; |
1797 | |
1798 | fmt = v4l2_subdev_state_get_format(state, 0); |
1799 | ret = alvium_set_framefmt(alvium, format: fmt); |
1800 | if (ret) |
1801 | goto out; |
1802 | |
1803 | ret = alvium_set_stream_mipi(alvium, on: enable); |
1804 | if (ret) |
1805 | goto out; |
1806 | |
1807 | } else { |
1808 | alvium_set_stream_mipi(alvium, on: enable); |
1809 | pm_runtime_mark_last_busy(dev: &client->dev); |
1810 | pm_runtime_put_autosuspend(dev: &client->dev); |
1811 | } |
1812 | |
1813 | alvium->streaming = !!enable; |
1814 | v4l2_subdev_unlock_state(state); |
1815 | |
1816 | return 0; |
1817 | |
1818 | out: |
1819 | pm_runtime_put(dev: &client->dev); |
1820 | v4l2_subdev_unlock_state(state); |
1821 | return ret; |
1822 | } |
1823 | |
1824 | static int alvium_init_state(struct v4l2_subdev *sd, |
1825 | struct v4l2_subdev_state *state) |
1826 | { |
1827 | struct alvium_dev *alvium = sd_to_alvium(sd); |
1828 | struct alvium_mode *mode = &alvium->mode; |
1829 | struct v4l2_fract *interval; |
1830 | struct v4l2_subdev_format sd_fmt = { |
1831 | .which = V4L2_SUBDEV_FORMAT_TRY, |
1832 | .format = alvium_csi2_default_fmt, |
1833 | }; |
1834 | struct v4l2_subdev_crop sd_crop = { |
1835 | .which = V4L2_SUBDEV_FORMAT_TRY, |
1836 | .rect = { |
1837 | .left = mode->crop.left, |
1838 | .top = mode->crop.top, |
1839 | .width = mode->crop.width, |
1840 | .height = mode->crop.height, |
1841 | }, |
1842 | }; |
1843 | |
1844 | *v4l2_subdev_state_get_crop(state, 0) = sd_crop.rect; |
1845 | *v4l2_subdev_state_get_format(state, 0) = sd_fmt.format; |
1846 | |
1847 | /* Setup initial frame interval*/ |
1848 | interval = v4l2_subdev_state_get_interval(state, 0); |
1849 | interval->numerator = 1; |
1850 | interval->denominator = ALVIUM_DEFAULT_FR_HZ; |
1851 | |
1852 | return 0; |
1853 | } |
1854 | |
1855 | static int alvium_set_fmt(struct v4l2_subdev *sd, |
1856 | struct v4l2_subdev_state *sd_state, |
1857 | struct v4l2_subdev_format *format) |
1858 | { |
1859 | struct alvium_dev *alvium = sd_to_alvium(sd); |
1860 | const struct alvium_pixfmt *alvium_csi2_fmt; |
1861 | struct v4l2_mbus_framefmt *fmt; |
1862 | struct v4l2_rect *crop; |
1863 | |
1864 | fmt = v4l2_subdev_state_get_format(sd_state, 0); |
1865 | crop = v4l2_subdev_state_get_crop(sd_state, 0); |
1866 | |
1867 | v4l_bound_align_image(width: &format->format.width, wmin: alvium->img_min_width, |
1868 | wmax: alvium->img_max_width, walign: 0, |
1869 | height: &format->format.height, hmin: alvium->img_min_height, |
1870 | hmax: alvium->img_max_height, halign: 0, salign: 0); |
1871 | |
1872 | /* Adjust left and top to prevent roll over sensor area */ |
1873 | crop->left = clamp((u32)crop->left, (u32)0, |
1874 | (alvium->img_max_width - fmt->width)); |
1875 | crop->top = clamp((u32)crop->top, (u32)0, |
1876 | (alvium->img_max_height - fmt->height)); |
1877 | |
1878 | /* Set also the crop width and height when set a new fmt */ |
1879 | crop->width = fmt->width; |
1880 | crop->height = fmt->height; |
1881 | |
1882 | alvium_csi2_fmt = alvium_code_to_pixfmt(alvium, code: format->format.code); |
1883 | fmt->code = alvium_csi2_fmt->code; |
1884 | |
1885 | *fmt = format->format; |
1886 | |
1887 | return 0; |
1888 | } |
1889 | |
1890 | static int alvium_set_selection(struct v4l2_subdev *sd, |
1891 | struct v4l2_subdev_state *sd_state, |
1892 | struct v4l2_subdev_selection *sel) |
1893 | { |
1894 | struct alvium_dev *alvium = sd_to_alvium(sd); |
1895 | struct v4l2_mbus_framefmt *fmt; |
1896 | struct v4l2_rect *crop; |
1897 | |
1898 | if (sel->target != V4L2_SEL_TGT_CROP) |
1899 | return -EINVAL; |
1900 | |
1901 | crop = v4l2_subdev_state_get_crop(sd_state, 0); |
1902 | fmt = v4l2_subdev_state_get_format(sd_state, 0); |
1903 | |
1904 | /* |
1905 | * Alvium can only shift the origin of the img |
1906 | * then we accept only value with the same value of the actual fmt |
1907 | */ |
1908 | if (sel->r.width != fmt->width) |
1909 | sel->r.width = fmt->width; |
1910 | |
1911 | if (sel->r.height != fmt->height) |
1912 | sel->r.height = fmt->height; |
1913 | |
1914 | /* alvium don't accept negative crop left/top */ |
1915 | crop->left = clamp((u32)max(0, sel->r.left), alvium->min_offx, |
1916 | alvium->img_max_width - sel->r.width); |
1917 | crop->top = clamp((u32)max(0, sel->r.top), alvium->min_offy, |
1918 | alvium->img_max_height - sel->r.height); |
1919 | |
1920 | sel->r = *crop; |
1921 | |
1922 | return 0; |
1923 | } |
1924 | |
1925 | static int alvium_get_selection(struct v4l2_subdev *sd, |
1926 | struct v4l2_subdev_state *sd_state, |
1927 | struct v4l2_subdev_selection *sel) |
1928 | { |
1929 | struct alvium_dev *alvium = sd_to_alvium(sd); |
1930 | |
1931 | switch (sel->target) { |
1932 | /* Current cropping area */ |
1933 | case V4L2_SEL_TGT_CROP: |
1934 | sel->r = *v4l2_subdev_state_get_crop(sd_state, 0); |
1935 | break; |
1936 | /* Cropping bounds */ |
1937 | case V4L2_SEL_TGT_NATIVE_SIZE: |
1938 | sel->r.top = 0; |
1939 | sel->r.left = 0; |
1940 | sel->r.width = alvium->img_max_width; |
1941 | sel->r.height = alvium->img_max_height; |
1942 | break; |
1943 | /* Default cropping area */ |
1944 | case V4L2_SEL_TGT_CROP_BOUNDS: |
1945 | case V4L2_SEL_TGT_CROP_DEFAULT: |
1946 | sel->r.top = alvium->min_offy; |
1947 | sel->r.left = alvium->min_offx; |
1948 | sel->r.width = alvium->img_max_width; |
1949 | sel->r.height = alvium->img_max_height; |
1950 | break; |
1951 | default: |
1952 | return -EINVAL; |
1953 | } |
1954 | |
1955 | return 0; |
1956 | } |
1957 | |
1958 | static int alvium_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
1959 | { |
1960 | struct v4l2_subdev *sd = ctrl_to_sd(ctrl); |
1961 | struct alvium_dev *alvium = sd_to_alvium(sd); |
1962 | int val; |
1963 | |
1964 | switch (ctrl->id) { |
1965 | case V4L2_CID_GAIN: |
1966 | val = alvium_get_gain(alvium); |
1967 | if (val < 0) |
1968 | return val; |
1969 | alvium->ctrls.gain->val = val; |
1970 | break; |
1971 | case V4L2_CID_EXPOSURE: |
1972 | val = alvium_get_exposure(alvium); |
1973 | if (val < 0) |
1974 | return val; |
1975 | alvium->ctrls.exposure->val = val; |
1976 | break; |
1977 | } |
1978 | |
1979 | return 0; |
1980 | } |
1981 | |
1982 | static int alvium_s_ctrl(struct v4l2_ctrl *ctrl) |
1983 | { |
1984 | struct v4l2_subdev *sd = ctrl_to_sd(ctrl); |
1985 | struct alvium_dev *alvium = sd_to_alvium(sd); |
1986 | struct i2c_client *client = v4l2_get_subdevdata(sd: &alvium->sd); |
1987 | int ret; |
1988 | |
1989 | /* |
1990 | * Applying V4L2 control value only happens |
1991 | * when power is up for streaming |
1992 | */ |
1993 | if (!pm_runtime_get_if_in_use(dev: &client->dev)) |
1994 | return 0; |
1995 | |
1996 | switch (ctrl->id) { |
1997 | case V4L2_CID_GAIN: |
1998 | ret = alvium_set_ctrl_gain(alvium, gain: ctrl->val); |
1999 | break; |
2000 | case V4L2_CID_AUTOGAIN: |
2001 | ret = alvium_set_ctrl_auto_gain(alvium, on: ctrl->val); |
2002 | break; |
2003 | case V4L2_CID_EXPOSURE: |
2004 | ret = alvium_set_ctrl_exposure(alvium, exposure_ns: ctrl->val); |
2005 | break; |
2006 | case V4L2_CID_EXPOSURE_AUTO: |
2007 | ret = alvium_set_ctrl_auto_exposure(alvium, on: ctrl->val); |
2008 | break; |
2009 | case V4L2_CID_RED_BALANCE: |
2010 | ret = alvium_set_ctrl_red_balance_ratio(alvium, red: ctrl->val); |
2011 | break; |
2012 | case V4L2_CID_BLUE_BALANCE: |
2013 | ret = alvium_set_ctrl_blue_balance_ratio(alvium, blue: ctrl->val); |
2014 | break; |
2015 | case V4L2_CID_AUTO_WHITE_BALANCE: |
2016 | ret = alvium_set_ctrl_awb(alvium, on: ctrl->val); |
2017 | break; |
2018 | case V4L2_CID_HUE: |
2019 | ret = alvium_set_ctrl_hue(alvium, val: ctrl->val); |
2020 | break; |
2021 | case V4L2_CID_CONTRAST: |
2022 | ret = alvium_set_ctrl_contrast(alvium, val: ctrl->val); |
2023 | break; |
2024 | case V4L2_CID_SATURATION: |
2025 | ret = alvium_set_ctrl_saturation(alvium, val: ctrl->val); |
2026 | break; |
2027 | case V4L2_CID_GAMMA: |
2028 | ret = alvium_set_ctrl_gamma(alvium, val: ctrl->val); |
2029 | break; |
2030 | case V4L2_CID_SHARPNESS: |
2031 | ret = alvium_set_ctrl_sharpness(alvium, val: ctrl->val); |
2032 | break; |
2033 | case V4L2_CID_HFLIP: |
2034 | ret = alvium_set_ctrl_hflip(alvium, val: ctrl->val); |
2035 | break; |
2036 | case V4L2_CID_VFLIP: |
2037 | ret = alvium_set_ctrl_vflip(alvium, val: ctrl->val); |
2038 | break; |
2039 | default: |
2040 | ret = -EINVAL; |
2041 | break; |
2042 | } |
2043 | |
2044 | pm_runtime_put(dev: &client->dev); |
2045 | |
2046 | return ret; |
2047 | } |
2048 | |
2049 | static const struct v4l2_ctrl_ops alvium_ctrl_ops = { |
2050 | .g_volatile_ctrl = alvium_g_volatile_ctrl, |
2051 | .s_ctrl = alvium_s_ctrl, |
2052 | }; |
2053 | |
2054 | static int alvium_ctrl_init(struct alvium_dev *alvium) |
2055 | { |
2056 | const struct v4l2_ctrl_ops *ops = &alvium_ctrl_ops; |
2057 | struct alvium_ctrls *ctrls = &alvium->ctrls; |
2058 | struct v4l2_ctrl_handler *hdl = &ctrls->handler; |
2059 | struct v4l2_fwnode_device_properties props; |
2060 | int ret; |
2061 | |
2062 | v4l2_ctrl_handler_init(hdl, 32); |
2063 | |
2064 | /* Pixel rate is fixed */ |
2065 | ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, |
2066 | V4L2_CID_PIXEL_RATE, min: 0, |
2067 | ALVIUM_DEFAULT_PIXEL_RATE_MHZ, step: 1, |
2068 | ALVIUM_DEFAULT_PIXEL_RATE_MHZ); |
2069 | ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY; |
2070 | |
2071 | /* Link freq is fixed */ |
2072 | ctrls->link_freq = v4l2_ctrl_new_int_menu(hdl, ops, |
2073 | V4L2_CID_LINK_FREQ, |
2074 | max: 0, def: 0, qmenu_int: &alvium->link_freq); |
2075 | ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; |
2076 | |
2077 | /* Auto/manual white balance */ |
2078 | if (alvium->avail_ft.auto_whiteb) { |
2079 | ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops, |
2080 | V4L2_CID_AUTO_WHITE_BALANCE, |
2081 | min: 0, max: 1, step: 1, def: 1); |
2082 | v4l2_ctrl_auto_cluster(ncontrols: 3, controls: &ctrls->auto_wb, manual_val: 0, set_volatile: false); |
2083 | } |
2084 | |
2085 | ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, |
2086 | V4L2_CID_BLUE_BALANCE, |
2087 | min: alvium->min_bbalance, |
2088 | max: alvium->max_bbalance, |
2089 | step: alvium->inc_bbalance, |
2090 | def: alvium->dft_bbalance); |
2091 | ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, |
2092 | V4L2_CID_RED_BALANCE, |
2093 | min: alvium->min_rbalance, |
2094 | max: alvium->max_rbalance, |
2095 | step: alvium->inc_rbalance, |
2096 | def: alvium->dft_rbalance); |
2097 | |
2098 | /* Auto/manual exposure */ |
2099 | if (alvium->avail_ft.auto_exp) { |
2100 | ctrls->auto_exp = |
2101 | v4l2_ctrl_new_std_menu(hdl, ops, |
2102 | V4L2_CID_EXPOSURE_AUTO, |
2103 | max: V4L2_EXPOSURE_MANUAL, mask: 0, |
2104 | def: V4L2_EXPOSURE_AUTO); |
2105 | v4l2_ctrl_auto_cluster(ncontrols: 2, controls: &ctrls->auto_exp, manual_val: 1, set_volatile: true); |
2106 | } |
2107 | |
2108 | ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, |
2109 | V4L2_CID_EXPOSURE, |
2110 | min: alvium->min_exp, |
2111 | max: alvium->max_exp, |
2112 | step: alvium->inc_exp, |
2113 | def: alvium->dft_exp); |
2114 | ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE; |
2115 | |
2116 | /* Auto/manual gain */ |
2117 | if (alvium->avail_ft.auto_gain) { |
2118 | ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, |
2119 | V4L2_CID_AUTOGAIN, |
2120 | min: 0, max: 1, step: 1, def: 1); |
2121 | v4l2_ctrl_auto_cluster(ncontrols: 2, controls: &ctrls->auto_gain, manual_val: 0, set_volatile: true); |
2122 | } |
2123 | |
2124 | if (alvium->avail_ft.gain) { |
2125 | ctrls->gain = v4l2_ctrl_new_std(hdl, ops, |
2126 | V4L2_CID_GAIN, |
2127 | min: alvium->min_gain, |
2128 | max: alvium->max_gain, |
2129 | step: alvium->inc_gain, |
2130 | def: alvium->dft_gain); |
2131 | ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE; |
2132 | } |
2133 | |
2134 | if (alvium->avail_ft.sat) |
2135 | ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, |
2136 | V4L2_CID_SATURATION, |
2137 | min: alvium->min_sat, |
2138 | max: alvium->max_sat, |
2139 | step: alvium->inc_sat, |
2140 | def: alvium->dft_sat); |
2141 | |
2142 | if (alvium->avail_ft.hue) |
2143 | ctrls->hue = v4l2_ctrl_new_std(hdl, ops, |
2144 | V4L2_CID_HUE, |
2145 | min: alvium->min_hue, |
2146 | max: alvium->max_hue, |
2147 | step: alvium->inc_hue, |
2148 | def: alvium->dft_hue); |
2149 | |
2150 | if (alvium->avail_ft.contrast) |
2151 | ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, |
2152 | V4L2_CID_CONTRAST, |
2153 | min: alvium->min_contrast, |
2154 | max: alvium->max_contrast, |
2155 | step: alvium->inc_contrast, |
2156 | def: alvium->dft_contrast); |
2157 | |
2158 | if (alvium->avail_ft.gamma) |
2159 | ctrls->gamma = v4l2_ctrl_new_std(hdl, ops, |
2160 | V4L2_CID_GAMMA, |
2161 | min: alvium->min_gamma, |
2162 | max: alvium->max_gamma, |
2163 | step: alvium->inc_gamma, |
2164 | def: alvium->dft_gamma); |
2165 | |
2166 | if (alvium->avail_ft.sharp) |
2167 | ctrls->sharpness = v4l2_ctrl_new_std(hdl, ops, |
2168 | V4L2_CID_SHARPNESS, |
2169 | min: alvium->min_sharp, |
2170 | max: alvium->max_sharp, |
2171 | step: alvium->inc_sharp, |
2172 | def: alvium->dft_sharp); |
2173 | |
2174 | if (alvium->avail_ft.rev_x) |
2175 | ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, |
2176 | V4L2_CID_HFLIP, |
2177 | min: 0, max: 1, step: 1, def: 0); |
2178 | |
2179 | if (alvium->avail_ft.rev_y) |
2180 | ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, |
2181 | V4L2_CID_VFLIP, |
2182 | min: 0, max: 1, step: 1, def: 0); |
2183 | |
2184 | if (hdl->error) { |
2185 | ret = hdl->error; |
2186 | goto free_ctrls; |
2187 | } |
2188 | |
2189 | ret = v4l2_fwnode_device_parse(dev: &alvium->i2c_client->dev, props: &props); |
2190 | if (ret) |
2191 | goto free_ctrls; |
2192 | |
2193 | ret = v4l2_ctrl_new_fwnode_properties(hdl, ctrl_ops: ops, p: &props); |
2194 | if (ret) |
2195 | goto free_ctrls; |
2196 | |
2197 | alvium->sd.ctrl_handler = hdl; |
2198 | return 0; |
2199 | |
2200 | free_ctrls: |
2201 | v4l2_ctrl_handler_free(hdl); |
2202 | return ret; |
2203 | } |
2204 | |
2205 | static const struct v4l2_subdev_core_ops alvium_core_ops = { |
2206 | .log_status = v4l2_ctrl_subdev_log_status, |
2207 | .subscribe_event = v4l2_ctrl_subdev_subscribe_event, |
2208 | .unsubscribe_event = v4l2_event_subdev_unsubscribe, |
2209 | }; |
2210 | |
2211 | static const struct v4l2_subdev_video_ops alvium_video_ops = { |
2212 | .s_stream = alvium_s_stream, |
2213 | }; |
2214 | |
2215 | static const struct v4l2_subdev_pad_ops alvium_pad_ops = { |
2216 | .enum_mbus_code = alvium_enum_mbus_code, |
2217 | .get_fmt = v4l2_subdev_get_fmt, |
2218 | .set_fmt = alvium_set_fmt, |
2219 | .get_selection = alvium_get_selection, |
2220 | .set_selection = alvium_set_selection, |
2221 | .get_frame_interval = v4l2_subdev_get_frame_interval, |
2222 | .set_frame_interval = alvium_s_frame_interval, |
2223 | }; |
2224 | |
2225 | static const struct v4l2_subdev_internal_ops alvium_internal_ops = { |
2226 | .init_state = alvium_init_state, |
2227 | }; |
2228 | |
2229 | static const struct v4l2_subdev_ops alvium_subdev_ops = { |
2230 | .core = &alvium_core_ops, |
2231 | .pad = &alvium_pad_ops, |
2232 | .video = &alvium_video_ops, |
2233 | }; |
2234 | |
2235 | static int alvium_subdev_init(struct alvium_dev *alvium) |
2236 | { |
2237 | struct i2c_client *client = alvium->i2c_client; |
2238 | struct device *dev = &alvium->i2c_client->dev; |
2239 | struct v4l2_subdev *sd = &alvium->sd; |
2240 | int ret; |
2241 | |
2242 | /* Setup the initial mode */ |
2243 | alvium->mode.fmt = alvium_csi2_default_fmt; |
2244 | alvium->mode.width = alvium_csi2_default_fmt.width; |
2245 | alvium->mode.height = alvium_csi2_default_fmt.height; |
2246 | alvium->mode.crop.left = alvium->min_offx; |
2247 | alvium->mode.crop.top = alvium->min_offy; |
2248 | alvium->mode.crop.width = alvium_csi2_default_fmt.width; |
2249 | alvium->mode.crop.height = alvium_csi2_default_fmt.height; |
2250 | |
2251 | /* init alvium sd */ |
2252 | v4l2_i2c_subdev_init(sd, client, ops: &alvium_subdev_ops); |
2253 | |
2254 | sd->internal_ops = &alvium_internal_ops; |
2255 | sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE; |
2256 | alvium->pad.flags = MEDIA_PAD_FL_SOURCE; |
2257 | sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; |
2258 | |
2259 | ret = media_entity_pads_init(entity: &sd->entity, num_pads: 1, pads: &alvium->pad); |
2260 | if (ret) { |
2261 | dev_err(dev, "Could not register media entity\n" ); |
2262 | return ret; |
2263 | } |
2264 | |
2265 | ret = alvium_ctrl_init(alvium); |
2266 | if (ret) { |
2267 | dev_err(dev, "Control initialization error %d\n" , ret); |
2268 | goto entity_cleanup; |
2269 | } |
2270 | |
2271 | alvium->sd.state_lock = alvium->ctrls.handler.lock; |
2272 | |
2273 | ret = v4l2_subdev_init_finalize(sd); |
2274 | if (ret < 0) { |
2275 | dev_err(dev, "subdev initialization error %d\n" , ret); |
2276 | goto err_ctrls; |
2277 | } |
2278 | |
2279 | return 0; |
2280 | |
2281 | err_ctrls: |
2282 | v4l2_ctrl_handler_free(hdl: &alvium->ctrls.handler); |
2283 | entity_cleanup: |
2284 | media_entity_cleanup(entity: &alvium->sd.entity); |
2285 | return ret; |
2286 | } |
2287 | |
2288 | static void alvium_subdev_cleanup(struct alvium_dev *alvium) |
2289 | { |
2290 | v4l2_fwnode_endpoint_free(vep: &alvium->ep); |
2291 | v4l2_subdev_cleanup(sd: &alvium->sd); |
2292 | media_entity_cleanup(entity: &alvium->sd.entity); |
2293 | v4l2_ctrl_handler_free(hdl: &alvium->ctrls.handler); |
2294 | } |
2295 | |
2296 | static int alvium_get_dt_data(struct alvium_dev *alvium) |
2297 | { |
2298 | struct device *dev = &alvium->i2c_client->dev; |
2299 | struct fwnode_handle *fwnode = dev_fwnode(dev); |
2300 | struct fwnode_handle *endpoint; |
2301 | |
2302 | if (!fwnode) |
2303 | return -EINVAL; |
2304 | |
2305 | /* Only CSI2 is supported for now: */ |
2306 | alvium->ep.bus_type = V4L2_MBUS_CSI2_DPHY; |
2307 | |
2308 | endpoint = fwnode_graph_get_endpoint_by_id(fwnode, port: 0, endpoint: 0, flags: 0); |
2309 | if (!endpoint) { |
2310 | dev_err(dev, "endpoint node not found\n" ); |
2311 | return -EINVAL; |
2312 | } |
2313 | |
2314 | if (v4l2_fwnode_endpoint_alloc_parse(fwnode: endpoint, vep: &alvium->ep)) { |
2315 | dev_err(dev, "could not parse endpoint\n" ); |
2316 | goto error_out; |
2317 | } |
2318 | |
2319 | if (!alvium->ep.nr_of_link_frequencies) { |
2320 | dev_err(dev, "no link frequencies defined" ); |
2321 | goto error_out; |
2322 | } |
2323 | |
2324 | return 0; |
2325 | |
2326 | error_out: |
2327 | v4l2_fwnode_endpoint_free(vep: &alvium->ep); |
2328 | fwnode_handle_put(fwnode: endpoint); |
2329 | |
2330 | return -EINVAL; |
2331 | } |
2332 | |
2333 | static int alvium_set_power(struct alvium_dev *alvium, bool on) |
2334 | { |
2335 | int ret; |
2336 | |
2337 | if (!on) |
2338 | return regulator_disable(regulator: alvium->reg_vcc); |
2339 | |
2340 | ret = regulator_enable(regulator: alvium->reg_vcc); |
2341 | if (ret) |
2342 | return ret; |
2343 | |
2344 | /* alvium boot time 7s */ |
2345 | msleep(msecs: 7000); |
2346 | return 0; |
2347 | } |
2348 | |
2349 | static int alvium_runtime_resume(struct device *dev) |
2350 | { |
2351 | struct v4l2_subdev *sd = dev_get_drvdata(dev); |
2352 | struct alvium_dev *alvium = sd_to_alvium(sd); |
2353 | int ret; |
2354 | |
2355 | ret = alvium_set_power(alvium, on: true); |
2356 | if (ret) |
2357 | return ret; |
2358 | |
2359 | ret = alvium_hw_init(alvium); |
2360 | if (ret) { |
2361 | alvium_set_power(alvium, on: false); |
2362 | return ret; |
2363 | } |
2364 | |
2365 | return 0; |
2366 | } |
2367 | |
2368 | static int alvium_runtime_suspend(struct device *dev) |
2369 | { |
2370 | struct v4l2_subdev *sd = dev_get_drvdata(dev); |
2371 | struct alvium_dev *alvium = sd_to_alvium(sd); |
2372 | |
2373 | alvium_set_power(alvium, on: false); |
2374 | |
2375 | return 0; |
2376 | } |
2377 | |
2378 | static const struct dev_pm_ops alvium_pm_ops = { |
2379 | RUNTIME_PM_OPS(alvium_runtime_suspend, alvium_runtime_resume, NULL) |
2380 | }; |
2381 | |
2382 | static int alvium_probe(struct i2c_client *client) |
2383 | { |
2384 | struct device *dev = &client->dev; |
2385 | struct alvium_dev *alvium; |
2386 | int ret; |
2387 | |
2388 | alvium = devm_kzalloc(dev, size: sizeof(*alvium), GFP_KERNEL); |
2389 | if (!alvium) |
2390 | return -ENOMEM; |
2391 | |
2392 | alvium->i2c_client = client; |
2393 | |
2394 | alvium->regmap = devm_cci_regmap_init_i2c(client, reg_addr_bits: 16); |
2395 | if (IS_ERR(ptr: alvium->regmap)) |
2396 | return PTR_ERR(ptr: alvium->regmap); |
2397 | |
2398 | ret = alvium_get_dt_data(alvium); |
2399 | if (ret) |
2400 | return ret; |
2401 | |
2402 | alvium->reg_vcc = devm_regulator_get_optional(dev, id: "vcc-ext-in" ); |
2403 | if (IS_ERR(ptr: alvium->reg_vcc)) |
2404 | return dev_err_probe(dev, err: PTR_ERR(ptr: alvium->reg_vcc), |
2405 | fmt: "no vcc-ext-in regulator provided\n" ); |
2406 | |
2407 | ret = alvium_set_power(alvium, on: true); |
2408 | if (ret) |
2409 | goto err_powerdown; |
2410 | |
2411 | if (!alvium_is_alive(alvium)) { |
2412 | ret = -ENODEV; |
2413 | dev_err_probe(dev, err: ret, fmt: "Device detection failed\n" ); |
2414 | goto err_powerdown; |
2415 | } |
2416 | |
2417 | ret = alvium_get_hw_info(alvium); |
2418 | if (ret) { |
2419 | dev_err_probe(dev, err: ret, fmt: "get_hw_info fail\n" ); |
2420 | goto err_powerdown; |
2421 | } |
2422 | |
2423 | ret = alvium_hw_init(alvium); |
2424 | if (ret) { |
2425 | dev_err_probe(dev, err: ret, fmt: "hw_init fail\n" ); |
2426 | goto err_powerdown; |
2427 | } |
2428 | |
2429 | ret = alvium_setup_mipi_fmt(alvium); |
2430 | if (ret) { |
2431 | dev_err_probe(dev, err: ret, fmt: "setup_mipi_fmt fail\n" ); |
2432 | goto err_powerdown; |
2433 | } |
2434 | |
2435 | /* |
2436 | * Enable runtime PM without autosuspend: |
2437 | * |
2438 | * Don't use pm autosuspend (alvium have ~7s boot time). |
2439 | * Alvium has been powered manually: |
2440 | * - mark it as active |
2441 | * - increase the usage count without resuming the device. |
2442 | */ |
2443 | pm_runtime_set_active(dev); |
2444 | pm_runtime_get_noresume(dev); |
2445 | pm_runtime_enable(dev); |
2446 | |
2447 | /* Initialize the V4L2 subdev. */ |
2448 | ret = alvium_subdev_init(alvium); |
2449 | if (ret) |
2450 | goto err_pm; |
2451 | |
2452 | ret = v4l2_async_register_subdev(sd: &alvium->sd); |
2453 | if (ret < 0) { |
2454 | dev_err_probe(dev, err: ret, fmt: "Could not register v4l2 device\n" ); |
2455 | goto err_subdev; |
2456 | } |
2457 | |
2458 | return 0; |
2459 | |
2460 | err_subdev: |
2461 | alvium_subdev_cleanup(alvium); |
2462 | err_pm: |
2463 | pm_runtime_disable(dev); |
2464 | pm_runtime_put_noidle(dev); |
2465 | kfree(objp: alvium->alvium_csi2_fmt); |
2466 | err_powerdown: |
2467 | alvium_set_power(alvium, on: false); |
2468 | |
2469 | return ret; |
2470 | } |
2471 | |
2472 | static void alvium_remove(struct i2c_client *client) |
2473 | { |
2474 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
2475 | struct alvium_dev *alvium = sd_to_alvium(sd); |
2476 | struct device *dev = &alvium->i2c_client->dev; |
2477 | |
2478 | v4l2_async_unregister_subdev(sd); |
2479 | alvium_subdev_cleanup(alvium); |
2480 | kfree(objp: alvium->alvium_csi2_fmt); |
2481 | /* |
2482 | * Disable runtime PM. In case runtime PM is disabled in the kernel, |
2483 | * make sure to turn power off manually. |
2484 | */ |
2485 | pm_runtime_disable(dev); |
2486 | if (!pm_runtime_status_suspended(dev)) |
2487 | alvium_set_power(alvium, on: false); |
2488 | pm_runtime_set_suspended(dev); |
2489 | } |
2490 | |
2491 | static const struct of_device_id alvium_of_ids[] = { |
2492 | { .compatible = "alliedvision,alvium-csi2" , }, |
2493 | { } |
2494 | }; |
2495 | MODULE_DEVICE_TABLE(of, alvium_of_ids); |
2496 | |
2497 | static struct i2c_driver alvium_i2c_driver = { |
2498 | .driver = { |
2499 | .name = "alvium-csi2" , |
2500 | .pm = pm_ptr(&alvium_pm_ops), |
2501 | .of_match_table = alvium_of_ids, |
2502 | }, |
2503 | .probe = alvium_probe, |
2504 | .remove = alvium_remove, |
2505 | }; |
2506 | |
2507 | module_i2c_driver(alvium_i2c_driver); |
2508 | |
2509 | MODULE_DESCRIPTION("Allied Vision's Alvium Camera Driver" ); |
2510 | MODULE_AUTHOR("Tommaso Merciai <tomm.merciai@gmail.com>" ); |
2511 | MODULE_AUTHOR("Martin Hecht <martin.hecht@avnet.eu>" ); |
2512 | MODULE_AUTHOR("Avnet Silica Software & Services EMEA" ); |
2513 | MODULE_LICENSE("GPL" ); |
2514 | |