1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Aptina Sensor PLL Configuration |
4 | * |
5 | * Copyright (C) 2012 Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
6 | */ |
7 | |
8 | #include <linux/device.h> |
9 | #include <linux/gcd.h> |
10 | #include <linux/kernel.h> |
11 | #include <linux/module.h> |
12 | |
13 | #include "aptina-pll.h" |
14 | |
15 | int aptina_pll_calculate(struct device *dev, |
16 | const struct aptina_pll_limits *limits, |
17 | struct aptina_pll *pll) |
18 | { |
19 | unsigned int mf_min; |
20 | unsigned int mf_max; |
21 | unsigned int p1_min; |
22 | unsigned int p1_max; |
23 | unsigned int p1; |
24 | unsigned int div; |
25 | |
26 | dev_dbg(dev, "PLL: ext clock %u pix clock %u\n" , |
27 | pll->ext_clock, pll->pix_clock); |
28 | |
29 | if (pll->ext_clock < limits->ext_clock_min || |
30 | pll->ext_clock > limits->ext_clock_max) { |
31 | dev_err(dev, "pll: invalid external clock frequency.\n" ); |
32 | return -EINVAL; |
33 | } |
34 | |
35 | if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { |
36 | dev_err(dev, "pll: invalid pixel clock frequency.\n" ); |
37 | return -EINVAL; |
38 | } |
39 | |
40 | /* Compute the multiplier M and combined N*P1 divisor. */ |
41 | div = gcd(a: pll->pix_clock, b: pll->ext_clock); |
42 | pll->m = pll->pix_clock / div; |
43 | div = pll->ext_clock / div; |
44 | |
45 | /* We now have the smallest M and N*P1 values that will result in the |
46 | * desired pixel clock frequency, but they might be out of the valid |
47 | * range. Compute the factor by which we should multiply them given the |
48 | * following constraints: |
49 | * |
50 | * - minimum/maximum multiplier |
51 | * - minimum/maximum multiplier output clock frequency assuming the |
52 | * minimum/maximum N value |
53 | * - minimum/maximum combined N*P1 divisor |
54 | */ |
55 | mf_min = DIV_ROUND_UP(limits->m_min, pll->m); |
56 | mf_min = max(mf_min, limits->out_clock_min / |
57 | (pll->ext_clock / limits->n_min * pll->m)); |
58 | mf_min = max(mf_min, limits->n_min * limits->p1_min / div); |
59 | mf_max = limits->m_max / pll->m; |
60 | mf_max = min(mf_max, limits->out_clock_max / |
61 | (pll->ext_clock / limits->n_max * pll->m)); |
62 | mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div)); |
63 | |
64 | dev_dbg(dev, "pll: mf min %u max %u\n" , mf_min, mf_max); |
65 | if (mf_min > mf_max) { |
66 | dev_err(dev, "pll: no valid combined N*P1 divisor.\n" ); |
67 | return -EINVAL; |
68 | } |
69 | |
70 | /* |
71 | * We're looking for the highest acceptable P1 value for which a |
72 | * multiplier factor MF exists that fulfills the following conditions: |
73 | * |
74 | * 1. p1 is in the [p1_min, p1_max] range given by the limits and is |
75 | * even |
76 | * 2. mf is in the [mf_min, mf_max] range computed above |
77 | * 3. div * mf is a multiple of p1, in order to compute |
78 | * n = div * mf / p1 |
79 | * m = pll->m * mf |
80 | * 4. the internal clock frequency, given by ext_clock / n, is in the |
81 | * [int_clock_min, int_clock_max] range given by the limits |
82 | * 5. the output clock frequency, given by ext_clock / n * m, is in the |
83 | * [out_clock_min, out_clock_max] range given by the limits |
84 | * |
85 | * The first naive approach is to iterate over all p1 values acceptable |
86 | * according to (1) and all mf values acceptable according to (2), and |
87 | * stop at the first combination that fulfills (3), (4) and (5). This |
88 | * has a O(n^2) complexity. |
89 | * |
90 | * Instead of iterating over all mf values in the [mf_min, mf_max] range |
91 | * we can compute the mf increment between two acceptable values |
92 | * according to (3) with |
93 | * |
94 | * mf_inc = p1 / gcd(div, p1) (6) |
95 | * |
96 | * and round the minimum up to the nearest multiple of mf_inc. This will |
97 | * restrict the number of mf values to be checked. |
98 | * |
99 | * Furthermore, conditions (4) and (5) only restrict the range of |
100 | * acceptable p1 and mf values by modifying the minimum and maximum |
101 | * limits. (5) can be expressed as |
102 | * |
103 | * ext_clock / (div * mf / p1) * m * mf >= out_clock_min |
104 | * ext_clock / (div * mf / p1) * m * mf <= out_clock_max |
105 | * |
106 | * or |
107 | * |
108 | * p1 >= out_clock_min * div / (ext_clock * m) (7) |
109 | * p1 <= out_clock_max * div / (ext_clock * m) |
110 | * |
111 | * Similarly, (4) can be expressed as |
112 | * |
113 | * mf >= ext_clock * p1 / (int_clock_max * div) (8) |
114 | * mf <= ext_clock * p1 / (int_clock_min * div) |
115 | * |
116 | * We can thus iterate over the restricted p1 range defined by the |
117 | * combination of (1) and (7), and then compute the restricted mf range |
118 | * defined by the combination of (2), (6) and (8). If the resulting mf |
119 | * range is not empty, any value in the mf range is acceptable. We thus |
120 | * select the mf lwoer bound and the corresponding p1 value. |
121 | */ |
122 | if (limits->p1_min == 0) { |
123 | dev_err(dev, "pll: P1 minimum value must be >0.\n" ); |
124 | return -EINVAL; |
125 | } |
126 | |
127 | p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div, |
128 | pll->ext_clock * pll->m)); |
129 | p1_max = min(limits->p1_max, limits->out_clock_max * div / |
130 | (pll->ext_clock * pll->m)); |
131 | |
132 | for (p1 = p1_max & ~1; p1 >= p1_min; p1 -= 2) { |
133 | unsigned int mf_inc = p1 / gcd(a: div, b: p1); |
134 | unsigned int mf_high; |
135 | unsigned int mf_low; |
136 | |
137 | mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1, |
138 | limits->int_clock_max * div)), mf_inc); |
139 | mf_high = min(mf_max, pll->ext_clock * p1 / |
140 | (limits->int_clock_min * div)); |
141 | |
142 | if (mf_low > mf_high) |
143 | continue; |
144 | |
145 | pll->n = div * mf_low / p1; |
146 | pll->m *= mf_low; |
147 | pll->p1 = p1; |
148 | dev_dbg(dev, "PLL: N %u M %u P1 %u\n" , pll->n, pll->m, pll->p1); |
149 | return 0; |
150 | } |
151 | |
152 | dev_err(dev, "pll: no valid N and P1 divisors found.\n" ); |
153 | return -EINVAL; |
154 | } |
155 | EXPORT_SYMBOL_GPL(aptina_pll_calculate); |
156 | |
157 | MODULE_DESCRIPTION("Aptina PLL Helpers" ); |
158 | MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>" ); |
159 | MODULE_LICENSE("GPL v2" ); |
160 | |