1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2020 MediaTek Inc. |
3 | |
4 | #include <linux/delay.h> |
5 | #include <linux/i2c.h> |
6 | #include <linux/module.h> |
7 | #include <linux/pm_runtime.h> |
8 | #include <linux/regulator/consumer.h> |
9 | #include <media/v4l2-async.h> |
10 | #include <media/v4l2-ctrls.h> |
11 | #include <media/v4l2-device.h> |
12 | #include <media/v4l2-fwnode.h> |
13 | #include <media/v4l2-subdev.h> |
14 | |
15 | #define DW9768_NAME "dw9768" |
16 | #define DW9768_MAX_FOCUS_POS (1024 - 1) |
17 | /* |
18 | * This sets the minimum granularity for the focus positions. |
19 | * A value of 1 gives maximum accuracy for a desired focus position |
20 | */ |
21 | #define DW9768_FOCUS_STEPS 1 |
22 | |
23 | /* |
24 | * Ring control and Power control register |
25 | * Bit[1] RING_EN |
26 | * 0: Direct mode |
27 | * 1: AAC mode (ringing control mode) |
28 | * Bit[0] PD |
29 | * 0: Normal operation mode |
30 | * 1: Power down mode |
31 | * DW9768 requires waiting time of Topr after PD reset takes place. |
32 | */ |
33 | #define DW9768_RING_PD_CONTROL_REG 0x02 |
34 | #define DW9768_PD_MODE_OFF 0x00 |
35 | #define DW9768_PD_MODE_EN BIT(0) |
36 | #define DW9768_AAC_MODE_EN BIT(1) |
37 | |
38 | /* |
39 | * DW9768 separates two registers to control the VCM position. |
40 | * One for MSB value, another is LSB value. |
41 | * DAC_MSB: D[9:8] (ADD: 0x03) |
42 | * DAC_LSB: D[7:0] (ADD: 0x04) |
43 | * D[9:0] DAC data input: positive output current = D[9:0] / 1023 * 100[mA] |
44 | */ |
45 | #define DW9768_MSB_ADDR 0x03 |
46 | #define DW9768_LSB_ADDR 0x04 |
47 | #define DW9768_STATUS_ADDR 0x05 |
48 | |
49 | /* |
50 | * AAC mode control & prescale register |
51 | * Bit[7:5] Namely AC[2:0], decide the VCM mode and operation time. |
52 | * 001 AAC2 0.48 x Tvib |
53 | * 010 AAC3 0.70 x Tvib |
54 | * 011 AAC4 0.75 x Tvib |
55 | * 101 AAC8 1.13 x Tvib |
56 | * Bit[2:0] Namely PRESC[2:0], set the internal clock dividing rate as follow. |
57 | * 000 2 |
58 | * 001 1 |
59 | * 010 1/2 |
60 | * 011 1/4 |
61 | * 100 8 |
62 | * 101 4 |
63 | */ |
64 | #define DW9768_AAC_PRESC_REG 0x06 |
65 | #define DW9768_AAC_MODE_SEL_MASK GENMASK(7, 5) |
66 | #define DW9768_CLOCK_PRE_SCALE_SEL_MASK GENMASK(2, 0) |
67 | |
68 | /* |
69 | * VCM period of vibration register |
70 | * Bit[5:0] Defined as VCM rising periodic time (Tvib) together with PRESC[2:0] |
71 | * Tvib = (6.3ms + AACT[5:0] * 0.1ms) * Dividing Rate |
72 | * Dividing Rate is the internal clock dividing rate that is defined at |
73 | * PRESCALE register (ADD: 0x06) |
74 | */ |
75 | #define DW9768_AAC_TIME_REG 0x07 |
76 | |
77 | /* |
78 | * DW9768 requires waiting time (delay time) of t_OPR after power-up, |
79 | * or in the case of PD reset taking place. |
80 | */ |
81 | #define DW9768_T_OPR_US 1000 |
82 | #define DW9768_TVIB_MS_BASE10 (64 - 1) |
83 | #define DW9768_AAC_MODE_DEFAULT 2 |
84 | #define DW9768_AAC_TIME_DEFAULT 0x20 |
85 | #define DW9768_CLOCK_PRE_SCALE_DEFAULT 1 |
86 | |
87 | /* |
88 | * This acts as the minimum granularity of lens movement. |
89 | * Keep this value power of 2, so the control steps can be |
90 | * uniformly adjusted for gradual lens movement, with desired |
91 | * number of control steps. |
92 | */ |
93 | #define DW9768_MOVE_STEPS 16 |
94 | |
95 | static const char * const dw9768_supply_names[] = { |
96 | "vin" , /* Digital I/O power */ |
97 | "vdd" , /* Digital core power */ |
98 | }; |
99 | |
100 | /* dw9768 device structure */ |
101 | struct dw9768 { |
102 | struct regulator_bulk_data supplies[ARRAY_SIZE(dw9768_supply_names)]; |
103 | struct v4l2_ctrl_handler ctrls; |
104 | struct v4l2_ctrl *focus; |
105 | struct v4l2_subdev sd; |
106 | |
107 | u32 aac_mode; |
108 | u32 aac_timing; |
109 | u32 clock_presc; |
110 | u32 move_delay_us; |
111 | }; |
112 | |
113 | static inline struct dw9768 *sd_to_dw9768(struct v4l2_subdev *subdev) |
114 | { |
115 | return container_of(subdev, struct dw9768, sd); |
116 | } |
117 | |
118 | struct regval_list { |
119 | u8 reg_num; |
120 | u8 value; |
121 | }; |
122 | |
123 | struct dw9768_aac_mode_ot_multi { |
124 | u32 aac_mode_enum; |
125 | u32 ot_multi_base100; |
126 | }; |
127 | |
128 | struct dw9768_clk_presc_dividing_rate { |
129 | u32 clk_presc_enum; |
130 | u32 dividing_rate_base100; |
131 | }; |
132 | |
133 | static const struct dw9768_aac_mode_ot_multi aac_mode_ot_multi[] = { |
134 | {1, 48}, |
135 | {2, 70}, |
136 | {3, 75}, |
137 | {5, 113}, |
138 | }; |
139 | |
140 | static const struct dw9768_clk_presc_dividing_rate presc_dividing_rate[] = { |
141 | {0, 200}, |
142 | {1, 100}, |
143 | {2, 50}, |
144 | {3, 25}, |
145 | {4, 800}, |
146 | {5, 400}, |
147 | }; |
148 | |
149 | static u32 dw9768_find_ot_multi(u32 aac_mode_param) |
150 | { |
151 | u32 cur_ot_multi_base100 = 70; |
152 | unsigned int i; |
153 | |
154 | for (i = 0; i < ARRAY_SIZE(aac_mode_ot_multi); i++) { |
155 | if (aac_mode_ot_multi[i].aac_mode_enum == aac_mode_param) { |
156 | cur_ot_multi_base100 = |
157 | aac_mode_ot_multi[i].ot_multi_base100; |
158 | } |
159 | } |
160 | |
161 | return cur_ot_multi_base100; |
162 | } |
163 | |
164 | static u32 dw9768_find_dividing_rate(u32 presc_param) |
165 | { |
166 | u32 cur_clk_dividing_rate_base100 = 100; |
167 | unsigned int i; |
168 | |
169 | for (i = 0; i < ARRAY_SIZE(presc_dividing_rate); i++) { |
170 | if (presc_dividing_rate[i].clk_presc_enum == presc_param) { |
171 | cur_clk_dividing_rate_base100 = |
172 | presc_dividing_rate[i].dividing_rate_base100; |
173 | } |
174 | } |
175 | |
176 | return cur_clk_dividing_rate_base100; |
177 | } |
178 | |
179 | /* |
180 | * DW9768_AAC_PRESC_REG & DW9768_AAC_TIME_REG determine VCM operation time. |
181 | * For current VCM mode: AAC3, Operation Time would be 0.70 x Tvib. |
182 | * Tvib = (6.3ms + AACT[5:0] * 0.1MS) * Dividing Rate. |
183 | * Below is calculation of the operation delay for each step. |
184 | */ |
185 | static inline u32 dw9768_cal_move_delay(u32 aac_mode_param, u32 presc_param, |
186 | u32 aac_timing_param) |
187 | { |
188 | u32 Tvib_us; |
189 | u32 ot_multi_base100; |
190 | u32 clk_dividing_rate_base100; |
191 | |
192 | ot_multi_base100 = dw9768_find_ot_multi(aac_mode_param); |
193 | |
194 | clk_dividing_rate_base100 = dw9768_find_dividing_rate(presc_param); |
195 | |
196 | Tvib_us = (DW9768_TVIB_MS_BASE10 + aac_timing_param) * |
197 | clk_dividing_rate_base100; |
198 | |
199 | return Tvib_us * ot_multi_base100 / 100; |
200 | } |
201 | |
202 | static int dw9768_mod_reg(struct dw9768 *dw9768, u8 reg, u8 mask, u8 val) |
203 | { |
204 | struct i2c_client *client = v4l2_get_subdevdata(sd: &dw9768->sd); |
205 | int ret; |
206 | |
207 | ret = i2c_smbus_read_byte_data(client, command: reg); |
208 | if (ret < 0) |
209 | return ret; |
210 | |
211 | val = ((unsigned char)ret & ~mask) | (val & mask); |
212 | |
213 | return i2c_smbus_write_byte_data(client, command: reg, value: val); |
214 | } |
215 | |
216 | static int dw9768_set_dac(struct dw9768 *dw9768, u16 val) |
217 | { |
218 | struct i2c_client *client = v4l2_get_subdevdata(sd: &dw9768->sd); |
219 | |
220 | /* Write VCM position to registers */ |
221 | return i2c_smbus_write_word_swapped(client, DW9768_MSB_ADDR, value: val); |
222 | } |
223 | |
224 | static int dw9768_init(struct dw9768 *dw9768) |
225 | { |
226 | struct i2c_client *client = v4l2_get_subdevdata(sd: &dw9768->sd); |
227 | int ret, val; |
228 | |
229 | /* Reset DW9768_RING_PD_CONTROL_REG to default status 0x00 */ |
230 | ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG, |
231 | DW9768_PD_MODE_OFF); |
232 | if (ret < 0) |
233 | return ret; |
234 | |
235 | /* |
236 | * DW9769 requires waiting delay time of t_OPR |
237 | * after PD reset takes place. |
238 | */ |
239 | usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100); |
240 | |
241 | /* Set DW9768_RING_PD_CONTROL_REG to DW9768_AAC_MODE_EN(0x01) */ |
242 | ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG, |
243 | DW9768_AAC_MODE_EN); |
244 | if (ret < 0) |
245 | return ret; |
246 | |
247 | /* Set AAC mode */ |
248 | ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG, |
249 | DW9768_AAC_MODE_SEL_MASK, |
250 | val: dw9768->aac_mode << 5); |
251 | if (ret < 0) |
252 | return ret; |
253 | |
254 | /* Set clock presc */ |
255 | if (dw9768->clock_presc != DW9768_CLOCK_PRE_SCALE_DEFAULT) { |
256 | ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG, |
257 | DW9768_CLOCK_PRE_SCALE_SEL_MASK, |
258 | val: dw9768->clock_presc); |
259 | if (ret < 0) |
260 | return ret; |
261 | } |
262 | |
263 | /* Set AAC Timing */ |
264 | if (dw9768->aac_timing != DW9768_AAC_TIME_DEFAULT) { |
265 | ret = i2c_smbus_write_byte_data(client, DW9768_AAC_TIME_REG, |
266 | value: dw9768->aac_timing); |
267 | if (ret < 0) |
268 | return ret; |
269 | } |
270 | |
271 | for (val = dw9768->focus->val % DW9768_MOVE_STEPS; |
272 | val <= dw9768->focus->val; |
273 | val += DW9768_MOVE_STEPS) { |
274 | ret = dw9768_set_dac(dw9768, val); |
275 | if (ret) { |
276 | dev_err(&client->dev, "I2C failure: %d" , ret); |
277 | return ret; |
278 | } |
279 | usleep_range(min: dw9768->move_delay_us, |
280 | max: dw9768->move_delay_us + 1000); |
281 | } |
282 | |
283 | return 0; |
284 | } |
285 | |
286 | static int dw9768_release(struct dw9768 *dw9768) |
287 | { |
288 | struct i2c_client *client = v4l2_get_subdevdata(sd: &dw9768->sd); |
289 | int ret, val; |
290 | |
291 | val = round_down(dw9768->focus->val, DW9768_MOVE_STEPS); |
292 | for ( ; val >= 0; val -= DW9768_MOVE_STEPS) { |
293 | ret = dw9768_set_dac(dw9768, val); |
294 | if (ret) { |
295 | dev_err(&client->dev, "I2C write fail: %d" , ret); |
296 | return ret; |
297 | } |
298 | usleep_range(min: dw9768->move_delay_us, |
299 | max: dw9768->move_delay_us + 1000); |
300 | } |
301 | |
302 | ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG, |
303 | DW9768_PD_MODE_EN); |
304 | if (ret < 0) |
305 | return ret; |
306 | |
307 | /* |
308 | * DW9769 requires waiting delay time of t_OPR |
309 | * after PD reset takes place. |
310 | */ |
311 | usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100); |
312 | |
313 | return 0; |
314 | } |
315 | |
316 | static int dw9768_runtime_suspend(struct device *dev) |
317 | { |
318 | struct v4l2_subdev *sd = dev_get_drvdata(dev); |
319 | struct dw9768 *dw9768 = sd_to_dw9768(subdev: sd); |
320 | |
321 | dw9768_release(dw9768); |
322 | regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names), |
323 | consumers: dw9768->supplies); |
324 | |
325 | return 0; |
326 | } |
327 | |
328 | static int dw9768_runtime_resume(struct device *dev) |
329 | { |
330 | struct v4l2_subdev *sd = dev_get_drvdata(dev); |
331 | struct dw9768 *dw9768 = sd_to_dw9768(subdev: sd); |
332 | int ret; |
333 | |
334 | ret = regulator_bulk_enable(ARRAY_SIZE(dw9768_supply_names), |
335 | consumers: dw9768->supplies); |
336 | if (ret < 0) { |
337 | dev_err(dev, "failed to enable regulators\n" ); |
338 | return ret; |
339 | } |
340 | |
341 | /* |
342 | * The datasheet refers to t_OPR that needs to be waited before sending |
343 | * I2C commands after power-up. |
344 | */ |
345 | usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100); |
346 | |
347 | ret = dw9768_init(dw9768); |
348 | if (ret < 0) |
349 | goto disable_regulator; |
350 | |
351 | return 0; |
352 | |
353 | disable_regulator: |
354 | regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names), |
355 | consumers: dw9768->supplies); |
356 | |
357 | return ret; |
358 | } |
359 | |
360 | static int dw9768_set_ctrl(struct v4l2_ctrl *ctrl) |
361 | { |
362 | struct dw9768 *dw9768 = container_of(ctrl->handler, |
363 | struct dw9768, ctrls); |
364 | |
365 | if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE) |
366 | return dw9768_set_dac(dw9768, val: ctrl->val); |
367 | |
368 | return 0; |
369 | } |
370 | |
371 | static const struct v4l2_ctrl_ops dw9768_ctrl_ops = { |
372 | .s_ctrl = dw9768_set_ctrl, |
373 | }; |
374 | |
375 | static int dw9768_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) |
376 | { |
377 | return pm_runtime_resume_and_get(dev: sd->dev); |
378 | } |
379 | |
380 | static int dw9768_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) |
381 | { |
382 | pm_runtime_put(dev: sd->dev); |
383 | |
384 | return 0; |
385 | } |
386 | |
387 | static const struct v4l2_subdev_internal_ops dw9768_int_ops = { |
388 | .open = dw9768_open, |
389 | .close = dw9768_close, |
390 | }; |
391 | |
392 | static const struct v4l2_subdev_ops dw9768_ops = { }; |
393 | |
394 | static int dw9768_init_controls(struct dw9768 *dw9768) |
395 | { |
396 | struct v4l2_ctrl_handler *hdl = &dw9768->ctrls; |
397 | const struct v4l2_ctrl_ops *ops = &dw9768_ctrl_ops; |
398 | |
399 | v4l2_ctrl_handler_init(hdl, 1); |
400 | |
401 | dw9768->focus = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE, min: 0, |
402 | DW9768_MAX_FOCUS_POS, |
403 | DW9768_FOCUS_STEPS, def: 0); |
404 | |
405 | if (hdl->error) |
406 | return hdl->error; |
407 | |
408 | dw9768->sd.ctrl_handler = hdl; |
409 | |
410 | return 0; |
411 | } |
412 | |
413 | static int dw9768_probe(struct i2c_client *client) |
414 | { |
415 | struct device *dev = &client->dev; |
416 | struct dw9768 *dw9768; |
417 | bool full_power; |
418 | unsigned int i; |
419 | int ret; |
420 | |
421 | dw9768 = devm_kzalloc(dev, size: sizeof(*dw9768), GFP_KERNEL); |
422 | if (!dw9768) |
423 | return -ENOMEM; |
424 | |
425 | /* Initialize subdev */ |
426 | v4l2_i2c_subdev_init(sd: &dw9768->sd, client, ops: &dw9768_ops); |
427 | |
428 | dw9768->aac_mode = DW9768_AAC_MODE_DEFAULT; |
429 | dw9768->aac_timing = DW9768_AAC_TIME_DEFAULT; |
430 | dw9768->clock_presc = DW9768_CLOCK_PRE_SCALE_DEFAULT; |
431 | |
432 | /* Optional indication of AAC mode select */ |
433 | fwnode_property_read_u32(dev_fwnode(dev), propname: "dongwoon,aac-mode" , |
434 | val: &dw9768->aac_mode); |
435 | |
436 | /* Optional indication of clock pre-scale select */ |
437 | fwnode_property_read_u32(dev_fwnode(dev), propname: "dongwoon,clock-presc" , |
438 | val: &dw9768->clock_presc); |
439 | |
440 | /* Optional indication of AAC Timing */ |
441 | fwnode_property_read_u32(dev_fwnode(dev), propname: "dongwoon,aac-timing" , |
442 | val: &dw9768->aac_timing); |
443 | |
444 | dw9768->move_delay_us = dw9768_cal_move_delay(aac_mode_param: dw9768->aac_mode, |
445 | presc_param: dw9768->clock_presc, |
446 | aac_timing_param: dw9768->aac_timing); |
447 | |
448 | for (i = 0; i < ARRAY_SIZE(dw9768_supply_names); i++) |
449 | dw9768->supplies[i].supply = dw9768_supply_names[i]; |
450 | |
451 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dw9768_supply_names), |
452 | consumers: dw9768->supplies); |
453 | if (ret) { |
454 | dev_err(dev, "failed to get regulators\n" ); |
455 | return ret; |
456 | } |
457 | |
458 | /* Initialize controls */ |
459 | ret = dw9768_init_controls(dw9768); |
460 | if (ret) |
461 | goto err_free_handler; |
462 | |
463 | /* Initialize subdev */ |
464 | dw9768->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
465 | dw9768->sd.internal_ops = &dw9768_int_ops; |
466 | |
467 | ret = media_entity_pads_init(entity: &dw9768->sd.entity, num_pads: 0, NULL); |
468 | if (ret < 0) |
469 | goto err_free_handler; |
470 | |
471 | dw9768->sd.entity.function = MEDIA_ENT_F_LENS; |
472 | |
473 | /* |
474 | * Figure out whether we're going to power up the device here. Generally |
475 | * this is done if CONFIG_PM is disabled in a DT system or the device is |
476 | * to be powered on in an ACPI system. Similarly for power off in |
477 | * remove. |
478 | */ |
479 | pm_runtime_enable(dev); |
480 | full_power = (is_acpi_node(dev_fwnode(dev)) && |
481 | acpi_dev_state_d0(dev)) || |
482 | (is_of_node(dev_fwnode(dev)) && !pm_runtime_enabled(dev)); |
483 | if (full_power) { |
484 | ret = dw9768_runtime_resume(dev); |
485 | if (ret < 0) { |
486 | dev_err(dev, "failed to power on: %d\n" , ret); |
487 | goto err_clean_entity; |
488 | } |
489 | pm_runtime_set_active(dev); |
490 | } |
491 | |
492 | ret = v4l2_async_register_subdev(sd: &dw9768->sd); |
493 | if (ret < 0) { |
494 | dev_err(dev, "failed to register V4L2 subdev: %d" , ret); |
495 | goto err_power_off; |
496 | } |
497 | |
498 | pm_runtime_idle(dev); |
499 | |
500 | return 0; |
501 | |
502 | err_power_off: |
503 | if (full_power) { |
504 | dw9768_runtime_suspend(dev); |
505 | pm_runtime_set_suspended(dev); |
506 | } |
507 | err_clean_entity: |
508 | pm_runtime_disable(dev); |
509 | media_entity_cleanup(entity: &dw9768->sd.entity); |
510 | err_free_handler: |
511 | v4l2_ctrl_handler_free(hdl: &dw9768->ctrls); |
512 | |
513 | return ret; |
514 | } |
515 | |
516 | static void dw9768_remove(struct i2c_client *client) |
517 | { |
518 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
519 | struct dw9768 *dw9768 = sd_to_dw9768(subdev: sd); |
520 | struct device *dev = &client->dev; |
521 | |
522 | v4l2_async_unregister_subdev(sd: &dw9768->sd); |
523 | v4l2_ctrl_handler_free(hdl: &dw9768->ctrls); |
524 | media_entity_cleanup(entity: &dw9768->sd.entity); |
525 | if ((is_acpi_node(dev_fwnode(dev)) && acpi_dev_state_d0(dev)) || |
526 | (is_of_node(dev_fwnode(dev)) && !pm_runtime_enabled(dev))) { |
527 | dw9768_runtime_suspend(dev); |
528 | pm_runtime_set_suspended(dev); |
529 | } |
530 | pm_runtime_disable(dev); |
531 | } |
532 | |
533 | static const struct of_device_id dw9768_of_table[] = { |
534 | { .compatible = "dongwoon,dw9768" }, |
535 | { .compatible = "giantec,gt9769" }, |
536 | {} |
537 | }; |
538 | MODULE_DEVICE_TABLE(of, dw9768_of_table); |
539 | |
540 | static const struct dev_pm_ops dw9768_pm_ops = { |
541 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
542 | pm_runtime_force_resume) |
543 | SET_RUNTIME_PM_OPS(dw9768_runtime_suspend, dw9768_runtime_resume, NULL) |
544 | }; |
545 | |
546 | static struct i2c_driver dw9768_i2c_driver = { |
547 | .driver = { |
548 | .name = DW9768_NAME, |
549 | .pm = &dw9768_pm_ops, |
550 | .of_match_table = dw9768_of_table, |
551 | }, |
552 | .probe = dw9768_probe, |
553 | .remove = dw9768_remove, |
554 | }; |
555 | module_i2c_driver(dw9768_i2c_driver); |
556 | |
557 | MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>" ); |
558 | MODULE_DESCRIPTION("DW9768 VCM driver" ); |
559 | MODULE_LICENSE("GPL v2" ); |
560 | |