1// SPDX-License-Identifier: GPL-2.0
2/*
3 * A V4L2 driver for Sony IMX219 cameras.
4 * Copyright (C) 2019, Raspberry Pi (Trading) Ltd
5 *
6 * Based on Sony imx258 camera driver
7 * Copyright (C) 2018 Intel Corporation
8 *
9 * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver
10 * Copyright 2018 Qtechnology A/S
11 *
12 * Flip handling taken from the Sony IMX319 driver.
13 * Copyright (C) 2018 Intel Corporation
14 *
15 */
16
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/gpio/consumer.h>
20#include <linux/i2c.h>
21#include <linux/minmax.h>
22#include <linux/module.h>
23#include <linux/pm_runtime.h>
24#include <linux/regulator/consumer.h>
25
26#include <media/v4l2-cci.h>
27#include <media/v4l2-ctrls.h>
28#include <media/v4l2-device.h>
29#include <media/v4l2-fwnode.h>
30#include <media/v4l2-mediabus.h>
31
32/* Chip ID */
33#define IMX219_REG_CHIP_ID CCI_REG16(0x0000)
34#define IMX219_CHIP_ID 0x0219
35
36#define IMX219_REG_MODE_SELECT CCI_REG8(0x0100)
37#define IMX219_MODE_STANDBY 0x00
38#define IMX219_MODE_STREAMING 0x01
39
40#define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114)
41#define IMX219_CSI_2_LANE_MODE 0x01
42#define IMX219_CSI_4_LANE_MODE 0x03
43
44#define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128)
45#define IMX219_DPHY_CTRL_TIMING_AUTO 0
46#define IMX219_DPHY_CTRL_TIMING_MANUAL 1
47
48#define IMX219_REG_EXCK_FREQ CCI_REG16(0x012a)
49#define IMX219_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */
50
51/* Analog gain control */
52#define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157)
53#define IMX219_ANA_GAIN_MIN 0
54#define IMX219_ANA_GAIN_MAX 232
55#define IMX219_ANA_GAIN_STEP 1
56#define IMX219_ANA_GAIN_DEFAULT 0x0
57
58/* Digital gain control */
59#define IMX219_REG_DIGITAL_GAIN CCI_REG16(0x0158)
60#define IMX219_DGTL_GAIN_MIN 0x0100
61#define IMX219_DGTL_GAIN_MAX 0x0fff
62#define IMX219_DGTL_GAIN_DEFAULT 0x0100
63#define IMX219_DGTL_GAIN_STEP 1
64
65/* Exposure control */
66#define IMX219_REG_EXPOSURE CCI_REG16(0x015a)
67#define IMX219_EXPOSURE_MIN 4
68#define IMX219_EXPOSURE_STEP 1
69#define IMX219_EXPOSURE_DEFAULT 0x640
70#define IMX219_EXPOSURE_MAX 65535
71#define IMX219_EXPOSURE_OFFSET 4
72
73/* V_TIMING internal */
74#define IMX219_REG_FRM_LENGTH_A CCI_REG16(0x0160)
75#define IMX219_FLL_MAX 0xffff
76#define IMX219_VBLANK_MIN 32
77#define IMX219_REG_LINE_LENGTH_A CCI_REG16(0x0162)
78#define IMX219_LLP_MIN 0x0d78
79#define IMX219_BINNED_LLP_MIN 0x0de8
80#define IMX219_LLP_MAX 0x7ff0
81
82#define IMX219_REG_X_ADD_STA_A CCI_REG16(0x0164)
83#define IMX219_REG_X_ADD_END_A CCI_REG16(0x0166)
84#define IMX219_REG_Y_ADD_STA_A CCI_REG16(0x0168)
85#define IMX219_REG_Y_ADD_END_A CCI_REG16(0x016a)
86#define IMX219_REG_X_OUTPUT_SIZE CCI_REG16(0x016c)
87#define IMX219_REG_Y_OUTPUT_SIZE CCI_REG16(0x016e)
88#define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170)
89#define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171)
90#define IMX219_REG_ORIENTATION CCI_REG8(0x0172)
91
92/* Binning Mode */
93#define IMX219_REG_BINNING_MODE_H CCI_REG8(0x0174)
94#define IMX219_REG_BINNING_MODE_V CCI_REG8(0x0175)
95#define IMX219_BINNING_NONE 0x00
96#define IMX219_BINNING_X2 0x01
97#define IMX219_BINNING_X2_ANALOG 0x03
98
99#define IMX219_REG_CSI_DATA_FORMAT_A CCI_REG16(0x018c)
100
101/* PLL Settings */
102#define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301)
103#define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303)
104#define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304)
105#define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305)
106#define IMX219_REG_PLL_VT_MPY CCI_REG16(0x0306)
107#define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309)
108#define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b)
109#define IMX219_REG_PLL_OP_MPY CCI_REG16(0x030c)
110
111/* Test Pattern Control */
112#define IMX219_REG_TEST_PATTERN CCI_REG16(0x0600)
113#define IMX219_TEST_PATTERN_DISABLE 0
114#define IMX219_TEST_PATTERN_SOLID_COLOR 1
115#define IMX219_TEST_PATTERN_COLOR_BARS 2
116#define IMX219_TEST_PATTERN_GREY_COLOR 3
117#define IMX219_TEST_PATTERN_PN9 4
118
119/* Test pattern colour components */
120#define IMX219_REG_TESTP_RED CCI_REG16(0x0602)
121#define IMX219_REG_TESTP_GREENR CCI_REG16(0x0604)
122#define IMX219_REG_TESTP_BLUE CCI_REG16(0x0606)
123#define IMX219_REG_TESTP_GREENB CCI_REG16(0x0608)
124#define IMX219_TESTP_COLOUR_MIN 0
125#define IMX219_TESTP_COLOUR_MAX 0x03ff
126#define IMX219_TESTP_COLOUR_STEP 1
127
128#define IMX219_REG_TP_WINDOW_WIDTH CCI_REG16(0x0624)
129#define IMX219_REG_TP_WINDOW_HEIGHT CCI_REG16(0x0626)
130
131/* External clock frequency is 24.0M */
132#define IMX219_XCLK_FREQ 24000000
133
134/* Pixel rate is fixed for all the modes */
135#define IMX219_PIXEL_RATE 182400000
136#define IMX219_PIXEL_RATE_4LANE 281600000
137
138#define IMX219_DEFAULT_LINK_FREQ 456000000
139#define IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED 363000000
140#define IMX219_DEFAULT_LINK_FREQ_4LANE 364000000
141
142/* IMX219 native and active pixel array size. */
143#define IMX219_NATIVE_WIDTH 3296U
144#define IMX219_NATIVE_HEIGHT 2480U
145#define IMX219_PIXEL_ARRAY_LEFT 8U
146#define IMX219_PIXEL_ARRAY_TOP 8U
147#define IMX219_PIXEL_ARRAY_WIDTH 3280U
148#define IMX219_PIXEL_ARRAY_HEIGHT 2464U
149
150/* Mode : resolution and related config&values */
151struct imx219_mode {
152 /* Frame width */
153 unsigned int width;
154 /* Frame height */
155 unsigned int height;
156
157 /* V-timing */
158 unsigned int fll_def;
159};
160
161static const struct cci_reg_sequence imx219_common_regs[] = {
162 { IMX219_REG_MODE_SELECT, 0x00 }, /* Mode Select */
163
164 /* To Access Addresses 3000-5fff, send the following commands */
165 { CCI_REG8(0x30eb), 0x05 },
166 { CCI_REG8(0x30eb), 0x0c },
167 { CCI_REG8(0x300a), 0xff },
168 { CCI_REG8(0x300b), 0xff },
169 { CCI_REG8(0x30eb), 0x05 },
170 { CCI_REG8(0x30eb), 0x09 },
171
172 /* Undocumented registers */
173 { CCI_REG8(0x455e), 0x00 },
174 { CCI_REG8(0x471e), 0x4b },
175 { CCI_REG8(0x4767), 0x0f },
176 { CCI_REG8(0x4750), 0x14 },
177 { CCI_REG8(0x4540), 0x00 },
178 { CCI_REG8(0x47b4), 0x14 },
179 { CCI_REG8(0x4713), 0x30 },
180 { CCI_REG8(0x478b), 0x10 },
181 { CCI_REG8(0x478f), 0x10 },
182 { CCI_REG8(0x4793), 0x10 },
183 { CCI_REG8(0x4797), 0x0e },
184 { CCI_REG8(0x479b), 0x0e },
185
186 /* Frame Bank Register Group "A" */
187 { IMX219_REG_X_ODD_INC_A, 1 },
188 { IMX219_REG_Y_ODD_INC_A, 1 },
189
190 /* Output setup registers */
191 { IMX219_REG_DPHY_CTRL, IMX219_DPHY_CTRL_TIMING_AUTO },
192 { IMX219_REG_EXCK_FREQ, IMX219_EXCK_FREQ(IMX219_XCLK_FREQ / 1000000) },
193};
194
195static const struct cci_reg_sequence imx219_2lane_regs[] = {
196 /* PLL Clock Table */
197 { IMX219_REG_VTPXCK_DIV, 5 },
198 { IMX219_REG_VTSYCK_DIV, 1 },
199 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */
200 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */
201 { IMX219_REG_PLL_VT_MPY, 57 },
202 { IMX219_REG_OPSYCK_DIV, 1 },
203 { IMX219_REG_PLL_OP_MPY, 114 },
204
205 /* 2-Lane CSI Mode */
206 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_2_LANE_MODE },
207};
208
209static const struct cci_reg_sequence imx219_4lane_regs[] = {
210 /* PLL Clock Table */
211 { IMX219_REG_VTPXCK_DIV, 5 },
212 { IMX219_REG_VTSYCK_DIV, 1 },
213 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */
214 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */
215 { IMX219_REG_PLL_VT_MPY, 88 },
216 { IMX219_REG_OPSYCK_DIV, 1 },
217 { IMX219_REG_PLL_OP_MPY, 91 },
218
219 /* 4-Lane CSI Mode */
220 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_4_LANE_MODE },
221};
222
223static const s64 imx219_link_freq_menu[] = {
224 IMX219_DEFAULT_LINK_FREQ,
225};
226
227static const s64 imx219_link_freq_4lane_menu[] = {
228 IMX219_DEFAULT_LINK_FREQ_4LANE,
229 /*
230 * This will never be advertised to userspace, but will be used for
231 * v4l2_link_freq_to_bitmap
232 */
233 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED,
234};
235
236static const char * const imx219_test_pattern_menu[] = {
237 "Disabled",
238 "Color Bars",
239 "Solid Color",
240 "Grey Color Bars",
241 "PN9"
242};
243
244static const int imx219_test_pattern_val[] = {
245 IMX219_TEST_PATTERN_DISABLE,
246 IMX219_TEST_PATTERN_COLOR_BARS,
247 IMX219_TEST_PATTERN_SOLID_COLOR,
248 IMX219_TEST_PATTERN_GREY_COLOR,
249 IMX219_TEST_PATTERN_PN9,
250};
251
252/* regulator supplies */
253static const char * const imx219_supply_name[] = {
254 /* Supplies can be enabled in any order */
255 "VANA", /* Analog (2.8V) supply */
256 "VDIG", /* Digital Core (1.8V) supply */
257 "VDDL", /* IF (1.2V) supply */
258};
259
260#define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name)
261
262/*
263 * The supported formats.
264 * This table MUST contain 4 entries per format, to cover the various flip
265 * combinations in the order
266 * - no flip
267 * - h flip
268 * - v flip
269 * - h&v flips
270 */
271static const u32 imx219_mbus_formats[] = {
272 MEDIA_BUS_FMT_SRGGB10_1X10,
273 MEDIA_BUS_FMT_SGRBG10_1X10,
274 MEDIA_BUS_FMT_SGBRG10_1X10,
275 MEDIA_BUS_FMT_SBGGR10_1X10,
276
277 MEDIA_BUS_FMT_SRGGB8_1X8,
278 MEDIA_BUS_FMT_SGRBG8_1X8,
279 MEDIA_BUS_FMT_SGBRG8_1X8,
280 MEDIA_BUS_FMT_SBGGR8_1X8,
281};
282
283/*
284 * Initialisation delay between XCLR low->high and the moment when the sensor
285 * can start capture (i.e. can leave software stanby) must be not less than:
286 * t4 + max(t5, t6 + <time to initialize the sensor register over I2C>)
287 * where
288 * t4 is fixed, and is max 200uS,
289 * t5 is fixed, and is 6000uS,
290 * t6 depends on the sensor external clock, and is max 32000 clock periods.
291 * As per sensor datasheet, the external clock must be from 6MHz to 27MHz.
292 * So for any acceptable external clock t6 is always within the range of
293 * 1185 to 5333 uS, and is always less than t5.
294 * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then
295 * initialize the sensor over I2C, and then exit the software standby.
296 *
297 * This start-up time can be optimized a bit more, if we start the writes
298 * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor
299 * initialization over I2C may complete before (t4+t5) expires, and we must
300 * ensure that capture is not started before (t4+t5).
301 *
302 * This delay doesn't account for the power supply startup time. If needed,
303 * this should be taken care of via the regulator framework. E.g. in the
304 * case of DT for regulator-fixed one should define the startup-delay-us
305 * property.
306 */
307#define IMX219_XCLR_MIN_DELAY_US 6200
308#define IMX219_XCLR_DELAY_RANGE_US 1000
309
310/* Mode configs */
311static const struct imx219_mode supported_modes[] = {
312 {
313 /* 8MPix 15fps mode */
314 .width = 3280,
315 .height = 2464,
316 .fll_def = 3526,
317 },
318 {
319 /* 1080P 30fps cropped */
320 .width = 1920,
321 .height = 1080,
322 .fll_def = 1763,
323 },
324 {
325 /* 2x2 binned 60fps mode */
326 .width = 1640,
327 .height = 1232,
328 .fll_def = 1707,
329 },
330 {
331 /* 640x480 60fps mode */
332 .width = 640,
333 .height = 480,
334 .fll_def = 1707,
335 },
336};
337
338struct imx219 {
339 struct v4l2_subdev sd;
340 struct media_pad pad;
341
342 struct regmap *regmap;
343 struct clk *xclk; /* system clock to IMX219 */
344 u32 xclk_freq;
345
346 struct gpio_desc *reset_gpio;
347 struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES];
348
349 struct v4l2_ctrl_handler ctrl_handler;
350 /* V4L2 Controls */
351 struct v4l2_ctrl *pixel_rate;
352 struct v4l2_ctrl *link_freq;
353 struct v4l2_ctrl *exposure;
354 struct v4l2_ctrl *vflip;
355 struct v4l2_ctrl *hflip;
356 struct v4l2_ctrl *vblank;
357 struct v4l2_ctrl *hblank;
358
359 /* Two or Four lanes */
360 u8 lanes;
361};
362
363static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd)
364{
365 return container_of(_sd, struct imx219, sd);
366}
367
368/* Get bayer order based on flip setting. */
369static u32 imx219_get_format_code(struct imx219 *imx219, u32 code)
370{
371 unsigned int i;
372
373 for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++)
374 if (imx219_mbus_formats[i] == code)
375 break;
376
377 if (i >= ARRAY_SIZE(imx219_mbus_formats))
378 i = 0;
379
380 i = (i & ~3) | (imx219->vflip->val ? 2 : 0) |
381 (imx219->hflip->val ? 1 : 0);
382
383 return imx219_mbus_formats[i];
384}
385
386static u32 imx219_get_format_bpp(const struct v4l2_mbus_framefmt *format)
387{
388 switch (format->code) {
389 case MEDIA_BUS_FMT_SRGGB8_1X8:
390 case MEDIA_BUS_FMT_SGRBG8_1X8:
391 case MEDIA_BUS_FMT_SGBRG8_1X8:
392 case MEDIA_BUS_FMT_SBGGR8_1X8:
393 return 8;
394
395 case MEDIA_BUS_FMT_SRGGB10_1X10:
396 case MEDIA_BUS_FMT_SGRBG10_1X10:
397 case MEDIA_BUS_FMT_SGBRG10_1X10:
398 case MEDIA_BUS_FMT_SBGGR10_1X10:
399 default:
400 return 10;
401 }
402}
403
404static void imx219_get_binning(struct v4l2_subdev_state *state, u8 *bin_h,
405 u8 *bin_v)
406{
407 const struct v4l2_mbus_framefmt *format =
408 v4l2_subdev_state_get_format(state, 0);
409 const struct v4l2_rect *crop = v4l2_subdev_state_get_crop(state, 0);
410 u32 hbin = crop->width / format->width;
411 u32 vbin = crop->height / format->height;
412
413 if (hbin == 2 && vbin == 2) {
414 *bin_h = IMX219_BINNING_X2_ANALOG;
415 *bin_v = IMX219_BINNING_X2_ANALOG;
416 } else {
417 *bin_h = IMX219_BINNING_NONE;
418 *bin_v = IMX219_BINNING_NONE;
419 }
420
421}
422
423static inline u32 imx219_get_rate_factor(struct v4l2_subdev_state *state)
424{
425 u8 bin_h, bin_v;
426
427 imx219_get_binning(state, bin_h: &bin_h, bin_v: &bin_v);
428
429 return (bin_h & bin_v) == IMX219_BINNING_X2_ANALOG ? 2 : 1;
430}
431
432/* -----------------------------------------------------------------------------
433 * Controls
434 */
435
436static int imx219_set_ctrl(struct v4l2_ctrl *ctrl)
437{
438 struct imx219 *imx219 =
439 container_of(ctrl->handler, struct imx219, ctrl_handler);
440 struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd);
441 const struct v4l2_mbus_framefmt *format;
442 struct v4l2_subdev_state *state;
443 u32 rate_factor;
444 int ret = 0;
445
446 state = v4l2_subdev_get_locked_active_state(sd: &imx219->sd);
447 format = v4l2_subdev_state_get_format(state, 0);
448 rate_factor = imx219_get_rate_factor(state);
449
450 if (ctrl->id == V4L2_CID_VBLANK) {
451 int exposure_max, exposure_def;
452
453 /* Update max exposure while meeting expected vblanking */
454 exposure_max = format->height + ctrl->val - IMX219_EXPOSURE_OFFSET;
455 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
456 exposure_max : IMX219_EXPOSURE_DEFAULT;
457 ret = __v4l2_ctrl_modify_range(ctrl: imx219->exposure,
458 min: imx219->exposure->minimum,
459 max: exposure_max,
460 step: imx219->exposure->step,
461 def: exposure_def);
462 if (ret)
463 return ret;
464
465 }
466
467 /*
468 * Applying V4L2 control value only happens
469 * when power is up for streaming
470 */
471 if (pm_runtime_get_if_in_use(dev: &client->dev) == 0)
472 return 0;
473
474 switch (ctrl->id) {
475 case V4L2_CID_ANALOGUE_GAIN:
476 cci_write(map: imx219->regmap, IMX219_REG_ANALOG_GAIN,
477 val: ctrl->val, err: &ret);
478 break;
479 case V4L2_CID_EXPOSURE:
480 cci_write(map: imx219->regmap, IMX219_REG_EXPOSURE,
481 val: ctrl->val / rate_factor, err: &ret);
482 break;
483 case V4L2_CID_DIGITAL_GAIN:
484 cci_write(map: imx219->regmap, IMX219_REG_DIGITAL_GAIN,
485 val: ctrl->val, err: &ret);
486 break;
487 case V4L2_CID_TEST_PATTERN:
488 cci_write(map: imx219->regmap, IMX219_REG_TEST_PATTERN,
489 val: imx219_test_pattern_val[ctrl->val], err: &ret);
490 break;
491 case V4L2_CID_HFLIP:
492 case V4L2_CID_VFLIP:
493 cci_write(map: imx219->regmap, IMX219_REG_ORIENTATION,
494 val: imx219->hflip->val | imx219->vflip->val << 1, err: &ret);
495 break;
496 case V4L2_CID_VBLANK:
497 cci_write(map: imx219->regmap, IMX219_REG_FRM_LENGTH_A,
498 val: (format->height + ctrl->val) / rate_factor, err: &ret);
499 break;
500 case V4L2_CID_HBLANK:
501 cci_write(map: imx219->regmap, IMX219_REG_LINE_LENGTH_A,
502 val: format->width + ctrl->val, err: &ret);
503 break;
504 case V4L2_CID_TEST_PATTERN_RED:
505 cci_write(map: imx219->regmap, IMX219_REG_TESTP_RED,
506 val: ctrl->val, err: &ret);
507 break;
508 case V4L2_CID_TEST_PATTERN_GREENR:
509 cci_write(map: imx219->regmap, IMX219_REG_TESTP_GREENR,
510 val: ctrl->val, err: &ret);
511 break;
512 case V4L2_CID_TEST_PATTERN_BLUE:
513 cci_write(map: imx219->regmap, IMX219_REG_TESTP_BLUE,
514 val: ctrl->val, err: &ret);
515 break;
516 case V4L2_CID_TEST_PATTERN_GREENB:
517 cci_write(map: imx219->regmap, IMX219_REG_TESTP_GREENB,
518 val: ctrl->val, err: &ret);
519 break;
520 default:
521 dev_info(&client->dev,
522 "ctrl(id:0x%x,val:0x%x) is not handled\n",
523 ctrl->id, ctrl->val);
524 ret = -EINVAL;
525 break;
526 }
527
528 pm_runtime_put(dev: &client->dev);
529
530 return ret;
531}
532
533static const struct v4l2_ctrl_ops imx219_ctrl_ops = {
534 .s_ctrl = imx219_set_ctrl,
535};
536
537static unsigned long imx219_get_pixel_rate(struct imx219 *imx219)
538{
539 return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE;
540}
541
542/* Initialize control handlers */
543static int imx219_init_controls(struct imx219 *imx219)
544{
545 struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd);
546 const struct imx219_mode *mode = &supported_modes[0];
547 struct v4l2_ctrl_handler *ctrl_hdlr;
548 struct v4l2_fwnode_device_properties props;
549 int exposure_max, exposure_def;
550 int i, ret;
551
552 ctrl_hdlr = &imx219->ctrl_handler;
553 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
554 if (ret)
555 return ret;
556
557 /* By default, PIXEL_RATE is read only */
558 imx219->pixel_rate = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops,
559 V4L2_CID_PIXEL_RATE,
560 min: imx219_get_pixel_rate(imx219),
561 max: imx219_get_pixel_rate(imx219), step: 1,
562 def: imx219_get_pixel_rate(imx219));
563
564 imx219->link_freq =
565 v4l2_ctrl_new_int_menu(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops,
566 V4L2_CID_LINK_FREQ,
567 ARRAY_SIZE(imx219_link_freq_menu) - 1, def: 0,
568 qmenu_int: (imx219->lanes == 2) ? imx219_link_freq_menu :
569 imx219_link_freq_4lane_menu);
570 if (imx219->link_freq)
571 imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
572
573 /* Initial blanking and exposure. Limits are updated during set_fmt */
574 imx219->vblank = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops,
575 V4L2_CID_VBLANK, IMX219_VBLANK_MIN,
576 IMX219_FLL_MAX - mode->height, step: 1,
577 def: mode->fll_def - mode->height);
578 imx219->hblank = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops,
579 V4L2_CID_HBLANK,
580 IMX219_LLP_MIN - mode->width,
581 IMX219_LLP_MAX - mode->width, step: 1,
582 IMX219_LLP_MIN - mode->width);
583 exposure_max = mode->fll_def - IMX219_EXPOSURE_OFFSET;
584 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
585 exposure_max : IMX219_EXPOSURE_DEFAULT;
586 imx219->exposure = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops,
587 V4L2_CID_EXPOSURE,
588 IMX219_EXPOSURE_MIN, max: exposure_max,
589 IMX219_EXPOSURE_STEP,
590 def: exposure_def);
591
592 v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
593 IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX,
594 IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT);
595
596 v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
597 IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX,
598 IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT);
599
600 imx219->hflip = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops,
601 V4L2_CID_HFLIP, min: 0, max: 1, step: 1, def: 0);
602 if (imx219->hflip)
603 imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
604
605 imx219->vflip = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops,
606 V4L2_CID_VFLIP, min: 0, max: 1, step: 1, def: 0);
607 if (imx219->vflip)
608 imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
609
610 v4l2_ctrl_new_std_menu_items(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops,
611 V4L2_CID_TEST_PATTERN,
612 ARRAY_SIZE(imx219_test_pattern_menu) - 1,
613 mask: 0, def: 0, qmenu: imx219_test_pattern_menu);
614 for (i = 0; i < 4; i++) {
615 /*
616 * The assumption is that
617 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1
618 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2
619 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3
620 */
621 v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops,
622 V4L2_CID_TEST_PATTERN_RED + i,
623 IMX219_TESTP_COLOUR_MIN,
624 IMX219_TESTP_COLOUR_MAX,
625 IMX219_TESTP_COLOUR_STEP,
626 IMX219_TESTP_COLOUR_MAX);
627 /* The "Solid color" pattern is white by default */
628 }
629
630 if (ctrl_hdlr->error) {
631 ret = ctrl_hdlr->error;
632 dev_err_probe(dev: &client->dev, err: ret, fmt: "Control init failed\n");
633 goto error;
634 }
635
636 ret = v4l2_fwnode_device_parse(dev: &client->dev, props: &props);
637 if (ret)
638 goto error;
639
640 ret = v4l2_ctrl_new_fwnode_properties(hdl: ctrl_hdlr, ctrl_ops: &imx219_ctrl_ops,
641 p: &props);
642 if (ret)
643 goto error;
644
645 imx219->sd.ctrl_handler = ctrl_hdlr;
646
647 return 0;
648
649error:
650 v4l2_ctrl_handler_free(hdl: ctrl_hdlr);
651
652 return ret;
653}
654
655static void imx219_free_controls(struct imx219 *imx219)
656{
657 v4l2_ctrl_handler_free(hdl: imx219->sd.ctrl_handler);
658}
659
660/* -----------------------------------------------------------------------------
661 * Subdev operations
662 */
663
664static int imx219_set_framefmt(struct imx219 *imx219,
665 struct v4l2_subdev_state *state)
666{
667 const struct v4l2_mbus_framefmt *format;
668 const struct v4l2_rect *crop;
669 u8 bin_h, bin_v;
670 u32 bpp;
671 int ret = 0;
672
673 format = v4l2_subdev_state_get_format(state, 0);
674 crop = v4l2_subdev_state_get_crop(state, 0);
675 bpp = imx219_get_format_bpp(format);
676
677 cci_write(map: imx219->regmap, IMX219_REG_X_ADD_STA_A,
678 val: crop->left - IMX219_PIXEL_ARRAY_LEFT, err: &ret);
679 cci_write(map: imx219->regmap, IMX219_REG_X_ADD_END_A,
680 val: crop->left - IMX219_PIXEL_ARRAY_LEFT + crop->width - 1, err: &ret);
681 cci_write(map: imx219->regmap, IMX219_REG_Y_ADD_STA_A,
682 val: crop->top - IMX219_PIXEL_ARRAY_TOP, err: &ret);
683 cci_write(map: imx219->regmap, IMX219_REG_Y_ADD_END_A,
684 val: crop->top - IMX219_PIXEL_ARRAY_TOP + crop->height - 1, err: &ret);
685
686 imx219_get_binning(state, bin_h: &bin_h, bin_v: &bin_v);
687 cci_write(map: imx219->regmap, IMX219_REG_BINNING_MODE_H, val: bin_h, err: &ret);
688 cci_write(map: imx219->regmap, IMX219_REG_BINNING_MODE_V, val: bin_v, err: &ret);
689
690 cci_write(map: imx219->regmap, IMX219_REG_X_OUTPUT_SIZE,
691 val: format->width, err: &ret);
692 cci_write(map: imx219->regmap, IMX219_REG_Y_OUTPUT_SIZE,
693 val: format->height, err: &ret);
694
695 cci_write(map: imx219->regmap, IMX219_REG_TP_WINDOW_WIDTH,
696 val: format->width, err: &ret);
697 cci_write(map: imx219->regmap, IMX219_REG_TP_WINDOW_HEIGHT,
698 val: format->height, err: &ret);
699
700 cci_write(map: imx219->regmap, IMX219_REG_CSI_DATA_FORMAT_A,
701 val: (bpp << 8) | bpp, err: &ret);
702 cci_write(map: imx219->regmap, IMX219_REG_OPPXCK_DIV, val: bpp, err: &ret);
703
704 return ret;
705}
706
707static int imx219_configure_lanes(struct imx219 *imx219)
708{
709 /* Write the appropriate PLL settings for the number of MIPI lanes */
710 return cci_multi_reg_write(map: imx219->regmap,
711 regs: imx219->lanes == 2 ? imx219_2lane_regs : imx219_4lane_regs,
712 num_regs: imx219->lanes == 2 ? ARRAY_SIZE(imx219_2lane_regs) :
713 ARRAY_SIZE(imx219_4lane_regs), NULL);
714};
715
716static int imx219_enable_streams(struct v4l2_subdev *sd,
717 struct v4l2_subdev_state *state, u32 pad,
718 u64 streams_mask)
719{
720 struct imx219 *imx219 = to_imx219(sd: sd);
721 struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd);
722 int ret;
723
724 ret = pm_runtime_resume_and_get(dev: &client->dev);
725 if (ret < 0)
726 return ret;
727
728 /* Send all registers that are common to all modes */
729 ret = cci_multi_reg_write(map: imx219->regmap, regs: imx219_common_regs,
730 ARRAY_SIZE(imx219_common_regs), NULL);
731 if (ret) {
732 dev_err(&client->dev, "%s failed to send mfg header\n", __func__);
733 goto err_rpm_put;
734 }
735
736 /* Configure two or four Lane mode */
737 ret = imx219_configure_lanes(imx219);
738 if (ret) {
739 dev_err(&client->dev, "%s failed to configure lanes\n", __func__);
740 goto err_rpm_put;
741 }
742
743 /* Apply format and crop settings. */
744 ret = imx219_set_framefmt(imx219, state);
745 if (ret) {
746 dev_err(&client->dev, "%s failed to set frame format: %d\n",
747 __func__, ret);
748 goto err_rpm_put;
749 }
750
751 /* Apply customized values from user */
752 ret = __v4l2_ctrl_handler_setup(hdl: imx219->sd.ctrl_handler);
753 if (ret)
754 goto err_rpm_put;
755
756 /* set stream on register */
757 ret = cci_write(map: imx219->regmap, IMX219_REG_MODE_SELECT,
758 IMX219_MODE_STREAMING, NULL);
759 if (ret)
760 goto err_rpm_put;
761
762 /* vflip and hflip cannot change during streaming */
763 __v4l2_ctrl_grab(ctrl: imx219->vflip, grabbed: true);
764 __v4l2_ctrl_grab(ctrl: imx219->hflip, grabbed: true);
765
766 return 0;
767
768err_rpm_put:
769 pm_runtime_put_autosuspend(dev: &client->dev);
770 return ret;
771}
772
773static int imx219_disable_streams(struct v4l2_subdev *sd,
774 struct v4l2_subdev_state *state, u32 pad,
775 u64 streams_mask)
776{
777 struct imx219 *imx219 = to_imx219(sd: sd);
778 struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd);
779 int ret;
780
781 /* set stream off register */
782 ret = cci_write(map: imx219->regmap, IMX219_REG_MODE_SELECT,
783 IMX219_MODE_STANDBY, NULL);
784 if (ret)
785 dev_err(&client->dev, "%s failed to set stream\n", __func__);
786
787 __v4l2_ctrl_grab(ctrl: imx219->vflip, grabbed: false);
788 __v4l2_ctrl_grab(ctrl: imx219->hflip, grabbed: false);
789
790 pm_runtime_put_autosuspend(dev: &client->dev);
791
792 return ret;
793}
794
795static void imx219_update_pad_format(struct imx219 *imx219,
796 const struct imx219_mode *mode,
797 struct v4l2_mbus_framefmt *fmt, u32 code)
798{
799 /* Bayer order varies with flips */
800 fmt->code = imx219_get_format_code(imx219, code);
801 fmt->width = mode->width;
802 fmt->height = mode->height;
803 fmt->field = V4L2_FIELD_NONE;
804 fmt->colorspace = V4L2_COLORSPACE_RAW;
805 fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
806 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
807 fmt->xfer_func = V4L2_XFER_FUNC_NONE;
808}
809
810static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
811 struct v4l2_subdev_state *state,
812 struct v4l2_subdev_mbus_code_enum *code)
813{
814 struct imx219 *imx219 = to_imx219(sd: sd);
815
816 if (code->index >= (ARRAY_SIZE(imx219_mbus_formats) / 4))
817 return -EINVAL;
818
819 code->code = imx219_get_format_code(imx219, code: imx219_mbus_formats[code->index * 4]);
820
821 return 0;
822}
823
824static int imx219_enum_frame_size(struct v4l2_subdev *sd,
825 struct v4l2_subdev_state *state,
826 struct v4l2_subdev_frame_size_enum *fse)
827{
828 struct imx219 *imx219 = to_imx219(sd: sd);
829 u32 code;
830
831 if (fse->index >= ARRAY_SIZE(supported_modes))
832 return -EINVAL;
833
834 code = imx219_get_format_code(imx219, code: fse->code);
835 if (fse->code != code)
836 return -EINVAL;
837
838 fse->min_width = supported_modes[fse->index].width;
839 fse->max_width = fse->min_width;
840 fse->min_height = supported_modes[fse->index].height;
841 fse->max_height = fse->min_height;
842
843 return 0;
844}
845
846static int imx219_set_pad_format(struct v4l2_subdev *sd,
847 struct v4l2_subdev_state *state,
848 struct v4l2_subdev_format *fmt)
849{
850 struct imx219 *imx219 = to_imx219(sd: sd);
851 const struct imx219_mode *mode;
852 struct v4l2_mbus_framefmt *format;
853 struct v4l2_rect *crop;
854 u8 bin_h, bin_v, binning;
855 u32 prev_line_len;
856 int ret;
857
858 format = v4l2_subdev_state_get_format(state, 0);
859 prev_line_len = format->width + imx219->hblank->val;
860
861 mode = v4l2_find_nearest_size(supported_modes,
862 ARRAY_SIZE(supported_modes),
863 width, height,
864 fmt->format.width, fmt->format.height);
865
866 imx219_update_pad_format(imx219, mode, fmt: &fmt->format, code: fmt->format.code);
867 *format = fmt->format;
868
869 /*
870 * Use binning to maximize the crop rectangle size, and centre it in the
871 * sensor.
872 */
873 bin_h = min(IMX219_PIXEL_ARRAY_WIDTH / format->width, 2U);
874 bin_v = min(IMX219_PIXEL_ARRAY_HEIGHT / format->height, 2U);
875
876 /* Ensure bin_h and bin_v are same to avoid 1:2 or 2:1 stretching */
877 binning = min(bin_h, bin_v);
878
879 crop = v4l2_subdev_state_get_crop(state, 0);
880 crop->width = format->width * binning;
881 crop->height = format->height * binning;
882 crop->left = (IMX219_NATIVE_WIDTH - crop->width) / 2;
883 crop->top = (IMX219_NATIVE_HEIGHT - crop->height) / 2;
884
885 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
886 int exposure_max;
887 int exposure_def;
888 int hblank, llp_min;
889 int pixel_rate;
890
891 /* Update limits and set FPS to default */
892 ret = __v4l2_ctrl_modify_range(ctrl: imx219->vblank, IMX219_VBLANK_MIN,
893 IMX219_FLL_MAX - mode->height, step: 1,
894 def: mode->fll_def - mode->height);
895 if (ret)
896 return ret;
897
898 ret = __v4l2_ctrl_s_ctrl(ctrl: imx219->vblank,
899 val: mode->fll_def - mode->height);
900 if (ret)
901 return ret;
902
903 /* Update max exposure while meeting expected vblanking */
904 exposure_max = mode->fll_def - IMX219_EXPOSURE_OFFSET;
905 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
906 exposure_max : IMX219_EXPOSURE_DEFAULT;
907 ret = __v4l2_ctrl_modify_range(ctrl: imx219->exposure,
908 min: imx219->exposure->minimum,
909 max: exposure_max,
910 step: imx219->exposure->step,
911 def: exposure_def);
912 if (ret)
913 return ret;
914
915 /*
916 * With analog binning the default minimum line length of 3448
917 * can cause artefacts with RAW10 formats, because the ADC
918 * operates on two lines together. So we switch to a higher
919 * minimum of 3560.
920 */
921 imx219_get_binning(state, bin_h: &bin_h, bin_v: &bin_v);
922 llp_min = (bin_h & bin_v) == IMX219_BINNING_X2_ANALOG ?
923 IMX219_BINNED_LLP_MIN : IMX219_LLP_MIN;
924 ret = __v4l2_ctrl_modify_range(ctrl: imx219->hblank,
925 min: llp_min - mode->width,
926 IMX219_LLP_MAX - mode->width, step: 1,
927 def: llp_min - mode->width);
928 if (ret)
929 return ret;
930 /*
931 * Retain PPL setting from previous mode so that the
932 * line time does not change on a mode change.
933 * Limits have to be recomputed as the controls define
934 * the blanking only, so PPL values need to have the
935 * mode width subtracted.
936 */
937 hblank = prev_line_len - mode->width;
938 ret = __v4l2_ctrl_s_ctrl(ctrl: imx219->hblank, val: hblank);
939 if (ret)
940 return ret;
941
942 /* Scale the pixel rate based on the mode specific factor */
943 pixel_rate = imx219_get_pixel_rate(imx219) *
944 imx219_get_rate_factor(state);
945 ret = __v4l2_ctrl_modify_range(ctrl: imx219->pixel_rate, min: pixel_rate,
946 max: pixel_rate, step: 1, def: pixel_rate);
947 if (ret)
948 return ret;
949 }
950
951 return 0;
952}
953
954static int imx219_get_selection(struct v4l2_subdev *sd,
955 struct v4l2_subdev_state *state,
956 struct v4l2_subdev_selection *sel)
957{
958 switch (sel->target) {
959 case V4L2_SEL_TGT_CROP:
960 sel->r = *v4l2_subdev_state_get_crop(state, 0);
961 return 0;
962
963 case V4L2_SEL_TGT_NATIVE_SIZE:
964 sel->r.top = 0;
965 sel->r.left = 0;
966 sel->r.width = IMX219_NATIVE_WIDTH;
967 sel->r.height = IMX219_NATIVE_HEIGHT;
968
969 return 0;
970
971 case V4L2_SEL_TGT_CROP_DEFAULT:
972 case V4L2_SEL_TGT_CROP_BOUNDS:
973 sel->r.top = IMX219_PIXEL_ARRAY_TOP;
974 sel->r.left = IMX219_PIXEL_ARRAY_LEFT;
975 sel->r.width = IMX219_PIXEL_ARRAY_WIDTH;
976 sel->r.height = IMX219_PIXEL_ARRAY_HEIGHT;
977
978 return 0;
979 }
980
981 return -EINVAL;
982}
983
984static int imx219_init_state(struct v4l2_subdev *sd,
985 struct v4l2_subdev_state *state)
986{
987 struct v4l2_subdev_format fmt = {
988 .which = V4L2_SUBDEV_FORMAT_TRY,
989 .pad = 0,
990 .format = {
991 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
992 .width = supported_modes[0].width,
993 .height = supported_modes[0].height,
994 },
995 };
996
997 return imx219_set_pad_format(sd, state, fmt: &fmt);
998}
999
1000static const struct v4l2_subdev_video_ops imx219_video_ops = {
1001 .s_stream = v4l2_subdev_s_stream_helper,
1002};
1003
1004static const struct v4l2_subdev_pad_ops imx219_pad_ops = {
1005 .enum_mbus_code = imx219_enum_mbus_code,
1006 .get_fmt = v4l2_subdev_get_fmt,
1007 .set_fmt = imx219_set_pad_format,
1008 .get_selection = imx219_get_selection,
1009 .enum_frame_size = imx219_enum_frame_size,
1010 .enable_streams = imx219_enable_streams,
1011 .disable_streams = imx219_disable_streams,
1012};
1013
1014static const struct v4l2_subdev_ops imx219_subdev_ops = {
1015 .video = &imx219_video_ops,
1016 .pad = &imx219_pad_ops,
1017};
1018
1019static const struct v4l2_subdev_internal_ops imx219_internal_ops = {
1020 .init_state = imx219_init_state,
1021};
1022
1023/* -----------------------------------------------------------------------------
1024 * Power management
1025 */
1026
1027static int imx219_power_on(struct device *dev)
1028{
1029 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1030 struct imx219 *imx219 = to_imx219(sd: sd);
1031 int ret;
1032
1033 ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES,
1034 consumers: imx219->supplies);
1035 if (ret) {
1036 dev_err(dev, "%s: failed to enable regulators\n",
1037 __func__);
1038 return ret;
1039 }
1040
1041 ret = clk_prepare_enable(clk: imx219->xclk);
1042 if (ret) {
1043 dev_err(dev, "%s: failed to enable clock\n",
1044 __func__);
1045 goto reg_off;
1046 }
1047
1048 /*
1049 * Note: Misinterpretation of reset assertion - do not re-use this code.
1050 * XCLR pin is using incorrect (for reset signal) logical level.
1051 */
1052 gpiod_set_value_cansleep(desc: imx219->reset_gpio, value: 1);
1053 usleep_range(IMX219_XCLR_MIN_DELAY_US,
1054 IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US);
1055
1056 return 0;
1057
1058reg_off:
1059 regulator_bulk_disable(IMX219_NUM_SUPPLIES, consumers: imx219->supplies);
1060
1061 return ret;
1062}
1063
1064static int imx219_power_off(struct device *dev)
1065{
1066 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1067 struct imx219 *imx219 = to_imx219(sd: sd);
1068
1069 gpiod_set_value_cansleep(desc: imx219->reset_gpio, value: 0);
1070 regulator_bulk_disable(IMX219_NUM_SUPPLIES, consumers: imx219->supplies);
1071 clk_disable_unprepare(clk: imx219->xclk);
1072
1073 return 0;
1074}
1075
1076/* -----------------------------------------------------------------------------
1077 * Probe & remove
1078 */
1079
1080static int imx219_get_regulators(struct imx219 *imx219)
1081{
1082 struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd);
1083 unsigned int i;
1084
1085 for (i = 0; i < IMX219_NUM_SUPPLIES; i++)
1086 imx219->supplies[i].supply = imx219_supply_name[i];
1087
1088 return devm_regulator_bulk_get(dev: &client->dev,
1089 IMX219_NUM_SUPPLIES,
1090 consumers: imx219->supplies);
1091}
1092
1093/* Verify chip ID */
1094static int imx219_identify_module(struct imx219 *imx219)
1095{
1096 struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd);
1097 int ret;
1098 u64 val;
1099
1100 ret = cci_read(map: imx219->regmap, IMX219_REG_CHIP_ID, val: &val, NULL);
1101 if (ret)
1102 return dev_err_probe(dev: &client->dev, err: ret,
1103 fmt: "failed to read chip id %x\n",
1104 IMX219_CHIP_ID);
1105
1106 if (val != IMX219_CHIP_ID)
1107 return dev_err_probe(dev: &client->dev, err: -EIO,
1108 fmt: "chip id mismatch: %x!=%llx\n",
1109 IMX219_CHIP_ID, val);
1110
1111 return 0;
1112}
1113
1114static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219)
1115{
1116 struct fwnode_handle *endpoint;
1117 struct v4l2_fwnode_endpoint ep_cfg = {
1118 .bus_type = V4L2_MBUS_CSI2_DPHY
1119 };
1120 unsigned long link_freq_bitmap;
1121 int ret = -EINVAL;
1122
1123 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1124 if (!endpoint)
1125 return dev_err_probe(dev, err: -EINVAL, fmt: "endpoint node not found\n");
1126
1127 if (v4l2_fwnode_endpoint_alloc_parse(fwnode: endpoint, vep: &ep_cfg)) {
1128 dev_err_probe(dev, err: -EINVAL, fmt: "could not parse endpoint\n");
1129 goto error_out;
1130 }
1131
1132 /* Check the number of MIPI CSI2 data lanes */
1133 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2 &&
1134 ep_cfg.bus.mipi_csi2.num_data_lanes != 4) {
1135 dev_err_probe(dev, err: -EINVAL,
1136 fmt: "only 2 or 4 data lanes are currently supported\n");
1137 goto error_out;
1138 }
1139 imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes;
1140
1141 /* Check the link frequency set in device tree */
1142 switch (imx219->lanes) {
1143 case 2:
1144 ret = v4l2_link_freq_to_bitmap(dev,
1145 fw_link_freqs: ep_cfg.link_frequencies,
1146 num_of_fw_link_freqs: ep_cfg.nr_of_link_frequencies,
1147 driver_link_freqs: imx219_link_freq_menu,
1148 ARRAY_SIZE(imx219_link_freq_menu),
1149 bitmap: &link_freq_bitmap);
1150 break;
1151 case 4:
1152 ret = v4l2_link_freq_to_bitmap(dev,
1153 fw_link_freqs: ep_cfg.link_frequencies,
1154 num_of_fw_link_freqs: ep_cfg.nr_of_link_frequencies,
1155 driver_link_freqs: imx219_link_freq_4lane_menu,
1156 ARRAY_SIZE(imx219_link_freq_4lane_menu),
1157 bitmap: &link_freq_bitmap);
1158
1159 if (!ret && (link_freq_bitmap & BIT(1))) {
1160 dev_warn(dev, "Link frequency of %d not supported, but has been incorrectly advertised previously\n",
1161 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED);
1162 dev_warn(dev, "Using link frequency of %d\n",
1163 IMX219_DEFAULT_LINK_FREQ_4LANE);
1164 link_freq_bitmap |= BIT(0);
1165 }
1166 break;
1167 }
1168
1169 if (ret || !(link_freq_bitmap & BIT(0))) {
1170 ret = -EINVAL;
1171 dev_err_probe(dev, err: -EINVAL,
1172 fmt: "Link frequency not supported: %lld\n",
1173 ep_cfg.link_frequencies[0]);
1174 }
1175
1176error_out:
1177 v4l2_fwnode_endpoint_free(vep: &ep_cfg);
1178 fwnode_handle_put(fwnode: endpoint);
1179
1180 return ret;
1181}
1182
1183static int imx219_probe(struct i2c_client *client)
1184{
1185 struct device *dev = &client->dev;
1186 struct imx219 *imx219;
1187 int ret;
1188
1189 imx219 = devm_kzalloc(dev: &client->dev, size: sizeof(*imx219), GFP_KERNEL);
1190 if (!imx219)
1191 return -ENOMEM;
1192
1193 v4l2_i2c_subdev_init(sd: &imx219->sd, client, ops: &imx219_subdev_ops);
1194 imx219->sd.internal_ops = &imx219_internal_ops;
1195
1196 /* Check the hardware configuration in device tree */
1197 if (imx219_check_hwcfg(dev, imx219))
1198 return -EINVAL;
1199
1200 imx219->regmap = devm_cci_regmap_init_i2c(client, reg_addr_bits: 16);
1201 if (IS_ERR(ptr: imx219->regmap))
1202 return dev_err_probe(dev, err: PTR_ERR(ptr: imx219->regmap),
1203 fmt: "failed to initialize CCI\n");
1204
1205 /* Get system clock (xclk) */
1206 imx219->xclk = devm_v4l2_sensor_clk_get(dev, NULL);
1207 if (IS_ERR(ptr: imx219->xclk))
1208 return dev_err_probe(dev, err: PTR_ERR(ptr: imx219->xclk),
1209 fmt: "failed to get xclk\n");
1210
1211 imx219->xclk_freq = clk_get_rate(clk: imx219->xclk);
1212 if (imx219->xclk_freq != IMX219_XCLK_FREQ)
1213 return dev_err_probe(dev, err: -EINVAL,
1214 fmt: "xclk frequency not supported: %d Hz\n",
1215 imx219->xclk_freq);
1216
1217 ret = imx219_get_regulators(imx219);
1218 if (ret)
1219 return dev_err_probe(dev, err: ret, fmt: "failed to get regulators\n");
1220
1221 /* Request optional enable pin */
1222 imx219->reset_gpio = devm_gpiod_get_optional(dev, con_id: "reset",
1223 flags: GPIOD_OUT_HIGH);
1224
1225 /*
1226 * The sensor must be powered for imx219_identify_module()
1227 * to be able to read the CHIP_ID register
1228 */
1229 ret = imx219_power_on(dev);
1230 if (ret)
1231 return ret;
1232
1233 ret = imx219_identify_module(imx219);
1234 if (ret)
1235 goto error_power_off;
1236
1237 /*
1238 * Sensor doesn't enter LP-11 state upon power up until and unless
1239 * streaming is started, so upon power up switch the modes to:
1240 * streaming -> standby
1241 */
1242 ret = cci_write(map: imx219->regmap, IMX219_REG_MODE_SELECT,
1243 IMX219_MODE_STREAMING, NULL);
1244 if (ret < 0)
1245 goto error_power_off;
1246
1247 usleep_range(min: 100, max: 110);
1248
1249 /* put sensor back to standby mode */
1250 ret = cci_write(map: imx219->regmap, IMX219_REG_MODE_SELECT,
1251 IMX219_MODE_STANDBY, NULL);
1252 if (ret < 0)
1253 goto error_power_off;
1254
1255 usleep_range(min: 100, max: 110);
1256
1257 ret = imx219_init_controls(imx219);
1258 if (ret)
1259 goto error_power_off;
1260
1261 /* Initialize subdev */
1262 imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1263 imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1264
1265 /* Initialize source pad */
1266 imx219->pad.flags = MEDIA_PAD_FL_SOURCE;
1267
1268 ret = media_entity_pads_init(entity: &imx219->sd.entity, num_pads: 1, pads: &imx219->pad);
1269 if (ret) {
1270 dev_err_probe(dev, err: ret, fmt: "failed to init entity pads\n");
1271 goto error_handler_free;
1272 }
1273
1274 imx219->sd.state_lock = imx219->ctrl_handler.lock;
1275 ret = v4l2_subdev_init_finalize(&imx219->sd);
1276 if (ret < 0) {
1277 dev_err_probe(dev, err: ret, fmt: "subdev init error\n");
1278 goto error_media_entity;
1279 }
1280
1281 pm_runtime_set_active(dev);
1282 pm_runtime_enable(dev);
1283
1284 ret = v4l2_async_register_subdev_sensor(sd: &imx219->sd);
1285 if (ret < 0) {
1286 dev_err_probe(dev, err: ret,
1287 fmt: "failed to register sensor sub-device\n");
1288 goto error_subdev_cleanup;
1289 }
1290
1291 pm_runtime_idle(dev);
1292 pm_runtime_set_autosuspend_delay(dev, delay: 1000);
1293 pm_runtime_use_autosuspend(dev);
1294
1295 return 0;
1296
1297error_subdev_cleanup:
1298 v4l2_subdev_cleanup(sd: &imx219->sd);
1299 pm_runtime_disable(dev);
1300 pm_runtime_set_suspended(dev);
1301
1302error_media_entity:
1303 media_entity_cleanup(entity: &imx219->sd.entity);
1304
1305error_handler_free:
1306 imx219_free_controls(imx219);
1307
1308error_power_off:
1309 imx219_power_off(dev);
1310
1311 return ret;
1312}
1313
1314static void imx219_remove(struct i2c_client *client)
1315{
1316 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1317 struct imx219 *imx219 = to_imx219(sd: sd);
1318
1319 v4l2_async_unregister_subdev(sd);
1320 v4l2_subdev_cleanup(sd);
1321 media_entity_cleanup(entity: &sd->entity);
1322 imx219_free_controls(imx219);
1323
1324 pm_runtime_disable(dev: &client->dev);
1325 if (!pm_runtime_status_suspended(dev: &client->dev)) {
1326 imx219_power_off(dev: &client->dev);
1327 pm_runtime_set_suspended(dev: &client->dev);
1328 }
1329}
1330
1331static const struct of_device_id imx219_dt_ids[] = {
1332 { .compatible = "sony,imx219" },
1333 { /* sentinel */ }
1334};
1335MODULE_DEVICE_TABLE(of, imx219_dt_ids);
1336
1337static const struct dev_pm_ops imx219_pm_ops = {
1338 SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL)
1339};
1340
1341static struct i2c_driver imx219_i2c_driver = {
1342 .driver = {
1343 .name = "imx219",
1344 .of_match_table = imx219_dt_ids,
1345 .pm = &imx219_pm_ops,
1346 },
1347 .probe = imx219_probe,
1348 .remove = imx219_remove,
1349};
1350
1351module_i2c_driver(imx219_i2c_driver);
1352
1353MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com");
1354MODULE_DESCRIPTION("Sony IMX219 sensor driver");
1355MODULE_LICENSE("GPL v2");
1356

source code of linux/drivers/media/i2c/imx219.c