1 | // SPDX-License-Identifier: GPL-2.0 |
---|---|
2 | /* |
3 | * A V4L2 driver for Sony IMX219 cameras. |
4 | * Copyright (C) 2019, Raspberry Pi (Trading) Ltd |
5 | * |
6 | * Based on Sony imx258 camera driver |
7 | * Copyright (C) 2018 Intel Corporation |
8 | * |
9 | * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver |
10 | * Copyright 2018 Qtechnology A/S |
11 | * |
12 | * Flip handling taken from the Sony IMX319 driver. |
13 | * Copyright (C) 2018 Intel Corporation |
14 | * |
15 | */ |
16 | |
17 | #include <linux/clk.h> |
18 | #include <linux/delay.h> |
19 | #include <linux/gpio/consumer.h> |
20 | #include <linux/i2c.h> |
21 | #include <linux/minmax.h> |
22 | #include <linux/module.h> |
23 | #include <linux/pm_runtime.h> |
24 | #include <linux/regulator/consumer.h> |
25 | |
26 | #include <media/v4l2-cci.h> |
27 | #include <media/v4l2-ctrls.h> |
28 | #include <media/v4l2-device.h> |
29 | #include <media/v4l2-fwnode.h> |
30 | #include <media/v4l2-mediabus.h> |
31 | |
32 | /* Chip ID */ |
33 | #define IMX219_REG_CHIP_ID CCI_REG16(0x0000) |
34 | #define IMX219_CHIP_ID 0x0219 |
35 | |
36 | #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100) |
37 | #define IMX219_MODE_STANDBY 0x00 |
38 | #define IMX219_MODE_STREAMING 0x01 |
39 | |
40 | #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114) |
41 | #define IMX219_CSI_2_LANE_MODE 0x01 |
42 | #define IMX219_CSI_4_LANE_MODE 0x03 |
43 | |
44 | #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128) |
45 | #define IMX219_DPHY_CTRL_TIMING_AUTO 0 |
46 | #define IMX219_DPHY_CTRL_TIMING_MANUAL 1 |
47 | |
48 | #define IMX219_REG_EXCK_FREQ CCI_REG16(0x012a) |
49 | #define IMX219_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */ |
50 | |
51 | /* Analog gain control */ |
52 | #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157) |
53 | #define IMX219_ANA_GAIN_MIN 0 |
54 | #define IMX219_ANA_GAIN_MAX 232 |
55 | #define IMX219_ANA_GAIN_STEP 1 |
56 | #define IMX219_ANA_GAIN_DEFAULT 0x0 |
57 | |
58 | /* Digital gain control */ |
59 | #define IMX219_REG_DIGITAL_GAIN CCI_REG16(0x0158) |
60 | #define IMX219_DGTL_GAIN_MIN 0x0100 |
61 | #define IMX219_DGTL_GAIN_MAX 0x0fff |
62 | #define IMX219_DGTL_GAIN_DEFAULT 0x0100 |
63 | #define IMX219_DGTL_GAIN_STEP 1 |
64 | |
65 | /* Exposure control */ |
66 | #define IMX219_REG_EXPOSURE CCI_REG16(0x015a) |
67 | #define IMX219_EXPOSURE_MIN 4 |
68 | #define IMX219_EXPOSURE_STEP 1 |
69 | #define IMX219_EXPOSURE_DEFAULT 0x640 |
70 | #define IMX219_EXPOSURE_MAX 65535 |
71 | |
72 | /* V_TIMING internal */ |
73 | #define IMX219_REG_FRM_LENGTH_A CCI_REG16(0x0160) |
74 | #define IMX219_FLL_MAX 0xffff |
75 | #define IMX219_VBLANK_MIN 32 |
76 | #define IMX219_REG_LINE_LENGTH_A CCI_REG16(0x0162) |
77 | #define IMX219_LLP_MIN 0x0d78 |
78 | #define IMX219_BINNED_LLP_MIN 0x0de8 |
79 | #define IMX219_LLP_MAX 0x7ff0 |
80 | |
81 | #define IMX219_REG_X_ADD_STA_A CCI_REG16(0x0164) |
82 | #define IMX219_REG_X_ADD_END_A CCI_REG16(0x0166) |
83 | #define IMX219_REG_Y_ADD_STA_A CCI_REG16(0x0168) |
84 | #define IMX219_REG_Y_ADD_END_A CCI_REG16(0x016a) |
85 | #define IMX219_REG_X_OUTPUT_SIZE CCI_REG16(0x016c) |
86 | #define IMX219_REG_Y_OUTPUT_SIZE CCI_REG16(0x016e) |
87 | #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170) |
88 | #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171) |
89 | #define IMX219_REG_ORIENTATION CCI_REG8(0x0172) |
90 | |
91 | /* Binning Mode */ |
92 | #define IMX219_REG_BINNING_MODE_H CCI_REG8(0x0174) |
93 | #define IMX219_REG_BINNING_MODE_V CCI_REG8(0x0175) |
94 | #define IMX219_BINNING_NONE 0x00 |
95 | #define IMX219_BINNING_X2 0x01 |
96 | #define IMX219_BINNING_X2_ANALOG 0x03 |
97 | |
98 | #define IMX219_REG_CSI_DATA_FORMAT_A CCI_REG16(0x018c) |
99 | |
100 | /* PLL Settings */ |
101 | #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301) |
102 | #define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303) |
103 | #define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304) |
104 | #define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305) |
105 | #define IMX219_REG_PLL_VT_MPY CCI_REG16(0x0306) |
106 | #define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309) |
107 | #define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b) |
108 | #define IMX219_REG_PLL_OP_MPY CCI_REG16(0x030c) |
109 | |
110 | /* Test Pattern Control */ |
111 | #define IMX219_REG_TEST_PATTERN CCI_REG16(0x0600) |
112 | #define IMX219_TEST_PATTERN_DISABLE 0 |
113 | #define IMX219_TEST_PATTERN_SOLID_COLOR 1 |
114 | #define IMX219_TEST_PATTERN_COLOR_BARS 2 |
115 | #define IMX219_TEST_PATTERN_GREY_COLOR 3 |
116 | #define IMX219_TEST_PATTERN_PN9 4 |
117 | |
118 | /* Test pattern colour components */ |
119 | #define IMX219_REG_TESTP_RED CCI_REG16(0x0602) |
120 | #define IMX219_REG_TESTP_GREENR CCI_REG16(0x0604) |
121 | #define IMX219_REG_TESTP_BLUE CCI_REG16(0x0606) |
122 | #define IMX219_REG_TESTP_GREENB CCI_REG16(0x0608) |
123 | #define IMX219_TESTP_COLOUR_MIN 0 |
124 | #define IMX219_TESTP_COLOUR_MAX 0x03ff |
125 | #define IMX219_TESTP_COLOUR_STEP 1 |
126 | |
127 | #define IMX219_REG_TP_WINDOW_WIDTH CCI_REG16(0x0624) |
128 | #define IMX219_REG_TP_WINDOW_HEIGHT CCI_REG16(0x0626) |
129 | |
130 | /* External clock frequency is 24.0M */ |
131 | #define IMX219_XCLK_FREQ 24000000 |
132 | |
133 | /* Pixel rate is fixed for all the modes */ |
134 | #define IMX219_PIXEL_RATE 182400000 |
135 | #define IMX219_PIXEL_RATE_4LANE 281600000 |
136 | |
137 | #define IMX219_DEFAULT_LINK_FREQ 456000000 |
138 | #define IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED 363000000 |
139 | #define IMX219_DEFAULT_LINK_FREQ_4LANE 364000000 |
140 | |
141 | /* IMX219 native and active pixel array size. */ |
142 | #define IMX219_NATIVE_WIDTH 3296U |
143 | #define IMX219_NATIVE_HEIGHT 2480U |
144 | #define IMX219_PIXEL_ARRAY_LEFT 8U |
145 | #define IMX219_PIXEL_ARRAY_TOP 8U |
146 | #define IMX219_PIXEL_ARRAY_WIDTH 3280U |
147 | #define IMX219_PIXEL_ARRAY_HEIGHT 2464U |
148 | |
149 | /* Mode : resolution and related config&values */ |
150 | struct imx219_mode { |
151 | /* Frame width */ |
152 | unsigned int width; |
153 | /* Frame height */ |
154 | unsigned int height; |
155 | |
156 | /* V-timing */ |
157 | unsigned int fll_def; |
158 | }; |
159 | |
160 | static const struct cci_reg_sequence imx219_common_regs[] = { |
161 | { IMX219_REG_MODE_SELECT, 0x00 }, /* Mode Select */ |
162 | |
163 | /* To Access Addresses 3000-5fff, send the following commands */ |
164 | { CCI_REG8(0x30eb), 0x05 }, |
165 | { CCI_REG8(0x30eb), 0x0c }, |
166 | { CCI_REG8(0x300a), 0xff }, |
167 | { CCI_REG8(0x300b), 0xff }, |
168 | { CCI_REG8(0x30eb), 0x05 }, |
169 | { CCI_REG8(0x30eb), 0x09 }, |
170 | |
171 | /* Undocumented registers */ |
172 | { CCI_REG8(0x455e), 0x00 }, |
173 | { CCI_REG8(0x471e), 0x4b }, |
174 | { CCI_REG8(0x4767), 0x0f }, |
175 | { CCI_REG8(0x4750), 0x14 }, |
176 | { CCI_REG8(0x4540), 0x00 }, |
177 | { CCI_REG8(0x47b4), 0x14 }, |
178 | { CCI_REG8(0x4713), 0x30 }, |
179 | { CCI_REG8(0x478b), 0x10 }, |
180 | { CCI_REG8(0x478f), 0x10 }, |
181 | { CCI_REG8(0x4793), 0x10 }, |
182 | { CCI_REG8(0x4797), 0x0e }, |
183 | { CCI_REG8(0x479b), 0x0e }, |
184 | |
185 | /* Frame Bank Register Group "A" */ |
186 | { IMX219_REG_X_ODD_INC_A, 1 }, |
187 | { IMX219_REG_Y_ODD_INC_A, 1 }, |
188 | |
189 | /* Output setup registers */ |
190 | { IMX219_REG_DPHY_CTRL, IMX219_DPHY_CTRL_TIMING_AUTO }, |
191 | { IMX219_REG_EXCK_FREQ, IMX219_EXCK_FREQ(IMX219_XCLK_FREQ / 1000000) }, |
192 | }; |
193 | |
194 | static const struct cci_reg_sequence imx219_2lane_regs[] = { |
195 | /* PLL Clock Table */ |
196 | { IMX219_REG_VTPXCK_DIV, 5 }, |
197 | { IMX219_REG_VTSYCK_DIV, 1 }, |
198 | { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */ |
199 | { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */ |
200 | { IMX219_REG_PLL_VT_MPY, 57 }, |
201 | { IMX219_REG_OPSYCK_DIV, 1 }, |
202 | { IMX219_REG_PLL_OP_MPY, 114 }, |
203 | |
204 | /* 2-Lane CSI Mode */ |
205 | { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_2_LANE_MODE }, |
206 | }; |
207 | |
208 | static const struct cci_reg_sequence imx219_4lane_regs[] = { |
209 | /* PLL Clock Table */ |
210 | { IMX219_REG_VTPXCK_DIV, 5 }, |
211 | { IMX219_REG_VTSYCK_DIV, 1 }, |
212 | { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */ |
213 | { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */ |
214 | { IMX219_REG_PLL_VT_MPY, 88 }, |
215 | { IMX219_REG_OPSYCK_DIV, 1 }, |
216 | { IMX219_REG_PLL_OP_MPY, 91 }, |
217 | |
218 | /* 4-Lane CSI Mode */ |
219 | { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_4_LANE_MODE }, |
220 | }; |
221 | |
222 | static const s64 imx219_link_freq_menu[] = { |
223 | IMX219_DEFAULT_LINK_FREQ, |
224 | }; |
225 | |
226 | static const s64 imx219_link_freq_4lane_menu[] = { |
227 | IMX219_DEFAULT_LINK_FREQ_4LANE, |
228 | /* |
229 | * This will never be advertised to userspace, but will be used for |
230 | * v4l2_link_freq_to_bitmap |
231 | */ |
232 | IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED, |
233 | }; |
234 | |
235 | static const char * const imx219_test_pattern_menu[] = { |
236 | "Disabled", |
237 | "Color Bars", |
238 | "Solid Color", |
239 | "Grey Color Bars", |
240 | "PN9" |
241 | }; |
242 | |
243 | static const int imx219_test_pattern_val[] = { |
244 | IMX219_TEST_PATTERN_DISABLE, |
245 | IMX219_TEST_PATTERN_COLOR_BARS, |
246 | IMX219_TEST_PATTERN_SOLID_COLOR, |
247 | IMX219_TEST_PATTERN_GREY_COLOR, |
248 | IMX219_TEST_PATTERN_PN9, |
249 | }; |
250 | |
251 | /* regulator supplies */ |
252 | static const char * const imx219_supply_name[] = { |
253 | /* Supplies can be enabled in any order */ |
254 | "VANA", /* Analog (2.8V) supply */ |
255 | "VDIG", /* Digital Core (1.8V) supply */ |
256 | "VDDL", /* IF (1.2V) supply */ |
257 | }; |
258 | |
259 | #define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name) |
260 | |
261 | /* |
262 | * The supported formats. |
263 | * This table MUST contain 4 entries per format, to cover the various flip |
264 | * combinations in the order |
265 | * - no flip |
266 | * - h flip |
267 | * - v flip |
268 | * - h&v flips |
269 | */ |
270 | static const u32 imx219_mbus_formats[] = { |
271 | MEDIA_BUS_FMT_SRGGB10_1X10, |
272 | MEDIA_BUS_FMT_SGRBG10_1X10, |
273 | MEDIA_BUS_FMT_SGBRG10_1X10, |
274 | MEDIA_BUS_FMT_SBGGR10_1X10, |
275 | |
276 | MEDIA_BUS_FMT_SRGGB8_1X8, |
277 | MEDIA_BUS_FMT_SGRBG8_1X8, |
278 | MEDIA_BUS_FMT_SGBRG8_1X8, |
279 | MEDIA_BUS_FMT_SBGGR8_1X8, |
280 | }; |
281 | |
282 | /* |
283 | * Initialisation delay between XCLR low->high and the moment when the sensor |
284 | * can start capture (i.e. can leave software stanby) must be not less than: |
285 | * t4 + max(t5, t6 + <time to initialize the sensor register over I2C>) |
286 | * where |
287 | * t4 is fixed, and is max 200uS, |
288 | * t5 is fixed, and is 6000uS, |
289 | * t6 depends on the sensor external clock, and is max 32000 clock periods. |
290 | * As per sensor datasheet, the external clock must be from 6MHz to 27MHz. |
291 | * So for any acceptable external clock t6 is always within the range of |
292 | * 1185 to 5333 uS, and is always less than t5. |
293 | * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then |
294 | * initialize the sensor over I2C, and then exit the software standby. |
295 | * |
296 | * This start-up time can be optimized a bit more, if we start the writes |
297 | * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor |
298 | * initialization over I2C may complete before (t4+t5) expires, and we must |
299 | * ensure that capture is not started before (t4+t5). |
300 | * |
301 | * This delay doesn't account for the power supply startup time. If needed, |
302 | * this should be taken care of via the regulator framework. E.g. in the |
303 | * case of DT for regulator-fixed one should define the startup-delay-us |
304 | * property. |
305 | */ |
306 | #define IMX219_XCLR_MIN_DELAY_US 6200 |
307 | #define IMX219_XCLR_DELAY_RANGE_US 1000 |
308 | |
309 | /* Mode configs */ |
310 | static const struct imx219_mode supported_modes[] = { |
311 | { |
312 | /* 8MPix 15fps mode */ |
313 | .width = 3280, |
314 | .height = 2464, |
315 | .fll_def = 3526, |
316 | }, |
317 | { |
318 | /* 1080P 30fps cropped */ |
319 | .width = 1920, |
320 | .height = 1080, |
321 | .fll_def = 1763, |
322 | }, |
323 | { |
324 | /* 2x2 binned 60fps mode */ |
325 | .width = 1640, |
326 | .height = 1232, |
327 | .fll_def = 1707, |
328 | }, |
329 | { |
330 | /* 640x480 60fps mode */ |
331 | .width = 640, |
332 | .height = 480, |
333 | .fll_def = 1707, |
334 | }, |
335 | }; |
336 | |
337 | struct imx219 { |
338 | struct v4l2_subdev sd; |
339 | struct media_pad pad; |
340 | |
341 | struct regmap *regmap; |
342 | struct clk *xclk; /* system clock to IMX219 */ |
343 | u32 xclk_freq; |
344 | |
345 | struct gpio_desc *reset_gpio; |
346 | struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES]; |
347 | |
348 | struct v4l2_ctrl_handler ctrl_handler; |
349 | /* V4L2 Controls */ |
350 | struct v4l2_ctrl *pixel_rate; |
351 | struct v4l2_ctrl *link_freq; |
352 | struct v4l2_ctrl *exposure; |
353 | struct v4l2_ctrl *vflip; |
354 | struct v4l2_ctrl *hflip; |
355 | struct v4l2_ctrl *vblank; |
356 | struct v4l2_ctrl *hblank; |
357 | |
358 | /* Two or Four lanes */ |
359 | u8 lanes; |
360 | }; |
361 | |
362 | static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd) |
363 | { |
364 | return container_of(_sd, struct imx219, sd); |
365 | } |
366 | |
367 | /* Get bayer order based on flip setting. */ |
368 | static u32 imx219_get_format_code(struct imx219 *imx219, u32 code) |
369 | { |
370 | unsigned int i; |
371 | |
372 | for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++) |
373 | if (imx219_mbus_formats[i] == code) |
374 | break; |
375 | |
376 | if (i >= ARRAY_SIZE(imx219_mbus_formats)) |
377 | i = 0; |
378 | |
379 | i = (i & ~3) | (imx219->vflip->val ? 2 : 0) | |
380 | (imx219->hflip->val ? 1 : 0); |
381 | |
382 | return imx219_mbus_formats[i]; |
383 | } |
384 | |
385 | static u32 imx219_get_format_bpp(const struct v4l2_mbus_framefmt *format) |
386 | { |
387 | switch (format->code) { |
388 | case MEDIA_BUS_FMT_SRGGB8_1X8: |
389 | case MEDIA_BUS_FMT_SGRBG8_1X8: |
390 | case MEDIA_BUS_FMT_SGBRG8_1X8: |
391 | case MEDIA_BUS_FMT_SBGGR8_1X8: |
392 | return 8; |
393 | |
394 | case MEDIA_BUS_FMT_SRGGB10_1X10: |
395 | case MEDIA_BUS_FMT_SGRBG10_1X10: |
396 | case MEDIA_BUS_FMT_SGBRG10_1X10: |
397 | case MEDIA_BUS_FMT_SBGGR10_1X10: |
398 | default: |
399 | return 10; |
400 | } |
401 | } |
402 | |
403 | static void imx219_get_binning(struct v4l2_subdev_state *state, u8 *bin_h, |
404 | u8 *bin_v) |
405 | { |
406 | const struct v4l2_mbus_framefmt *format = |
407 | v4l2_subdev_state_get_format(state, 0); |
408 | const struct v4l2_rect *crop = v4l2_subdev_state_get_crop(state, 0); |
409 | u32 hbin = crop->width / format->width; |
410 | u32 vbin = crop->height / format->height; |
411 | |
412 | *bin_h = IMX219_BINNING_NONE; |
413 | *bin_v = IMX219_BINNING_NONE; |
414 | |
415 | /* |
416 | * Use analog binning only if both dimensions are binned, as it crops |
417 | * the other dimension. |
418 | */ |
419 | if (hbin == 2 && vbin == 2) { |
420 | *bin_h = IMX219_BINNING_X2_ANALOG; |
421 | *bin_v = IMX219_BINNING_X2_ANALOG; |
422 | |
423 | return; |
424 | } |
425 | |
426 | if (hbin == 2) |
427 | *bin_h = IMX219_BINNING_X2; |
428 | if (vbin == 2) |
429 | *bin_v = IMX219_BINNING_X2; |
430 | } |
431 | |
432 | static inline u32 imx219_get_rate_factor(struct v4l2_subdev_state *state) |
433 | { |
434 | u8 bin_h, bin_v; |
435 | |
436 | imx219_get_binning(state, bin_h: &bin_h, bin_v: &bin_v); |
437 | |
438 | return (bin_h & bin_v) == IMX219_BINNING_X2_ANALOG ? 2 : 1; |
439 | } |
440 | |
441 | /* ----------------------------------------------------------------------------- |
442 | * Controls |
443 | */ |
444 | |
445 | static int imx219_set_ctrl(struct v4l2_ctrl *ctrl) |
446 | { |
447 | struct imx219 *imx219 = |
448 | container_of(ctrl->handler, struct imx219, ctrl_handler); |
449 | struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd); |
450 | const struct v4l2_mbus_framefmt *format; |
451 | struct v4l2_subdev_state *state; |
452 | u32 rate_factor; |
453 | int ret = 0; |
454 | |
455 | state = v4l2_subdev_get_locked_active_state(sd: &imx219->sd); |
456 | format = v4l2_subdev_state_get_format(state, 0); |
457 | rate_factor = imx219_get_rate_factor(state); |
458 | |
459 | if (ctrl->id == V4L2_CID_VBLANK) { |
460 | int exposure_max, exposure_def; |
461 | |
462 | /* Update max exposure while meeting expected vblanking */ |
463 | exposure_max = format->height + ctrl->val - 4; |
464 | exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? |
465 | exposure_max : IMX219_EXPOSURE_DEFAULT; |
466 | __v4l2_ctrl_modify_range(ctrl: imx219->exposure, |
467 | min: imx219->exposure->minimum, |
468 | max: exposure_max, step: imx219->exposure->step, |
469 | def: exposure_def); |
470 | } |
471 | |
472 | /* |
473 | * Applying V4L2 control value only happens |
474 | * when power is up for streaming |
475 | */ |
476 | if (pm_runtime_get_if_in_use(dev: &client->dev) == 0) |
477 | return 0; |
478 | |
479 | switch (ctrl->id) { |
480 | case V4L2_CID_ANALOGUE_GAIN: |
481 | cci_write(map: imx219->regmap, IMX219_REG_ANALOG_GAIN, |
482 | val: ctrl->val, err: &ret); |
483 | break; |
484 | case V4L2_CID_EXPOSURE: |
485 | cci_write(map: imx219->regmap, IMX219_REG_EXPOSURE, |
486 | val: ctrl->val / rate_factor, err: &ret); |
487 | break; |
488 | case V4L2_CID_DIGITAL_GAIN: |
489 | cci_write(map: imx219->regmap, IMX219_REG_DIGITAL_GAIN, |
490 | val: ctrl->val, err: &ret); |
491 | break; |
492 | case V4L2_CID_TEST_PATTERN: |
493 | cci_write(map: imx219->regmap, IMX219_REG_TEST_PATTERN, |
494 | val: imx219_test_pattern_val[ctrl->val], err: &ret); |
495 | break; |
496 | case V4L2_CID_HFLIP: |
497 | case V4L2_CID_VFLIP: |
498 | cci_write(map: imx219->regmap, IMX219_REG_ORIENTATION, |
499 | val: imx219->hflip->val | imx219->vflip->val << 1, err: &ret); |
500 | break; |
501 | case V4L2_CID_VBLANK: |
502 | cci_write(map: imx219->regmap, IMX219_REG_FRM_LENGTH_A, |
503 | val: (format->height + ctrl->val) / rate_factor, err: &ret); |
504 | break; |
505 | case V4L2_CID_HBLANK: |
506 | cci_write(map: imx219->regmap, IMX219_REG_LINE_LENGTH_A, |
507 | val: format->width + ctrl->val, err: &ret); |
508 | break; |
509 | case V4L2_CID_TEST_PATTERN_RED: |
510 | cci_write(map: imx219->regmap, IMX219_REG_TESTP_RED, |
511 | val: ctrl->val, err: &ret); |
512 | break; |
513 | case V4L2_CID_TEST_PATTERN_GREENR: |
514 | cci_write(map: imx219->regmap, IMX219_REG_TESTP_GREENR, |
515 | val: ctrl->val, err: &ret); |
516 | break; |
517 | case V4L2_CID_TEST_PATTERN_BLUE: |
518 | cci_write(map: imx219->regmap, IMX219_REG_TESTP_BLUE, |
519 | val: ctrl->val, err: &ret); |
520 | break; |
521 | case V4L2_CID_TEST_PATTERN_GREENB: |
522 | cci_write(map: imx219->regmap, IMX219_REG_TESTP_GREENB, |
523 | val: ctrl->val, err: &ret); |
524 | break; |
525 | default: |
526 | dev_info(&client->dev, |
527 | "ctrl(id:0x%x,val:0x%x) is not handled\n", |
528 | ctrl->id, ctrl->val); |
529 | ret = -EINVAL; |
530 | break; |
531 | } |
532 | |
533 | pm_runtime_put(dev: &client->dev); |
534 | |
535 | return ret; |
536 | } |
537 | |
538 | static const struct v4l2_ctrl_ops imx219_ctrl_ops = { |
539 | .s_ctrl = imx219_set_ctrl, |
540 | }; |
541 | |
542 | static unsigned long imx219_get_pixel_rate(struct imx219 *imx219) |
543 | { |
544 | return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE; |
545 | } |
546 | |
547 | /* Initialize control handlers */ |
548 | static int imx219_init_controls(struct imx219 *imx219) |
549 | { |
550 | struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd); |
551 | const struct imx219_mode *mode = &supported_modes[0]; |
552 | struct v4l2_ctrl_handler *ctrl_hdlr; |
553 | struct v4l2_fwnode_device_properties props; |
554 | int exposure_max, exposure_def; |
555 | int i, ret; |
556 | |
557 | ctrl_hdlr = &imx219->ctrl_handler; |
558 | ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); |
559 | if (ret) |
560 | return ret; |
561 | |
562 | /* By default, PIXEL_RATE is read only */ |
563 | imx219->pixel_rate = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, |
564 | V4L2_CID_PIXEL_RATE, |
565 | min: imx219_get_pixel_rate(imx219), |
566 | max: imx219_get_pixel_rate(imx219), step: 1, |
567 | def: imx219_get_pixel_rate(imx219)); |
568 | |
569 | imx219->link_freq = |
570 | v4l2_ctrl_new_int_menu(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, |
571 | V4L2_CID_LINK_FREQ, |
572 | ARRAY_SIZE(imx219_link_freq_menu) - 1, def: 0, |
573 | qmenu_int: (imx219->lanes == 2) ? imx219_link_freq_menu : |
574 | imx219_link_freq_4lane_menu); |
575 | if (imx219->link_freq) |
576 | imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; |
577 | |
578 | /* Initial blanking and exposure. Limits are updated during set_fmt */ |
579 | imx219->vblank = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, |
580 | V4L2_CID_VBLANK, IMX219_VBLANK_MIN, |
581 | IMX219_FLL_MAX - mode->height, step: 1, |
582 | def: mode->fll_def - mode->height); |
583 | imx219->hblank = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, |
584 | V4L2_CID_HBLANK, |
585 | IMX219_LLP_MIN - mode->width, |
586 | IMX219_LLP_MAX - mode->width, step: 1, |
587 | IMX219_LLP_MIN - mode->width); |
588 | exposure_max = mode->fll_def - 4; |
589 | exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? |
590 | exposure_max : IMX219_EXPOSURE_DEFAULT; |
591 | imx219->exposure = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, |
592 | V4L2_CID_EXPOSURE, |
593 | IMX219_EXPOSURE_MIN, max: exposure_max, |
594 | IMX219_EXPOSURE_STEP, |
595 | def: exposure_def); |
596 | |
597 | v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, |
598 | IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX, |
599 | IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT); |
600 | |
601 | v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN, |
602 | IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX, |
603 | IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT); |
604 | |
605 | imx219->hflip = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, |
606 | V4L2_CID_HFLIP, min: 0, max: 1, step: 1, def: 0); |
607 | if (imx219->hflip) |
608 | imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; |
609 | |
610 | imx219->vflip = v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, |
611 | V4L2_CID_VFLIP, min: 0, max: 1, step: 1, def: 0); |
612 | if (imx219->vflip) |
613 | imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; |
614 | |
615 | v4l2_ctrl_new_std_menu_items(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, |
616 | V4L2_CID_TEST_PATTERN, |
617 | ARRAY_SIZE(imx219_test_pattern_menu) - 1, |
618 | mask: 0, def: 0, qmenu: imx219_test_pattern_menu); |
619 | for (i = 0; i < 4; i++) { |
620 | /* |
621 | * The assumption is that |
622 | * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1 |
623 | * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2 |
624 | * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3 |
625 | */ |
626 | v4l2_ctrl_new_std(hdl: ctrl_hdlr, ops: &imx219_ctrl_ops, |
627 | V4L2_CID_TEST_PATTERN_RED + i, |
628 | IMX219_TESTP_COLOUR_MIN, |
629 | IMX219_TESTP_COLOUR_MAX, |
630 | IMX219_TESTP_COLOUR_STEP, |
631 | IMX219_TESTP_COLOUR_MAX); |
632 | /* The "Solid color" pattern is white by default */ |
633 | } |
634 | |
635 | if (ctrl_hdlr->error) { |
636 | ret = ctrl_hdlr->error; |
637 | dev_err_probe(dev: &client->dev, err: ret, fmt: "Control init failed\n"); |
638 | goto error; |
639 | } |
640 | |
641 | ret = v4l2_fwnode_device_parse(dev: &client->dev, props: &props); |
642 | if (ret) |
643 | goto error; |
644 | |
645 | ret = v4l2_ctrl_new_fwnode_properties(hdl: ctrl_hdlr, ctrl_ops: &imx219_ctrl_ops, |
646 | p: &props); |
647 | if (ret) |
648 | goto error; |
649 | |
650 | imx219->sd.ctrl_handler = ctrl_hdlr; |
651 | |
652 | return 0; |
653 | |
654 | error: |
655 | v4l2_ctrl_handler_free(hdl: ctrl_hdlr); |
656 | |
657 | return ret; |
658 | } |
659 | |
660 | static void imx219_free_controls(struct imx219 *imx219) |
661 | { |
662 | v4l2_ctrl_handler_free(hdl: imx219->sd.ctrl_handler); |
663 | } |
664 | |
665 | /* ----------------------------------------------------------------------------- |
666 | * Subdev operations |
667 | */ |
668 | |
669 | static int imx219_set_framefmt(struct imx219 *imx219, |
670 | struct v4l2_subdev_state *state) |
671 | { |
672 | const struct v4l2_mbus_framefmt *format; |
673 | const struct v4l2_rect *crop; |
674 | u8 bin_h, bin_v; |
675 | u32 bpp; |
676 | int ret = 0; |
677 | |
678 | format = v4l2_subdev_state_get_format(state, 0); |
679 | crop = v4l2_subdev_state_get_crop(state, 0); |
680 | bpp = imx219_get_format_bpp(format); |
681 | |
682 | cci_write(map: imx219->regmap, IMX219_REG_X_ADD_STA_A, |
683 | val: crop->left - IMX219_PIXEL_ARRAY_LEFT, err: &ret); |
684 | cci_write(map: imx219->regmap, IMX219_REG_X_ADD_END_A, |
685 | val: crop->left - IMX219_PIXEL_ARRAY_LEFT + crop->width - 1, err: &ret); |
686 | cci_write(map: imx219->regmap, IMX219_REG_Y_ADD_STA_A, |
687 | val: crop->top - IMX219_PIXEL_ARRAY_TOP, err: &ret); |
688 | cci_write(map: imx219->regmap, IMX219_REG_Y_ADD_END_A, |
689 | val: crop->top - IMX219_PIXEL_ARRAY_TOP + crop->height - 1, err: &ret); |
690 | |
691 | imx219_get_binning(state, bin_h: &bin_h, bin_v: &bin_v); |
692 | cci_write(map: imx219->regmap, IMX219_REG_BINNING_MODE_H, val: bin_h, err: &ret); |
693 | cci_write(map: imx219->regmap, IMX219_REG_BINNING_MODE_V, val: bin_v, err: &ret); |
694 | |
695 | cci_write(map: imx219->regmap, IMX219_REG_X_OUTPUT_SIZE, |
696 | val: format->width, err: &ret); |
697 | cci_write(map: imx219->regmap, IMX219_REG_Y_OUTPUT_SIZE, |
698 | val: format->height, err: &ret); |
699 | |
700 | cci_write(map: imx219->regmap, IMX219_REG_TP_WINDOW_WIDTH, |
701 | val: format->width, err: &ret); |
702 | cci_write(map: imx219->regmap, IMX219_REG_TP_WINDOW_HEIGHT, |
703 | val: format->height, err: &ret); |
704 | |
705 | cci_write(map: imx219->regmap, IMX219_REG_CSI_DATA_FORMAT_A, |
706 | val: (bpp << 8) | bpp, err: &ret); |
707 | cci_write(map: imx219->regmap, IMX219_REG_OPPXCK_DIV, val: bpp, err: &ret); |
708 | |
709 | return ret; |
710 | } |
711 | |
712 | static int imx219_configure_lanes(struct imx219 *imx219) |
713 | { |
714 | /* Write the appropriate PLL settings for the number of MIPI lanes */ |
715 | return cci_multi_reg_write(map: imx219->regmap, |
716 | regs: imx219->lanes == 2 ? imx219_2lane_regs : imx219_4lane_regs, |
717 | num_regs: imx219->lanes == 2 ? ARRAY_SIZE(imx219_2lane_regs) : |
718 | ARRAY_SIZE(imx219_4lane_regs), NULL); |
719 | }; |
720 | |
721 | static int imx219_enable_streams(struct v4l2_subdev *sd, |
722 | struct v4l2_subdev_state *state, u32 pad, |
723 | u64 streams_mask) |
724 | { |
725 | struct imx219 *imx219 = to_imx219(sd: sd); |
726 | struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd); |
727 | int ret; |
728 | |
729 | ret = pm_runtime_resume_and_get(dev: &client->dev); |
730 | if (ret < 0) |
731 | return ret; |
732 | |
733 | /* Send all registers that are common to all modes */ |
734 | ret = cci_multi_reg_write(map: imx219->regmap, regs: imx219_common_regs, |
735 | ARRAY_SIZE(imx219_common_regs), NULL); |
736 | if (ret) { |
737 | dev_err(&client->dev, "%s failed to send mfg header\n", __func__); |
738 | goto err_rpm_put; |
739 | } |
740 | |
741 | /* Configure two or four Lane mode */ |
742 | ret = imx219_configure_lanes(imx219); |
743 | if (ret) { |
744 | dev_err(&client->dev, "%s failed to configure lanes\n", __func__); |
745 | goto err_rpm_put; |
746 | } |
747 | |
748 | /* Apply format and crop settings. */ |
749 | ret = imx219_set_framefmt(imx219, state); |
750 | if (ret) { |
751 | dev_err(&client->dev, "%s failed to set frame format: %d\n", |
752 | __func__, ret); |
753 | goto err_rpm_put; |
754 | } |
755 | |
756 | /* Apply customized values from user */ |
757 | ret = __v4l2_ctrl_handler_setup(hdl: imx219->sd.ctrl_handler); |
758 | if (ret) |
759 | goto err_rpm_put; |
760 | |
761 | /* set stream on register */ |
762 | ret = cci_write(map: imx219->regmap, IMX219_REG_MODE_SELECT, |
763 | IMX219_MODE_STREAMING, NULL); |
764 | if (ret) |
765 | goto err_rpm_put; |
766 | |
767 | /* vflip and hflip cannot change during streaming */ |
768 | __v4l2_ctrl_grab(ctrl: imx219->vflip, grabbed: true); |
769 | __v4l2_ctrl_grab(ctrl: imx219->hflip, grabbed: true); |
770 | |
771 | return 0; |
772 | |
773 | err_rpm_put: |
774 | pm_runtime_mark_last_busy(dev: &client->dev); |
775 | pm_runtime_put_autosuspend(dev: &client->dev); |
776 | return ret; |
777 | } |
778 | |
779 | static int imx219_disable_streams(struct v4l2_subdev *sd, |
780 | struct v4l2_subdev_state *state, u32 pad, |
781 | u64 streams_mask) |
782 | { |
783 | struct imx219 *imx219 = to_imx219(sd: sd); |
784 | struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd); |
785 | int ret; |
786 | |
787 | /* set stream off register */ |
788 | ret = cci_write(map: imx219->regmap, IMX219_REG_MODE_SELECT, |
789 | IMX219_MODE_STANDBY, NULL); |
790 | if (ret) |
791 | dev_err(&client->dev, "%s failed to set stream\n", __func__); |
792 | |
793 | __v4l2_ctrl_grab(ctrl: imx219->vflip, grabbed: false); |
794 | __v4l2_ctrl_grab(ctrl: imx219->hflip, grabbed: false); |
795 | |
796 | pm_runtime_mark_last_busy(dev: &client->dev); |
797 | pm_runtime_put_autosuspend(dev: &client->dev); |
798 | |
799 | return ret; |
800 | } |
801 | |
802 | static void imx219_update_pad_format(struct imx219 *imx219, |
803 | const struct imx219_mode *mode, |
804 | struct v4l2_mbus_framefmt *fmt, u32 code) |
805 | { |
806 | /* Bayer order varies with flips */ |
807 | fmt->code = imx219_get_format_code(imx219, code); |
808 | fmt->width = mode->width; |
809 | fmt->height = mode->height; |
810 | fmt->field = V4L2_FIELD_NONE; |
811 | fmt->colorspace = V4L2_COLORSPACE_RAW; |
812 | fmt->ycbcr_enc = V4L2_YCBCR_ENC_601; |
813 | fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; |
814 | fmt->xfer_func = V4L2_XFER_FUNC_NONE; |
815 | } |
816 | |
817 | static int imx219_enum_mbus_code(struct v4l2_subdev *sd, |
818 | struct v4l2_subdev_state *state, |
819 | struct v4l2_subdev_mbus_code_enum *code) |
820 | { |
821 | struct imx219 *imx219 = to_imx219(sd: sd); |
822 | |
823 | if (code->index >= (ARRAY_SIZE(imx219_mbus_formats) / 4)) |
824 | return -EINVAL; |
825 | |
826 | code->code = imx219_get_format_code(imx219, code: imx219_mbus_formats[code->index * 4]); |
827 | |
828 | return 0; |
829 | } |
830 | |
831 | static int imx219_enum_frame_size(struct v4l2_subdev *sd, |
832 | struct v4l2_subdev_state *state, |
833 | struct v4l2_subdev_frame_size_enum *fse) |
834 | { |
835 | struct imx219 *imx219 = to_imx219(sd: sd); |
836 | u32 code; |
837 | |
838 | if (fse->index >= ARRAY_SIZE(supported_modes)) |
839 | return -EINVAL; |
840 | |
841 | code = imx219_get_format_code(imx219, code: fse->code); |
842 | if (fse->code != code) |
843 | return -EINVAL; |
844 | |
845 | fse->min_width = supported_modes[fse->index].width; |
846 | fse->max_width = fse->min_width; |
847 | fse->min_height = supported_modes[fse->index].height; |
848 | fse->max_height = fse->min_height; |
849 | |
850 | return 0; |
851 | } |
852 | |
853 | static int imx219_set_pad_format(struct v4l2_subdev *sd, |
854 | struct v4l2_subdev_state *state, |
855 | struct v4l2_subdev_format *fmt) |
856 | { |
857 | struct imx219 *imx219 = to_imx219(sd: sd); |
858 | const struct imx219_mode *mode; |
859 | struct v4l2_mbus_framefmt *format; |
860 | struct v4l2_rect *crop; |
861 | u8 bin_h, bin_v; |
862 | u32 prev_line_len; |
863 | |
864 | format = v4l2_subdev_state_get_format(state, 0); |
865 | prev_line_len = format->width + imx219->hblank->val; |
866 | |
867 | mode = v4l2_find_nearest_size(supported_modes, |
868 | ARRAY_SIZE(supported_modes), |
869 | width, height, |
870 | fmt->format.width, fmt->format.height); |
871 | |
872 | imx219_update_pad_format(imx219, mode, fmt: &fmt->format, code: fmt->format.code); |
873 | *format = fmt->format; |
874 | |
875 | /* |
876 | * Use binning to maximize the crop rectangle size, and centre it in the |
877 | * sensor. |
878 | */ |
879 | bin_h = min(IMX219_PIXEL_ARRAY_WIDTH / format->width, 2U); |
880 | bin_v = min(IMX219_PIXEL_ARRAY_HEIGHT / format->height, 2U); |
881 | |
882 | crop = v4l2_subdev_state_get_crop(state, 0); |
883 | crop->width = format->width * bin_h; |
884 | crop->height = format->height * bin_v; |
885 | crop->left = (IMX219_NATIVE_WIDTH - crop->width) / 2; |
886 | crop->top = (IMX219_NATIVE_HEIGHT - crop->height) / 2; |
887 | |
888 | if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { |
889 | int exposure_max; |
890 | int exposure_def; |
891 | int hblank, llp_min; |
892 | int pixel_rate; |
893 | |
894 | /* Update limits and set FPS to default */ |
895 | __v4l2_ctrl_modify_range(ctrl: imx219->vblank, IMX219_VBLANK_MIN, |
896 | IMX219_FLL_MAX - mode->height, step: 1, |
897 | def: mode->fll_def - mode->height); |
898 | __v4l2_ctrl_s_ctrl(ctrl: imx219->vblank, |
899 | val: mode->fll_def - mode->height); |
900 | /* Update max exposure while meeting expected vblanking */ |
901 | exposure_max = mode->fll_def - 4; |
902 | exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? |
903 | exposure_max : IMX219_EXPOSURE_DEFAULT; |
904 | __v4l2_ctrl_modify_range(ctrl: imx219->exposure, |
905 | min: imx219->exposure->minimum, |
906 | max: exposure_max, step: imx219->exposure->step, |
907 | def: exposure_def); |
908 | |
909 | /* |
910 | * With analog binning the default minimum line length of 3448 |
911 | * can cause artefacts with RAW10 formats, because the ADC |
912 | * operates on two lines together. So we switch to a higher |
913 | * minimum of 3560. |
914 | */ |
915 | imx219_get_binning(state, bin_h: &bin_h, bin_v: &bin_v); |
916 | llp_min = (bin_h & bin_v) == IMX219_BINNING_X2_ANALOG ? |
917 | IMX219_BINNED_LLP_MIN : IMX219_LLP_MIN; |
918 | __v4l2_ctrl_modify_range(ctrl: imx219->hblank, min: llp_min - mode->width, |
919 | IMX219_LLP_MAX - mode->width, step: 1, |
920 | def: llp_min - mode->width); |
921 | /* |
922 | * Retain PPL setting from previous mode so that the |
923 | * line time does not change on a mode change. |
924 | * Limits have to be recomputed as the controls define |
925 | * the blanking only, so PPL values need to have the |
926 | * mode width subtracted. |
927 | */ |
928 | hblank = prev_line_len - mode->width; |
929 | __v4l2_ctrl_s_ctrl(ctrl: imx219->hblank, val: hblank); |
930 | |
931 | /* Scale the pixel rate based on the mode specific factor */ |
932 | pixel_rate = imx219_get_pixel_rate(imx219) * |
933 | imx219_get_rate_factor(state); |
934 | __v4l2_ctrl_modify_range(ctrl: imx219->pixel_rate, min: pixel_rate, |
935 | max: pixel_rate, step: 1, def: pixel_rate); |
936 | } |
937 | |
938 | return 0; |
939 | } |
940 | |
941 | static int imx219_get_selection(struct v4l2_subdev *sd, |
942 | struct v4l2_subdev_state *state, |
943 | struct v4l2_subdev_selection *sel) |
944 | { |
945 | switch (sel->target) { |
946 | case V4L2_SEL_TGT_CROP: |
947 | sel->r = *v4l2_subdev_state_get_crop(state, 0); |
948 | return 0; |
949 | |
950 | case V4L2_SEL_TGT_NATIVE_SIZE: |
951 | sel->r.top = 0; |
952 | sel->r.left = 0; |
953 | sel->r.width = IMX219_NATIVE_WIDTH; |
954 | sel->r.height = IMX219_NATIVE_HEIGHT; |
955 | |
956 | return 0; |
957 | |
958 | case V4L2_SEL_TGT_CROP_DEFAULT: |
959 | case V4L2_SEL_TGT_CROP_BOUNDS: |
960 | sel->r.top = IMX219_PIXEL_ARRAY_TOP; |
961 | sel->r.left = IMX219_PIXEL_ARRAY_LEFT; |
962 | sel->r.width = IMX219_PIXEL_ARRAY_WIDTH; |
963 | sel->r.height = IMX219_PIXEL_ARRAY_HEIGHT; |
964 | |
965 | return 0; |
966 | } |
967 | |
968 | return -EINVAL; |
969 | } |
970 | |
971 | static int imx219_init_state(struct v4l2_subdev *sd, |
972 | struct v4l2_subdev_state *state) |
973 | { |
974 | struct v4l2_subdev_format fmt = { |
975 | .which = V4L2_SUBDEV_FORMAT_TRY, |
976 | .pad = 0, |
977 | .format = { |
978 | .code = MEDIA_BUS_FMT_SRGGB10_1X10, |
979 | .width = supported_modes[0].width, |
980 | .height = supported_modes[0].height, |
981 | }, |
982 | }; |
983 | |
984 | imx219_set_pad_format(sd, state, fmt: &fmt); |
985 | |
986 | return 0; |
987 | } |
988 | |
989 | static const struct v4l2_subdev_video_ops imx219_video_ops = { |
990 | .s_stream = v4l2_subdev_s_stream_helper, |
991 | }; |
992 | |
993 | static const struct v4l2_subdev_pad_ops imx219_pad_ops = { |
994 | .enum_mbus_code = imx219_enum_mbus_code, |
995 | .get_fmt = v4l2_subdev_get_fmt, |
996 | .set_fmt = imx219_set_pad_format, |
997 | .get_selection = imx219_get_selection, |
998 | .enum_frame_size = imx219_enum_frame_size, |
999 | .enable_streams = imx219_enable_streams, |
1000 | .disable_streams = imx219_disable_streams, |
1001 | }; |
1002 | |
1003 | static const struct v4l2_subdev_ops imx219_subdev_ops = { |
1004 | .video = &imx219_video_ops, |
1005 | .pad = &imx219_pad_ops, |
1006 | }; |
1007 | |
1008 | static const struct v4l2_subdev_internal_ops imx219_internal_ops = { |
1009 | .init_state = imx219_init_state, |
1010 | }; |
1011 | |
1012 | /* ----------------------------------------------------------------------------- |
1013 | * Power management |
1014 | */ |
1015 | |
1016 | static int imx219_power_on(struct device *dev) |
1017 | { |
1018 | struct v4l2_subdev *sd = dev_get_drvdata(dev); |
1019 | struct imx219 *imx219 = to_imx219(sd: sd); |
1020 | int ret; |
1021 | |
1022 | ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES, |
1023 | consumers: imx219->supplies); |
1024 | if (ret) { |
1025 | dev_err(dev, "%s: failed to enable regulators\n", |
1026 | __func__); |
1027 | return ret; |
1028 | } |
1029 | |
1030 | ret = clk_prepare_enable(clk: imx219->xclk); |
1031 | if (ret) { |
1032 | dev_err(dev, "%s: failed to enable clock\n", |
1033 | __func__); |
1034 | goto reg_off; |
1035 | } |
1036 | |
1037 | gpiod_set_value_cansleep(desc: imx219->reset_gpio, value: 1); |
1038 | usleep_range(IMX219_XCLR_MIN_DELAY_US, |
1039 | IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US); |
1040 | |
1041 | return 0; |
1042 | |
1043 | reg_off: |
1044 | regulator_bulk_disable(IMX219_NUM_SUPPLIES, consumers: imx219->supplies); |
1045 | |
1046 | return ret; |
1047 | } |
1048 | |
1049 | static int imx219_power_off(struct device *dev) |
1050 | { |
1051 | struct v4l2_subdev *sd = dev_get_drvdata(dev); |
1052 | struct imx219 *imx219 = to_imx219(sd: sd); |
1053 | |
1054 | gpiod_set_value_cansleep(desc: imx219->reset_gpio, value: 0); |
1055 | regulator_bulk_disable(IMX219_NUM_SUPPLIES, consumers: imx219->supplies); |
1056 | clk_disable_unprepare(clk: imx219->xclk); |
1057 | |
1058 | return 0; |
1059 | } |
1060 | |
1061 | /* ----------------------------------------------------------------------------- |
1062 | * Probe & remove |
1063 | */ |
1064 | |
1065 | static int imx219_get_regulators(struct imx219 *imx219) |
1066 | { |
1067 | struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd); |
1068 | unsigned int i; |
1069 | |
1070 | for (i = 0; i < IMX219_NUM_SUPPLIES; i++) |
1071 | imx219->supplies[i].supply = imx219_supply_name[i]; |
1072 | |
1073 | return devm_regulator_bulk_get(dev: &client->dev, |
1074 | IMX219_NUM_SUPPLIES, |
1075 | consumers: imx219->supplies); |
1076 | } |
1077 | |
1078 | /* Verify chip ID */ |
1079 | static int imx219_identify_module(struct imx219 *imx219) |
1080 | { |
1081 | struct i2c_client *client = v4l2_get_subdevdata(sd: &imx219->sd); |
1082 | int ret; |
1083 | u64 val; |
1084 | |
1085 | ret = cci_read(map: imx219->regmap, IMX219_REG_CHIP_ID, val: &val, NULL); |
1086 | if (ret) |
1087 | return dev_err_probe(dev: &client->dev, err: ret, |
1088 | fmt: "failed to read chip id %x\n", |
1089 | IMX219_CHIP_ID); |
1090 | |
1091 | if (val != IMX219_CHIP_ID) |
1092 | return dev_err_probe(dev: &client->dev, err: -EIO, |
1093 | fmt: "chip id mismatch: %x!=%llx\n", |
1094 | IMX219_CHIP_ID, val); |
1095 | |
1096 | return 0; |
1097 | } |
1098 | |
1099 | static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219) |
1100 | { |
1101 | struct fwnode_handle *endpoint; |
1102 | struct v4l2_fwnode_endpoint ep_cfg = { |
1103 | .bus_type = V4L2_MBUS_CSI2_DPHY |
1104 | }; |
1105 | unsigned long link_freq_bitmap; |
1106 | int ret = -EINVAL; |
1107 | |
1108 | endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); |
1109 | if (!endpoint) |
1110 | return dev_err_probe(dev, err: -EINVAL, fmt: "endpoint node not found\n"); |
1111 | |
1112 | if (v4l2_fwnode_endpoint_alloc_parse(fwnode: endpoint, vep: &ep_cfg)) { |
1113 | dev_err_probe(dev, err: -EINVAL, fmt: "could not parse endpoint\n"); |
1114 | goto error_out; |
1115 | } |
1116 | |
1117 | /* Check the number of MIPI CSI2 data lanes */ |
1118 | if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2 && |
1119 | ep_cfg.bus.mipi_csi2.num_data_lanes != 4) { |
1120 | dev_err_probe(dev, err: -EINVAL, |
1121 | fmt: "only 2 or 4 data lanes are currently supported\n"); |
1122 | goto error_out; |
1123 | } |
1124 | imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes; |
1125 | |
1126 | /* Check the link frequency set in device tree */ |
1127 | switch (imx219->lanes) { |
1128 | case 2: |
1129 | ret = v4l2_link_freq_to_bitmap(dev, |
1130 | fw_link_freqs: ep_cfg.link_frequencies, |
1131 | num_of_fw_link_freqs: ep_cfg.nr_of_link_frequencies, |
1132 | driver_link_freqs: imx219_link_freq_menu, |
1133 | ARRAY_SIZE(imx219_link_freq_menu), |
1134 | bitmap: &link_freq_bitmap); |
1135 | break; |
1136 | case 4: |
1137 | ret = v4l2_link_freq_to_bitmap(dev, |
1138 | fw_link_freqs: ep_cfg.link_frequencies, |
1139 | num_of_fw_link_freqs: ep_cfg.nr_of_link_frequencies, |
1140 | driver_link_freqs: imx219_link_freq_4lane_menu, |
1141 | ARRAY_SIZE(imx219_link_freq_4lane_menu), |
1142 | bitmap: &link_freq_bitmap); |
1143 | |
1144 | if (!ret && (link_freq_bitmap & BIT(1))) { |
1145 | dev_warn(dev, "Link frequency of %d not supported, but has been incorrectly advertised previously\n", |
1146 | IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED); |
1147 | dev_warn(dev, "Using link frequency of %d\n", |
1148 | IMX219_DEFAULT_LINK_FREQ_4LANE); |
1149 | link_freq_bitmap |= BIT(0); |
1150 | } |
1151 | break; |
1152 | } |
1153 | |
1154 | if (ret || !(link_freq_bitmap & BIT(0))) { |
1155 | ret = -EINVAL; |
1156 | dev_err_probe(dev, err: -EINVAL, |
1157 | fmt: "Link frequency not supported: %lld\n", |
1158 | ep_cfg.link_frequencies[0]); |
1159 | } |
1160 | |
1161 | error_out: |
1162 | v4l2_fwnode_endpoint_free(vep: &ep_cfg); |
1163 | fwnode_handle_put(fwnode: endpoint); |
1164 | |
1165 | return ret; |
1166 | } |
1167 | |
1168 | static int imx219_probe(struct i2c_client *client) |
1169 | { |
1170 | struct device *dev = &client->dev; |
1171 | struct imx219 *imx219; |
1172 | int ret; |
1173 | |
1174 | imx219 = devm_kzalloc(dev: &client->dev, size: sizeof(*imx219), GFP_KERNEL); |
1175 | if (!imx219) |
1176 | return -ENOMEM; |
1177 | |
1178 | v4l2_i2c_subdev_init(sd: &imx219->sd, client, ops: &imx219_subdev_ops); |
1179 | imx219->sd.internal_ops = &imx219_internal_ops; |
1180 | |
1181 | /* Check the hardware configuration in device tree */ |
1182 | if (imx219_check_hwcfg(dev, imx219)) |
1183 | return -EINVAL; |
1184 | |
1185 | imx219->regmap = devm_cci_regmap_init_i2c(client, reg_addr_bits: 16); |
1186 | if (IS_ERR(ptr: imx219->regmap)) |
1187 | return dev_err_probe(dev, err: PTR_ERR(ptr: imx219->regmap), |
1188 | fmt: "failed to initialize CCI\n"); |
1189 | |
1190 | /* Get system clock (xclk) */ |
1191 | imx219->xclk = devm_clk_get(dev, NULL); |
1192 | if (IS_ERR(ptr: imx219->xclk)) |
1193 | return dev_err_probe(dev, err: PTR_ERR(ptr: imx219->xclk), |
1194 | fmt: "failed to get xclk\n"); |
1195 | |
1196 | imx219->xclk_freq = clk_get_rate(clk: imx219->xclk); |
1197 | if (imx219->xclk_freq != IMX219_XCLK_FREQ) |
1198 | return dev_err_probe(dev, err: -EINVAL, |
1199 | fmt: "xclk frequency not supported: %d Hz\n", |
1200 | imx219->xclk_freq); |
1201 | |
1202 | ret = imx219_get_regulators(imx219); |
1203 | if (ret) |
1204 | return dev_err_probe(dev, err: ret, fmt: "failed to get regulators\n"); |
1205 | |
1206 | /* Request optional enable pin */ |
1207 | imx219->reset_gpio = devm_gpiod_get_optional(dev, con_id: "reset", |
1208 | flags: GPIOD_OUT_HIGH); |
1209 | |
1210 | /* |
1211 | * The sensor must be powered for imx219_identify_module() |
1212 | * to be able to read the CHIP_ID register |
1213 | */ |
1214 | ret = imx219_power_on(dev); |
1215 | if (ret) |
1216 | return ret; |
1217 | |
1218 | ret = imx219_identify_module(imx219); |
1219 | if (ret) |
1220 | goto error_power_off; |
1221 | |
1222 | /* |
1223 | * Sensor doesn't enter LP-11 state upon power up until and unless |
1224 | * streaming is started, so upon power up switch the modes to: |
1225 | * streaming -> standby |
1226 | */ |
1227 | ret = cci_write(map: imx219->regmap, IMX219_REG_MODE_SELECT, |
1228 | IMX219_MODE_STREAMING, NULL); |
1229 | if (ret < 0) |
1230 | goto error_power_off; |
1231 | |
1232 | usleep_range(min: 100, max: 110); |
1233 | |
1234 | /* put sensor back to standby mode */ |
1235 | ret = cci_write(map: imx219->regmap, IMX219_REG_MODE_SELECT, |
1236 | IMX219_MODE_STANDBY, NULL); |
1237 | if (ret < 0) |
1238 | goto error_power_off; |
1239 | |
1240 | usleep_range(min: 100, max: 110); |
1241 | |
1242 | ret = imx219_init_controls(imx219); |
1243 | if (ret) |
1244 | goto error_power_off; |
1245 | |
1246 | /* Initialize subdev */ |
1247 | imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
1248 | imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; |
1249 | |
1250 | /* Initialize source pad */ |
1251 | imx219->pad.flags = MEDIA_PAD_FL_SOURCE; |
1252 | |
1253 | ret = media_entity_pads_init(entity: &imx219->sd.entity, num_pads: 1, pads: &imx219->pad); |
1254 | if (ret) { |
1255 | dev_err_probe(dev, err: ret, fmt: "failed to init entity pads\n"); |
1256 | goto error_handler_free; |
1257 | } |
1258 | |
1259 | imx219->sd.state_lock = imx219->ctrl_handler.lock; |
1260 | ret = v4l2_subdev_init_finalize(&imx219->sd); |
1261 | if (ret < 0) { |
1262 | dev_err_probe(dev, err: ret, fmt: "subdev init error\n"); |
1263 | goto error_media_entity; |
1264 | } |
1265 | |
1266 | pm_runtime_set_active(dev); |
1267 | pm_runtime_enable(dev); |
1268 | |
1269 | ret = v4l2_async_register_subdev_sensor(sd: &imx219->sd); |
1270 | if (ret < 0) { |
1271 | dev_err_probe(dev, err: ret, |
1272 | fmt: "failed to register sensor sub-device\n"); |
1273 | goto error_subdev_cleanup; |
1274 | } |
1275 | |
1276 | pm_runtime_idle(dev); |
1277 | pm_runtime_set_autosuspend_delay(dev, delay: 1000); |
1278 | pm_runtime_use_autosuspend(dev); |
1279 | |
1280 | return 0; |
1281 | |
1282 | error_subdev_cleanup: |
1283 | v4l2_subdev_cleanup(sd: &imx219->sd); |
1284 | pm_runtime_disable(dev); |
1285 | pm_runtime_set_suspended(dev); |
1286 | |
1287 | error_media_entity: |
1288 | media_entity_cleanup(entity: &imx219->sd.entity); |
1289 | |
1290 | error_handler_free: |
1291 | imx219_free_controls(imx219); |
1292 | |
1293 | error_power_off: |
1294 | imx219_power_off(dev); |
1295 | |
1296 | return ret; |
1297 | } |
1298 | |
1299 | static void imx219_remove(struct i2c_client *client) |
1300 | { |
1301 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
1302 | struct imx219 *imx219 = to_imx219(sd: sd); |
1303 | |
1304 | v4l2_async_unregister_subdev(sd); |
1305 | v4l2_subdev_cleanup(sd); |
1306 | media_entity_cleanup(entity: &sd->entity); |
1307 | imx219_free_controls(imx219); |
1308 | |
1309 | pm_runtime_disable(dev: &client->dev); |
1310 | if (!pm_runtime_status_suspended(dev: &client->dev)) { |
1311 | imx219_power_off(dev: &client->dev); |
1312 | pm_runtime_set_suspended(dev: &client->dev); |
1313 | } |
1314 | } |
1315 | |
1316 | static const struct of_device_id imx219_dt_ids[] = { |
1317 | { .compatible = "sony,imx219"}, |
1318 | { /* sentinel */ } |
1319 | }; |
1320 | MODULE_DEVICE_TABLE(of, imx219_dt_ids); |
1321 | |
1322 | static const struct dev_pm_ops imx219_pm_ops = { |
1323 | SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL) |
1324 | }; |
1325 | |
1326 | static struct i2c_driver imx219_i2c_driver = { |
1327 | .driver = { |
1328 | .name = "imx219", |
1329 | .of_match_table = imx219_dt_ids, |
1330 | .pm = &imx219_pm_ops, |
1331 | }, |
1332 | .probe = imx219_probe, |
1333 | .remove = imx219_remove, |
1334 | }; |
1335 | |
1336 | module_i2c_driver(imx219_i2c_driver); |
1337 | |
1338 | MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com"); |
1339 | MODULE_DESCRIPTION("Sony IMX219 sensor driver"); |
1340 | MODULE_LICENSE("GPL v2"); |
1341 |
Definitions
- imx219_mode
- imx219_common_regs
- imx219_2lane_regs
- imx219_4lane_regs
- imx219_link_freq_menu
- imx219_link_freq_4lane_menu
- imx219_test_pattern_menu
- imx219_test_pattern_val
- imx219_supply_name
- imx219_mbus_formats
- supported_modes
- imx219
- to_imx219
- imx219_get_format_code
- imx219_get_format_bpp
- imx219_get_binning
- imx219_get_rate_factor
- imx219_set_ctrl
- imx219_ctrl_ops
- imx219_get_pixel_rate
- imx219_init_controls
- imx219_free_controls
- imx219_set_framefmt
- imx219_configure_lanes
- imx219_enable_streams
- imx219_disable_streams
- imx219_update_pad_format
- imx219_enum_mbus_code
- imx219_enum_frame_size
- imx219_set_pad_format
- imx219_get_selection
- imx219_init_state
- imx219_video_ops
- imx219_pad_ops
- imx219_subdev_ops
- imx219_internal_ops
- imx219_power_on
- imx219_power_off
- imx219_get_regulators
- imx219_identify_module
- imx219_check_hwcfg
- imx219_probe
- imx219_remove
- imx219_dt_ids
- imx219_pm_ops
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