1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Sony imx335 Camera Sensor Driver
4 *
5 * Copyright (C) 2021 Intel Corporation
6 */
7#include <linux/unaligned.h>
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/i2c.h>
12#include <linux/module.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15
16#include <media/v4l2-cci.h>
17#include <media/v4l2-ctrls.h>
18#include <media/v4l2-fwnode.h>
19#include <media/v4l2-subdev.h>
20
21/* Streaming Mode */
22#define IMX335_REG_MODE_SELECT CCI_REG8(0x3000)
23#define IMX335_MODE_STANDBY 0x01
24#define IMX335_MODE_STREAMING 0x00
25
26/* Group hold register */
27#define IMX335_REG_HOLD CCI_REG8(0x3001)
28
29#define IMX335_REG_MASTER_MODE CCI_REG8(0x3002)
30#define IMX335_REG_BCWAIT_TIME CCI_REG8(0x300c)
31#define IMX335_REG_CPWAIT_TIME CCI_REG8(0x300d)
32#define IMX335_REG_WINMODE CCI_REG8(0x3018)
33#define IMX335_REG_HTRIMMING_START CCI_REG16_LE(0x302c)
34#define IMX335_REG_HNUM CCI_REG16_LE(0x302e)
35
36/* Lines per frame */
37#define IMX335_REG_VMAX CCI_REG24_LE(0x3030)
38#define IMX335_REG_HMAX CCI_REG16_LE(0x3034)
39
40#define IMX335_REG_OPB_SIZE_V CCI_REG8(0x304c)
41#define IMX335_REG_ADBIT CCI_REG8(0x3050)
42#define IMX335_REG_Y_OUT_SIZE CCI_REG16_LE(0x3056)
43
44#define IMX335_REG_SHUTTER CCI_REG24_LE(0x3058)
45#define IMX335_EXPOSURE_MIN 1
46#define IMX335_SHUTTER_MIN 9
47#define IMX335_SHUTTER_MIN_BINNED 17
48#define IMX335_EXPOSURE_STEP 1
49#define IMX335_EXPOSURE_DEFAULT 0x0648
50
51#define IMX335_REG_AREA2_WIDTH_1 CCI_REG16_LE(0x3072)
52
53#define IMX335_REG_AREA3_ST_ADR_1 CCI_REG16_LE(0x3074)
54#define IMX335_REG_AREA3_WIDTH_1 CCI_REG16_LE(0x3076)
55
56/* Analog and Digital gain control */
57#define IMX335_REG_GAIN CCI_REG8(0x30e8)
58#define IMX335_AGAIN_MIN 0
59#define IMX335_AGAIN_MAX 100
60#define IMX335_AGAIN_STEP 1
61#define IMX335_AGAIN_DEFAULT 0
62
63/* Vertical flip */
64#define IMX335_REG_VREVERSE CCI_REG8(0x304f)
65
66#define IMX335_REG_TPG_TESTCLKEN CCI_REG8(0x3148)
67
68#define IMX335_REG_INCLKSEL1 CCI_REG16_LE(0x314c)
69#define IMX335_REG_INCLKSEL2 CCI_REG8(0x315a)
70#define IMX335_REG_INCLKSEL3 CCI_REG8(0x3168)
71#define IMX335_REG_INCLKSEL4 CCI_REG8(0x316a)
72
73#define IMX335_REG_MDBIT CCI_REG8(0x319d)
74#define IMX335_REG_SYSMODE CCI_REG8(0x319e)
75
76#define IMX335_REG_XVS_XHS_DRV CCI_REG8(0x31a1)
77
78/* Test pattern generator */
79#define IMX335_REG_TPG_DIG_CLP_MODE CCI_REG8(0x3280)
80#define IMX335_REG_TPG_EN_DUOUT CCI_REG8(0x329c)
81#define IMX335_REG_TPG CCI_REG8(0x329e)
82#define IMX335_TPG_ALL_000 0
83#define IMX335_TPG_ALL_FFF 1
84#define IMX335_TPG_ALL_555 2
85#define IMX335_TPG_ALL_AAA 3
86#define IMX335_TPG_TOG_555_AAA 4
87#define IMX335_TPG_TOG_AAA_555 5
88#define IMX335_TPG_TOG_000_555 6
89#define IMX335_TPG_TOG_555_000 7
90#define IMX335_TPG_TOG_000_FFF 8
91#define IMX335_TPG_TOG_FFF_000 9
92#define IMX335_TPG_H_COLOR_BARS 10
93#define IMX335_TPG_V_COLOR_BARS 11
94#define IMX335_REG_TPG_COLORWIDTH CCI_REG8(0x32a0)
95
96#define IMX335_REG_BLKLEVEL CCI_REG16_LE(0x3302)
97
98#define IMX335_REG_WRJ_OPEN CCI_REG8(0x336c)
99
100#define IMX335_REG_ADBIT1 CCI_REG16_LE(0x341c)
101
102/* Chip ID */
103#define IMX335_REG_ID CCI_REG8(0x3912)
104#define IMX335_ID 0x00
105
106/* Data Lanes */
107#define IMX335_REG_LANEMODE CCI_REG8(0x3a01)
108#define IMX335_2LANE 1
109#define IMX335_4LANE 3
110
111#define IMX335_REG_TCLKPOST CCI_REG16_LE(0x3a18)
112#define IMX335_REG_TCLKPREPARE CCI_REG16_LE(0x3a1a)
113#define IMX335_REG_TCLK_TRAIL CCI_REG16_LE(0x3a1c)
114#define IMX335_REG_TCLK_ZERO CCI_REG16_LE(0x3a1e)
115#define IMX335_REG_THS_PREPARE CCI_REG16_LE(0x3a20)
116#define IMX335_REG_THS_ZERO CCI_REG16_LE(0x3a22)
117#define IMX335_REG_THS_TRAIL CCI_REG16_LE(0x3a24)
118#define IMX335_REG_THS_EXIT CCI_REG16_LE(0x3a26)
119#define IMX335_REG_TPLX CCI_REG16_LE(0x3a28)
120
121/* Input clock rate */
122#define IMX335_INCLK_RATE 24000000
123
124/* CSI2 HW configuration */
125#define IMX335_LINK_FREQ_594MHz 594000000LL
126#define IMX335_LINK_FREQ_445MHz 445500000LL
127
128#define IMX335_NUM_DATA_LANES 4
129
130/* IMX335 native and active pixel array size. */
131static const struct v4l2_rect imx335_native_area = {
132 .top = 0,
133 .left = 0,
134 .width = 2696,
135 .height = 2044,
136};
137
138static const struct v4l2_rect imx335_active_area = {
139 .top = 50,
140 .left = 36,
141 .width = 2624,
142 .height = 1944,
143};
144
145/**
146 * struct imx335_reg_list - imx335 sensor register list
147 * @num_of_regs: Number of registers in the list
148 * @regs: Pointer to register list
149 */
150struct imx335_reg_list {
151 u32 num_of_regs;
152 const struct cci_reg_sequence *regs;
153};
154
155static const char * const imx335_supply_name[] = {
156 "avdd", /* Analog (2.9V) supply */
157 "ovdd", /* Digital I/O (1.8V) supply */
158 "dvdd", /* Digital Core (1.2V) supply */
159};
160
161enum imx335_scan_mode {
162 IMX335_ALL_PIXEL,
163 IMX335_2_2_BINNING,
164};
165
166/**
167 * struct imx335_mode - imx335 sensor mode structure
168 * @scan_mode: Configuration scan mode (All pixel / 2x2Binning)
169 * @width: Frame width
170 * @height: Frame height
171 * @code: Format code
172 * @hblank: Horizontal blanking in lines
173 * @vblank: Vertical blanking in lines
174 * @vblank_min: Minimum vertical blanking in lines
175 * @vblank_max: Maximum vertical blanking in lines
176 * @pclk: Sensor pixel clock
177 * @reg_list: Register list for sensor mode
178 * @vflip_normal: Register list vflip (normal readout)
179 * @vflip_inverted: Register list vflip (inverted readout)
180 */
181struct imx335_mode {
182 enum imx335_scan_mode scan_mode;
183 u32 width;
184 u32 height;
185 u32 code;
186 u32 hblank;
187 u32 vblank;
188 u32 vblank_min;
189 u32 vblank_max;
190 u64 pclk;
191 struct imx335_reg_list reg_list;
192 struct imx335_reg_list vflip_normal;
193 struct imx335_reg_list vflip_inverted;
194};
195
196/**
197 * struct imx335 - imx335 sensor device structure
198 * @dev: Pointer to generic device
199 * @client: Pointer to i2c client
200 * @sd: V4L2 sub-device
201 * @pad: Media pad. Only one pad supported
202 * @reset_gpio: Sensor reset gpio
203 * @supplies: Regulator supplies to handle power control
204 * @cci: CCI register map
205 * @inclk: Sensor input clock
206 * @ctrl_handler: V4L2 control handler
207 * @link_freq_ctrl: Pointer to link frequency control
208 * @pclk_ctrl: Pointer to pixel clock control
209 * @hblank_ctrl: Pointer to horizontal blanking control
210 * @vblank_ctrl: Pointer to vertical blanking control
211 * @vflip: Pointer to vertical flip control
212 * @exp_ctrl: Pointer to exposure control
213 * @again_ctrl: Pointer to analog gain control
214 * @vblank: Vertical blanking in lines
215 * @lane_mode: Mode for number of connected data lanes
216 * @cur_mode: Pointer to current selected sensor mode
217 * @link_freq_bitmap: Menu bitmap for link_freq_ctrl
218 * @cur_mbus_code: Currently selected media bus format code
219 */
220struct imx335 {
221 struct device *dev;
222 struct i2c_client *client;
223 struct v4l2_subdev sd;
224 struct media_pad pad;
225 struct gpio_desc *reset_gpio;
226 struct regulator_bulk_data supplies[ARRAY_SIZE(imx335_supply_name)];
227 struct regmap *cci;
228
229 struct clk *inclk;
230 struct v4l2_ctrl_handler ctrl_handler;
231 struct v4l2_ctrl *link_freq_ctrl;
232 struct v4l2_ctrl *pclk_ctrl;
233 struct v4l2_ctrl *hblank_ctrl;
234 struct v4l2_ctrl *vblank_ctrl;
235 struct v4l2_ctrl *vflip;
236 struct {
237 struct v4l2_ctrl *exp_ctrl;
238 struct v4l2_ctrl *again_ctrl;
239 };
240 u32 vblank;
241 u32 lane_mode;
242 const struct imx335_mode *cur_mode;
243 unsigned long link_freq_bitmap;
244 u32 cur_mbus_code;
245};
246
247static const char * const imx335_tpg_menu[] = {
248 "Disabled",
249 "All 000h",
250 "All FFFh",
251 "All 555h",
252 "All AAAh",
253 "Toggle 555/AAAh",
254 "Toggle AAA/555h",
255 "Toggle 000/555h",
256 "Toggle 555/000h",
257 "Toggle 000/FFFh",
258 "Toggle FFF/000h",
259 "Horizontal color bars",
260 "Vertical color bars",
261};
262
263static const int imx335_tpg_val[] = {
264 IMX335_TPG_ALL_000,
265 IMX335_TPG_ALL_000,
266 IMX335_TPG_ALL_FFF,
267 IMX335_TPG_ALL_555,
268 IMX335_TPG_ALL_AAA,
269 IMX335_TPG_TOG_555_AAA,
270 IMX335_TPG_TOG_AAA_555,
271 IMX335_TPG_TOG_000_555,
272 IMX335_TPG_TOG_555_000,
273 IMX335_TPG_TOG_000_FFF,
274 IMX335_TPG_TOG_FFF_000,
275 IMX335_TPG_H_COLOR_BARS,
276 IMX335_TPG_V_COLOR_BARS,
277};
278
279/* Sensor mode registers */
280static const struct cci_reg_sequence mode_2592x1944_regs[] = {
281 { IMX335_REG_MODE_SELECT, IMX335_MODE_STANDBY },
282 { IMX335_REG_MASTER_MODE, 0x00 },
283 { IMX335_REG_WINMODE, 0x04 },
284 { IMX335_REG_HMAX, 550 },
285 { IMX335_REG_HTRIMMING_START, 48 },
286 { IMX335_REG_HNUM, 2592 },
287 { IMX335_REG_Y_OUT_SIZE, 1944 },
288 { IMX335_REG_AREA2_WIDTH_1, 40 },
289 { IMX335_REG_AREA3_WIDTH_1, 3928 },
290 { IMX335_REG_OPB_SIZE_V, 0 },
291 { IMX335_REG_XVS_XHS_DRV, 0x00 },
292};
293
294static const struct cci_reg_sequence mode_1312x972_regs[] = {
295 { IMX335_REG_MODE_SELECT, IMX335_MODE_STANDBY },
296 { IMX335_REG_MASTER_MODE, 0x00 },
297 { IMX335_REG_WINMODE, 0x01 },
298 { IMX335_REG_HMAX, 275 },
299 { IMX335_REG_HTRIMMING_START, 48 },
300 { IMX335_REG_HNUM, 2600 },
301 { IMX335_REG_Y_OUT_SIZE, 972 },
302 { IMX335_REG_AREA2_WIDTH_1, 48 },
303 { IMX335_REG_AREA3_WIDTH_1, 3936 },
304 { IMX335_REG_OPB_SIZE_V, 0 },
305 { IMX335_REG_XVS_XHS_DRV, 0x00 },
306 { CCI_REG8(0x3300), 1 }, /* TCYCLE */
307 { CCI_REG8(0x3199), 0x30 }, /* HADD/VADD */
308};
309
310static const struct cci_reg_sequence imx335_common_regs[] = {
311 { CCI_REG8(0x3288), 0x21 },
312 { CCI_REG8(0x328a), 0x02 },
313 { CCI_REG8(0x3414), 0x05 },
314 { CCI_REG8(0x3416), 0x18 },
315 { CCI_REG8(0x3648), 0x01 },
316 { CCI_REG8(0x364a), 0x04 },
317 { CCI_REG8(0x364c), 0x04 },
318 { CCI_REG8(0x3678), 0x01 },
319 { CCI_REG8(0x367c), 0x31 },
320 { CCI_REG8(0x367e), 0x31 },
321 { CCI_REG8(0x3706), 0x10 },
322 { CCI_REG8(0x3708), 0x03 },
323 { CCI_REG8(0x3714), 0x02 },
324 { CCI_REG8(0x3715), 0x02 },
325 { CCI_REG8(0x3716), 0x01 },
326 { CCI_REG8(0x3717), 0x03 },
327 { CCI_REG8(0x371c), 0x3d },
328 { CCI_REG8(0x371d), 0x3f },
329 { CCI_REG8(0x372c), 0x00 },
330 { CCI_REG8(0x372d), 0x00 },
331 { CCI_REG8(0x372e), 0x46 },
332 { CCI_REG8(0x372f), 0x00 },
333 { CCI_REG8(0x3730), 0x89 },
334 { CCI_REG8(0x3731), 0x00 },
335 { CCI_REG8(0x3732), 0x08 },
336 { CCI_REG8(0x3733), 0x01 },
337 { CCI_REG8(0x3734), 0xfe },
338 { CCI_REG8(0x3735), 0x05 },
339 { CCI_REG8(0x3740), 0x02 },
340 { CCI_REG8(0x375d), 0x00 },
341 { CCI_REG8(0x375e), 0x00 },
342 { CCI_REG8(0x375f), 0x11 },
343 { CCI_REG8(0x3760), 0x01 },
344 { CCI_REG8(0x3768), 0x1b },
345 { CCI_REG8(0x3769), 0x1b },
346 { CCI_REG8(0x376a), 0x1b },
347 { CCI_REG8(0x376b), 0x1b },
348 { CCI_REG8(0x376c), 0x1a },
349 { CCI_REG8(0x376d), 0x17 },
350 { CCI_REG8(0x376e), 0x0f },
351 { CCI_REG8(0x3776), 0x00 },
352 { CCI_REG8(0x3777), 0x00 },
353 { CCI_REG8(0x3778), 0x46 },
354 { CCI_REG8(0x3779), 0x00 },
355 { CCI_REG8(0x377a), 0x89 },
356 { CCI_REG8(0x377b), 0x00 },
357 { CCI_REG8(0x377c), 0x08 },
358 { CCI_REG8(0x377d), 0x01 },
359 { CCI_REG8(0x377e), 0x23 },
360 { CCI_REG8(0x377f), 0x02 },
361 { CCI_REG8(0x3780), 0xd9 },
362 { CCI_REG8(0x3781), 0x03 },
363 { CCI_REG8(0x3782), 0xf5 },
364 { CCI_REG8(0x3783), 0x06 },
365 { CCI_REG8(0x3784), 0xa5 },
366 { CCI_REG8(0x3788), 0x0f },
367 { CCI_REG8(0x378a), 0xd9 },
368 { CCI_REG8(0x378b), 0x03 },
369 { CCI_REG8(0x378c), 0xeb },
370 { CCI_REG8(0x378d), 0x05 },
371 { CCI_REG8(0x378e), 0x87 },
372 { CCI_REG8(0x378f), 0x06 },
373 { CCI_REG8(0x3790), 0xf5 },
374 { CCI_REG8(0x3792), 0x43 },
375 { CCI_REG8(0x3794), 0x7a },
376 { CCI_REG8(0x3796), 0xa1 },
377 { CCI_REG8(0x37b0), 0x36 },
378 { CCI_REG8(0x3a00), 0x00 },
379};
380
381static const struct cci_reg_sequence mode_2592x1944_vflip_normal[] = {
382 { IMX335_REG_AREA3_ST_ADR_1, 176 },
383
384 /* Undocumented V-Flip related registers on Page 55 of datasheet. */
385 { CCI_REG8(0x3081), 0x02, },
386 { CCI_REG8(0x3083), 0x02, },
387 { CCI_REG16_LE(0x30b6), 0x00 },
388 { CCI_REG16_LE(0x3116), 0x08 },
389};
390
391static const struct cci_reg_sequence mode_2592x1944_vflip_inverted[] = {
392 { IMX335_REG_AREA3_ST_ADR_1, 4112 },
393
394 /* Undocumented V-Flip related registers on Page 55 of datasheet. */
395 { CCI_REG8(0x3081), 0xfe, },
396 { CCI_REG8(0x3083), 0xfe, },
397 { CCI_REG16_LE(0x30b6), 0x1fa },
398 { CCI_REG16_LE(0x3116), 0x002 },
399};
400
401static const struct cci_reg_sequence mode_1312x972_vflip_normal[] = {
402 { IMX335_REG_AREA3_ST_ADR_1, 176 },
403
404 /* Undocumented */
405 { CCI_REG8(0x3078), 0x04 },
406 { CCI_REG8(0x3079), 0xfd },
407 { CCI_REG8(0x307a), 0x04 },
408 { CCI_REG8(0x307b), 0xfe },
409 { CCI_REG8(0x307c), 0x04 },
410 { CCI_REG8(0x307d), 0xfb },
411 { CCI_REG8(0x307e), 0x04 },
412 { CCI_REG8(0x307f), 0x02 },
413 { CCI_REG8(0x3080), 0x04 },
414 { CCI_REG8(0x3081), 0xfd },
415 { CCI_REG8(0x3082), 0x04 },
416 { CCI_REG8(0x3083), 0xfe },
417 { CCI_REG8(0x3084), 0x04 },
418 { CCI_REG8(0x3085), 0xfb },
419 { CCI_REG8(0x3086), 0x04 },
420 { CCI_REG8(0x3087), 0x02 },
421 { CCI_REG8(0x30a4), 0x77 },
422 { CCI_REG8(0x30a8), 0x20 },
423 { CCI_REG8(0x30a9), 0x00 },
424 { CCI_REG8(0x30ac), 0x08 },
425 { CCI_REG8(0x30ad), 0x08 },
426 { CCI_REG8(0x30b0), 0x20 },
427 { CCI_REG8(0x30b1), 0x00 },
428 { CCI_REG8(0x30b4), 0x10 },
429 { CCI_REG8(0x30b5), 0x10 },
430 { CCI_REG16_LE(0x30b6), 0x00 },
431 { CCI_REG16_LE(0x3112), 0x10 },
432 { CCI_REG16_LE(0x3116), 0x10 },
433};
434
435static const struct cci_reg_sequence mode_1312x972_vflip_inverted[] = {
436 { IMX335_REG_AREA3_ST_ADR_1, 4112 },
437
438 /* Undocumented */
439 { CCI_REG8(0x3078), 0x04 },
440 { CCI_REG8(0x3079), 0xfd },
441 { CCI_REG8(0x307a), 0x04 },
442 { CCI_REG8(0x307b), 0xfe },
443 { CCI_REG8(0x307c), 0x04 },
444 { CCI_REG8(0x307d), 0xfb },
445 { CCI_REG8(0x307e), 0x04 },
446 { CCI_REG8(0x307f), 0x02 },
447 { CCI_REG8(0x3080), 0xfc },
448 { CCI_REG8(0x3081), 0x05 },
449 { CCI_REG8(0x3082), 0xfc },
450 { CCI_REG8(0x3083), 0x02 },
451 { CCI_REG8(0x3084), 0xfc },
452 { CCI_REG8(0x3085), 0x03 },
453 { CCI_REG8(0x3086), 0xfc },
454 { CCI_REG8(0x3087), 0xfe },
455 { CCI_REG8(0x30a4), 0x77 },
456 { CCI_REG8(0x30a8), 0x20 },
457 { CCI_REG8(0x30a9), 0x00 },
458 { CCI_REG8(0x30ac), 0x08 },
459 { CCI_REG8(0x30ad), 0x78 },
460 { CCI_REG8(0x30b0), 0x20 },
461 { CCI_REG8(0x30b1), 0x00 },
462 { CCI_REG8(0x30b4), 0x10 },
463 { CCI_REG8(0x30b5), 0x70 },
464 { CCI_REG16_LE(0x30b6), 0x01f2 },
465 { CCI_REG16_LE(0x3112), 0x10 },
466 { CCI_REG16_LE(0x3116), 0x02 },
467};
468
469static const struct cci_reg_sequence mipi_data_rate_1188Mbps[] = {
470 { IMX335_REG_BCWAIT_TIME, 0x3b },
471 { IMX335_REG_CPWAIT_TIME, 0x2a },
472 { IMX335_REG_INCLKSEL1, 0x00c6 },
473 { IMX335_REG_INCLKSEL2, 0x02 },
474 { IMX335_REG_INCLKSEL3, 0xa0 },
475 { IMX335_REG_INCLKSEL4, 0x7e },
476 { IMX335_REG_SYSMODE, 0x01 },
477 { IMX335_REG_TCLKPOST, 0x8f },
478 { IMX335_REG_TCLKPREPARE, 0x4f },
479 { IMX335_REG_TCLK_TRAIL, 0x47 },
480 { IMX335_REG_TCLK_ZERO, 0x0137 },
481 { IMX335_REG_THS_PREPARE, 0x4f },
482 { IMX335_REG_THS_ZERO, 0x87 },
483 { IMX335_REG_THS_TRAIL, 0x4f },
484 { IMX335_REG_THS_EXIT, 0x7f },
485 { IMX335_REG_TPLX, 0x3f },
486};
487
488static const struct cci_reg_sequence mipi_data_rate_891Mbps[] = {
489 { IMX335_REG_BCWAIT_TIME, 0x3b },
490 { IMX335_REG_CPWAIT_TIME, 0x2a },
491 { IMX335_REG_INCLKSEL1, 0x0129 },
492 { IMX335_REG_INCLKSEL2, 0x06 },
493 { IMX335_REG_INCLKSEL3, 0xa0 },
494 { IMX335_REG_INCLKSEL4, 0x7e },
495 { IMX335_REG_SYSMODE, 0x02 },
496 { IMX335_REG_TCLKPOST, 0x7f },
497 { IMX335_REG_TCLKPREPARE, 0x37 },
498 { IMX335_REG_TCLK_TRAIL, 0x37 },
499 { IMX335_REG_TCLK_ZERO, 0xf7 },
500 { IMX335_REG_THS_PREPARE, 0x3f },
501 { IMX335_REG_THS_ZERO, 0x6f },
502 { IMX335_REG_THS_TRAIL, 0x3f },
503 { IMX335_REG_THS_EXIT, 0x5f },
504 { IMX335_REG_TPLX, 0x2f },
505};
506
507static const s64 link_freq[] = {
508 /* Corresponds to 1188Mbps data lane rate */
509 IMX335_LINK_FREQ_594MHz,
510 /* Corresponds to 891Mbps data lane rate */
511 IMX335_LINK_FREQ_445MHz,
512};
513
514static const struct imx335_reg_list link_freq_reglist[] = {
515 {
516 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1188Mbps),
517 .regs = mipi_data_rate_1188Mbps,
518 },
519 {
520 .num_of_regs = ARRAY_SIZE(mipi_data_rate_891Mbps),
521 .regs = mipi_data_rate_891Mbps,
522 },
523};
524
525static const u32 imx335_mbus_codes[] = {
526 MEDIA_BUS_FMT_SRGGB12_1X12,
527 MEDIA_BUS_FMT_SRGGB10_1X10,
528};
529
530/* Supported sensor mode configurations */
531static const struct imx335_mode supported_modes[] = {
532 {
533 .scan_mode = IMX335_ALL_PIXEL,
534 .width = 2592,
535 .height = 1944,
536 .hblank = 342,
537 .vblank = 2556,
538 .vblank_min = 2556,
539 .vblank_max = 133060,
540 .pclk = 396000000,
541 .reg_list = {
542 .num_of_regs = ARRAY_SIZE(mode_2592x1944_regs),
543 .regs = mode_2592x1944_regs,
544 },
545 .vflip_normal = {
546 .num_of_regs = ARRAY_SIZE(mode_2592x1944_vflip_normal),
547 .regs = mode_2592x1944_vflip_normal,
548 },
549 .vflip_inverted = {
550 .num_of_regs = ARRAY_SIZE(mode_2592x1944_vflip_inverted),
551 .regs = mode_2592x1944_vflip_inverted,
552 }
553 }, {
554 .scan_mode = IMX335_2_2_BINNING,
555 .width = 1312,
556 .height = 972,
557 .hblank = 155,
558 .vblank = 3528,
559 .vblank_min = 3528,
560 .vblank_max = 133060,
561 .pclk = 396000000,
562 .reg_list = {
563 .num_of_regs = ARRAY_SIZE(mode_1312x972_regs),
564 .regs = mode_1312x972_regs,
565 },
566 .vflip_normal = {
567 .num_of_regs = ARRAY_SIZE(mode_1312x972_vflip_normal),
568 .regs = mode_1312x972_vflip_normal,
569 },
570 .vflip_inverted = {
571 .num_of_regs = ARRAY_SIZE(mode_1312x972_vflip_inverted),
572 .regs = mode_1312x972_vflip_inverted,
573 },
574 },
575};
576
577/**
578 * to_imx335() - imx335 V4L2 sub-device to imx335 device.
579 * @subdev: pointer to imx335 V4L2 sub-device
580 *
581 * Return: pointer to imx335 device
582 */
583static inline struct imx335 *to_imx335(struct v4l2_subdev *subdev)
584{
585 return container_of(subdev, struct imx335, sd);
586}
587
588/**
589 * imx335_update_controls() - Update control ranges based on streaming mode
590 * @imx335: pointer to imx335 device
591 * @mode: pointer to imx335_mode sensor mode
592 *
593 * Return: 0 if successful, error code otherwise.
594 */
595static int imx335_update_controls(struct imx335 *imx335,
596 const struct imx335_mode *mode)
597{
598 int ret;
599
600 ret = __v4l2_ctrl_s_ctrl(ctrl: imx335->link_freq_ctrl,
601 __ffs(imx335->link_freq_bitmap));
602 if (ret)
603 return ret;
604
605 ret = __v4l2_ctrl_modify_range(ctrl: imx335->hblank_ctrl, min: mode->hblank,
606 max: mode->hblank, step: 1, def: mode->hblank);
607 if (ret)
608 return ret;
609
610 return __v4l2_ctrl_modify_range(ctrl: imx335->vblank_ctrl, min: mode->vblank_min,
611 max: mode->vblank_max, step: 1, def: mode->vblank);
612}
613
614/**
615 * imx335_update_exp_gain() - Set updated exposure and gain
616 * @imx335: pointer to imx335 device
617 * @exposure: updated exposure value
618 * @gain: updated analog gain value
619 *
620 * Return: 0 if successful, error code otherwise.
621 */
622static int imx335_update_exp_gain(struct imx335 *imx335, u32 exposure, u32 gain)
623{
624 u32 lpfr, shutter;
625 int ret_hold;
626 int ret = 0;
627
628 lpfr = imx335->vblank + imx335->cur_mode->height;
629 shutter = lpfr - exposure;
630
631 dev_dbg(imx335->dev, "Set exp %u, analog gain %u, shutter %u, lpfr %u\n",
632 exposure, gain, shutter, lpfr);
633
634 cci_write(map: imx335->cci, IMX335_REG_HOLD, val: 1, err: &ret);
635 cci_write(map: imx335->cci, IMX335_REG_VMAX, val: lpfr, err: &ret);
636 cci_write(map: imx335->cci, IMX335_REG_SHUTTER, val: shutter, err: &ret);
637 cci_write(map: imx335->cci, IMX335_REG_GAIN, val: gain, err: &ret);
638 /*
639 * Unconditionally attempt to release the hold, but track the
640 * error if the unhold itself fails.
641 */
642 ret_hold = cci_write(map: imx335->cci, IMX335_REG_HOLD, val: 0, NULL);
643 if (ret_hold)
644 ret = ret_hold;
645
646 return ret;
647}
648
649static int imx335_update_vertical_flip(struct imx335 *imx335, u32 vflip)
650{
651 const struct imx335_reg_list * const vflip_regs =
652 vflip ? &imx335->cur_mode->vflip_inverted :
653 &imx335->cur_mode->vflip_normal;
654 int ret = 0;
655
656 cci_multi_reg_write(map: imx335->cci, regs: vflip_regs->regs,
657 num_regs: vflip_regs->num_of_regs, err: &ret);
658
659 return cci_write(map: imx335->cci, IMX335_REG_VREVERSE, val: vflip, err: &ret);
660}
661
662static int imx335_update_test_pattern(struct imx335 *imx335, u32 pattern_index)
663{
664 int ret = 0;
665
666 if (pattern_index >= ARRAY_SIZE(imx335_tpg_val))
667 return -EINVAL;
668
669 if (pattern_index) {
670 const struct cci_reg_sequence tpg_enable_regs[] = {
671 { IMX335_REG_TPG_TESTCLKEN, 0x10 },
672 { IMX335_REG_TPG_DIG_CLP_MODE, 0x00 },
673 { IMX335_REG_TPG_EN_DUOUT, 0x01 },
674 { IMX335_REG_TPG_COLORWIDTH, 0x11 },
675 { IMX335_REG_BLKLEVEL, 0x00 },
676 { IMX335_REG_WRJ_OPEN, 0x00 },
677 };
678
679 cci_write(map: imx335->cci, IMX335_REG_TPG,
680 val: imx335_tpg_val[pattern_index], err: &ret);
681
682 cci_multi_reg_write(map: imx335->cci, regs: tpg_enable_regs,
683 ARRAY_SIZE(tpg_enable_regs), err: &ret);
684 } else {
685 const struct cci_reg_sequence tpg_disable_regs[] = {
686 { IMX335_REG_TPG_TESTCLKEN, 0x00 },
687 { IMX335_REG_TPG_DIG_CLP_MODE, 0x01 },
688 { IMX335_REG_TPG_EN_DUOUT, 0x00 },
689 { IMX335_REG_TPG_COLORWIDTH, 0x10 },
690 { IMX335_REG_BLKLEVEL, 0x32 },
691 { IMX335_REG_WRJ_OPEN, 0x01 },
692 };
693
694 cci_multi_reg_write(map: imx335->cci, regs: tpg_disable_regs,
695 ARRAY_SIZE(tpg_disable_regs), err: &ret);
696 }
697
698 return ret;
699}
700
701/**
702 * imx335_set_ctrl() - Set subdevice control
703 * @ctrl: pointer to v4l2_ctrl structure
704 *
705 * Supported controls:
706 * - V4L2_CID_VBLANK
707 * - cluster controls:
708 * - V4L2_CID_ANALOGUE_GAIN
709 * - V4L2_CID_EXPOSURE
710 *
711 * Return: 0 if successful, error code otherwise.
712 */
713static int imx335_set_ctrl(struct v4l2_ctrl *ctrl)
714{
715 struct imx335 *imx335 =
716 container_of(ctrl->handler, struct imx335, ctrl_handler);
717 u32 analog_gain;
718 u32 exposure;
719 int ret;
720
721 /* Propagate change of current control to all related controls */
722 if (ctrl->id == V4L2_CID_VBLANK) {
723 u32 shutter_min = IMX335_SHUTTER_MIN;
724 u32 lpfr;
725
726 imx335->vblank = imx335->vblank_ctrl->val;
727 lpfr = imx335->vblank + imx335->cur_mode->height;
728
729 dev_dbg(imx335->dev, "Received vblank %u, new lpfr %u\n",
730 imx335->vblank, lpfr);
731
732 if (imx335->cur_mode->scan_mode == IMX335_2_2_BINNING)
733 shutter_min = IMX335_SHUTTER_MIN_BINNED;
734
735 ret = __v4l2_ctrl_modify_range(ctrl: imx335->exp_ctrl,
736 IMX335_EXPOSURE_MIN,
737 max: lpfr - shutter_min, step: 1,
738 IMX335_EXPOSURE_DEFAULT);
739 if (ret)
740 return ret;
741 }
742
743 /*
744 * Applying V4L2 control value only happens
745 * when power is up for streaming.
746 */
747 if (pm_runtime_get_if_in_use(dev: imx335->dev) == 0)
748 return 0;
749
750 switch (ctrl->id) {
751 case V4L2_CID_VBLANK:
752 exposure = imx335->exp_ctrl->val;
753 analog_gain = imx335->again_ctrl->val;
754
755 ret = imx335_update_exp_gain(imx335, exposure, gain: analog_gain);
756
757 break;
758 case V4L2_CID_EXPOSURE:
759 exposure = ctrl->val;
760 analog_gain = imx335->again_ctrl->val;
761
762 dev_dbg(imx335->dev, "Received exp %u, analog gain %u\n",
763 exposure, analog_gain);
764
765 ret = imx335_update_exp_gain(imx335, exposure, gain: analog_gain);
766
767 break;
768 case V4L2_CID_VFLIP:
769 ret = imx335_update_vertical_flip(imx335, vflip: ctrl->val);
770
771 break;
772 case V4L2_CID_TEST_PATTERN:
773 ret = imx335_update_test_pattern(imx335, pattern_index: ctrl->val);
774
775 break;
776 default:
777 dev_err(imx335->dev, "Invalid control %d\n", ctrl->id);
778 ret = -EINVAL;
779 }
780
781 pm_runtime_put(dev: imx335->dev);
782
783 return ret;
784}
785
786/* V4l2 subdevice control ops*/
787static const struct v4l2_ctrl_ops imx335_ctrl_ops = {
788 .s_ctrl = imx335_set_ctrl,
789};
790
791static int imx335_get_format_code(struct imx335 *imx335, u32 code)
792{
793 unsigned int i;
794
795 for (i = 0; i < ARRAY_SIZE(imx335_mbus_codes); i++) {
796 if (imx335_mbus_codes[i] == code)
797 return imx335_mbus_codes[i];
798 }
799
800 return imx335_mbus_codes[0];
801}
802
803/**
804 * imx335_enum_mbus_code() - Enumerate V4L2 sub-device mbus codes
805 * @sd: pointer to imx335 V4L2 sub-device structure
806 * @sd_state: V4L2 sub-device configuration
807 * @code: V4L2 sub-device code enumeration need to be filled
808 *
809 * Return: 0 if successful, error code otherwise.
810 */
811static int imx335_enum_mbus_code(struct v4l2_subdev *sd,
812 struct v4l2_subdev_state *sd_state,
813 struct v4l2_subdev_mbus_code_enum *code)
814{
815 if (code->index >= ARRAY_SIZE(imx335_mbus_codes))
816 return -EINVAL;
817
818 code->code = imx335_mbus_codes[code->index];
819
820 return 0;
821}
822
823/**
824 * imx335_enum_frame_size() - Enumerate V4L2 sub-device frame sizes
825 * @sd: pointer to imx335 V4L2 sub-device structure
826 * @sd_state: V4L2 sub-device configuration
827 * @fsize: V4L2 sub-device size enumeration need to be filled
828 *
829 * Return: 0 if successful, error code otherwise.
830 */
831static int imx335_enum_frame_size(struct v4l2_subdev *sd,
832 struct v4l2_subdev_state *sd_state,
833 struct v4l2_subdev_frame_size_enum *fsize)
834{
835 struct imx335 *imx335 = to_imx335(subdev: sd);
836 u32 code;
837
838 if (fsize->index >= ARRAY_SIZE(supported_modes))
839 return -EINVAL;
840
841 code = imx335_get_format_code(imx335, code: fsize->code);
842 if (fsize->code != code)
843 return -EINVAL;
844
845 fsize->min_width = supported_modes[fsize->index].width;
846 fsize->max_width = fsize->min_width;
847 fsize->min_height = supported_modes[fsize->index].height;
848 fsize->max_height = fsize->min_height;
849
850 return 0;
851}
852
853/**
854 * imx335_fill_pad_format() - Fill subdevice pad format
855 * from selected sensor mode
856 * @imx335: pointer to imx335 device
857 * @mode: pointer to imx335_mode sensor mode
858 * @fmt: V4L2 sub-device format need to be filled
859 */
860static void imx335_fill_pad_format(struct imx335 *imx335,
861 const struct imx335_mode *mode,
862 struct v4l2_subdev_format *fmt)
863{
864 fmt->format.width = mode->width;
865 fmt->format.height = mode->height;
866 fmt->format.code = imx335->cur_mbus_code;
867 fmt->format.field = V4L2_FIELD_NONE;
868 fmt->format.colorspace = V4L2_COLORSPACE_RAW;
869 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
870 fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT;
871 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
872}
873
874/**
875 * imx335_set_pad_format() - Set subdevice pad format
876 * @sd: pointer to imx335 V4L2 sub-device structure
877 * @sd_state: V4L2 sub-device configuration
878 * @fmt: V4L2 sub-device format need to be set
879 *
880 * Return: 0 if successful, error code otherwise.
881 */
882static int imx335_set_pad_format(struct v4l2_subdev *sd,
883 struct v4l2_subdev_state *sd_state,
884 struct v4l2_subdev_format *fmt)
885{
886 struct imx335 *imx335 = to_imx335(subdev: sd);
887 struct v4l2_mbus_framefmt *format;
888 const struct imx335_mode *mode;
889 struct v4l2_rect *crop;
890 int i, ret = 0;
891
892 mode = v4l2_find_nearest_size(supported_modes,
893 ARRAY_SIZE(supported_modes),
894 width, height,
895 fmt->format.width, fmt->format.height);
896
897 for (i = 0; i < ARRAY_SIZE(imx335_mbus_codes); i++) {
898 if (imx335_mbus_codes[i] == fmt->format.code)
899 imx335->cur_mbus_code = imx335_mbus_codes[i];
900 }
901
902 imx335_fill_pad_format(imx335, mode, fmt);
903
904 format = v4l2_subdev_state_get_format(sd_state, fmt->pad);
905 *format = fmt->format;
906
907 crop = v4l2_subdev_state_get_crop(sd_state, fmt->pad);
908 crop->width = fmt->format.width;
909 crop->height = fmt->format.height;
910 if (mode->scan_mode == IMX335_2_2_BINNING) {
911 crop->width *= 2;
912 crop->height *= 2;
913 }
914 crop->left = (imx335_native_area.width - crop->width) / 2;
915 crop->top = (imx335_native_area.height - crop->height) / 2;
916
917 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
918 ret = imx335_update_controls(imx335, mode);
919 if (!ret)
920 imx335->cur_mode = mode;
921 }
922
923 return ret;
924}
925
926/**
927 * imx335_init_state() - Initialize sub-device state
928 * @sd: pointer to imx335 V4L2 sub-device structure
929 * @sd_state: V4L2 sub-device configuration
930 *
931 * Return: 0 if successful, error code otherwise.
932 */
933static int imx335_init_state(struct v4l2_subdev *sd,
934 struct v4l2_subdev_state *sd_state)
935{
936 struct imx335 *imx335 = to_imx335(subdev: sd);
937 struct v4l2_subdev_format fmt = { 0 };
938
939 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
940 imx335_fill_pad_format(imx335, mode: &supported_modes[0], fmt: &fmt);
941
942 __v4l2_ctrl_modify_range(ctrl: imx335->link_freq_ctrl, min: 0,
943 max: __fls(word: imx335->link_freq_bitmap),
944 step: ~(imx335->link_freq_bitmap),
945 __ffs(imx335->link_freq_bitmap));
946
947 return imx335_set_pad_format(sd, sd_state, fmt: &fmt);
948}
949
950/**
951 * imx335_get_selection() - Selection API
952 * @sd: pointer to imx335 V4L2 sub-device structure
953 * @sd_state: V4L2 sub-device configuration
954 * @sel: V4L2 selection info
955 *
956 * Return: 0 if successful, error code otherwise.
957 */
958static int imx335_get_selection(struct v4l2_subdev *sd,
959 struct v4l2_subdev_state *sd_state,
960 struct v4l2_subdev_selection *sel)
961{
962 switch (sel->target) {
963 case V4L2_SEL_TGT_CROP:
964 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);
965
966 return 0;
967
968 case V4L2_SEL_TGT_NATIVE_SIZE:
969 sel->r = imx335_native_area;
970 return 0;
971
972 case V4L2_SEL_TGT_CROP_DEFAULT:
973 case V4L2_SEL_TGT_CROP_BOUNDS:
974 sel->r = imx335_active_area;
975 return 0;
976 }
977
978 return -EINVAL;
979}
980
981static int imx335_set_framefmt(struct imx335 *imx335)
982{
983 /*
984 * In the all-pixel scan mode the AD conversion shall match the output
985 * bit width requested.
986 *
987 * However, when 2/2 binning is enabled, the AD conversion is always
988 * 10-bit, so we ensure ADBIT is clear and ADBIT1 is assigned 0x1ff.
989 * That's as much as the documentation gives us...
990 */
991 int ret = 0;
992 u8 bpp = imx335->cur_mbus_code == MEDIA_BUS_FMT_SRGGB10_1X10 ? 10 : 12;
993 u8 ad_conv = bpp;
994
995 /* Start with the output mode */
996 cci_write(map: imx335->cci, IMX335_REG_MDBIT, val: bpp == 12, err: &ret);
997
998 /* Enforce 10 bit AD on binning modes */
999 if (imx335->cur_mode->scan_mode == IMX335_2_2_BINNING)
1000 ad_conv = 10;
1001
1002 /* AD Conversion configuration */
1003 if (ad_conv == 10) {
1004 cci_write(map: imx335->cci, IMX335_REG_ADBIT, val: 0x00, err: &ret);
1005 cci_write(map: imx335->cci, IMX335_REG_ADBIT1, val: 0x1ff, err: &ret);
1006 } else { /* 12 bit AD Conversion */
1007 cci_write(map: imx335->cci, IMX335_REG_ADBIT, val: 0x01, err: &ret);
1008 cci_write(map: imx335->cci, IMX335_REG_ADBIT1, val: 0x47, err: &ret);
1009 }
1010
1011 return ret;
1012}
1013
1014/**
1015 * imx335_enable_streams() - Enable sensor streams
1016 * @sd: V4L2 subdevice
1017 * @state: V4L2 subdevice state
1018 * @pad: The pad to enable
1019 * @streams_mask: Bitmask of streams to enable
1020 *
1021 * Return: 0 if successful, error code otherwise.
1022 */
1023static int imx335_enable_streams(struct v4l2_subdev *sd,
1024 struct v4l2_subdev_state *state, u32 pad,
1025 u64 streams_mask)
1026{
1027 struct imx335 *imx335 = to_imx335(subdev: sd);
1028 const struct imx335_reg_list *reg_list;
1029 int ret;
1030
1031 ret = pm_runtime_resume_and_get(dev: imx335->dev);
1032 if (ret < 0)
1033 return ret;
1034
1035 /* Setup PLL */
1036 reg_list = &link_freq_reglist[__ffs(imx335->link_freq_bitmap)];
1037 ret = cci_multi_reg_write(map: imx335->cci, regs: reg_list->regs,
1038 num_regs: reg_list->num_of_regs, NULL);
1039 if (ret) {
1040 dev_err(imx335->dev, "%s failed to set plls\n", __func__);
1041 goto err_rpm_put;
1042 }
1043
1044 /* Write sensor mode registers */
1045 reg_list = &imx335->cur_mode->reg_list;
1046 ret = cci_multi_reg_write(map: imx335->cci, regs: reg_list->regs,
1047 num_regs: reg_list->num_of_regs, NULL);
1048 if (ret) {
1049 dev_err(imx335->dev, "fail to write initial registers\n");
1050 goto err_rpm_put;
1051 }
1052
1053 /* Write sensor common registers */
1054 ret = cci_multi_reg_write(map: imx335->cci, regs: imx335_common_regs,
1055 ARRAY_SIZE(imx335_common_regs), NULL);
1056 if (ret) {
1057 dev_err(imx335->dev, "fail to write initial registers\n");
1058 goto err_rpm_put;
1059 }
1060
1061 ret = imx335_set_framefmt(imx335);
1062 if (ret) {
1063 dev_err(imx335->dev, "%s failed to set frame format: %d\n",
1064 __func__, ret);
1065 goto err_rpm_put;
1066 }
1067
1068 /* Configure lanes */
1069 ret = cci_write(map: imx335->cci, IMX335_REG_LANEMODE,
1070 val: imx335->lane_mode, NULL);
1071 if (ret)
1072 goto err_rpm_put;
1073
1074 /* Setup handler will write actual exposure and gain */
1075 ret = __v4l2_ctrl_handler_setup(hdl: imx335->sd.ctrl_handler);
1076 if (ret) {
1077 dev_err(imx335->dev, "fail to setup handler\n");
1078 goto err_rpm_put;
1079 }
1080
1081 /* Start streaming */
1082 ret = cci_write(map: imx335->cci, IMX335_REG_MODE_SELECT,
1083 IMX335_MODE_STREAMING, NULL);
1084 if (ret) {
1085 dev_err(imx335->dev, "fail to start streaming\n");
1086 goto err_rpm_put;
1087 }
1088
1089 /* Initial regulator stabilization period */
1090 usleep_range(min: 18000, max: 20000);
1091
1092 return 0;
1093
1094err_rpm_put:
1095 pm_runtime_put(dev: imx335->dev);
1096
1097 return ret;
1098}
1099
1100/**
1101 * imx335_disable_streams() - Disable sensor streams
1102 * @sd: V4L2 subdevice
1103 * @state: V4L2 subdevice state
1104 * @pad: The pad to disable
1105 * @streams_mask: Bitmask of streams to disable
1106 *
1107 * Return: 0 if successful, error code otherwise.
1108 */
1109static int imx335_disable_streams(struct v4l2_subdev *sd,
1110 struct v4l2_subdev_state *state, u32 pad,
1111 u64 streams_mask)
1112{
1113 struct imx335 *imx335 = to_imx335(subdev: sd);
1114 int ret;
1115
1116 ret = cci_write(map: imx335->cci, IMX335_REG_MODE_SELECT,
1117 IMX335_MODE_STANDBY, NULL);
1118 pm_runtime_put(dev: imx335->dev);
1119
1120 return ret;
1121}
1122
1123/**
1124 * imx335_detect() - Detect imx335 sensor
1125 * @imx335: pointer to imx335 device
1126 *
1127 * Return: 0 if successful, -EIO if sensor id does not match
1128 */
1129static int imx335_detect(struct imx335 *imx335)
1130{
1131 int ret;
1132 u64 val;
1133
1134 ret = cci_read(map: imx335->cci, IMX335_REG_ID, val: &val, NULL);
1135 if (ret)
1136 return ret;
1137
1138 if (val != IMX335_ID) {
1139 dev_err(imx335->dev, "chip id mismatch: %x!=%llx\n",
1140 IMX335_ID, val);
1141 return -ENXIO;
1142 }
1143
1144 return 0;
1145}
1146
1147/**
1148 * imx335_parse_hw_config() - Parse HW configuration and check if supported
1149 * @imx335: pointer to imx335 device
1150 *
1151 * Return: 0 if successful, error code otherwise.
1152 */
1153static int imx335_parse_hw_config(struct imx335 *imx335)
1154{
1155 struct fwnode_handle *fwnode = dev_fwnode(imx335->dev);
1156 struct v4l2_fwnode_endpoint bus_cfg = {
1157 .bus_type = V4L2_MBUS_CSI2_DPHY
1158 };
1159 struct fwnode_handle *ep;
1160 unsigned long rate;
1161 unsigned int i;
1162 int ret;
1163
1164 if (!fwnode)
1165 return -ENXIO;
1166
1167 /* Request optional reset pin */
1168 imx335->reset_gpio = devm_gpiod_get_optional(dev: imx335->dev, con_id: "reset",
1169 flags: GPIOD_OUT_HIGH);
1170 if (IS_ERR(ptr: imx335->reset_gpio)) {
1171 dev_err(imx335->dev, "failed to get reset gpio %pe\n",
1172 imx335->reset_gpio);
1173 return PTR_ERR(ptr: imx335->reset_gpio);
1174 }
1175
1176 for (i = 0; i < ARRAY_SIZE(imx335_supply_name); i++)
1177 imx335->supplies[i].supply = imx335_supply_name[i];
1178
1179 ret = devm_regulator_bulk_get(dev: imx335->dev,
1180 ARRAY_SIZE(imx335_supply_name),
1181 consumers: imx335->supplies);
1182 if (ret) {
1183 dev_err(imx335->dev, "Failed to get regulators\n");
1184 return ret;
1185 }
1186
1187 /* Get sensor input clock */
1188 imx335->inclk = devm_v4l2_sensor_clk_get(dev: imx335->dev, NULL);
1189 if (IS_ERR(ptr: imx335->inclk))
1190 return dev_err_probe(dev: imx335->dev, err: PTR_ERR(ptr: imx335->inclk),
1191 fmt: "could not get inclk\n");
1192
1193 rate = clk_get_rate(clk: imx335->inclk);
1194 if (rate != IMX335_INCLK_RATE) {
1195 dev_err(imx335->dev, "inclk frequency mismatch\n");
1196 return -EINVAL;
1197 }
1198
1199 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1200 if (!ep) {
1201 dev_err(imx335->dev, "Failed to get next endpoint\n");
1202 return -ENXIO;
1203 }
1204
1205 ret = v4l2_fwnode_endpoint_alloc_parse(fwnode: ep, vep: &bus_cfg);
1206 fwnode_handle_put(fwnode: ep);
1207 if (ret)
1208 return ret;
1209
1210 switch (bus_cfg.bus.mipi_csi2.num_data_lanes) {
1211 case 2:
1212 imx335->lane_mode = IMX335_2LANE;
1213 break;
1214 case 4:
1215 imx335->lane_mode = IMX335_4LANE;
1216 break;
1217 default:
1218 dev_err(imx335->dev,
1219 "number of CSI2 data lanes %d is not supported\n",
1220 bus_cfg.bus.mipi_csi2.num_data_lanes);
1221 ret = -EINVAL;
1222 goto done_endpoint_free;
1223 }
1224
1225 ret = v4l2_link_freq_to_bitmap(dev: imx335->dev, fw_link_freqs: bus_cfg.link_frequencies,
1226 num_of_fw_link_freqs: bus_cfg.nr_of_link_frequencies,
1227 driver_link_freqs: link_freq, ARRAY_SIZE(link_freq),
1228 bitmap: &imx335->link_freq_bitmap);
1229
1230done_endpoint_free:
1231 v4l2_fwnode_endpoint_free(vep: &bus_cfg);
1232
1233 return ret;
1234}
1235
1236/* V4l2 subdevice ops */
1237static const struct v4l2_subdev_video_ops imx335_video_ops = {
1238 .s_stream = v4l2_subdev_s_stream_helper,
1239};
1240
1241static const struct v4l2_subdev_pad_ops imx335_pad_ops = {
1242 .enum_mbus_code = imx335_enum_mbus_code,
1243 .enum_frame_size = imx335_enum_frame_size,
1244 .get_selection = imx335_get_selection,
1245 .set_selection = imx335_get_selection,
1246 .get_fmt = v4l2_subdev_get_fmt,
1247 .set_fmt = imx335_set_pad_format,
1248 .enable_streams = imx335_enable_streams,
1249 .disable_streams = imx335_disable_streams,
1250};
1251
1252static const struct v4l2_subdev_ops imx335_subdev_ops = {
1253 .video = &imx335_video_ops,
1254 .pad = &imx335_pad_ops,
1255};
1256
1257static const struct v4l2_subdev_internal_ops imx335_internal_ops = {
1258 .init_state = imx335_init_state,
1259};
1260
1261/**
1262 * imx335_power_on() - Sensor power on sequence
1263 * @dev: pointer to i2c device
1264 *
1265 * Return: 0 if successful, error code otherwise.
1266 */
1267static int imx335_power_on(struct device *dev)
1268{
1269 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1270 struct imx335 *imx335 = to_imx335(subdev: sd);
1271 int ret;
1272
1273 ret = regulator_bulk_enable(ARRAY_SIZE(imx335_supply_name),
1274 consumers: imx335->supplies);
1275 if (ret) {
1276 dev_err(dev, "%s: failed to enable regulators\n",
1277 __func__);
1278 return ret;
1279 }
1280
1281 usleep_range(min: 500, max: 550); /* Tlow */
1282
1283 gpiod_set_value_cansleep(desc: imx335->reset_gpio, value: 0);
1284
1285 ret = clk_prepare_enable(clk: imx335->inclk);
1286 if (ret) {
1287 dev_err(imx335->dev, "fail to enable inclk\n");
1288 goto error_reset;
1289 }
1290
1291 usleep_range(min: 20, max: 22); /* T4 */
1292
1293 return 0;
1294
1295error_reset:
1296 gpiod_set_value_cansleep(desc: imx335->reset_gpio, value: 1);
1297 regulator_bulk_disable(ARRAY_SIZE(imx335_supply_name), consumers: imx335->supplies);
1298
1299 return ret;
1300}
1301
1302/**
1303 * imx335_power_off() - Sensor power off sequence
1304 * @dev: pointer to i2c device
1305 *
1306 * Return: 0 if successful, error code otherwise.
1307 */
1308static int imx335_power_off(struct device *dev)
1309{
1310 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1311 struct imx335 *imx335 = to_imx335(subdev: sd);
1312
1313 gpiod_set_value_cansleep(desc: imx335->reset_gpio, value: 1);
1314 clk_disable_unprepare(clk: imx335->inclk);
1315 regulator_bulk_disable(ARRAY_SIZE(imx335_supply_name), consumers: imx335->supplies);
1316
1317 return 0;
1318}
1319
1320/**
1321 * imx335_init_controls() - Initialize sensor subdevice controls
1322 * @imx335: pointer to imx335 device
1323 *
1324 * Return: 0 if successful, error code otherwise.
1325 */
1326static int imx335_init_controls(struct imx335 *imx335)
1327{
1328 struct v4l2_ctrl_handler *ctrl_hdlr = &imx335->ctrl_handler;
1329 const struct imx335_mode *mode = imx335->cur_mode;
1330 struct v4l2_fwnode_device_properties props;
1331 u32 lpfr, shutter_min;
1332 int ret;
1333
1334 ret = v4l2_fwnode_device_parse(dev: imx335->dev, props: &props);
1335 if (ret)
1336 return ret;
1337
1338 /* v4l2_fwnode_device_properties can add two more controls */
1339 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1340 if (ret)
1341 return ret;
1342
1343 /* Initialize exposure and gain */
1344 lpfr = mode->vblank + mode->height;
1345 shutter_min = IMX335_SHUTTER_MIN;
1346 if (mode->scan_mode == IMX335_2_2_BINNING)
1347 shutter_min = IMX335_SHUTTER_MIN_BINNED;
1348 imx335->exp_ctrl = v4l2_ctrl_new_std(hdl: ctrl_hdlr,
1349 ops: &imx335_ctrl_ops,
1350 V4L2_CID_EXPOSURE,
1351 IMX335_EXPOSURE_MIN,
1352 max: lpfr - shutter_min,
1353 IMX335_EXPOSURE_STEP,
1354 IMX335_EXPOSURE_DEFAULT);
1355
1356 /*
1357 * The sensor has an analog gain and a digital gain, both controlled
1358 * through a single gain value, expressed in 0.3dB increments. Values
1359 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values
1360 * up to 72.0dB (240) add further digital gain. Limit the range to
1361 * analog gain only, support for digital gain can be added separately
1362 * if needed.
1363 */
1364 imx335->again_ctrl = v4l2_ctrl_new_std(hdl: ctrl_hdlr,
1365 ops: &imx335_ctrl_ops,
1366 V4L2_CID_ANALOGUE_GAIN,
1367 IMX335_AGAIN_MIN,
1368 IMX335_AGAIN_MAX,
1369 IMX335_AGAIN_STEP,
1370 IMX335_AGAIN_DEFAULT);
1371
1372 v4l2_ctrl_cluster(ncontrols: 2, controls: &imx335->exp_ctrl);
1373
1374 imx335->vflip = v4l2_ctrl_new_std(hdl: ctrl_hdlr,
1375 ops: &imx335_ctrl_ops,
1376 V4L2_CID_VFLIP,
1377 min: 0, max: 1, step: 1, def: 0);
1378 if (imx335->vflip)
1379 imx335->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
1380
1381 imx335->vblank_ctrl = v4l2_ctrl_new_std(hdl: ctrl_hdlr,
1382 ops: &imx335_ctrl_ops,
1383 V4L2_CID_VBLANK,
1384 min: mode->vblank_min,
1385 max: mode->vblank_max,
1386 step: 1, def: mode->vblank);
1387
1388 v4l2_ctrl_new_std_menu_items(hdl: ctrl_hdlr,
1389 ops: &imx335_ctrl_ops,
1390 V4L2_CID_TEST_PATTERN,
1391 ARRAY_SIZE(imx335_tpg_menu) - 1,
1392 mask: 0, def: 0, qmenu: imx335_tpg_menu);
1393
1394 /* Read only controls */
1395 imx335->pclk_ctrl = v4l2_ctrl_new_std(hdl: ctrl_hdlr,
1396 ops: &imx335_ctrl_ops,
1397 V4L2_CID_PIXEL_RATE,
1398 min: mode->pclk, max: mode->pclk,
1399 step: 1, def: mode->pclk);
1400
1401 imx335->link_freq_ctrl = v4l2_ctrl_new_int_menu(hdl: ctrl_hdlr,
1402 ops: &imx335_ctrl_ops,
1403 V4L2_CID_LINK_FREQ,
1404 max: __fls(word: imx335->link_freq_bitmap),
1405 __ffs(imx335->link_freq_bitmap),
1406 qmenu_int: link_freq);
1407 if (imx335->link_freq_ctrl)
1408 imx335->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1409
1410 imx335->hblank_ctrl = v4l2_ctrl_new_std(hdl: ctrl_hdlr,
1411 ops: &imx335_ctrl_ops,
1412 V4L2_CID_HBLANK,
1413 min: mode->hblank,
1414 max: mode->hblank,
1415 step: 1, def: mode->hblank);
1416 if (imx335->hblank_ctrl)
1417 imx335->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1418
1419 v4l2_ctrl_new_fwnode_properties(hdl: ctrl_hdlr, ctrl_ops: &imx335_ctrl_ops, p: &props);
1420
1421 if (ctrl_hdlr->error) {
1422 dev_err(imx335->dev, "control init failed: %d\n",
1423 ctrl_hdlr->error);
1424 v4l2_ctrl_handler_free(hdl: ctrl_hdlr);
1425 return ctrl_hdlr->error;
1426 }
1427
1428 imx335->sd.ctrl_handler = ctrl_hdlr;
1429
1430 return 0;
1431}
1432
1433/**
1434 * imx335_probe() - I2C client device binding
1435 * @client: pointer to i2c client device
1436 *
1437 * Return: 0 if successful, error code otherwise.
1438 */
1439static int imx335_probe(struct i2c_client *client)
1440{
1441 struct imx335 *imx335;
1442 int ret;
1443
1444 imx335 = devm_kzalloc(dev: &client->dev, size: sizeof(*imx335), GFP_KERNEL);
1445 if (!imx335)
1446 return -ENOMEM;
1447
1448 imx335->dev = &client->dev;
1449 imx335->cci = devm_cci_regmap_init_i2c(client, reg_addr_bits: 16);
1450 if (IS_ERR(ptr: imx335->cci)) {
1451 dev_err(imx335->dev, "Unable to initialize I2C\n");
1452 return -ENODEV;
1453 }
1454
1455 /* Initialize subdev */
1456 v4l2_i2c_subdev_init(sd: &imx335->sd, client, ops: &imx335_subdev_ops);
1457 imx335->sd.internal_ops = &imx335_internal_ops;
1458
1459 ret = imx335_parse_hw_config(imx335);
1460 if (ret) {
1461 dev_err(imx335->dev, "HW configuration is not supported\n");
1462 return ret;
1463 }
1464
1465 ret = imx335_power_on(dev: imx335->dev);
1466 if (ret) {
1467 dev_err(imx335->dev, "failed to power-on the sensor\n");
1468 return ret;
1469 }
1470
1471 /* Check module identity */
1472 ret = imx335_detect(imx335);
1473 if (ret) {
1474 dev_err(imx335->dev, "failed to find sensor: %d\n", ret);
1475 goto error_power_off;
1476 }
1477
1478 /* Set default mode to max resolution */
1479 imx335->cur_mode = &supported_modes[0];
1480 imx335->cur_mbus_code = imx335_mbus_codes[0];
1481 imx335->vblank = imx335->cur_mode->vblank;
1482
1483 ret = imx335_init_controls(imx335);
1484 if (ret) {
1485 dev_err(imx335->dev, "failed to init controls: %d\n", ret);
1486 goto error_power_off;
1487 }
1488
1489 /* Initialize subdev */
1490 imx335->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1491 imx335->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1492
1493 /* Initialize source pad */
1494 imx335->pad.flags = MEDIA_PAD_FL_SOURCE;
1495 ret = media_entity_pads_init(entity: &imx335->sd.entity, num_pads: 1, pads: &imx335->pad);
1496 if (ret) {
1497 dev_err(imx335->dev, "failed to init entity pads: %d\n", ret);
1498 goto error_handler_free;
1499 }
1500
1501 imx335->sd.state_lock = imx335->ctrl_handler.lock;
1502 ret = v4l2_subdev_init_finalize(&imx335->sd);
1503 if (ret < 0) {
1504 dev_err(imx335->dev, "subdev init error\n");
1505 goto error_media_entity;
1506 }
1507
1508 ret = v4l2_async_register_subdev_sensor(sd: &imx335->sd);
1509 if (ret < 0) {
1510 dev_err(imx335->dev,
1511 "failed to register async subdev: %d\n", ret);
1512 goto error_subdev_cleanup;
1513 }
1514
1515 pm_runtime_set_active(dev: imx335->dev);
1516 pm_runtime_enable(dev: imx335->dev);
1517 pm_runtime_idle(dev: imx335->dev);
1518
1519 return 0;
1520
1521error_subdev_cleanup:
1522 v4l2_subdev_cleanup(sd: &imx335->sd);
1523error_media_entity:
1524 media_entity_cleanup(entity: &imx335->sd.entity);
1525error_handler_free:
1526 v4l2_ctrl_handler_free(hdl: imx335->sd.ctrl_handler);
1527error_power_off:
1528 imx335_power_off(dev: imx335->dev);
1529
1530 return ret;
1531}
1532
1533/**
1534 * imx335_remove() - I2C client device unbinding
1535 * @client: pointer to I2C client device
1536 *
1537 * Return: 0 if successful, error code otherwise.
1538 */
1539static void imx335_remove(struct i2c_client *client)
1540{
1541 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1542
1543 v4l2_async_unregister_subdev(sd);
1544 v4l2_subdev_cleanup(sd);
1545 media_entity_cleanup(entity: &sd->entity);
1546 v4l2_ctrl_handler_free(hdl: sd->ctrl_handler);
1547
1548 pm_runtime_disable(dev: &client->dev);
1549 if (!pm_runtime_status_suspended(dev: &client->dev))
1550 imx335_power_off(dev: &client->dev);
1551 pm_runtime_set_suspended(dev: &client->dev);
1552}
1553
1554static const struct dev_pm_ops imx335_pm_ops = {
1555 SET_RUNTIME_PM_OPS(imx335_power_off, imx335_power_on, NULL)
1556};
1557
1558static const struct of_device_id imx335_of_match[] = {
1559 { .compatible = "sony,imx335" },
1560 { }
1561};
1562
1563MODULE_DEVICE_TABLE(of, imx335_of_match);
1564
1565static struct i2c_driver imx335_driver = {
1566 .probe = imx335_probe,
1567 .remove = imx335_remove,
1568 .driver = {
1569 .name = "imx335",
1570 .pm = &imx335_pm_ops,
1571 .of_match_table = imx335_of_match,
1572 },
1573};
1574
1575module_i2c_driver(imx335_driver);
1576
1577MODULE_DESCRIPTION("Sony imx335 sensor driver");
1578MODULE_LICENSE("GPL");
1579

source code of linux/drivers/media/i2c/imx335.c