1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for the Sony IMX415 CMOS Image Sensor.
4 *
5 * Copyright (C) 2023 WolfVision GmbH.
6 */
7
8#include <linux/clk.h>
9#include <linux/gpio/consumer.h>
10#include <linux/i2c.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15#include <linux/regulator/consumer.h>
16#include <linux/slab.h>
17#include <linux/videodev2.h>
18
19#include <media/v4l2-cci.h>
20#include <media/v4l2-ctrls.h>
21#include <media/v4l2-fwnode.h>
22#include <media/v4l2-subdev.h>
23
24#define IMX415_PIXEL_ARRAY_TOP 0
25#define IMX415_PIXEL_ARRAY_LEFT 0
26#define IMX415_PIXEL_ARRAY_WIDTH 3864
27#define IMX415_PIXEL_ARRAY_HEIGHT 2192
28#define IMX415_PIXEL_ARRAY_VBLANK 58
29#define IMX415_EXPOSURE_OFFSET 8
30
31#define IMX415_PIXEL_RATE_74_25MHZ 891000000
32#define IMX415_PIXEL_RATE_72MHZ 864000000
33
34#define IMX415_NUM_CLK_PARAM_REGS 11
35
36#define IMX415_MODE CCI_REG8(0x3000)
37#define IMX415_MODE_OPERATING (0)
38#define IMX415_MODE_STANDBY BIT(0)
39#define IMX415_REGHOLD CCI_REG8(0x3001)
40#define IMX415_REGHOLD_INVALID (0)
41#define IMX415_REGHOLD_VALID BIT(0)
42#define IMX415_XMSTA CCI_REG8(0x3002)
43#define IMX415_XMSTA_START (0)
44#define IMX415_XMSTA_STOP BIT(0)
45#define IMX415_BCWAIT_TIME CCI_REG16_LE(0x3008)
46#define IMX415_CPWAIT_TIME CCI_REG16_LE(0x300a)
47#define IMX415_WINMODE CCI_REG8(0x301c)
48#define IMX415_ADDMODE CCI_REG8(0x3022)
49#define IMX415_REVERSE CCI_REG8(0x3030)
50#define IMX415_HREVERSE_SHIFT (0)
51#define IMX415_VREVERSE_SHIFT BIT(0)
52#define IMX415_ADBIT CCI_REG8(0x3031)
53#define IMX415_MDBIT CCI_REG8(0x3032)
54#define IMX415_SYS_MODE CCI_REG8(0x3033)
55#define IMX415_OUTSEL CCI_REG8(0x30c0)
56#define IMX415_DRV CCI_REG8(0x30c1)
57#define IMX415_VMAX CCI_REG24_LE(0x3024)
58#define IMX415_VMAX_MAX 0xfffff
59#define IMX415_HMAX CCI_REG16_LE(0x3028)
60#define IMX415_HMAX_MAX 0xffff
61#define IMX415_HMAX_MULTIPLIER 12
62#define IMX415_SHR0 CCI_REG24_LE(0x3050)
63#define IMX415_GAIN_PCG_0 CCI_REG16_LE(0x3090)
64#define IMX415_AGAIN_MIN 0
65#define IMX415_AGAIN_MAX 100
66#define IMX415_AGAIN_STEP 1
67#define IMX415_BLKLEVEL CCI_REG16_LE(0x30e2)
68#define IMX415_BLKLEVEL_DEFAULT 50
69#define IMX415_TPG_EN_DUOUT CCI_REG8(0x30e4)
70#define IMX415_TPG_PATSEL_DUOUT CCI_REG8(0x30e6)
71#define IMX415_TPG_COLORWIDTH CCI_REG8(0x30e8)
72#define IMX415_TESTCLKEN_MIPI CCI_REG8(0x3110)
73#define IMX415_INCKSEL1 CCI_REG8(0x3115)
74#define IMX415_INCKSEL2 CCI_REG8(0x3116)
75#define IMX415_INCKSEL3 CCI_REG16_LE(0x3118)
76#define IMX415_INCKSEL4 CCI_REG16_LE(0x311a)
77#define IMX415_INCKSEL5 CCI_REG8(0x311e)
78#define IMX415_DIG_CLP_MODE CCI_REG8(0x32c8)
79#define IMX415_WRJ_OPEN CCI_REG8(0x3390)
80#define IMX415_SENSOR_INFO CCI_REG16_LE(0x3f12)
81#define IMX415_SENSOR_INFO_MASK 0xfff
82#define IMX415_CHIP_ID 0x514
83#define IMX415_LANEMODE CCI_REG16_LE(0x4001)
84#define IMX415_LANEMODE_2 1
85#define IMX415_LANEMODE_4 3
86#define IMX415_TXCLKESC_FREQ CCI_REG16_LE(0x4004)
87#define IMX415_INCKSEL6 CCI_REG8(0x400c)
88#define IMX415_TCLKPOST CCI_REG16_LE(0x4018)
89#define IMX415_TCLKPREPARE CCI_REG16_LE(0x401a)
90#define IMX415_TCLKTRAIL CCI_REG16_LE(0x401c)
91#define IMX415_TCLKZERO CCI_REG16_LE(0x401e)
92#define IMX415_THSPREPARE CCI_REG16_LE(0x4020)
93#define IMX415_THSZERO CCI_REG16_LE(0x4022)
94#define IMX415_THSTRAIL CCI_REG16_LE(0x4024)
95#define IMX415_THSEXIT CCI_REG16_LE(0x4026)
96#define IMX415_TLPX CCI_REG16_LE(0x4028)
97#define IMX415_INCKSEL7 CCI_REG8(0x4074)
98
99static const char *const imx415_supply_names[] = {
100 "dvdd",
101 "ovdd",
102 "avdd",
103};
104
105/*
106 * The IMX415 data sheet uses lane rates but v4l2 uses link frequency to
107 * describe MIPI CSI-2 speed. This driver uses lane rates wherever possible
108 * and converts them to link frequencies by a factor of two when needed.
109 */
110static const s64 link_freq_menu_items[] = {
111 594000000 / 2, 720000000 / 2, 891000000 / 2,
112 1440000000 / 2, 1485000000 / 2,
113};
114
115struct imx415_clk_params {
116 u64 lane_rate;
117 u64 inck;
118 struct cci_reg_sequence regs[IMX415_NUM_CLK_PARAM_REGS];
119};
120
121/* INCK Settings - includes all lane rate and INCK dependent registers */
122static const struct imx415_clk_params imx415_clk_params[] = {
123 {
124 .lane_rate = 594000000UL,
125 .inck = 27000000,
126 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
127 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
128 .regs[2] = { IMX415_SYS_MODE, 0x7 },
129 .regs[3] = { IMX415_INCKSEL1, 0x00 },
130 .regs[4] = { IMX415_INCKSEL2, 0x23 },
131 .regs[5] = { IMX415_INCKSEL3, 0x084 },
132 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
133 .regs[7] = { IMX415_INCKSEL5, 0x23 },
134 .regs[8] = { IMX415_INCKSEL6, 0x0 },
135 .regs[9] = { IMX415_INCKSEL7, 0x1 },
136 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
137 },
138 {
139 .lane_rate = 594000000UL,
140 .inck = 37125000,
141 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
142 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
143 .regs[2] = { IMX415_SYS_MODE, 0x7 },
144 .regs[3] = { IMX415_INCKSEL1, 0x00 },
145 .regs[4] = { IMX415_INCKSEL2, 0x24 },
146 .regs[5] = { IMX415_INCKSEL3, 0x080 },
147 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
148 .regs[7] = { IMX415_INCKSEL5, 0x24 },
149 .regs[8] = { IMX415_INCKSEL6, 0x0 },
150 .regs[9] = { IMX415_INCKSEL7, 0x1 },
151 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0984 },
152 },
153 {
154 .lane_rate = 594000000UL,
155 .inck = 74250000,
156 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
157 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
158 .regs[2] = { IMX415_SYS_MODE, 0x7 },
159 .regs[3] = { IMX415_INCKSEL1, 0x00 },
160 .regs[4] = { IMX415_INCKSEL2, 0x28 },
161 .regs[5] = { IMX415_INCKSEL3, 0x080 },
162 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
163 .regs[7] = { IMX415_INCKSEL5, 0x28 },
164 .regs[8] = { IMX415_INCKSEL6, 0x0 },
165 .regs[9] = { IMX415_INCKSEL7, 0x1 },
166 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
167 },
168 {
169 .lane_rate = 720000000UL,
170 .inck = 24000000,
171 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
172 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
173 .regs[2] = { IMX415_SYS_MODE, 0x9 },
174 .regs[3] = { IMX415_INCKSEL1, 0x00 },
175 .regs[4] = { IMX415_INCKSEL2, 0x23 },
176 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },
177 .regs[6] = { IMX415_INCKSEL4, 0x0FC },
178 .regs[7] = { IMX415_INCKSEL5, 0x23 },
179 .regs[8] = { IMX415_INCKSEL6, 0x0 },
180 .regs[9] = { IMX415_INCKSEL7, 0x1 },
181 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
182 },
183 {
184 .lane_rate = 720000000UL,
185 .inck = 72000000,
186 .regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
187 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
188 .regs[2] = { IMX415_SYS_MODE, 0x9 },
189 .regs[3] = { IMX415_INCKSEL1, 0x00 },
190 .regs[4] = { IMX415_INCKSEL2, 0x28 },
191 .regs[5] = { IMX415_INCKSEL3, 0x0A0 },
192 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
193 .regs[7] = { IMX415_INCKSEL5, 0x28 },
194 .regs[8] = { IMX415_INCKSEL6, 0x0 },
195 .regs[9] = { IMX415_INCKSEL7, 0x1 },
196 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
197 },
198 {
199 .lane_rate = 891000000UL,
200 .inck = 27000000,
201 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
202 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
203 .regs[2] = { IMX415_SYS_MODE, 0x5 },
204 .regs[3] = { IMX415_INCKSEL1, 0x00 },
205 .regs[4] = { IMX415_INCKSEL2, 0x23 },
206 .regs[5] = { IMX415_INCKSEL3, 0x0C6 },
207 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
208 .regs[7] = { IMX415_INCKSEL5, 0x23 },
209 .regs[8] = { IMX415_INCKSEL6, 0x0 },
210 .regs[9] = { IMX415_INCKSEL7, 0x1 },
211 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
212 },
213 {
214 .lane_rate = 891000000UL,
215 .inck = 37125000,
216 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
217 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
218 .regs[2] = { IMX415_SYS_MODE, 0x5 },
219 .regs[3] = { IMX415_INCKSEL1, 0x00 },
220 .regs[4] = { IMX415_INCKSEL2, 0x24 },
221 .regs[5] = { IMX415_INCKSEL3, 0x0C0 },
222 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
223 .regs[7] = { IMX415_INCKSEL5, 0x24 },
224 .regs[8] = { IMX415_INCKSEL6, 0x0 },
225 .regs[9] = { IMX415_INCKSEL7, 0x1 },
226 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
227 },
228 {
229 .lane_rate = 891000000UL,
230 .inck = 74250000,
231 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
232 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
233 .regs[2] = { IMX415_SYS_MODE, 0x5 },
234 .regs[3] = { IMX415_INCKSEL1, 0x00 },
235 .regs[4] = { IMX415_INCKSEL2, 0x28 },
236 .regs[5] = { IMX415_INCKSEL3, 0x0C0 },
237 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
238 .regs[7] = { IMX415_INCKSEL5, 0x28 },
239 .regs[8] = { IMX415_INCKSEL6, 0x0 },
240 .regs[9] = { IMX415_INCKSEL7, 0x1 },
241 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
242 },
243 {
244 .lane_rate = 1440000000UL,
245 .inck = 24000000,
246 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
247 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
248 .regs[2] = { IMX415_SYS_MODE, 0x8 },
249 .regs[3] = { IMX415_INCKSEL1, 0x00 },
250 .regs[4] = { IMX415_INCKSEL2, 0x23 },
251 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },
252 .regs[6] = { IMX415_INCKSEL4, 0x0FC },
253 .regs[7] = { IMX415_INCKSEL5, 0x23 },
254 .regs[8] = { IMX415_INCKSEL6, 0x1 },
255 .regs[9] = { IMX415_INCKSEL7, 0x0 },
256 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
257 },
258 {
259 .lane_rate = 1440000000UL,
260 .inck = 72000000,
261 .regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
262 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
263 .regs[2] = { IMX415_SYS_MODE, 0x8 },
264 .regs[3] = { IMX415_INCKSEL1, 0x00 },
265 .regs[4] = { IMX415_INCKSEL2, 0x28 },
266 .regs[5] = { IMX415_INCKSEL3, 0x0A0 },
267 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
268 .regs[7] = { IMX415_INCKSEL5, 0x28 },
269 .regs[8] = { IMX415_INCKSEL6, 0x1 },
270 .regs[9] = { IMX415_INCKSEL7, 0x0 },
271 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
272 },
273 {
274 .lane_rate = 1485000000UL,
275 .inck = 27000000,
276 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
277 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
278 .regs[2] = { IMX415_SYS_MODE, 0x8 },
279 .regs[3] = { IMX415_INCKSEL1, 0x00 },
280 .regs[4] = { IMX415_INCKSEL2, 0x23 },
281 .regs[5] = { IMX415_INCKSEL3, 0x0A5 },
282 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
283 .regs[7] = { IMX415_INCKSEL5, 0x23 },
284 .regs[8] = { IMX415_INCKSEL6, 0x1 },
285 .regs[9] = { IMX415_INCKSEL7, 0x0 },
286 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
287 },
288 {
289 .lane_rate = 1485000000UL,
290 .inck = 37125000,
291 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
292 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
293 .regs[2] = { IMX415_SYS_MODE, 0x8 },
294 .regs[3] = { IMX415_INCKSEL1, 0x00 },
295 .regs[4] = { IMX415_INCKSEL2, 0x24 },
296 .regs[5] = { IMX415_INCKSEL3, 0x0A0 },
297 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
298 .regs[7] = { IMX415_INCKSEL5, 0x24 },
299 .regs[8] = { IMX415_INCKSEL6, 0x1 },
300 .regs[9] = { IMX415_INCKSEL7, 0x0 },
301 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
302 },
303 {
304 .lane_rate = 1485000000UL,
305 .inck = 74250000,
306 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
307 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
308 .regs[2] = { IMX415_SYS_MODE, 0x8 },
309 .regs[3] = { IMX415_INCKSEL1, 0x00 },
310 .regs[4] = { IMX415_INCKSEL2, 0x28 },
311 .regs[5] = { IMX415_INCKSEL3, 0x0A0 },
312 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
313 .regs[7] = { IMX415_INCKSEL5, 0x28 },
314 .regs[8] = { IMX415_INCKSEL6, 0x1 },
315 .regs[9] = { IMX415_INCKSEL7, 0x0 },
316 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
317 },
318 {
319 .lane_rate = 1782000000UL,
320 .inck = 27000000,
321 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
322 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
323 .regs[2] = { IMX415_SYS_MODE, 0x4 },
324 .regs[3] = { IMX415_INCKSEL1, 0x00 },
325 .regs[4] = { IMX415_INCKSEL2, 0x23 },
326 .regs[5] = { IMX415_INCKSEL3, 0x0C6 },
327 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
328 .regs[7] = { IMX415_INCKSEL5, 0x23 },
329 .regs[8] = { IMX415_INCKSEL6, 0x1 },
330 .regs[9] = { IMX415_INCKSEL7, 0x0 },
331 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
332 },
333 {
334 .lane_rate = 1782000000UL,
335 .inck = 37125000,
336 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
337 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
338 .regs[2] = { IMX415_SYS_MODE, 0x4 },
339 .regs[3] = { IMX415_INCKSEL1, 0x00 },
340 .regs[4] = { IMX415_INCKSEL2, 0x24 },
341 .regs[5] = { IMX415_INCKSEL3, 0x0C0 },
342 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
343 .regs[7] = { IMX415_INCKSEL5, 0x24 },
344 .regs[8] = { IMX415_INCKSEL6, 0x1 },
345 .regs[9] = { IMX415_INCKSEL7, 0x0 },
346 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
347 },
348 {
349 .lane_rate = 1782000000UL,
350 .inck = 74250000,
351 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
352 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
353 .regs[2] = { IMX415_SYS_MODE, 0x4 },
354 .regs[3] = { IMX415_INCKSEL1, 0x00 },
355 .regs[4] = { IMX415_INCKSEL2, 0x28 },
356 .regs[5] = { IMX415_INCKSEL3, 0x0C0 },
357 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
358 .regs[7] = { IMX415_INCKSEL5, 0x28 },
359 .regs[8] = { IMX415_INCKSEL6, 0x1 },
360 .regs[9] = { IMX415_INCKSEL7, 0x0 },
361 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
362 },
363 {
364 .lane_rate = 2079000000UL,
365 .inck = 27000000,
366 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
367 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
368 .regs[2] = { IMX415_SYS_MODE, 0x2 },
369 .regs[3] = { IMX415_INCKSEL1, 0x00 },
370 .regs[4] = { IMX415_INCKSEL2, 0x23 },
371 .regs[5] = { IMX415_INCKSEL3, 0x0E7 },
372 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
373 .regs[7] = { IMX415_INCKSEL5, 0x23 },
374 .regs[8] = { IMX415_INCKSEL6, 0x1 },
375 .regs[9] = { IMX415_INCKSEL7, 0x0 },
376 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
377 },
378 {
379 .lane_rate = 2079000000UL,
380 .inck = 37125000,
381 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
382 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
383 .regs[2] = { IMX415_SYS_MODE, 0x2 },
384 .regs[3] = { IMX415_INCKSEL1, 0x00 },
385 .regs[4] = { IMX415_INCKSEL2, 0x24 },
386 .regs[5] = { IMX415_INCKSEL3, 0x0E0 },
387 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
388 .regs[7] = { IMX415_INCKSEL5, 0x24 },
389 .regs[8] = { IMX415_INCKSEL6, 0x1 },
390 .regs[9] = { IMX415_INCKSEL7, 0x0 },
391 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
392 },
393 {
394 .lane_rate = 2079000000UL,
395 .inck = 74250000,
396 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
397 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
398 .regs[2] = { IMX415_SYS_MODE, 0x2 },
399 .regs[3] = { IMX415_INCKSEL1, 0x00 },
400 .regs[4] = { IMX415_INCKSEL2, 0x28 },
401 .regs[5] = { IMX415_INCKSEL3, 0x0E0 },
402 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
403 .regs[7] = { IMX415_INCKSEL5, 0x28 },
404 .regs[8] = { IMX415_INCKSEL6, 0x1 },
405 .regs[9] = { IMX415_INCKSEL7, 0x0 },
406 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
407 },
408 {
409 .lane_rate = 2376000000UL,
410 .inck = 27000000,
411 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
412 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
413 .regs[2] = { IMX415_SYS_MODE, 0x0 },
414 .regs[3] = { IMX415_INCKSEL1, 0x00 },
415 .regs[4] = { IMX415_INCKSEL2, 0x23 },
416 .regs[5] = { IMX415_INCKSEL3, 0x108 },
417 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
418 .regs[7] = { IMX415_INCKSEL5, 0x23 },
419 .regs[8] = { IMX415_INCKSEL6, 0x1 },
420 .regs[9] = { IMX415_INCKSEL7, 0x0 },
421 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
422 },
423 {
424 .lane_rate = 2376000000UL,
425 .inck = 37125000,
426 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
427 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
428 .regs[2] = { IMX415_SYS_MODE, 0x0 },
429 .regs[3] = { IMX415_INCKSEL1, 0x00 },
430 .regs[4] = { IMX415_INCKSEL2, 0x24 },
431 .regs[5] = { IMX415_INCKSEL3, 0x100 },
432 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
433 .regs[7] = { IMX415_INCKSEL5, 0x24 },
434 .regs[8] = { IMX415_INCKSEL6, 0x1 },
435 .regs[9] = { IMX415_INCKSEL7, 0x0 },
436 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
437 },
438 {
439 .lane_rate = 2376000000UL,
440 .inck = 74250000,
441 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
442 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
443 .regs[2] = { IMX415_SYS_MODE, 0x0 },
444 .regs[3] = { IMX415_INCKSEL1, 0x00 },
445 .regs[4] = { IMX415_INCKSEL2, 0x28 },
446 .regs[5] = { IMX415_INCKSEL3, 0x100 },
447 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },
448 .regs[7] = { IMX415_INCKSEL5, 0x28 },
449 .regs[8] = { IMX415_INCKSEL6, 0x1 },
450 .regs[9] = { IMX415_INCKSEL7, 0x0 },
451 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
452 },
453};
454
455/* 720 Mbps CSI configuration */
456static const struct cci_reg_sequence imx415_linkrate_720mbps[] = {
457 { IMX415_TCLKPOST, 0x006F },
458 { IMX415_TCLKPREPARE, 0x002F },
459 { IMX415_TCLKTRAIL, 0x002F },
460 { IMX415_TCLKZERO, 0x00BF },
461 { IMX415_THSPREPARE, 0x002F },
462 { IMX415_THSZERO, 0x0057 },
463 { IMX415_THSTRAIL, 0x002F },
464 { IMX415_THSEXIT, 0x004F },
465 { IMX415_TLPX, 0x0027 },
466};
467
468/* 1440 Mbps CSI configuration */
469static const struct cci_reg_sequence imx415_linkrate_1440mbps[] = {
470 { IMX415_TCLKPOST, 0x009F },
471 { IMX415_TCLKPREPARE, 0x0057 },
472 { IMX415_TCLKTRAIL, 0x0057 },
473 { IMX415_TCLKZERO, 0x0187 },
474 { IMX415_THSPREPARE, 0x005F },
475 { IMX415_THSZERO, 0x00A7 },
476 { IMX415_THSTRAIL, 0x005F },
477 { IMX415_THSEXIT, 0x0097 },
478 { IMX415_TLPX, 0x004F },
479};
480
481/* 891 Mbps CSI configuration */
482static const struct cci_reg_sequence imx415_linkrate_891mbps[] = {
483 { IMX415_TCLKPOST, 0x007F },
484 { IMX415_TCLKPREPARE, 0x0037 },
485 { IMX415_TCLKTRAIL, 0x0037 },
486 { IMX415_TCLKZERO, 0x00F7 },
487 { IMX415_THSPREPARE, 0x003F },
488 { IMX415_THSZERO, 0x006F },
489 { IMX415_THSTRAIL, 0x003F },
490 { IMX415_THSEXIT, 0x005F },
491 { IMX415_TLPX, 0x002F },
492};
493
494struct imx415_mode_reg_list {
495 u32 num_of_regs;
496 const struct cci_reg_sequence *regs;
497};
498
499struct imx415_mode {
500 u64 lane_rate;
501 u32 hmax_min[2];
502 struct imx415_mode_reg_list reg_list;
503};
504
505/* mode configs */
506static const struct imx415_mode supported_modes[] = {
507 {
508 .lane_rate = 720000000,
509 .hmax_min = { 2032, 1066 },
510 .reg_list = {
511 .num_of_regs = ARRAY_SIZE(imx415_linkrate_720mbps),
512 .regs = imx415_linkrate_720mbps,
513 },
514 },
515 {
516 .lane_rate = 1440000000,
517 .hmax_min = { 1066, 533 },
518 .reg_list = {
519 .num_of_regs = ARRAY_SIZE(imx415_linkrate_1440mbps),
520 .regs = imx415_linkrate_1440mbps,
521 },
522 },
523 {
524 .lane_rate = 891000000,
525 .hmax_min = { 2200, 1100 },
526 .reg_list = {
527 .num_of_regs = ARRAY_SIZE(imx415_linkrate_891mbps),
528 .regs = imx415_linkrate_891mbps,
529 },
530 },
531};
532
533static const char *const imx415_test_pattern_menu[] = {
534 "disabled",
535 "solid black",
536 "solid white",
537 "solid dark gray",
538 "solid light gray",
539 "stripes light/dark grey",
540 "stripes dark/light grey",
541 "stripes black/dark grey",
542 "stripes dark grey/black",
543 "stripes black/white",
544 "stripes white/black",
545 "horizontal color bar",
546 "vertical color bar",
547};
548
549struct imx415 {
550 struct device *dev;
551 struct clk *clk;
552 unsigned long pixel_rate;
553 struct regulator_bulk_data supplies[ARRAY_SIZE(imx415_supply_names)];
554 struct gpio_desc *reset;
555 struct regmap *regmap;
556
557 const struct imx415_clk_params *clk_params;
558
559 struct v4l2_subdev subdev;
560 struct media_pad pad;
561
562 struct v4l2_ctrl_handler ctrls;
563 struct v4l2_ctrl *vblank;
564 struct v4l2_ctrl *hblank;
565 struct v4l2_ctrl *hflip;
566 struct v4l2_ctrl *vflip;
567 struct v4l2_ctrl *exposure;
568
569 unsigned int cur_mode;
570 unsigned int num_data_lanes;
571};
572
573/*
574 * This table includes fixed register settings and a bunch of undocumented
575 * registers that have to be set to another value than default.
576 */
577static const struct cci_reg_sequence imx415_init_table[] = {
578 /* use all-pixel readout mode, no flip */
579 { IMX415_WINMODE, 0x00 },
580 { IMX415_ADDMODE, 0x00 },
581 { IMX415_REVERSE, 0x00 },
582 /* use RAW 10-bit mode */
583 { IMX415_ADBIT, 0x00 },
584 { IMX415_MDBIT, 0x00 },
585 /* output VSYNC on XVS and low on XHS */
586 { IMX415_OUTSEL, 0x22 },
587 { IMX415_DRV, 0x00 },
588
589 /* SONY magic registers */
590 { CCI_REG8(0x32D4), 0x21 },
591 { CCI_REG8(0x32EC), 0xA1 },
592 { CCI_REG8(0x3452), 0x7F },
593 { CCI_REG8(0x3453), 0x03 },
594 { CCI_REG8(0x358A), 0x04 },
595 { CCI_REG8(0x35A1), 0x02 },
596 { CCI_REG8(0x36BC), 0x0C },
597 { CCI_REG8(0x36CC), 0x53 },
598 { CCI_REG8(0x36CD), 0x00 },
599 { CCI_REG8(0x36CE), 0x3C },
600 { CCI_REG8(0x36D0), 0x8C },
601 { CCI_REG8(0x36D1), 0x00 },
602 { CCI_REG8(0x36D2), 0x71 },
603 { CCI_REG8(0x36D4), 0x3C },
604 { CCI_REG8(0x36D6), 0x53 },
605 { CCI_REG8(0x36D7), 0x00 },
606 { CCI_REG8(0x36D8), 0x71 },
607 { CCI_REG8(0x36DA), 0x8C },
608 { CCI_REG8(0x36DB), 0x00 },
609 { CCI_REG8(0x3724), 0x02 },
610 { CCI_REG8(0x3726), 0x02 },
611 { CCI_REG8(0x3732), 0x02 },
612 { CCI_REG8(0x3734), 0x03 },
613 { CCI_REG8(0x3736), 0x03 },
614 { CCI_REG8(0x3742), 0x03 },
615 { CCI_REG8(0x3862), 0xE0 },
616 { CCI_REG8(0x38CC), 0x30 },
617 { CCI_REG8(0x38CD), 0x2F },
618 { CCI_REG8(0x395C), 0x0C },
619 { CCI_REG8(0x3A42), 0xD1 },
620 { CCI_REG8(0x3A4C), 0x77 },
621 { CCI_REG8(0x3AE0), 0x02 },
622 { CCI_REG8(0x3AEC), 0x0C },
623 { CCI_REG8(0x3B00), 0x2E },
624 { CCI_REG8(0x3B06), 0x29 },
625 { CCI_REG8(0x3B98), 0x25 },
626 { CCI_REG8(0x3B99), 0x21 },
627 { CCI_REG8(0x3B9B), 0x13 },
628 { CCI_REG8(0x3B9C), 0x13 },
629 { CCI_REG8(0x3B9D), 0x13 },
630 { CCI_REG8(0x3B9E), 0x13 },
631 { CCI_REG8(0x3BA1), 0x00 },
632 { CCI_REG8(0x3BA2), 0x06 },
633 { CCI_REG8(0x3BA3), 0x0B },
634 { CCI_REG8(0x3BA4), 0x10 },
635 { CCI_REG8(0x3BA5), 0x14 },
636 { CCI_REG8(0x3BA6), 0x18 },
637 { CCI_REG8(0x3BA7), 0x1A },
638 { CCI_REG8(0x3BA8), 0x1A },
639 { CCI_REG8(0x3BA9), 0x1A },
640 { CCI_REG8(0x3BAC), 0xED },
641 { CCI_REG8(0x3BAD), 0x01 },
642 { CCI_REG8(0x3BAE), 0xF6 },
643 { CCI_REG8(0x3BAF), 0x02 },
644 { CCI_REG8(0x3BB0), 0xA2 },
645 { CCI_REG8(0x3BB1), 0x03 },
646 { CCI_REG8(0x3BB2), 0xE0 },
647 { CCI_REG8(0x3BB3), 0x03 },
648 { CCI_REG8(0x3BB4), 0xE0 },
649 { CCI_REG8(0x3BB5), 0x03 },
650 { CCI_REG8(0x3BB6), 0xE0 },
651 { CCI_REG8(0x3BB7), 0x03 },
652 { CCI_REG8(0x3BB8), 0xE0 },
653 { CCI_REG8(0x3BBA), 0xE0 },
654 { CCI_REG8(0x3BBC), 0xDA },
655 { CCI_REG8(0x3BBE), 0x88 },
656 { CCI_REG8(0x3BC0), 0x44 },
657 { CCI_REG8(0x3BC2), 0x7B },
658 { CCI_REG8(0x3BC4), 0xA2 },
659 { CCI_REG8(0x3BC8), 0xBD },
660 { CCI_REG8(0x3BCA), 0xBD },
661};
662
663static inline struct imx415 *to_imx415(struct v4l2_subdev *sd)
664{
665 return container_of(sd, struct imx415, subdev);
666}
667
668static int imx415_set_testpattern(struct imx415 *sensor, int val)
669{
670 int ret = 0;
671
672 if (val) {
673 cci_write(map: sensor->regmap, IMX415_BLKLEVEL, val: 0x00, err: &ret);
674 cci_write(map: sensor->regmap, IMX415_TPG_EN_DUOUT, val: 0x01, err: &ret);
675 cci_write(map: sensor->regmap, IMX415_TPG_PATSEL_DUOUT,
676 val: val - 1, err: &ret);
677 cci_write(map: sensor->regmap, IMX415_TPG_COLORWIDTH, val: 0x01, err: &ret);
678 cci_write(map: sensor->regmap, IMX415_TESTCLKEN_MIPI, val: 0x20, err: &ret);
679 cci_write(map: sensor->regmap, IMX415_DIG_CLP_MODE, val: 0x00, err: &ret);
680 cci_write(map: sensor->regmap, IMX415_WRJ_OPEN, val: 0x00, err: &ret);
681 } else {
682 cci_write(map: sensor->regmap, IMX415_BLKLEVEL,
683 IMX415_BLKLEVEL_DEFAULT, err: &ret);
684 cci_write(map: sensor->regmap, IMX415_TPG_EN_DUOUT, val: 0x00, err: &ret);
685 cci_write(map: sensor->regmap, IMX415_TESTCLKEN_MIPI, val: 0x00, err: &ret);
686 cci_write(map: sensor->regmap, IMX415_DIG_CLP_MODE, val: 0x01, err: &ret);
687 cci_write(map: sensor->regmap, IMX415_WRJ_OPEN, val: 0x01, err: &ret);
688 }
689 return 0;
690}
691
692static int imx415_s_ctrl(struct v4l2_ctrl *ctrl)
693{
694 struct imx415 *sensor = container_of(ctrl->handler, struct imx415,
695 ctrls);
696 const struct v4l2_mbus_framefmt *format;
697 struct v4l2_subdev_state *state;
698 u32 exposure_max;
699 unsigned int vmax;
700 unsigned int flip;
701 int ret;
702
703 state = v4l2_subdev_get_locked_active_state(sd: &sensor->subdev);
704 format = v4l2_subdev_state_get_format(state, 0);
705
706 if (ctrl->id == V4L2_CID_VBLANK) {
707 exposure_max = format->height + ctrl->val -
708 IMX415_EXPOSURE_OFFSET;
709 __v4l2_ctrl_modify_range(ctrl: sensor->exposure,
710 min: sensor->exposure->minimum,
711 max: exposure_max, step: sensor->exposure->step,
712 def: sensor->exposure->default_value);
713 }
714
715 if (!pm_runtime_get_if_in_use(dev: sensor->dev))
716 return 0;
717
718 switch (ctrl->id) {
719 case V4L2_CID_VBLANK:
720 ret = cci_write(map: sensor->regmap, IMX415_VMAX,
721 val: format->height + ctrl->val, NULL);
722 if (ret)
723 return ret;
724 /*
725 * Exposure is set based on VMAX which has just changed, so
726 * program exposure register as well
727 */
728 ctrl = sensor->exposure;
729 fallthrough;
730 case V4L2_CID_EXPOSURE:
731 /* clamp the exposure value to VMAX. */
732 vmax = format->height + sensor->vblank->cur.val;
733 ctrl->val = min_t(int, ctrl->val, vmax);
734 ret = cci_write(map: sensor->regmap, IMX415_SHR0,
735 val: vmax - ctrl->val, NULL);
736 break;
737
738 case V4L2_CID_ANALOGUE_GAIN:
739 /* analogue gain in 0.3 dB step size */
740 ret = cci_write(map: sensor->regmap, IMX415_GAIN_PCG_0,
741 val: ctrl->val, NULL);
742 break;
743
744 case V4L2_CID_HFLIP:
745 case V4L2_CID_VFLIP:
746 flip = (sensor->hflip->val << IMX415_HREVERSE_SHIFT) |
747 (sensor->vflip->val << IMX415_VREVERSE_SHIFT);
748 ret = cci_write(map: sensor->regmap, IMX415_REVERSE, val: flip, NULL);
749 break;
750
751 case V4L2_CID_TEST_PATTERN:
752 ret = imx415_set_testpattern(sensor, val: ctrl->val);
753 break;
754
755 case V4L2_CID_HBLANK:
756 ret = cci_write(map: sensor->regmap, IMX415_HMAX,
757 val: (format->width + ctrl->val) /
758 IMX415_HMAX_MULTIPLIER,
759 NULL);
760 break;
761
762 default:
763 ret = -EINVAL;
764 break;
765 }
766
767 pm_runtime_put(dev: sensor->dev);
768
769 return ret;
770}
771
772static const struct v4l2_ctrl_ops imx415_ctrl_ops = {
773 .s_ctrl = imx415_s_ctrl,
774};
775
776static int imx415_ctrls_init(struct imx415 *sensor)
777{
778 struct v4l2_fwnode_device_properties props;
779 struct v4l2_ctrl *ctrl;
780 const struct imx415_mode *cur_mode = &supported_modes[sensor->cur_mode];
781 u64 lane_rate = cur_mode->lane_rate;
782 u32 exposure_max = IMX415_PIXEL_ARRAY_HEIGHT +
783 IMX415_PIXEL_ARRAY_VBLANK -
784 IMX415_EXPOSURE_OFFSET;
785 u32 hblank_min, hblank_max;
786 unsigned int i;
787 int ret;
788
789 ret = v4l2_fwnode_device_parse(dev: sensor->dev, props: &props);
790 if (ret < 0)
791 return ret;
792
793 v4l2_ctrl_handler_init(&sensor->ctrls, 10);
794
795 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); ++i) {
796 if (lane_rate == link_freq_menu_items[i] * 2)
797 break;
798 }
799 if (i == ARRAY_SIZE(link_freq_menu_items)) {
800 return dev_err_probe(dev: sensor->dev, err: -EINVAL,
801 fmt: "lane rate %llu not supported\n",
802 lane_rate);
803 }
804
805 ctrl = v4l2_ctrl_new_int_menu(hdl: &sensor->ctrls, ops: &imx415_ctrl_ops,
806 V4L2_CID_LINK_FREQ,
807 ARRAY_SIZE(link_freq_menu_items) - 1, def: i,
808 qmenu_int: link_freq_menu_items);
809
810 if (ctrl)
811 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
812
813 sensor->exposure = v4l2_ctrl_new_std(hdl: &sensor->ctrls, ops: &imx415_ctrl_ops,
814 V4L2_CID_EXPOSURE, min: 4,
815 max: exposure_max, step: 1, def: exposure_max);
816
817 v4l2_ctrl_new_std(hdl: &sensor->ctrls, ops: &imx415_ctrl_ops,
818 V4L2_CID_ANALOGUE_GAIN, IMX415_AGAIN_MIN,
819 IMX415_AGAIN_MAX, IMX415_AGAIN_STEP,
820 IMX415_AGAIN_MIN);
821
822 hblank_min = (cur_mode->hmax_min[sensor->num_data_lanes == 2 ? 0 : 1] *
823 IMX415_HMAX_MULTIPLIER) - IMX415_PIXEL_ARRAY_WIDTH;
824 hblank_max = (IMX415_HMAX_MAX * IMX415_HMAX_MULTIPLIER) -
825 IMX415_PIXEL_ARRAY_WIDTH;
826 ctrl = v4l2_ctrl_new_std(hdl: &sensor->ctrls, ops: &imx415_ctrl_ops,
827 V4L2_CID_HBLANK, min: hblank_min,
828 max: hblank_max, IMX415_HMAX_MULTIPLIER,
829 def: hblank_min);
830
831 sensor->vblank = v4l2_ctrl_new_std(hdl: &sensor->ctrls, ops: &imx415_ctrl_ops,
832 V4L2_CID_VBLANK,
833 IMX415_PIXEL_ARRAY_VBLANK,
834 IMX415_VMAX_MAX - IMX415_PIXEL_ARRAY_HEIGHT,
835 step: 1, IMX415_PIXEL_ARRAY_VBLANK);
836
837 v4l2_ctrl_new_std(hdl: &sensor->ctrls, NULL, V4L2_CID_PIXEL_RATE,
838 min: sensor->pixel_rate, max: sensor->pixel_rate, step: 1,
839 def: sensor->pixel_rate);
840
841 sensor->hflip = v4l2_ctrl_new_std(hdl: &sensor->ctrls, ops: &imx415_ctrl_ops,
842 V4L2_CID_HFLIP, min: 0, max: 1, step: 1, def: 0);
843 sensor->vflip = v4l2_ctrl_new_std(hdl: &sensor->ctrls, ops: &imx415_ctrl_ops,
844 V4L2_CID_VFLIP, min: 0, max: 1, step: 1, def: 0);
845
846 v4l2_ctrl_new_std_menu_items(hdl: &sensor->ctrls, ops: &imx415_ctrl_ops,
847 V4L2_CID_TEST_PATTERN,
848 ARRAY_SIZE(imx415_test_pattern_menu) - 1,
849 mask: 0, def: 0, qmenu: imx415_test_pattern_menu);
850
851 v4l2_ctrl_new_fwnode_properties(hdl: &sensor->ctrls, ctrl_ops: &imx415_ctrl_ops,
852 p: &props);
853
854 if (sensor->ctrls.error) {
855 dev_err_probe(dev: sensor->dev, err: sensor->ctrls.error,
856 fmt: "failed to add controls\n");
857 v4l2_ctrl_handler_free(hdl: &sensor->ctrls);
858 return sensor->ctrls.error;
859 }
860 sensor->subdev.ctrl_handler = &sensor->ctrls;
861
862 return 0;
863}
864
865static int imx415_set_mode(struct imx415 *sensor, int mode)
866{
867 int ret = 0;
868
869 if (mode >= ARRAY_SIZE(supported_modes)) {
870 dev_err(sensor->dev, "Mode %d not supported\n", mode);
871 return -EINVAL;
872 }
873
874 cci_multi_reg_write(map: sensor->regmap,
875 regs: supported_modes[mode].reg_list.regs,
876 num_regs: supported_modes[mode].reg_list.num_of_regs,
877 err: &ret);
878
879 cci_multi_reg_write(map: sensor->regmap,
880 regs: sensor->clk_params->regs,
881 IMX415_NUM_CLK_PARAM_REGS,
882 err: &ret);
883
884 ret = cci_write(map: sensor->regmap, IMX415_LANEMODE,
885 val: sensor->num_data_lanes == 2 ? IMX415_LANEMODE_2 :
886 IMX415_LANEMODE_4,
887 NULL);
888
889 return ret;
890}
891
892static int imx415_setup(struct imx415 *sensor, struct v4l2_subdev_state *state)
893{
894 int ret;
895
896 ret = cci_multi_reg_write(map: sensor->regmap,
897 regs: imx415_init_table,
898 ARRAY_SIZE(imx415_init_table),
899 NULL);
900 if (ret)
901 return ret;
902
903 return imx415_set_mode(sensor, mode: sensor->cur_mode);
904}
905
906static int imx415_wakeup(struct imx415 *sensor)
907{
908 int ret;
909
910 ret = cci_write(map: sensor->regmap, IMX415_MODE,
911 IMX415_MODE_OPERATING, NULL);
912 if (ret)
913 return ret;
914
915 /*
916 * According to the datasheet we have to wait at least 63 us after
917 * leaving standby mode. But this doesn't work even after 30 ms.
918 * So probably this should be 63 ms and therefore we wait for 80 ms.
919 */
920 msleep(msecs: 80);
921
922 return 0;
923}
924
925static int imx415_stream_on(struct imx415 *sensor)
926{
927 int ret;
928
929 ret = imx415_wakeup(sensor);
930 return cci_write(map: sensor->regmap, IMX415_XMSTA,
931 IMX415_XMSTA_START, err: &ret);
932}
933
934static int imx415_stream_off(struct imx415 *sensor)
935{
936 int ret;
937
938 ret = cci_write(map: sensor->regmap, IMX415_XMSTA,
939 IMX415_XMSTA_STOP, NULL);
940 return cci_write(map: sensor->regmap, IMX415_MODE,
941 IMX415_MODE_STANDBY, err: &ret);
942}
943
944static int imx415_s_stream(struct v4l2_subdev *sd, int enable)
945{
946 struct imx415 *sensor = to_imx415(sd);
947 struct v4l2_subdev_state *state;
948 int ret;
949
950 state = v4l2_subdev_lock_and_get_active_state(sd);
951
952 if (!enable) {
953 ret = imx415_stream_off(sensor);
954
955 pm_runtime_mark_last_busy(dev: sensor->dev);
956 pm_runtime_put_autosuspend(dev: sensor->dev);
957
958 goto unlock;
959 }
960
961 ret = pm_runtime_resume_and_get(dev: sensor->dev);
962 if (ret < 0)
963 goto unlock;
964
965 ret = imx415_setup(sensor, state);
966 if (ret)
967 goto err_pm;
968
969 ret = __v4l2_ctrl_handler_setup(hdl: &sensor->ctrls);
970 if (ret < 0)
971 goto err_pm;
972
973 ret = imx415_stream_on(sensor);
974 if (ret)
975 goto err_pm;
976
977 ret = 0;
978
979unlock:
980 v4l2_subdev_unlock_state(state);
981
982 return ret;
983
984err_pm:
985 /*
986 * In case of error, turn the power off synchronously as the device
987 * likely has no other chance to recover.
988 */
989 pm_runtime_put_sync(dev: sensor->dev);
990
991 goto unlock;
992}
993
994static int imx415_enum_mbus_code(struct v4l2_subdev *sd,
995 struct v4l2_subdev_state *state,
996 struct v4l2_subdev_mbus_code_enum *code)
997{
998 if (code->index != 0)
999 return -EINVAL;
1000
1001 code->code = MEDIA_BUS_FMT_SGBRG10_1X10;
1002
1003 return 0;
1004}
1005
1006static int imx415_enum_frame_size(struct v4l2_subdev *sd,
1007 struct v4l2_subdev_state *state,
1008 struct v4l2_subdev_frame_size_enum *fse)
1009{
1010 const struct v4l2_mbus_framefmt *format;
1011
1012 format = v4l2_subdev_state_get_format(state, fse->pad);
1013
1014 if (fse->index > 0 || fse->code != format->code)
1015 return -EINVAL;
1016
1017 fse->min_width = IMX415_PIXEL_ARRAY_WIDTH;
1018 fse->max_width = fse->min_width;
1019 fse->min_height = IMX415_PIXEL_ARRAY_HEIGHT;
1020 fse->max_height = fse->min_height;
1021 return 0;
1022}
1023
1024static int imx415_set_format(struct v4l2_subdev *sd,
1025 struct v4l2_subdev_state *state,
1026 struct v4l2_subdev_format *fmt)
1027{
1028 struct v4l2_mbus_framefmt *format;
1029
1030 format = v4l2_subdev_state_get_format(state, fmt->pad);
1031
1032 format->width = fmt->format.width;
1033 format->height = fmt->format.height;
1034 format->code = MEDIA_BUS_FMT_SGBRG10_1X10;
1035 format->field = V4L2_FIELD_NONE;
1036 format->colorspace = V4L2_COLORSPACE_RAW;
1037 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1038 format->quantization = V4L2_QUANTIZATION_DEFAULT;
1039 format->xfer_func = V4L2_XFER_FUNC_NONE;
1040
1041 fmt->format = *format;
1042 return 0;
1043}
1044
1045static int imx415_get_selection(struct v4l2_subdev *sd,
1046 struct v4l2_subdev_state *sd_state,
1047 struct v4l2_subdev_selection *sel)
1048{
1049 switch (sel->target) {
1050 case V4L2_SEL_TGT_CROP:
1051 case V4L2_SEL_TGT_CROP_DEFAULT:
1052 case V4L2_SEL_TGT_CROP_BOUNDS:
1053 sel->r.top = IMX415_PIXEL_ARRAY_TOP;
1054 sel->r.left = IMX415_PIXEL_ARRAY_LEFT;
1055 sel->r.width = IMX415_PIXEL_ARRAY_WIDTH;
1056 sel->r.height = IMX415_PIXEL_ARRAY_HEIGHT;
1057
1058 return 0;
1059 }
1060
1061 return -EINVAL;
1062}
1063
1064static int imx415_init_state(struct v4l2_subdev *sd,
1065 struct v4l2_subdev_state *state)
1066{
1067 struct v4l2_subdev_format format = {
1068 .format = {
1069 .width = IMX415_PIXEL_ARRAY_WIDTH,
1070 .height = IMX415_PIXEL_ARRAY_HEIGHT,
1071 },
1072 };
1073
1074 imx415_set_format(sd, state, fmt: &format);
1075
1076 return 0;
1077}
1078
1079static const struct v4l2_subdev_video_ops imx415_subdev_video_ops = {
1080 .s_stream = imx415_s_stream,
1081};
1082
1083static const struct v4l2_subdev_pad_ops imx415_subdev_pad_ops = {
1084 .enum_mbus_code = imx415_enum_mbus_code,
1085 .enum_frame_size = imx415_enum_frame_size,
1086 .get_fmt = v4l2_subdev_get_fmt,
1087 .set_fmt = imx415_set_format,
1088 .get_selection = imx415_get_selection,
1089};
1090
1091static const struct v4l2_subdev_ops imx415_subdev_ops = {
1092 .video = &imx415_subdev_video_ops,
1093 .pad = &imx415_subdev_pad_ops,
1094};
1095
1096static const struct v4l2_subdev_internal_ops imx415_internal_ops = {
1097 .init_state = imx415_init_state,
1098};
1099
1100static int imx415_subdev_init(struct imx415 *sensor)
1101{
1102 struct i2c_client *client = to_i2c_client(sensor->dev);
1103 int ret;
1104
1105 v4l2_i2c_subdev_init(sd: &sensor->subdev, client, ops: &imx415_subdev_ops);
1106 sensor->subdev.internal_ops = &imx415_internal_ops;
1107
1108 ret = imx415_ctrls_init(sensor);
1109 if (ret)
1110 return ret;
1111
1112 sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1113 sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
1114 sensor->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1115 ret = media_entity_pads_init(entity: &sensor->subdev.entity, num_pads: 1, pads: &sensor->pad);
1116 if (ret < 0) {
1117 v4l2_ctrl_handler_free(hdl: &sensor->ctrls);
1118 return ret;
1119 }
1120
1121 sensor->subdev.state_lock = sensor->subdev.ctrl_handler->lock;
1122 v4l2_subdev_init_finalize(&sensor->subdev);
1123
1124 return 0;
1125}
1126
1127static void imx415_subdev_cleanup(struct imx415 *sensor)
1128{
1129 media_entity_cleanup(entity: &sensor->subdev.entity);
1130 v4l2_ctrl_handler_free(hdl: &sensor->ctrls);
1131}
1132
1133static int imx415_power_on(struct imx415 *sensor)
1134{
1135 int ret;
1136
1137 ret = regulator_bulk_enable(ARRAY_SIZE(sensor->supplies),
1138 consumers: sensor->supplies);
1139 if (ret < 0)
1140 return ret;
1141
1142 gpiod_set_value_cansleep(desc: sensor->reset, value: 0);
1143
1144 udelay(usec: 1);
1145
1146 ret = clk_prepare_enable(clk: sensor->clk);
1147 if (ret < 0)
1148 goto err_reset;
1149
1150 /*
1151 * Data sheet states that 20 us are required before communication start,
1152 * but this doesn't work in all cases. Use 100 us to be on the safe
1153 * side.
1154 */
1155 usleep_range(min: 100, max: 200);
1156
1157 return 0;
1158
1159err_reset:
1160 gpiod_set_value_cansleep(desc: sensor->reset, value: 1);
1161 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), consumers: sensor->supplies);
1162 return ret;
1163}
1164
1165static void imx415_power_off(struct imx415 *sensor)
1166{
1167 clk_disable_unprepare(clk: sensor->clk);
1168 gpiod_set_value_cansleep(desc: sensor->reset, value: 1);
1169 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), consumers: sensor->supplies);
1170}
1171
1172static int imx415_identify_model(struct imx415 *sensor)
1173{
1174 int model, ret;
1175 u64 chip_id;
1176
1177 /*
1178 * While most registers can be read when the sensor is in standby, this
1179 * is not the case of the sensor info register :-(
1180 */
1181 ret = imx415_wakeup(sensor);
1182 if (ret)
1183 return dev_err_probe(dev: sensor->dev, err: ret,
1184 fmt: "failed to get sensor out of standby\n");
1185
1186 ret = cci_read(map: sensor->regmap, IMX415_SENSOR_INFO, val: &chip_id, NULL);
1187 if (ret < 0) {
1188 dev_err_probe(dev: sensor->dev, err: ret,
1189 fmt: "failed to read sensor information\n");
1190 goto done;
1191 }
1192
1193 model = chip_id & IMX415_SENSOR_INFO_MASK;
1194
1195 switch (model) {
1196 case IMX415_CHIP_ID:
1197 dev_info(sensor->dev, "Detected IMX415 image sensor\n");
1198 break;
1199 default:
1200 ret = dev_err_probe(dev: sensor->dev, err: -ENODEV,
1201 fmt: "invalid device model 0x%04x\n", model);
1202 goto done;
1203 }
1204
1205 ret = 0;
1206
1207done:
1208 cci_write(map: sensor->regmap, IMX415_MODE, IMX415_MODE_STANDBY, err: &ret);
1209 return ret;
1210}
1211
1212static int imx415_check_inck(unsigned long inck, u64 link_frequency)
1213{
1214 unsigned int i;
1215
1216 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {
1217 if ((imx415_clk_params[i].lane_rate == link_frequency * 2) &&
1218 imx415_clk_params[i].inck == inck)
1219 break;
1220 }
1221
1222 if (i == ARRAY_SIZE(imx415_clk_params))
1223 return -EINVAL;
1224 else
1225 return 0;
1226}
1227
1228static int imx415_parse_hw_config(struct imx415 *sensor)
1229{
1230 struct v4l2_fwnode_endpoint bus_cfg = {
1231 .bus_type = V4L2_MBUS_CSI2_DPHY,
1232 };
1233 struct fwnode_handle *ep;
1234 u64 lane_rate;
1235 unsigned long inck;
1236 unsigned int i, j;
1237 int ret;
1238
1239 for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i)
1240 sensor->supplies[i].supply = imx415_supply_names[i];
1241
1242 ret = devm_regulator_bulk_get(dev: sensor->dev, ARRAY_SIZE(sensor->supplies),
1243 consumers: sensor->supplies);
1244 if (ret)
1245 return dev_err_probe(dev: sensor->dev, err: ret,
1246 fmt: "failed to get supplies\n");
1247
1248 sensor->reset = devm_gpiod_get_optional(dev: sensor->dev, con_id: "reset",
1249 flags: GPIOD_OUT_HIGH);
1250 if (IS_ERR(ptr: sensor->reset))
1251 return dev_err_probe(dev: sensor->dev, err: PTR_ERR(ptr: sensor->reset),
1252 fmt: "failed to get reset GPIO\n");
1253
1254 sensor->clk = devm_clk_get(dev: sensor->dev, id: "inck");
1255 if (IS_ERR(ptr: sensor->clk))
1256 return dev_err_probe(dev: sensor->dev, err: PTR_ERR(ptr: sensor->clk),
1257 fmt: "failed to get clock\n");
1258
1259 ep = fwnode_graph_get_next_endpoint(dev_fwnode(sensor->dev), NULL);
1260 if (!ep)
1261 return -ENXIO;
1262
1263 ret = v4l2_fwnode_endpoint_alloc_parse(fwnode: ep, vep: &bus_cfg);
1264 fwnode_handle_put(fwnode: ep);
1265 if (ret)
1266 return ret;
1267
1268 switch (bus_cfg.bus.mipi_csi2.num_data_lanes) {
1269 case 2:
1270 case 4:
1271 sensor->num_data_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
1272 break;
1273 default:
1274 ret = dev_err_probe(dev: sensor->dev, err: -EINVAL,
1275 fmt: "invalid number of CSI2 data lanes %d\n",
1276 bus_cfg.bus.mipi_csi2.num_data_lanes);
1277 goto done_endpoint_free;
1278 }
1279
1280 if (!bus_cfg.nr_of_link_frequencies) {
1281 ret = dev_err_probe(dev: sensor->dev, err: -EINVAL,
1282 fmt: "no link frequencies defined");
1283 goto done_endpoint_free;
1284 }
1285
1286 /*
1287 * Check if there exists a sensor mode defined for current INCK,
1288 * number of lanes and given lane rates.
1289 */
1290 inck = clk_get_rate(clk: sensor->clk);
1291 for (i = 0; i < bus_cfg.nr_of_link_frequencies; ++i) {
1292 if (imx415_check_inck(inck, link_frequency: bus_cfg.link_frequencies[i])) {
1293 dev_dbg(sensor->dev,
1294 "INCK %lu Hz not supported for this link freq",
1295 inck);
1296 continue;
1297 }
1298
1299 for (j = 0; j < ARRAY_SIZE(supported_modes); ++j) {
1300 if (bus_cfg.link_frequencies[i] * 2 !=
1301 supported_modes[j].lane_rate)
1302 continue;
1303 sensor->cur_mode = j;
1304 break;
1305 }
1306 if (j < ARRAY_SIZE(supported_modes))
1307 break;
1308 }
1309 if (i == bus_cfg.nr_of_link_frequencies) {
1310 ret = dev_err_probe(dev: sensor->dev, err: -EINVAL,
1311 fmt: "no valid sensor mode defined\n");
1312 goto done_endpoint_free;
1313 }
1314 switch (inck) {
1315 case 27000000:
1316 case 37125000:
1317 case 74250000:
1318 sensor->pixel_rate = IMX415_PIXEL_RATE_74_25MHZ;
1319 break;
1320 case 24000000:
1321 case 72000000:
1322 sensor->pixel_rate = IMX415_PIXEL_RATE_72MHZ;
1323 break;
1324 }
1325
1326 lane_rate = supported_modes[sensor->cur_mode].lane_rate;
1327 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {
1328 if (lane_rate == imx415_clk_params[i].lane_rate &&
1329 inck == imx415_clk_params[i].inck) {
1330 sensor->clk_params = &imx415_clk_params[i];
1331 break;
1332 }
1333 }
1334 if (i == ARRAY_SIZE(imx415_clk_params)) {
1335 ret = dev_err_probe(dev: sensor->dev, err: -EINVAL,
1336 fmt: "Mode %d not supported\n",
1337 sensor->cur_mode);
1338 goto done_endpoint_free;
1339 }
1340
1341 ret = 0;
1342 dev_dbg(sensor->dev, "clock: %lu Hz, lane_rate: %llu bps, lanes: %d\n",
1343 inck, lane_rate, sensor->num_data_lanes);
1344
1345done_endpoint_free:
1346 v4l2_fwnode_endpoint_free(vep: &bus_cfg);
1347
1348 return ret;
1349}
1350
1351static int imx415_probe(struct i2c_client *client)
1352{
1353 struct imx415 *sensor;
1354 int ret;
1355
1356 sensor = devm_kzalloc(dev: &client->dev, size: sizeof(*sensor), GFP_KERNEL);
1357 if (!sensor)
1358 return -ENOMEM;
1359
1360 sensor->dev = &client->dev;
1361
1362 ret = imx415_parse_hw_config(sensor);
1363 if (ret)
1364 return ret;
1365
1366 sensor->regmap = devm_cci_regmap_init_i2c(client, reg_addr_bits: 16);
1367 if (IS_ERR(ptr: sensor->regmap))
1368 return PTR_ERR(ptr: sensor->regmap);
1369
1370 /*
1371 * Enable power management. The driver supports runtime PM, but needs to
1372 * work when runtime PM is disabled in the kernel. To that end, power
1373 * the sensor on manually here, identify it, and fully initialize it.
1374 */
1375 ret = imx415_power_on(sensor);
1376 if (ret)
1377 return ret;
1378
1379 ret = imx415_identify_model(sensor);
1380 if (ret)
1381 goto err_power;
1382
1383 ret = imx415_subdev_init(sensor);
1384 if (ret)
1385 goto err_power;
1386
1387 /*
1388 * Enable runtime PM. As the device has been powered manually, mark it
1389 * as active, and increase the usage count without resuming the device.
1390 */
1391 pm_runtime_set_active(dev: sensor->dev);
1392 pm_runtime_get_noresume(dev: sensor->dev);
1393 pm_runtime_enable(dev: sensor->dev);
1394
1395 ret = v4l2_async_register_subdev_sensor(sd: &sensor->subdev);
1396 if (ret < 0)
1397 goto err_pm;
1398
1399 /*
1400 * Finally, enable autosuspend and decrease the usage count. The device
1401 * will get suspended after the autosuspend delay, turning the power
1402 * off.
1403 */
1404 pm_runtime_set_autosuspend_delay(dev: sensor->dev, delay: 1000);
1405 pm_runtime_use_autosuspend(dev: sensor->dev);
1406 pm_runtime_put_autosuspend(dev: sensor->dev);
1407
1408 return 0;
1409
1410err_pm:
1411 pm_runtime_disable(dev: sensor->dev);
1412 pm_runtime_put_noidle(dev: sensor->dev);
1413 imx415_subdev_cleanup(sensor);
1414err_power:
1415 imx415_power_off(sensor);
1416 return ret;
1417}
1418
1419static void imx415_remove(struct i2c_client *client)
1420{
1421 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1422 struct imx415 *sensor = to_imx415(sd: subdev);
1423
1424 v4l2_async_unregister_subdev(sd: subdev);
1425
1426 imx415_subdev_cleanup(sensor);
1427
1428 /*
1429 * Disable runtime PM. In case runtime PM is disabled in the kernel,
1430 * make sure to turn power off manually.
1431 */
1432 pm_runtime_disable(dev: sensor->dev);
1433 if (!pm_runtime_status_suspended(dev: sensor->dev))
1434 imx415_power_off(sensor);
1435 pm_runtime_set_suspended(dev: sensor->dev);
1436}
1437
1438static int imx415_runtime_resume(struct device *dev)
1439{
1440 struct i2c_client *client = to_i2c_client(dev);
1441 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1442 struct imx415 *sensor = to_imx415(sd: subdev);
1443
1444 return imx415_power_on(sensor);
1445}
1446
1447static int imx415_runtime_suspend(struct device *dev)
1448{
1449 struct i2c_client *client = to_i2c_client(dev);
1450 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1451 struct imx415 *sensor = to_imx415(sd: subdev);
1452
1453 imx415_power_off(sensor);
1454
1455 return 0;
1456}
1457
1458static DEFINE_RUNTIME_DEV_PM_OPS(imx415_pm_ops, imx415_runtime_suspend,
1459 imx415_runtime_resume, NULL);
1460
1461static const struct of_device_id imx415_of_match[] = {
1462 { .compatible = "sony,imx415" },
1463 { /* sentinel */ }
1464};
1465
1466MODULE_DEVICE_TABLE(of, imx415_of_match);
1467
1468static struct i2c_driver imx415_driver = {
1469 .probe = imx415_probe,
1470 .remove = imx415_remove,
1471 .driver = {
1472 .name = "imx415",
1473 .of_match_table = imx415_of_match,
1474 .pm = pm_ptr(&imx415_pm_ops),
1475 },
1476};
1477
1478module_i2c_driver(imx415_driver);
1479
1480MODULE_DESCRIPTION("Sony IMX415 image sensor driver");
1481MODULE_AUTHOR("Gerald Loacker <gerald.loacker@wolfvision.net>");
1482MODULE_AUTHOR("Michael Riesch <michael.riesch@wolfvision.net>");
1483MODULE_LICENSE("GPL");
1484

source code of linux/drivers/media/i2c/imx415.c