1// SPDX-License-Identifier: GPL-2.0
2/*
3 * V4L2 sensor driver for OmniVision OV64A40
4 *
5 * Copyright (C) 2023 Ideas On Board Oy
6 * Copyright (C) 2023 Arducam
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/i2c.h>
13#include <linux/mod_devicetable.h>
14#include <linux/module.h>
15#include <linux/pm_runtime.h>
16#include <linux/regulator/consumer.h>
17
18#include <media/v4l2-cci.h>
19#include <media/v4l2-ctrls.h>
20#include <media/v4l2-device.h>
21#include <media/v4l2-fwnode.h>
22#include <media/v4l2-mediabus.h>
23#include <media/v4l2-subdev.h>
24
25#define OV64A40_XCLK_FREQ 24000000
26
27#define OV64A40_NATIVE_WIDTH 9286
28#define OV64A40_NATIVE_HEIGHT 6976
29#define OV64A40_PIXEL_ARRAY_TOP 0
30#define OV64A40_PIXEL_ARRAY_LEFT 0
31#define OV64A40_PIXEL_ARRAY_WIDTH 9248
32#define OV64A40_PIXEL_ARRAY_HEIGHT 6944
33
34#define OV64A40_PIXEL_RATE 300000000
35
36#define OV64A40_LINK_FREQ_360M 360000000
37#define OV64A40_LINK_FREQ_456M 456000000
38
39#define OV64A40_PLL1_PRE_DIV0 CCI_REG8(0x0301)
40#define OV64A40_PLL1_PRE_DIV CCI_REG8(0x0303)
41#define OV64A40_PLL1_MULTIPLIER CCI_REG16(0x0304)
42#define OV64A40_PLL1_M_DIV CCI_REG8(0x0307)
43#define OV64A40_PLL2_SEL_BAK_SA1 CCI_REG8(0x0320)
44#define OV64A40_PLL2_PRE_DIV CCI_REG8(0x0323)
45#define OV64A40_PLL2_MULTIPLIER CCI_REG16(0x0324)
46#define OV64A40_PLL2_PRE_DIV0 CCI_REG8(0x0326)
47#define OV64A40_PLL2_DIVDAC CCI_REG8(0x0329)
48#define OV64A40_PLL2_DIVSP CCI_REG8(0x032d)
49#define OV64A40_PLL2_DACPREDIV CCI_REG8(0x032e)
50
51/* TODO: validate vblank_min, it's not characterized in the datasheet. */
52#define OV64A40_VBLANK_MIN 128
53#define OV64A40_VTS_MAX 0xffffff
54
55#define OV64A40_REG_MEC_LONG_EXPO CCI_REG24(0x3500)
56#define OV64A40_EXPOSURE_MIN 16
57#define OV64A40_EXPOSURE_MARGIN 32
58
59#define OV64A40_REG_MEC_LONG_GAIN CCI_REG16(0x3508)
60#define OV64A40_ANA_GAIN_MIN 0x80
61#define OV64A40_ANA_GAIN_MAX 0x7ff
62#define OV64A40_ANA_GAIN_DEFAULT 0x80
63
64#define OV64A40_REG_TIMING_CTRL0 CCI_REG16(0x3800)
65#define OV64A40_REG_TIMING_CTRL2 CCI_REG16(0x3802)
66#define OV64A40_REG_TIMING_CTRL4 CCI_REG16(0x3804)
67#define OV64A40_REG_TIMING_CTRL6 CCI_REG16(0x3806)
68#define OV64A40_REG_TIMING_CTRL8 CCI_REG16(0x3808)
69#define OV64A40_REG_TIMING_CTRLA CCI_REG16(0x380a)
70#define OV64A40_REG_TIMING_CTRLC CCI_REG16(0x380c)
71#define OV64A40_REG_TIMING_CTRLE CCI_REG16(0x380e)
72#define OV64A40_REG_TIMING_CTRL10 CCI_REG16(0x3810)
73#define OV64A40_REG_TIMING_CTRL12 CCI_REG16(0x3812)
74
75/*
76 * Careful: a typo in the datasheet calls this register
77 * OV64A40_REG_TIMING_CTRL20.
78 */
79#define OV64A40_REG_TIMING_CTRL14 CCI_REG8(0x3814)
80#define OV64A40_REG_TIMING_CTRL15 CCI_REG8(0x3815)
81#define OV64A40_ODD_INC_SHIFT 4
82#define OV64A40_SKIPPING_CONFIG(_odd, _even) \
83 (((_odd) << OV64A40_ODD_INC_SHIFT) | (_even))
84
85#define OV64A40_REG_TIMING_CTRL_20 CCI_REG8(0x3820)
86#define OV64A40_TIMING_CTRL_20_VFLIP BIT(2)
87#define OV64A40_TIMING_CTRL_20_VBIN BIT(1)
88
89#define OV64A40_REG_TIMING_CTRL_21 CCI_REG8(0x3821)
90#define OV64A40_TIMING_CTRL_21_HBIN BIT(4)
91#define OV64A40_TIMING_CTRL_21_HFLIP BIT(2)
92#define OV64A40_TIMING_CTRL_21_DSPEED BIT(0)
93#define OV64A40_TIMING_CTRL_21_HBIN_CONF \
94 (OV64A40_TIMING_CTRL_21_HBIN | \
95 OV64A40_TIMING_CTRL_21_DSPEED)
96
97#define OV64A40_REG_TIMINGS_VTS_HIGH CCI_REG8(0x3840)
98#define OV64A40_REG_TIMINGS_VTS_MID CCI_REG8(0x380e)
99#define OV64A40_REG_TIMINGS_VTS_LOW CCI_REG8(0x380f)
100
101/* The test pattern control is weirdly named PRE_ISP_2325_D2V2_TOP_1 in TRM. */
102#define OV64A40_REG_TEST_PATTERN CCI_REG8(0x50c1)
103#define OV64A40_TEST_PATTERN_DISABLED 0x00
104#define OV64A40_TEST_PATTERN_TYPE1 BIT(0)
105#define OV64A40_TEST_PATTERN_TYPE2 (BIT(4) | BIT(0))
106#define OV64A40_TEST_PATTERN_TYPE3 (BIT(5) | BIT(0))
107#define OV64A40_TEST_PATTERN_TYPE4 (BIT(5) | BIT(4) | BIT(0))
108
109#define OV64A40_REG_CHIP_ID CCI_REG24(0x300a)
110#define OV64A40_CHIP_ID 0x566441
111
112#define OV64A40_REG_SMIA CCI_REG8(0x0100)
113#define OV64A40_REG_SMIA_STREAMING BIT(0)
114
115enum ov64a40_link_freq_ids {
116 OV64A40_LINK_FREQ_456M_ID,
117 OV64A40_LINK_FREQ_360M_ID,
118 OV64A40_NUM_LINK_FREQ,
119};
120
121static const char * const ov64a40_supply_names[] = {
122 /* Supplies can be enabled in any order */
123 "avdd", /* Analog (2.8V) supply */
124 "dovdd", /* Digital Core (1.8V) supply */
125 "dvdd", /* IF (1.1V) supply */
126};
127
128static const char * const ov64a40_test_pattern_menu[] = {
129 "Disabled",
130 "Type1",
131 "Type2",
132 "Type3",
133 "Type4",
134};
135
136static const int ov64a40_test_pattern_val[] = {
137 OV64A40_TEST_PATTERN_DISABLED,
138 OV64A40_TEST_PATTERN_TYPE1,
139 OV64A40_TEST_PATTERN_TYPE2,
140 OV64A40_TEST_PATTERN_TYPE3,
141 OV64A40_TEST_PATTERN_TYPE4,
142};
143
144static const unsigned int ov64a40_mbus_codes[] = {
145 MEDIA_BUS_FMT_SBGGR10_1X10,
146 MEDIA_BUS_FMT_SGRBG10_1X10,
147 MEDIA_BUS_FMT_SGBRG10_1X10,
148 MEDIA_BUS_FMT_SRGGB10_1X10,
149};
150
151static const struct cci_reg_sequence ov64a40_init[] = {
152 { CCI_REG8(0x0103), 0x01 }, { CCI_REG8(0x0301), 0x88 },
153 { CCI_REG8(0x0304), 0x00 }, { CCI_REG8(0x0305), 0x96 },
154 { CCI_REG8(0x0306), 0x03 }, { CCI_REG8(0x0307), 0x00 },
155 { CCI_REG8(0x0345), 0x2c }, { CCI_REG8(0x034a), 0x02 },
156 { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x0350), 0xc0 },
157 { CCI_REG8(0x0360), 0x09 }, { CCI_REG8(0x3012), 0x31 },
158 { CCI_REG8(0x3015), 0xf0 }, { CCI_REG8(0x3017), 0xf0 },
159 { CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 },
160 { CCI_REG8(0x3022), 0xf0 }, { CCI_REG8(0x3400), 0x08 },
161 { CCI_REG8(0x3608), 0x41 }, { CCI_REG8(0x3421), 0x02 },
162 { CCI_REG8(0x3500), 0x00 }, { CCI_REG8(0x3501), 0x00 },
163 { CCI_REG8(0x3502), 0x18 }, { CCI_REG8(0x3504), 0x0c },
164 { CCI_REG8(0x3508), 0x01 }, { CCI_REG8(0x3509), 0x00 },
165 { CCI_REG8(0x350a), 0x01 }, { CCI_REG8(0x350b), 0x00 },
166 { CCI_REG8(0x350b), 0x00 }, { CCI_REG8(0x3540), 0x00 },
167 { CCI_REG8(0x3541), 0x00 }, { CCI_REG8(0x3542), 0x08 },
168 { CCI_REG8(0x3548), 0x01 }, { CCI_REG8(0x3549), 0xa0 },
169 { CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3549), 0x00 },
170 { CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3580), 0x00 },
171 { CCI_REG8(0x3581), 0x00 }, { CCI_REG8(0x3582), 0x04 },
172 { CCI_REG8(0x3588), 0x01 }, { CCI_REG8(0x3589), 0xf0 },
173 { CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x3589), 0x00 },
174 { CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x360d), 0x83 },
175 { CCI_REG8(0x3616), 0xa0 }, { CCI_REG8(0x3617), 0x31 },
176 { CCI_REG8(0x3623), 0x10 }, { CCI_REG8(0x3633), 0x03 },
177 { CCI_REG8(0x3634), 0x03 }, { CCI_REG8(0x3635), 0x77 },
178 { CCI_REG8(0x3640), 0x19 }, { CCI_REG8(0x3641), 0x80 },
179 { CCI_REG8(0x364d), 0x0f }, { CCI_REG8(0x3680), 0x80 },
180 { CCI_REG8(0x3682), 0x00 }, { CCI_REG8(0x3683), 0x00 },
181 { CCI_REG8(0x3684), 0x07 }, { CCI_REG8(0x3688), 0x01 },
182 { CCI_REG8(0x3689), 0x08 }, { CCI_REG8(0x368a), 0x26 },
183 { CCI_REG8(0x368b), 0xc8 }, { CCI_REG8(0x368e), 0x70 },
184 { CCI_REG8(0x368f), 0x00 }, { CCI_REG8(0x3692), 0x04 },
185 { CCI_REG8(0x3693), 0x00 }, { CCI_REG8(0x3696), 0xd1 },
186 { CCI_REG8(0x3697), 0xe0 }, { CCI_REG8(0x3698), 0x80 },
187 { CCI_REG8(0x3699), 0x2b }, { CCI_REG8(0x369a), 0x00 },
188 { CCI_REG8(0x369d), 0x00 }, { CCI_REG8(0x369e), 0x14 },
189 { CCI_REG8(0x369f), 0x20 }, { CCI_REG8(0x36a5), 0x80 },
190 { CCI_REG8(0x36a6), 0x00 }, { CCI_REG8(0x36a7), 0x00 },
191 { CCI_REG8(0x36a8), 0x00 }, { CCI_REG8(0x36b5), 0x17 },
192 { CCI_REG8(0x3701), 0x30 }, { CCI_REG8(0x3706), 0x2b },
193 { CCI_REG8(0x3709), 0x8d }, { CCI_REG8(0x370b), 0x4f },
194 { CCI_REG8(0x3711), 0x00 }, { CCI_REG8(0x3712), 0x01 },
195 { CCI_REG8(0x3713), 0x00 }, { CCI_REG8(0x3720), 0x08 },
196 { CCI_REG8(0x3727), 0x22 }, { CCI_REG8(0x3728), 0x01 },
197 { CCI_REG8(0x375e), 0x00 }, { CCI_REG8(0x3760), 0x08 },
198 { CCI_REG8(0x3761), 0x10 }, { CCI_REG8(0x3762), 0x08 },
199 { CCI_REG8(0x3765), 0x10 }, { CCI_REG8(0x3766), 0x18 },
200 { CCI_REG8(0x376a), 0x08 }, { CCI_REG8(0x376b), 0x00 },
201 { CCI_REG8(0x376d), 0x1b }, { CCI_REG8(0x3791), 0x2b },
202 { CCI_REG8(0x3793), 0x2b }, { CCI_REG8(0x3795), 0x2b },
203 { CCI_REG8(0x3797), 0x4f }, { CCI_REG8(0x3799), 0x4f },
204 { CCI_REG8(0x379b), 0x4f }, { CCI_REG8(0x37a0), 0x22 },
205 { CCI_REG8(0x37da), 0x04 }, { CCI_REG8(0x37f9), 0x02 },
206 { CCI_REG8(0x37fa), 0x02 }, { CCI_REG8(0x37fb), 0x02 },
207 { CCI_REG8(0x3814), 0x11 }, { CCI_REG8(0x3815), 0x11 },
208 { CCI_REG8(0x3820), 0x40 }, { CCI_REG8(0x3821), 0x04 },
209 { CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3823), 0x04 },
210 { CCI_REG8(0x3827), 0x08 }, { CCI_REG8(0x3828), 0x00 },
211 { CCI_REG8(0x382a), 0x81 }, { CCI_REG8(0x382e), 0x70 },
212 { CCI_REG8(0x3837), 0x10 }, { CCI_REG8(0x3839), 0x00 },
213 { CCI_REG8(0x383b), 0x00 }, { CCI_REG8(0x383c), 0x00 },
214 { CCI_REG8(0x383d), 0x10 }, { CCI_REG8(0x383f), 0x00 },
215 { CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0x8c },
216 { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x10 },
217 { CCI_REG8(0x3857), 0x10 }, { CCI_REG8(0x3858), 0x20 },
218 { CCI_REG8(0x3859), 0x20 }, { CCI_REG8(0x3894), 0x00 },
219 { CCI_REG8(0x3895), 0x00 }, { CCI_REG8(0x3896), 0x00 },
220 { CCI_REG8(0x3897), 0x00 }, { CCI_REG8(0x3900), 0x40 },
221 { CCI_REG8(0x3aed), 0x6e }, { CCI_REG8(0x3af1), 0x73 },
222 { CCI_REG8(0x3d86), 0x12 }, { CCI_REG8(0x3d87), 0x30 },
223 { CCI_REG8(0x3d8c), 0xab }, { CCI_REG8(0x3d8d), 0xb0 },
224 { CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f00), 0x12 },
225 { CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f01), 0x03 },
226 { CCI_REG8(0x4009), 0x01 }, { CCI_REG8(0x400e), 0xc6 },
227 { CCI_REG8(0x400f), 0x00 }, { CCI_REG8(0x4010), 0x28 },
228 { CCI_REG8(0x4011), 0x01 }, { CCI_REG8(0x4012), 0x0c },
229 { CCI_REG8(0x4015), 0x00 }, { CCI_REG8(0x4016), 0x1f },
230 { CCI_REG8(0x4017), 0x00 }, { CCI_REG8(0x4018), 0x07 },
231 { CCI_REG8(0x401a), 0x40 }, { CCI_REG8(0x4028), 0x01 },
232 { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4506), 0x01 },
233 { CCI_REG8(0x4508), 0x00 }, { CCI_REG8(0x4509), 0x35 },
234 { CCI_REG8(0x450a), 0x08 }, { CCI_REG8(0x450c), 0x00 },
235 { CCI_REG8(0x450d), 0x20 }, { CCI_REG8(0x450e), 0x00 },
236 { CCI_REG8(0x450f), 0x20 }, { CCI_REG8(0x451e), 0x00 },
237 { CCI_REG8(0x451f), 0x00 }, { CCI_REG8(0x4523), 0x00 },
238 { CCI_REG8(0x4526), 0x00 }, { CCI_REG8(0x4527), 0x18 },
239 { CCI_REG8(0x4580), 0x01 }, { CCI_REG8(0x4583), 0x00 },
240 { CCI_REG8(0x4584), 0x00 }, { CCI_REG8(0x45c0), 0xa1 },
241 { CCI_REG8(0x4602), 0x08 }, { CCI_REG8(0x4603), 0x05 },
242 { CCI_REG8(0x4606), 0x12 }, { CCI_REG8(0x4607), 0x30 },
243 { CCI_REG8(0x460b), 0x00 }, { CCI_REG8(0x460d), 0x00 },
244 { CCI_REG8(0x4640), 0x00 }, { CCI_REG8(0x4641), 0x24 },
245 { CCI_REG8(0x4643), 0x08 }, { CCI_REG8(0x4645), 0x14 },
246 { CCI_REG8(0x4648), 0x0a }, { CCI_REG8(0x4649), 0x06 },
247 { CCI_REG8(0x464a), 0x00 }, { CCI_REG8(0x464b), 0x30 },
248 { CCI_REG8(0x4800), 0x04 }, { CCI_REG8(0x4802), 0x02 },
249 { CCI_REG8(0x480b), 0x10 }, { CCI_REG8(0x480c), 0x80 },
250 { CCI_REG8(0x480e), 0x04 }, { CCI_REG8(0x480f), 0x32 },
251 { CCI_REG8(0x481b), 0x12 }, { CCI_REG8(0x4833), 0x30 },
252 { CCI_REG8(0x4837), 0x08 }, { CCI_REG8(0x484b), 0x27 },
253 { CCI_REG8(0x4850), 0x42 }, { CCI_REG8(0x4851), 0xaa },
254 { CCI_REG8(0x4860), 0x01 }, { CCI_REG8(0x4861), 0xec },
255 { CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x4888), 0x00 },
256 { CCI_REG8(0x4889), 0x03 }, { CCI_REG8(0x488c), 0x60 },
257 { CCI_REG8(0x4910), 0x28 }, { CCI_REG8(0x4911), 0x01 },
258 { CCI_REG8(0x4912), 0x0c }, { CCI_REG8(0x491a), 0x40 },
259 { CCI_REG8(0x4915), 0x00 }, { CCI_REG8(0x4916), 0x0f },
260 { CCI_REG8(0x4917), 0x00 }, { CCI_REG8(0x4918), 0x07 },
261 { CCI_REG8(0x4a10), 0x28 }, { CCI_REG8(0x4a11), 0x01 },
262 { CCI_REG8(0x4a12), 0x0c }, { CCI_REG8(0x4a1a), 0x40 },
263 { CCI_REG8(0x4a15), 0x00 }, { CCI_REG8(0x4a16), 0x0f },
264 { CCI_REG8(0x4a17), 0x00 }, { CCI_REG8(0x4a18), 0x07 },
265 { CCI_REG8(0x4d00), 0x04 }, { CCI_REG8(0x4d01), 0x5a },
266 { CCI_REG8(0x4d02), 0xbb }, { CCI_REG8(0x4d03), 0x84 },
267 { CCI_REG8(0x4d04), 0xd1 }, { CCI_REG8(0x4d05), 0x68 },
268 { CCI_REG8(0xc4fa), 0x10 }, { CCI_REG8(0x3b56), 0x0a },
269 { CCI_REG8(0x3b57), 0x0a }, { CCI_REG8(0x3b58), 0x0c },
270 { CCI_REG8(0x3b59), 0x10 }, { CCI_REG8(0x3a1d), 0x30 },
271 { CCI_REG8(0x3a1e), 0x30 }, { CCI_REG8(0x3a21), 0x30 },
272 { CCI_REG8(0x3a22), 0x30 }, { CCI_REG8(0x3992), 0x02 },
273 { CCI_REG8(0x399e), 0x02 }, { CCI_REG8(0x39fb), 0x30 },
274 { CCI_REG8(0x39fc), 0x30 }, { CCI_REG8(0x39fd), 0x30 },
275 { CCI_REG8(0x39fe), 0x30 }, { CCI_REG8(0x3a6d), 0x83 },
276 { CCI_REG8(0x3a5e), 0x83 }, { CCI_REG8(0xc500), 0x12 },
277 { CCI_REG8(0xc501), 0x12 }, { CCI_REG8(0xc502), 0x12 },
278 { CCI_REG8(0xc503), 0x12 }, { CCI_REG8(0xc505), 0x12 },
279 { CCI_REG8(0xc506), 0x12 }, { CCI_REG8(0xc507), 0x12 },
280 { CCI_REG8(0xc508), 0x12 }, { CCI_REG8(0x3a77), 0x12 },
281 { CCI_REG8(0x3a73), 0x12 }, { CCI_REG8(0x3a7b), 0x12 },
282 { CCI_REG8(0x3a7f), 0x12 }, { CCI_REG8(0x3b2e), 0x13 },
283 { CCI_REG8(0x3b29), 0x13 }, { CCI_REG8(0xc439), 0x13 },
284 { CCI_REG8(0xc469), 0x13 }, { CCI_REG8(0xc41c), 0x89 },
285 { CCI_REG8(0x3618), 0x80 }, { CCI_REG8(0xc514), 0x51 },
286 { CCI_REG8(0xc515), 0x2c }, { CCI_REG8(0xc516), 0x16 },
287 { CCI_REG8(0xc517), 0x0d }, { CCI_REG8(0x3615), 0x7f },
288 { CCI_REG8(0x3632), 0x99 }, { CCI_REG8(0x3642), 0x00 },
289 { CCI_REG8(0x3645), 0x80 }, { CCI_REG8(0x3702), 0x2a },
290 { CCI_REG8(0x3703), 0x2a }, { CCI_REG8(0x3708), 0x2f },
291 { CCI_REG8(0x3721), 0x15 }, { CCI_REG8(0x3744), 0x28 },
292 { CCI_REG8(0x3991), 0x0c }, { CCI_REG8(0x371d), 0x24 },
293 { CCI_REG8(0x371f), 0x0c }, { CCI_REG8(0x374b), 0x03 },
294 { CCI_REG8(0x37d0), 0x00 }, { CCI_REG8(0x391d), 0x55 },
295 { CCI_REG8(0x391e), 0x52 }, { CCI_REG8(0x399d), 0x0c },
296 { CCI_REG8(0x3a2f), 0x01 }, { CCI_REG8(0x3a30), 0x01 },
297 { CCI_REG8(0x3a31), 0x01 }, { CCI_REG8(0x3a32), 0x01 },
298 { CCI_REG8(0x3a34), 0x01 }, { CCI_REG8(0x3a35), 0x01 },
299 { CCI_REG8(0x3a36), 0x01 }, { CCI_REG8(0x3a37), 0x01 },
300 { CCI_REG8(0x3a43), 0x01 }, { CCI_REG8(0x3a44), 0x01 },
301 { CCI_REG8(0x3a45), 0x01 }, { CCI_REG8(0x3a46), 0x01 },
302 { CCI_REG8(0x3a48), 0x01 }, { CCI_REG8(0x3a49), 0x01 },
303 { CCI_REG8(0x3a4a), 0x01 }, { CCI_REG8(0x3a4b), 0x01 },
304 { CCI_REG8(0x3a50), 0x14 }, { CCI_REG8(0x3a54), 0x14 },
305 { CCI_REG8(0x3a60), 0x20 }, { CCI_REG8(0x3a6f), 0x20 },
306 { CCI_REG8(0x3ac5), 0x01 }, { CCI_REG8(0x3ac6), 0x01 },
307 { CCI_REG8(0x3ac7), 0x01 }, { CCI_REG8(0x3ac8), 0x01 },
308 { CCI_REG8(0x3ac9), 0x01 }, { CCI_REG8(0x3aca), 0x01 },
309 { CCI_REG8(0x3acb), 0x01 }, { CCI_REG8(0x3acc), 0x01 },
310 { CCI_REG8(0x3acd), 0x01 }, { CCI_REG8(0x3ace), 0x01 },
311 { CCI_REG8(0x3acf), 0x01 }, { CCI_REG8(0x3ad0), 0x01 },
312 { CCI_REG8(0x3ad1), 0x01 }, { CCI_REG8(0x3ad2), 0x01 },
313 { CCI_REG8(0x3ad3), 0x01 }, { CCI_REG8(0x3ad4), 0x01 },
314 { CCI_REG8(0x3add), 0x1f }, { CCI_REG8(0x3adf), 0x24 },
315 { CCI_REG8(0x3aef), 0x1f }, { CCI_REG8(0x3af0), 0x24 },
316 { CCI_REG8(0x3b92), 0x08 }, { CCI_REG8(0x3b93), 0x08 },
317 { CCI_REG8(0x3b94), 0x08 }, { CCI_REG8(0x3b95), 0x08 },
318 { CCI_REG8(0x3be7), 0x1e }, { CCI_REG8(0x3be8), 0x26 },
319 { CCI_REG8(0xc44a), 0x20 }, { CCI_REG8(0xc44c), 0x20 },
320 { CCI_REG8(0xc483), 0x00 }, { CCI_REG8(0xc484), 0x00 },
321 { CCI_REG8(0xc485), 0x00 }, { CCI_REG8(0xc486), 0x00 },
322 { CCI_REG8(0xc487), 0x01 }, { CCI_REG8(0xc488), 0x01 },
323 { CCI_REG8(0xc489), 0x01 }, { CCI_REG8(0xc48a), 0x01 },
324 { CCI_REG8(0xc4c1), 0x00 }, { CCI_REG8(0xc4c2), 0x00 },
325 { CCI_REG8(0xc4c3), 0x00 }, { CCI_REG8(0xc4c4), 0x00 },
326 { CCI_REG8(0xc4c6), 0x10 }, { CCI_REG8(0xc4c7), 0x10 },
327 { CCI_REG8(0xc4c8), 0x10 }, { CCI_REG8(0xc4c9), 0x10 },
328 { CCI_REG8(0xc4ca), 0x10 }, { CCI_REG8(0xc4cb), 0x10 },
329 { CCI_REG8(0xc4cc), 0x10 }, { CCI_REG8(0xc4cd), 0x10 },
330 { CCI_REG8(0xc4ea), 0x07 }, { CCI_REG8(0xc4eb), 0x07 },
331 { CCI_REG8(0xc4ec), 0x07 }, { CCI_REG8(0xc4ed), 0x07 },
332 { CCI_REG8(0xc4ee), 0x07 }, { CCI_REG8(0xc4f6), 0x10 },
333 { CCI_REG8(0xc4f7), 0x10 }, { CCI_REG8(0xc4f8), 0x10 },
334 { CCI_REG8(0xc4f9), 0x10 }, { CCI_REG8(0xc518), 0x0e },
335 { CCI_REG8(0xc519), 0x0e }, { CCI_REG8(0xc51a), 0x0e },
336 { CCI_REG8(0xc51b), 0x0e }, { CCI_REG8(0xc51c), 0x0e },
337 { CCI_REG8(0xc51d), 0x0e }, { CCI_REG8(0xc51e), 0x0e },
338 { CCI_REG8(0xc51f), 0x0e }, { CCI_REG8(0xc520), 0x0e },
339 { CCI_REG8(0xc521), 0x0e }, { CCI_REG8(0xc522), 0x0e },
340 { CCI_REG8(0xc523), 0x0e }, { CCI_REG8(0xc524), 0x0e },
341 { CCI_REG8(0xc525), 0x0e }, { CCI_REG8(0xc526), 0x0e },
342 { CCI_REG8(0xc527), 0x0e }, { CCI_REG8(0xc528), 0x0e },
343 { CCI_REG8(0xc529), 0x0e }, { CCI_REG8(0xc52a), 0x0e },
344 { CCI_REG8(0xc52b), 0x0e }, { CCI_REG8(0xc52c), 0x0e },
345 { CCI_REG8(0xc52d), 0x0e }, { CCI_REG8(0xc52e), 0x0e },
346 { CCI_REG8(0xc52f), 0x0e }, { CCI_REG8(0xc530), 0x0e },
347 { CCI_REG8(0xc531), 0x0e }, { CCI_REG8(0xc532), 0x0e },
348 { CCI_REG8(0xc533), 0x0e }, { CCI_REG8(0xc534), 0x0e },
349 { CCI_REG8(0xc535), 0x0e }, { CCI_REG8(0xc536), 0x0e },
350 { CCI_REG8(0xc537), 0x0e }, { CCI_REG8(0xc538), 0x0e },
351 { CCI_REG8(0xc539), 0x0e }, { CCI_REG8(0xc53a), 0x0e },
352 { CCI_REG8(0xc53b), 0x0e }, { CCI_REG8(0xc53c), 0x0e },
353 { CCI_REG8(0xc53d), 0x0e }, { CCI_REG8(0xc53e), 0x0e },
354 { CCI_REG8(0xc53f), 0x0e }, { CCI_REG8(0xc540), 0x0e },
355 { CCI_REG8(0xc541), 0x0e }, { CCI_REG8(0xc542), 0x0e },
356 { CCI_REG8(0xc543), 0x0e }, { CCI_REG8(0xc544), 0x0e },
357 { CCI_REG8(0xc545), 0x0e }, { CCI_REG8(0xc546), 0x0e },
358 { CCI_REG8(0xc547), 0x0e }, { CCI_REG8(0xc548), 0x0e },
359 { CCI_REG8(0xc549), 0x0e }, { CCI_REG8(0xc57f), 0x22 },
360 { CCI_REG8(0xc580), 0x22 }, { CCI_REG8(0xc581), 0x22 },
361 { CCI_REG8(0xc582), 0x22 }, { CCI_REG8(0xc583), 0x22 },
362 { CCI_REG8(0xc584), 0x22 }, { CCI_REG8(0xc585), 0x22 },
363 { CCI_REG8(0xc586), 0x22 }, { CCI_REG8(0xc587), 0x22 },
364 { CCI_REG8(0xc588), 0x22 }, { CCI_REG8(0xc589), 0x22 },
365 { CCI_REG8(0xc58a), 0x22 }, { CCI_REG8(0xc58b), 0x22 },
366 { CCI_REG8(0xc58c), 0x22 }, { CCI_REG8(0xc58d), 0x22 },
367 { CCI_REG8(0xc58e), 0x22 }, { CCI_REG8(0xc58f), 0x22 },
368 { CCI_REG8(0xc590), 0x22 }, { CCI_REG8(0xc591), 0x22 },
369 { CCI_REG8(0xc592), 0x22 }, { CCI_REG8(0xc598), 0x22 },
370 { CCI_REG8(0xc599), 0x22 }, { CCI_REG8(0xc59a), 0x22 },
371 { CCI_REG8(0xc59b), 0x22 }, { CCI_REG8(0xc59c), 0x22 },
372 { CCI_REG8(0xc59d), 0x22 }, { CCI_REG8(0xc59e), 0x22 },
373 { CCI_REG8(0xc59f), 0x22 }, { CCI_REG8(0xc5a0), 0x22 },
374 { CCI_REG8(0xc5a1), 0x22 }, { CCI_REG8(0xc5a2), 0x22 },
375 { CCI_REG8(0xc5a3), 0x22 }, { CCI_REG8(0xc5a4), 0x22 },
376 { CCI_REG8(0xc5a5), 0x22 }, { CCI_REG8(0xc5a6), 0x22 },
377 { CCI_REG8(0xc5a7), 0x22 }, { CCI_REG8(0xc5a8), 0x22 },
378 { CCI_REG8(0xc5a9), 0x22 }, { CCI_REG8(0xc5aa), 0x22 },
379 { CCI_REG8(0xc5ab), 0x22 }, { CCI_REG8(0xc5b1), 0x2a },
380 { CCI_REG8(0xc5b2), 0x2a }, { CCI_REG8(0xc5b3), 0x2a },
381 { CCI_REG8(0xc5b4), 0x2a }, { CCI_REG8(0xc5b5), 0x2a },
382 { CCI_REG8(0xc5b6), 0x2a }, { CCI_REG8(0xc5b7), 0x2a },
383 { CCI_REG8(0xc5b8), 0x2a }, { CCI_REG8(0xc5b9), 0x2a },
384 { CCI_REG8(0xc5ba), 0x2a }, { CCI_REG8(0xc5bb), 0x2a },
385 { CCI_REG8(0xc5bc), 0x2a }, { CCI_REG8(0xc5bd), 0x2a },
386 { CCI_REG8(0xc5be), 0x2a }, { CCI_REG8(0xc5bf), 0x2a },
387 { CCI_REG8(0xc5c0), 0x2a }, { CCI_REG8(0xc5c1), 0x2a },
388 { CCI_REG8(0xc5c2), 0x2a }, { CCI_REG8(0xc5c3), 0x2a },
389 { CCI_REG8(0xc5c4), 0x2a }, { CCI_REG8(0xc5ca), 0x2a },
390 { CCI_REG8(0xc5cb), 0x2a }, { CCI_REG8(0xc5cc), 0x2a },
391 { CCI_REG8(0xc5cd), 0x2a }, { CCI_REG8(0xc5ce), 0x2a },
392 { CCI_REG8(0xc5cf), 0x2a }, { CCI_REG8(0xc5d0), 0x2a },
393 { CCI_REG8(0xc5d1), 0x2a }, { CCI_REG8(0xc5d2), 0x2a },
394 { CCI_REG8(0xc5d3), 0x2a }, { CCI_REG8(0xc5d4), 0x2a },
395 { CCI_REG8(0xc5d5), 0x2a }, { CCI_REG8(0xc5d6), 0x2a },
396 { CCI_REG8(0xc5d7), 0x2a }, { CCI_REG8(0xc5d8), 0x2a },
397 { CCI_REG8(0xc5d9), 0x2a }, { CCI_REG8(0xc5da), 0x2a },
398 { CCI_REG8(0xc5db), 0x2a }, { CCI_REG8(0xc5dc), 0x2a },
399 { CCI_REG8(0xc5dd), 0x2a }, { CCI_REG8(0xc5e8), 0x22 },
400 { CCI_REG8(0xc5ea), 0x22 }, { CCI_REG8(0x4540), 0x12 },
401 { CCI_REG8(0x4541), 0x30 }, { CCI_REG8(0x3d86), 0x12 },
402 { CCI_REG8(0x3d87), 0x30 }, { CCI_REG8(0x4606), 0x12 },
403 { CCI_REG8(0x4607), 0x30 }, { CCI_REG8(0x4648), 0x0a },
404 { CCI_REG8(0x4649), 0x06 }, { CCI_REG8(0x3220), 0x12 },
405 { CCI_REG8(0x3221), 0x30 }, { CCI_REG8(0x40c2), 0x12 },
406 { CCI_REG8(0x49c2), 0x12 }, { CCI_REG8(0x4ac2), 0x12 },
407 { CCI_REG8(0x40c3), 0x30 }, { CCI_REG8(0x49c3), 0x30 },
408 { CCI_REG8(0x4ac3), 0x30 }, { CCI_REG8(0x36b0), 0x12 },
409 { CCI_REG8(0x36b1), 0x30 }, { CCI_REG8(0x45cb), 0x12 },
410 { CCI_REG8(0x45cc), 0x30 }, { CCI_REG8(0x4585), 0x12 },
411 { CCI_REG8(0x4586), 0x30 }, { CCI_REG8(0x36b2), 0x12 },
412 { CCI_REG8(0x36b3), 0x30 }, { CCI_REG8(0x5a40), 0x75 },
413 { CCI_REG8(0x5a41), 0x75 }, { CCI_REG8(0x5a42), 0x75 },
414 { CCI_REG8(0x5a43), 0x75 }, { CCI_REG8(0x5a44), 0x75 },
415 { CCI_REG8(0x5a45), 0x75 }, { CCI_REG8(0x5a46), 0x75 },
416 { CCI_REG8(0x5a47), 0x75 }, { CCI_REG8(0x5a48), 0x75 },
417 { CCI_REG8(0x5a49), 0x75 }, { CCI_REG8(0x5a4a), 0x75 },
418 { CCI_REG8(0x5a4b), 0x75 }, { CCI_REG8(0x5a4c), 0x75 },
419 { CCI_REG8(0x5a4d), 0x75 }, { CCI_REG8(0x5a4e), 0x75 },
420 { CCI_REG8(0x5a4f), 0x75 }, { CCI_REG8(0x5a50), 0x75 },
421 { CCI_REG8(0x5a51), 0x75 }, { CCI_REG8(0x5a52), 0x75 },
422 { CCI_REG8(0x5a53), 0x75 }, { CCI_REG8(0x5a54), 0x75 },
423 { CCI_REG8(0x5a55), 0x75 }, { CCI_REG8(0x5a56), 0x75 },
424 { CCI_REG8(0x5a57), 0x75 }, { CCI_REG8(0x5a58), 0x75 },
425 { CCI_REG8(0x5a59), 0x75 }, { CCI_REG8(0x5a5a), 0x75 },
426 { CCI_REG8(0x5a5b), 0x75 }, { CCI_REG8(0x5a5c), 0x75 },
427 { CCI_REG8(0x5a5d), 0x75 }, { CCI_REG8(0x5a5e), 0x75 },
428 { CCI_REG8(0x5a5f), 0x75 }, { CCI_REG8(0x5a60), 0x75 },
429 { CCI_REG8(0x5a61), 0x75 }, { CCI_REG8(0x5a62), 0x75 },
430 { CCI_REG8(0x5a63), 0x75 }, { CCI_REG8(0x5a64), 0x75 },
431 { CCI_REG8(0x5a65), 0x75 }, { CCI_REG8(0x5a66), 0x75 },
432 { CCI_REG8(0x5a67), 0x75 }, { CCI_REG8(0x5a68), 0x75 },
433 { CCI_REG8(0x5a69), 0x75 }, { CCI_REG8(0x5a6a), 0x75 },
434 { CCI_REG8(0x5a6b), 0x75 }, { CCI_REG8(0x5a6c), 0x75 },
435 { CCI_REG8(0x5a6d), 0x75 }, { CCI_REG8(0x5a6e), 0x75 },
436 { CCI_REG8(0x5a6f), 0x75 }, { CCI_REG8(0x5a70), 0x75 },
437 { CCI_REG8(0x5a71), 0x75 }, { CCI_REG8(0x5a72), 0x75 },
438 { CCI_REG8(0x5a73), 0x75 }, { CCI_REG8(0x5a74), 0x75 },
439 { CCI_REG8(0x5a75), 0x75 }, { CCI_REG8(0x5a76), 0x75 },
440 { CCI_REG8(0x5a77), 0x75 }, { CCI_REG8(0x5a78), 0x75 },
441 { CCI_REG8(0x5a79), 0x75 }, { CCI_REG8(0x5a7a), 0x75 },
442 { CCI_REG8(0x5a7b), 0x75 }, { CCI_REG8(0x5a7c), 0x75 },
443 { CCI_REG8(0x5a7d), 0x75 }, { CCI_REG8(0x5a7e), 0x75 },
444 { CCI_REG8(0x5a7f), 0x75 }, { CCI_REG8(0x5a80), 0x75 },
445 { CCI_REG8(0x5a81), 0x75 }, { CCI_REG8(0x5a82), 0x75 },
446 { CCI_REG8(0x5a83), 0x75 }, { CCI_REG8(0x5a84), 0x75 },
447 { CCI_REG8(0x5a85), 0x75 }, { CCI_REG8(0x5a86), 0x75 },
448 { CCI_REG8(0x5a87), 0x75 }, { CCI_REG8(0x5a88), 0x75 },
449 { CCI_REG8(0x5a89), 0x75 }, { CCI_REG8(0x5a8a), 0x75 },
450 { CCI_REG8(0x5a8b), 0x75 }, { CCI_REG8(0x5a8c), 0x75 },
451 { CCI_REG8(0x5a8d), 0x75 }, { CCI_REG8(0x5a8e), 0x75 },
452 { CCI_REG8(0x5a8f), 0x75 }, { CCI_REG8(0x5a90), 0x75 },
453 { CCI_REG8(0x5a91), 0x75 }, { CCI_REG8(0x5a92), 0x75 },
454 { CCI_REG8(0x5a93), 0x75 }, { CCI_REG8(0x5a94), 0x75 },
455 { CCI_REG8(0x5a95), 0x75 }, { CCI_REG8(0x5a96), 0x75 },
456 { CCI_REG8(0x5a97), 0x75 }, { CCI_REG8(0x5a98), 0x75 },
457 { CCI_REG8(0x5a99), 0x75 }, { CCI_REG8(0x5a9a), 0x75 },
458 { CCI_REG8(0x5a9b), 0x75 }, { CCI_REG8(0x5a9c), 0x75 },
459 { CCI_REG8(0x5a9d), 0x75 }, { CCI_REG8(0x5a9e), 0x75 },
460 { CCI_REG8(0x5a9f), 0x75 }, { CCI_REG8(0x5aa0), 0x75 },
461 { CCI_REG8(0x5aa1), 0x75 }, { CCI_REG8(0x5aa2), 0x75 },
462 { CCI_REG8(0x5aa3), 0x75 }, { CCI_REG8(0x5aa4), 0x75 },
463 { CCI_REG8(0x5aa5), 0x75 }, { CCI_REG8(0x5aa6), 0x75 },
464 { CCI_REG8(0x5aa7), 0x75 }, { CCI_REG8(0x5aa8), 0x75 },
465 { CCI_REG8(0x5aa9), 0x75 }, { CCI_REG8(0x5aaa), 0x75 },
466 { CCI_REG8(0x5aab), 0x75 }, { CCI_REG8(0x5aac), 0x75 },
467 { CCI_REG8(0x5aad), 0x75 }, { CCI_REG8(0x5aae), 0x75 },
468 { CCI_REG8(0x5aaf), 0x75 }, { CCI_REG8(0x5ab0), 0x75 },
469 { CCI_REG8(0x5ab1), 0x75 }, { CCI_REG8(0x5ab2), 0x75 },
470 { CCI_REG8(0x5ab3), 0x75 }, { CCI_REG8(0x5ab4), 0x75 },
471 { CCI_REG8(0x5ab5), 0x75 }, { CCI_REG8(0x5ab6), 0x75 },
472 { CCI_REG8(0x5ab7), 0x75 }, { CCI_REG8(0x5ab8), 0x75 },
473 { CCI_REG8(0x5ab9), 0x75 }, { CCI_REG8(0x5aba), 0x75 },
474 { CCI_REG8(0x5abb), 0x75 }, { CCI_REG8(0x5abc), 0x75 },
475 { CCI_REG8(0x5abd), 0x75 }, { CCI_REG8(0x5abe), 0x75 },
476 { CCI_REG8(0x5abf), 0x75 }, { CCI_REG8(0x5ac0), 0x75 },
477 { CCI_REG8(0x5ac1), 0x75 }, { CCI_REG8(0x5ac2), 0x75 },
478 { CCI_REG8(0x5ac3), 0x75 }, { CCI_REG8(0x5ac4), 0x75 },
479 { CCI_REG8(0x5ac5), 0x75 }, { CCI_REG8(0x5ac6), 0x75 },
480 { CCI_REG8(0x5ac7), 0x75 }, { CCI_REG8(0x5ac8), 0x75 },
481 { CCI_REG8(0x5ac9), 0x75 }, { CCI_REG8(0x5aca), 0x75 },
482 { CCI_REG8(0x5acb), 0x75 }, { CCI_REG8(0x5acc), 0x75 },
483 { CCI_REG8(0x5acd), 0x75 }, { CCI_REG8(0x5ace), 0x75 },
484 { CCI_REG8(0x5acf), 0x75 }, { CCI_REG8(0x5ad0), 0x75 },
485 { CCI_REG8(0x5ad1), 0x75 }, { CCI_REG8(0x5ad2), 0x75 },
486 { CCI_REG8(0x5ad3), 0x75 }, { CCI_REG8(0x5ad4), 0x75 },
487 { CCI_REG8(0x5ad5), 0x75 }, { CCI_REG8(0x5ad6), 0x75 },
488 { CCI_REG8(0x5ad7), 0x75 }, { CCI_REG8(0x5ad8), 0x75 },
489 { CCI_REG8(0x5ad9), 0x75 }, { CCI_REG8(0x5ada), 0x75 },
490 { CCI_REG8(0x5adb), 0x75 }, { CCI_REG8(0x5adc), 0x75 },
491 { CCI_REG8(0x5add), 0x75 }, { CCI_REG8(0x5ade), 0x75 },
492 { CCI_REG8(0x5adf), 0x75 }, { CCI_REG8(0x5ae0), 0x75 },
493 { CCI_REG8(0x5ae1), 0x75 }, { CCI_REG8(0x5ae2), 0x75 },
494 { CCI_REG8(0x5ae3), 0x75 }, { CCI_REG8(0x5ae4), 0x75 },
495 { CCI_REG8(0x5ae5), 0x75 }, { CCI_REG8(0x5ae6), 0x75 },
496 { CCI_REG8(0x5ae7), 0x75 }, { CCI_REG8(0x5ae8), 0x75 },
497 { CCI_REG8(0x5ae9), 0x75 }, { CCI_REG8(0x5aea), 0x75 },
498 { CCI_REG8(0x5aeb), 0x75 }, { CCI_REG8(0x5aec), 0x75 },
499 { CCI_REG8(0x5aed), 0x75 }, { CCI_REG8(0x5aee), 0x75 },
500 { CCI_REG8(0x5aef), 0x75 }, { CCI_REG8(0x5af0), 0x75 },
501 { CCI_REG8(0x5af1), 0x75 }, { CCI_REG8(0x5af2), 0x75 },
502 { CCI_REG8(0x5af3), 0x75 }, { CCI_REG8(0x5af4), 0x75 },
503 { CCI_REG8(0x5af5), 0x75 }, { CCI_REG8(0x5af6), 0x75 },
504 { CCI_REG8(0x5af7), 0x75 }, { CCI_REG8(0x5af8), 0x75 },
505 { CCI_REG8(0x5af9), 0x75 }, { CCI_REG8(0x5afa), 0x75 },
506 { CCI_REG8(0x5afb), 0x75 }, { CCI_REG8(0x5afc), 0x75 },
507 { CCI_REG8(0x5afd), 0x75 }, { CCI_REG8(0x5afe), 0x75 },
508 { CCI_REG8(0x5aff), 0x75 }, { CCI_REG8(0x5b00), 0x75 },
509 { CCI_REG8(0x5b01), 0x75 }, { CCI_REG8(0x5b02), 0x75 },
510 { CCI_REG8(0x5b03), 0x75 }, { CCI_REG8(0x5b04), 0x75 },
511 { CCI_REG8(0x5b05), 0x75 }, { CCI_REG8(0x5b06), 0x75 },
512 { CCI_REG8(0x5b07), 0x75 }, { CCI_REG8(0x5b08), 0x75 },
513 { CCI_REG8(0x5b09), 0x75 }, { CCI_REG8(0x5b0a), 0x75 },
514 { CCI_REG8(0x5b0b), 0x75 }, { CCI_REG8(0x5b0c), 0x75 },
515 { CCI_REG8(0x5b0d), 0x75 }, { CCI_REG8(0x5b0e), 0x75 },
516 { CCI_REG8(0x5b0f), 0x75 }, { CCI_REG8(0x5b10), 0x75 },
517 { CCI_REG8(0x5b11), 0x75 }, { CCI_REG8(0x5b12), 0x75 },
518 { CCI_REG8(0x5b13), 0x75 }, { CCI_REG8(0x5b14), 0x75 },
519 { CCI_REG8(0x5b15), 0x75 }, { CCI_REG8(0x5b16), 0x75 },
520 { CCI_REG8(0x5b17), 0x75 }, { CCI_REG8(0x5b18), 0x75 },
521 { CCI_REG8(0x5b19), 0x75 }, { CCI_REG8(0x5b1a), 0x75 },
522 { CCI_REG8(0x5b1b), 0x75 }, { CCI_REG8(0x5b1c), 0x75 },
523 { CCI_REG8(0x5b1d), 0x75 }, { CCI_REG8(0x5b1e), 0x75 },
524 { CCI_REG8(0x5b1f), 0x75 }, { CCI_REG8(0x5b20), 0x75 },
525 { CCI_REG8(0x5b21), 0x75 }, { CCI_REG8(0x5b22), 0x75 },
526 { CCI_REG8(0x5b23), 0x75 }, { CCI_REG8(0x5b24), 0x75 },
527 { CCI_REG8(0x5b25), 0x75 }, { CCI_REG8(0x5b26), 0x75 },
528 { CCI_REG8(0x5b27), 0x75 }, { CCI_REG8(0x5b28), 0x75 },
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588 { CCI_REG8(0x5bbf), 0x75 }, { CCI_REG8(0x5bc0), 0x75 },
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600 { CCI_REG8(0x5bd7), 0x75 }, { CCI_REG8(0x5bd8), 0x75 },
601 { CCI_REG8(0x5bd9), 0x75 }, { CCI_REG8(0x5bda), 0x75 },
602 { CCI_REG8(0x5bdb), 0x75 }, { CCI_REG8(0x5bdc), 0x75 },
603 { CCI_REG8(0x5bdd), 0x75 }, { CCI_REG8(0x5bde), 0x75 },
604 { CCI_REG8(0x5bdf), 0x75 }, { CCI_REG8(0x5be0), 0x75 },
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607 { CCI_REG8(0x5be5), 0x75 }, { CCI_REG8(0x5be6), 0x75 },
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609 { CCI_REG8(0x5be9), 0x75 }, { CCI_REG8(0x5bea), 0x75 },
610 { CCI_REG8(0x5beb), 0x75 }, { CCI_REG8(0x5bec), 0x75 },
611 { CCI_REG8(0x5bed), 0x75 }, { CCI_REG8(0x5bee), 0x75 },
612 { CCI_REG8(0x5bef), 0x75 }, { CCI_REG8(0x5bf0), 0x75 },
613 { CCI_REG8(0x5bf1), 0x75 }, { CCI_REG8(0x5bf2), 0x75 },
614 { CCI_REG8(0x5bf3), 0x75 }, { CCI_REG8(0x5bf4), 0x75 },
615 { CCI_REG8(0x5bf5), 0x75 }, { CCI_REG8(0x5bf6), 0x75 },
616 { CCI_REG8(0x5bf7), 0x75 }, { CCI_REG8(0x5bf8), 0x75 },
617 { CCI_REG8(0x5bf9), 0x75 }, { CCI_REG8(0x5bfa), 0x75 },
618 { CCI_REG8(0x5bfb), 0x75 }, { CCI_REG8(0x5bfc), 0x75 },
619 { CCI_REG8(0x5bfd), 0x75 }, { CCI_REG8(0x5bfe), 0x75 },
620 { CCI_REG8(0x5bff), 0x75 }, { CCI_REG8(0x5c00), 0x75 },
621 { CCI_REG8(0x5c01), 0x75 }, { CCI_REG8(0x5c02), 0x75 },
622 { CCI_REG8(0x5c03), 0x75 }, { CCI_REG8(0x5c04), 0x75 },
623 { CCI_REG8(0x5c05), 0x75 }, { CCI_REG8(0x5c06), 0x75 },
624 { CCI_REG8(0x5c07), 0x75 }, { CCI_REG8(0x5c08), 0x75 },
625 { CCI_REG8(0x5c09), 0x75 }, { CCI_REG8(0x5c0a), 0x75 },
626 { CCI_REG8(0x5c0b), 0x75 }, { CCI_REG8(0x5c0c), 0x75 },
627 { CCI_REG8(0x5c0d), 0x75 }, { CCI_REG8(0x5c0e), 0x75 },
628 { CCI_REG8(0x5c0f), 0x75 }, { CCI_REG8(0x5c10), 0x75 },
629 { CCI_REG8(0x5c11), 0x75 }, { CCI_REG8(0x5c12), 0x75 },
630 { CCI_REG8(0x5c13), 0x75 }, { CCI_REG8(0x5c14), 0x75 },
631 { CCI_REG8(0x5c15), 0x75 }, { CCI_REG8(0x5c16), 0x75 },
632 { CCI_REG8(0x5c17), 0x75 }, { CCI_REG8(0x5c18), 0x75 },
633 { CCI_REG8(0x5c19), 0x75 }, { CCI_REG8(0x5c1a), 0x75 },
634 { CCI_REG8(0x5c1b), 0x75 }, { CCI_REG8(0x5c1c), 0x75 },
635 { CCI_REG8(0x5c1d), 0x75 }, { CCI_REG8(0x5c1e), 0x75 },
636 { CCI_REG8(0x5c1f), 0x75 }, { CCI_REG8(0x5c20), 0x75 },
637 { CCI_REG8(0x5c21), 0x75 }, { CCI_REG8(0x5c22), 0x75 },
638 { CCI_REG8(0x5c23), 0x75 }, { CCI_REG8(0x5c24), 0x75 },
639 { CCI_REG8(0x5c25), 0x75 }, { CCI_REG8(0x5c26), 0x75 },
640 { CCI_REG8(0x5c27), 0x75 }, { CCI_REG8(0x5c28), 0x75 },
641 { CCI_REG8(0x5c29), 0x75 }, { CCI_REG8(0x5c2a), 0x75 },
642 { CCI_REG8(0x5c2b), 0x75 }, { CCI_REG8(0x5c2c), 0x75 },
643 { CCI_REG8(0x5c2d), 0x75 }, { CCI_REG8(0x5c2e), 0x75 },
644 { CCI_REG8(0x5c2f), 0x75 }, { CCI_REG8(0x5c30), 0x75 },
645 { CCI_REG8(0x5c31), 0x75 }, { CCI_REG8(0x5c32), 0x75 },
646 { CCI_REG8(0x5c33), 0x75 }, { CCI_REG8(0x5c34), 0x75 },
647 { CCI_REG8(0x5c35), 0x75 }, { CCI_REG8(0x5c36), 0x75 },
648 { CCI_REG8(0x5c37), 0x75 }, { CCI_REG8(0x5c38), 0x75 },
649 { CCI_REG8(0x5c39), 0x75 }, { CCI_REG8(0x5c3a), 0x75 },
650 { CCI_REG8(0x5c3b), 0x75 }, { CCI_REG8(0x5c3c), 0x75 },
651 { CCI_REG8(0x5c3d), 0x75 }, { CCI_REG8(0x5c3e), 0x75 },
652 { CCI_REG8(0x5c3f), 0x75 }, { CCI_REG8(0x5c40), 0x75 },
653 { CCI_REG8(0x5c41), 0x75 }, { CCI_REG8(0x5c42), 0x75 },
654 { CCI_REG8(0x5c43), 0x75 }, { CCI_REG8(0x5c44), 0x75 },
655 { CCI_REG8(0x5c45), 0x75 }, { CCI_REG8(0x5c46), 0x75 },
656 { CCI_REG8(0x5c47), 0x75 }, { CCI_REG8(0x5c48), 0x75 },
657 { CCI_REG8(0x5c49), 0x75 }, { CCI_REG8(0x5c4a), 0x75 },
658 { CCI_REG8(0x5c4b), 0x75 }, { CCI_REG8(0x5c4c), 0x75 },
659 { CCI_REG8(0x5c4d), 0x75 }, { CCI_REG8(0x5c4e), 0x75 },
660 { CCI_REG8(0x5c4f), 0x75 }, { CCI_REG8(0x5c50), 0x75 },
661 { CCI_REG8(0x5c51), 0x75 }, { CCI_REG8(0x5c52), 0x75 },
662 { CCI_REG8(0x5c53), 0x75 }, { CCI_REG8(0x5c54), 0x75 },
663 { CCI_REG8(0x5c55), 0x75 }, { CCI_REG8(0x5c56), 0x75 },
664 { CCI_REG8(0x5c57), 0x75 }, { CCI_REG8(0x5c58), 0x75 },
665 { CCI_REG8(0x5c59), 0x75 }, { CCI_REG8(0x5c5a), 0x75 },
666 { CCI_REG8(0x5c5b), 0x75 }, { CCI_REG8(0x5c5c), 0x75 },
667 { CCI_REG8(0x5c5d), 0x75 }, { CCI_REG8(0x5c5e), 0x75 },
668 { CCI_REG8(0x5c5f), 0x75 }, { CCI_REG8(0x5c60), 0x75 },
669 { CCI_REG8(0x5c61), 0x75 }, { CCI_REG8(0x5c62), 0x75 },
670 { CCI_REG8(0x5c63), 0x75 }, { CCI_REG8(0x5c64), 0x75 },
671 { CCI_REG8(0x5c65), 0x75 }, { CCI_REG8(0x5c66), 0x75 },
672 { CCI_REG8(0x5c67), 0x75 }, { CCI_REG8(0x5c68), 0x75 },
673 { CCI_REG8(0x5c69), 0x75 }, { CCI_REG8(0x5c6a), 0x75 },
674 { CCI_REG8(0x5c6b), 0x75 }, { CCI_REG8(0x5c6c), 0x75 },
675 { CCI_REG8(0x5c6d), 0x75 }, { CCI_REG8(0x5c6e), 0x75 },
676 { CCI_REG8(0x5c6f), 0x75 }, { CCI_REG8(0x5c70), 0x75 },
677 { CCI_REG8(0x5c71), 0x75 }, { CCI_REG8(0x5c72), 0x75 },
678 { CCI_REG8(0x5c73), 0x75 }, { CCI_REG8(0x5c74), 0x75 },
679 { CCI_REG8(0x5c75), 0x75 }, { CCI_REG8(0x5c76), 0x75 },
680 { CCI_REG8(0x5c77), 0x75 }, { CCI_REG8(0x5c78), 0x75 },
681 { CCI_REG8(0x5c79), 0x75 }, { CCI_REG8(0x5c7a), 0x75 },
682 { CCI_REG8(0x5c7b), 0x75 }, { CCI_REG8(0x5c7c), 0x75 },
683 { CCI_REG8(0x5c7d), 0x75 }, { CCI_REG8(0x5c7e), 0x75 },
684 { CCI_REG8(0x5c7f), 0x75 }, { CCI_REG8(0x5c80), 0x75 },
685 { CCI_REG8(0x5c81), 0x75 }, { CCI_REG8(0x5c82), 0x75 },
686 { CCI_REG8(0x5c83), 0x75 }, { CCI_REG8(0x5c84), 0x75 },
687 { CCI_REG8(0x5c85), 0x75 }, { CCI_REG8(0x5c86), 0x75 },
688 { CCI_REG8(0x5c87), 0x75 }, { CCI_REG8(0x5c88), 0x75 },
689 { CCI_REG8(0x5c89), 0x75 }, { CCI_REG8(0x5c8a), 0x75 },
690 { CCI_REG8(0x5c8b), 0x75 }, { CCI_REG8(0x5c8c), 0x75 },
691 { CCI_REG8(0x5c8d), 0x75 }, { CCI_REG8(0x5c8e), 0x75 },
692 { CCI_REG8(0x5c8f), 0x75 }, { CCI_REG8(0x5c90), 0x75 },
693 { CCI_REG8(0x5c91), 0x75 }, { CCI_REG8(0x5c92), 0x75 },
694 { CCI_REG8(0x5c93), 0x75 }, { CCI_REG8(0x5c94), 0x75 },
695 { CCI_REG8(0x5c95), 0x75 }, { CCI_REG8(0x5c96), 0x75 },
696 { CCI_REG8(0x5c97), 0x75 }, { CCI_REG8(0x5c98), 0x75 },
697 { CCI_REG8(0x5c99), 0x75 }, { CCI_REG8(0x5c9a), 0x75 },
698 { CCI_REG8(0x5c9b), 0x75 }, { CCI_REG8(0x5c9c), 0x75 },
699 { CCI_REG8(0x5c9d), 0x75 }, { CCI_REG8(0x5c9e), 0x75 },
700 { CCI_REG8(0x5c9f), 0x75 }, { CCI_REG8(0x5ca0), 0x75 },
701 { CCI_REG8(0x5ca1), 0x75 }, { CCI_REG8(0x5ca2), 0x75 },
702 { CCI_REG8(0x5ca3), 0x75 }, { CCI_REG8(0x5ca4), 0x75 },
703 { CCI_REG8(0x5ca5), 0x75 }, { CCI_REG8(0x5ca6), 0x75 },
704 { CCI_REG8(0x5ca7), 0x75 }, { CCI_REG8(0x5ca8), 0x75 },
705 { CCI_REG8(0x5ca9), 0x75 }, { CCI_REG8(0x5caa), 0x75 },
706 { CCI_REG8(0x5cab), 0x75 }, { CCI_REG8(0x5cac), 0x75 },
707 { CCI_REG8(0x5cad), 0x75 }, { CCI_REG8(0x5cae), 0x75 },
708 { CCI_REG8(0x5caf), 0x75 }, { CCI_REG8(0x5cb0), 0x75 },
709 { CCI_REG8(0x5cb1), 0x75 }, { CCI_REG8(0x5cb2), 0x75 },
710 { CCI_REG8(0x5cb3), 0x75 }, { CCI_REG8(0x5cb4), 0x75 },
711 { CCI_REG8(0x5cb5), 0x75 }, { CCI_REG8(0x5cb6), 0x75 },
712 { CCI_REG8(0x5cb7), 0x75 }, { CCI_REG8(0x5cb8), 0x75 },
713 { CCI_REG8(0x5cb9), 0x75 }, { CCI_REG8(0x5cba), 0x75 },
714 { CCI_REG8(0x5cbb), 0x75 }, { CCI_REG8(0x5cbc), 0x75 },
715 { CCI_REG8(0x5cbd), 0x75 }, { CCI_REG8(0x5cbe), 0x75 },
716 { CCI_REG8(0x5cbf), 0x75 }, { CCI_REG8(0x5cc0), 0x75 },
717 { CCI_REG8(0x5cc1), 0x75 }, { CCI_REG8(0x5cc2), 0x75 },
718 { CCI_REG8(0x5cc3), 0x75 }, { CCI_REG8(0x5cc4), 0x75 },
719 { CCI_REG8(0x5cc5), 0x75 }, { CCI_REG8(0x5cc6), 0x75 },
720 { CCI_REG8(0x5cc7), 0x75 }, { CCI_REG8(0x5cc8), 0x75 },
721 { CCI_REG8(0x5cc9), 0x75 }, { CCI_REG8(0x5cca), 0x75 },
722 { CCI_REG8(0x5ccb), 0x75 }, { CCI_REG8(0x5ccc), 0x75 },
723 { CCI_REG8(0x5ccd), 0x75 }, { CCI_REG8(0x5cce), 0x75 },
724 { CCI_REG8(0x5ccf), 0x75 }, { CCI_REG8(0x5cd0), 0x75 },
725 { CCI_REG8(0x5cd1), 0x75 }, { CCI_REG8(0x5cd2), 0x75 },
726 { CCI_REG8(0x5cd3), 0x75 }, { CCI_REG8(0x5cd4), 0x75 },
727 { CCI_REG8(0x5cd5), 0x75 }, { CCI_REG8(0x5cd6), 0x75 },
728 { CCI_REG8(0x5cd7), 0x75 }, { CCI_REG8(0x5cd8), 0x75 },
729 { CCI_REG8(0x5cd9), 0x75 }, { CCI_REG8(0x5cda), 0x75 },
730 { CCI_REG8(0x5cdb), 0x75 }, { CCI_REG8(0x5cdc), 0x75 },
731 { CCI_REG8(0x5cdd), 0x75 }, { CCI_REG8(0x5cde), 0x75 },
732 { CCI_REG8(0x5cdf), 0x75 }, { CCI_REG8(0x5ce0), 0x75 },
733 { CCI_REG8(0x5ce1), 0x75 }, { CCI_REG8(0x5ce2), 0x75 },
734 { CCI_REG8(0x5ce3), 0x75 }, { CCI_REG8(0x5ce4), 0x75 },
735 { CCI_REG8(0x5ce5), 0x75 }, { CCI_REG8(0x5ce6), 0x75 },
736 { CCI_REG8(0x5ce7), 0x75 }, { CCI_REG8(0x5ce8), 0x75 },
737 { CCI_REG8(0x5ce9), 0x75 }, { CCI_REG8(0x5cea), 0x75 },
738 { CCI_REG8(0x5ceb), 0x75 }, { CCI_REG8(0x5cec), 0x75 },
739 { CCI_REG8(0x5ced), 0x75 }, { CCI_REG8(0x5cee), 0x75 },
740 { CCI_REG8(0x5cef), 0x75 }, { CCI_REG8(0x5cf0), 0x75 },
741 { CCI_REG8(0x5cf1), 0x75 }, { CCI_REG8(0x5cf2), 0x75 },
742 { CCI_REG8(0x5cf3), 0x75 }, { CCI_REG8(0x5cf4), 0x75 },
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744 { CCI_REG8(0x5cf7), 0x75 }, { CCI_REG8(0x5cf8), 0x75 },
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851 { CCI_REG8(0x5dcd), 0x75 }, { CCI_REG8(0x5dce), 0x75 },
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885 { CCI_REG8(0x5e11), 0x75 }, { CCI_REG8(0x5e12), 0x75 },
886 { CCI_REG8(0x5e13), 0x75 }, { CCI_REG8(0x5e14), 0x75 },
887 { CCI_REG8(0x5e15), 0x75 }, { CCI_REG8(0x5e16), 0x75 },
888 { CCI_REG8(0x5e17), 0x75 }, { CCI_REG8(0x5e18), 0x75 },
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893 { CCI_REG8(0x5e21), 0x75 }, { CCI_REG8(0x5e22), 0x75 },
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896 { CCI_REG8(0x5e27), 0x75 }, { CCI_REG8(0x5e28), 0x75 },
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898 { CCI_REG8(0x5e2b), 0x75 }, { CCI_REG8(0x5e2c), 0x75 },
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907 { CCI_REG8(0x5e3d), 0x75 }, { CCI_REG8(0x5e3e), 0x75 },
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912 { CCI_REG8(0x5e47), 0x75 }, { CCI_REG8(0x5e48), 0x75 },
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915 { CCI_REG8(0x5e4d), 0x75 }, { CCI_REG8(0x5e4e), 0x75 },
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924 { CCI_REG8(0x5e5f), 0x75 }, { CCI_REG8(0x5e60), 0x75 },
925 { CCI_REG8(0x5e61), 0x75 }, { CCI_REG8(0x5e62), 0x75 },
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930 { CCI_REG8(0x5e6b), 0x75 }, { CCI_REG8(0x5e6c), 0x75 },
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937 { CCI_REG8(0x5e79), 0x75 }, { CCI_REG8(0x5e7a), 0x75 },
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950 { CCI_REG8(0x5e93), 0x75 }, { CCI_REG8(0x5e94), 0x75 },
951 { CCI_REG8(0x5e95), 0x75 }, { CCI_REG8(0x5e96), 0x75 },
952 { CCI_REG8(0x5e97), 0x75 }, { CCI_REG8(0x5e98), 0x75 },
953 { CCI_REG8(0x5e99), 0x75 }, { CCI_REG8(0x5e9a), 0x75 },
954 { CCI_REG8(0x5e9b), 0x75 }, { CCI_REG8(0x5e9c), 0x75 },
955 { CCI_REG8(0x5e9d), 0x75 }, { CCI_REG8(0x5e9e), 0x75 },
956 { CCI_REG8(0x5e9f), 0x75 }, { CCI_REG8(0x5ea0), 0x75 },
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1101 { CCI_REG8(0x557d), 0x4b }, { CCI_REG8(0x5590), 0x00 },
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1111 { CCI_REG8(0x55a3), 0x00 }, { CCI_REG8(0x55a4), 0x01 },
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1122 { CCI_REG8(0x55b9), 0x50 }, { CCI_REG8(0x55ba), 0x01 },
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1124 { CCI_REG8(0x55bd), 0x00 }, { CCI_REG8(0x55be), 0x00 },
1125 { CCI_REG8(0x55bf), 0x50 }, { CCI_REG8(0x55c0), 0x00 },
1126 { CCI_REG8(0x55c1), 0x50 }, { CCI_REG8(0x55c2), 0x01 },
1127 { CCI_REG8(0x55c3), 0x00 }, { CCI_REG8(0x55c4), 0x01 },
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1129 { CCI_REG8(0x55c7), 0x50 }, { CCI_REG8(0x55c8), 0x00 },
1130 { CCI_REG8(0x55c9), 0x50 }, { CCI_REG8(0x55ca), 0x00 },
1131 { CCI_REG8(0x55cb), 0x50 }, { CCI_REG8(0x55cc), 0x00 },
1132 { CCI_REG8(0x55cd), 0x50 }, { CCI_REG8(0x55ce), 0x00 },
1133 { CCI_REG8(0x55cf), 0x50 }, { CCI_REG8(0x55f0), 0x04 },
1134 { CCI_REG8(0x55f1), 0x03 }, { CCI_REG8(0x55f2), 0x02 },
1135 { CCI_REG8(0x55f3), 0x01 }, { CCI_REG8(0x55f4), 0x08 },
1136 { CCI_REG8(0x55f5), 0x07 }, { CCI_REG8(0x55f6), 0x06 },
1137 { CCI_REG8(0x55f7), 0x05 }, { CCI_REG8(0x55f8), 0x0c },
1138 { CCI_REG8(0x55f9), 0x0b }, { CCI_REG8(0x55fa), 0x0a },
1139 { CCI_REG8(0x55fb), 0x09 }, { CCI_REG8(0x55fc), 0x10 },
1140 { CCI_REG8(0x55fd), 0x0f }, { CCI_REG8(0x55fe), 0x0e },
1141 { CCI_REG8(0x55ff), 0x0d }, { CCI_REG8(0x5600), 0x14 },
1142 { CCI_REG8(0x5601), 0x13 }, { CCI_REG8(0x5602), 0x12 },
1143 { CCI_REG8(0x5603), 0x11 }, { CCI_REG8(0x5604), 0x18 },
1144 { CCI_REG8(0x5605), 0x17 }, { CCI_REG8(0x5606), 0x16 },
1145 { CCI_REG8(0x5607), 0x15 }, { CCI_REG8(0x5608), 0x1c },
1146 { CCI_REG8(0x5609), 0x1b }, { CCI_REG8(0x560a), 0x1a },
1147 { CCI_REG8(0x560b), 0x19 }, { CCI_REG8(0x560c), 0x20 },
1148 { CCI_REG8(0x560d), 0x1f }, { CCI_REG8(0x560e), 0x1e },
1149 { CCI_REG8(0x560f), 0x1d }, { CCI_REG8(0x5631), 0x02 },
1150 { CCI_REG8(0x5632), 0x42 }, { CCI_REG8(0x5633), 0x24 },
1151 { CCI_REG8(0x5653), 0x09 }, { CCI_REG8(0x5654), 0x00 },
1152 { CCI_REG8(0x5714), 0x03 }, { CCI_REG8(0x57b0), 0x10 },
1153 { CCI_REG8(0x57b3), 0x0e }, { CCI_REG8(0x57b5), 0x02 },
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1155 { CCI_REG8(0x57b8), 0x00 }, { CCI_REG8(0x57b9), 0x70 },
1156 { CCI_REG8(0x57ba), 0x00 }, { CCI_REG8(0x57bb), 0x10 },
1157 { CCI_REG8(0x57bc), 0x00 }, { CCI_REG8(0x57bd), 0x00 },
1158 { CCI_REG8(0x57d2), 0xff }, { CCI_REG8(0x57d3), 0x1c },
1159 { CCI_REG8(0x5810), 0x03 }, { CCI_REG8(0x5811), 0xe8 },
1160 { CCI_REG8(0x5850), 0x6c }, { CCI_REG8(0x5851), 0x00 },
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1162 { CCI_REG8(0x587c), 0x00 }, { CCI_REG8(0x587d), 0x4b },
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1164 { CCI_REG8(0x5892), 0x00 }, { CCI_REG8(0x5893), 0x50 },
1165 { CCI_REG8(0x5894), 0x00 }, { CCI_REG8(0x5895), 0x50 },
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1167 { CCI_REG8(0x5898), 0x00 }, { CCI_REG8(0x5899), 0x50 },
1168 { CCI_REG8(0x589a), 0x01 }, { CCI_REG8(0x589b), 0x00 },
1169 { CCI_REG8(0x589c), 0x01 }, { CCI_REG8(0x589d), 0x00 },
1170 { CCI_REG8(0x589e), 0x00 }, { CCI_REG8(0x589f), 0x50 },
1171 { CCI_REG8(0x58a0), 0x00 }, { CCI_REG8(0x58a1), 0x50 },
1172 { CCI_REG8(0x58a2), 0x01 }, { CCI_REG8(0x58a3), 0x00 },
1173 { CCI_REG8(0x58a4), 0x01 }, { CCI_REG8(0x58a5), 0x00 },
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1175 { CCI_REG8(0x58a8), 0x00 }, { CCI_REG8(0x58a9), 0x50 },
1176 { CCI_REG8(0x58aa), 0x00 }, { CCI_REG8(0x58ab), 0x50 },
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1399 { CCI_REG8(0x7707), 0x00 }, { CCI_REG8(0x7708), 0x00 },
1400 { CCI_REG8(0x7709), 0x00 }, { CCI_REG8(0x770a), 0x10 },
1401 { CCI_REG8(0x770b), 0x00 }, { CCI_REG8(0x770c), 0x00 },
1402 { CCI_REG8(0x770d), 0x00 }, { CCI_REG8(0x770e), 0x10 },
1403 { CCI_REG8(0x770f), 0x00 }, { CCI_REG8(0x7710), 0x00 },
1404 { CCI_REG8(0x7711), 0x00 }, { CCI_REG8(0x7712), 0x10 },
1405 { CCI_REG8(0x7713), 0x00 }, { CCI_REG8(0x7714), 0x00 },
1406 { CCI_REG8(0x7715), 0x00 }, { CCI_REG8(0x7716), 0x10 },
1407 { CCI_REG8(0x7717), 0x00 }, { CCI_REG8(0x7718), 0x00 },
1408 { CCI_REG8(0x7719), 0x00 }, { CCI_REG8(0x771a), 0x10 },
1409 { CCI_REG8(0x771b), 0x00 }, { CCI_REG8(0x771c), 0x00 },
1410 { CCI_REG8(0x771d), 0x00 }, { CCI_REG8(0x771e), 0x10 },
1411 { CCI_REG8(0x771f), 0x00 }, { CCI_REG8(0x7720), 0x00 },
1412 { CCI_REG8(0x7721), 0x00 }, { CCI_REG8(0x7722), 0x10 },
1413 { CCI_REG8(0x7723), 0x00 }, { CCI_REG8(0x7724), 0x00 },
1414 { CCI_REG8(0x7725), 0x00 }, { CCI_REG8(0x7726), 0x10 },
1415 { CCI_REG8(0x7727), 0x00 }, { CCI_REG8(0x7728), 0x00 },
1416 { CCI_REG8(0x7729), 0x00 }, { CCI_REG8(0x772a), 0x10 },
1417 { CCI_REG8(0x772b), 0x00 }, { CCI_REG8(0x772c), 0x00 },
1418 { CCI_REG8(0x772d), 0x00 }, { CCI_REG8(0x772e), 0x10 },
1419 { CCI_REG8(0x772f), 0x00 }, { CCI_REG8(0x7730), 0x00 },
1420 { CCI_REG8(0x7731), 0x00 }, { CCI_REG8(0x7732), 0x10 },
1421 { CCI_REG8(0x7733), 0x00 }, { CCI_REG8(0x7734), 0x00 },
1422 { CCI_REG8(0x7735), 0x00 }, { CCI_REG8(0x7736), 0x10 },
1423 { CCI_REG8(0x7737), 0x00 }, { CCI_REG8(0x7738), 0x00 },
1424 { CCI_REG8(0x7739), 0x00 }, { CCI_REG8(0x773a), 0x10 },
1425 { CCI_REG8(0x773b), 0x00 }, { CCI_REG8(0x773c), 0x00 },
1426 { CCI_REG8(0x773d), 0x00 }, { CCI_REG8(0x773e), 0x10 },
1427 { CCI_REG8(0x773f), 0x00 }, { CCI_REG8(0x7740), 0x00 },
1428 { CCI_REG8(0x7741), 0x00 }, { CCI_REG8(0x7742), 0x10 },
1429 { CCI_REG8(0x7743), 0x00 }, { CCI_REG8(0x3421), 0x02 },
1430 { CCI_REG8(0x37d0), 0x00 }, { CCI_REG8(0x3632), 0x99 },
1431 { CCI_REG8(0xc518), 0x1f }, { CCI_REG8(0xc519), 0x1f },
1432 { CCI_REG8(0xc51a), 0x1f }, { CCI_REG8(0xc51b), 0x1f },
1433 { CCI_REG8(0xc51c), 0x1f }, { CCI_REG8(0xc51d), 0x1f },
1434 { CCI_REG8(0xc51e), 0x1f }, { CCI_REG8(0xc51f), 0x1f },
1435 { CCI_REG8(0xc520), 0x1f }, { CCI_REG8(0xc521), 0x1f },
1436 { CCI_REG8(0x3616), 0xa0 }, { CCI_REG8(0x3615), 0xc5 },
1437 { CCI_REG8(0xc4c1), 0x02 }, { CCI_REG8(0xc4c2), 0x02 },
1438 { CCI_REG8(0xc4c3), 0x03 }, { CCI_REG8(0xc4c4), 0x03 },
1439 { CCI_REG8(0xc4f6), 0x0a }, { CCI_REG8(0xc4f7), 0x0a },
1440 { CCI_REG8(0xc4f8), 0x0a }, { CCI_REG8(0xc4f9), 0x0a },
1441 { CCI_REG8(0xc4fa), 0x0a }, { CCI_REG8(0xc4c6), 0x0a },
1442 { CCI_REG8(0xc4c7), 0x0a }, { CCI_REG8(0xc4c8), 0x0a },
1443 { CCI_REG8(0xc4c9), 0x0a }, { CCI_REG8(0xc4ca), 0x14 },
1444 { CCI_REG8(0xc4cb), 0x14 }, { CCI_REG8(0xc4cc), 0x14 },
1445 { CCI_REG8(0xc4cd), 0x14 }, { CCI_REG8(0x3b92), 0x05 },
1446 { CCI_REG8(0x3b93), 0x05 }, { CCI_REG8(0x3b94), 0x05 },
1447 { CCI_REG8(0x3b95), 0x05 }, { CCI_REG8(0x3623), 0x10 },
1448 { CCI_REG8(0xc522), 0x18 }, { CCI_REG8(0xc523), 0x12 },
1449 { CCI_REG8(0xc524), 0x0e }, { CCI_REG8(0xc525), 0x0b },
1450 { CCI_REG8(0xc526), 0x18 }, { CCI_REG8(0xc527), 0x12 },
1451 { CCI_REG8(0xc528), 0x0c }, { CCI_REG8(0xc529), 0x08 },
1452 { CCI_REG8(0xc52a), 0x18 }, { CCI_REG8(0xc52b), 0x12 },
1453 { CCI_REG8(0xc52c), 0x0e }, { CCI_REG8(0xc52d), 0x0b },
1454 { CCI_REG8(0xc52e), 0x18 }, { CCI_REG8(0xc52f), 0x12 },
1455 { CCI_REG8(0xc530), 0x0e }, { CCI_REG8(0xc531), 0x0b },
1456 { CCI_REG8(0xc532), 0x18 }, { CCI_REG8(0xc533), 0x12 },
1457 { CCI_REG8(0xc534), 0x0e }, { CCI_REG8(0xc535), 0x0b },
1458 { CCI_REG8(0xc536), 0x18 }, { CCI_REG8(0xc537), 0x12 },
1459 { CCI_REG8(0xc538), 0x0e }, { CCI_REG8(0xc539), 0x0b },
1460 { CCI_REG8(0xc53a), 0x18 }, { CCI_REG8(0xc53b), 0x12 },
1461 { CCI_REG8(0xc53c), 0x0c }, { CCI_REG8(0xc53d), 0x08 },
1462 { CCI_REG8(0xc53e), 0x18 }, { CCI_REG8(0xc53f), 0x12 },
1463 { CCI_REG8(0xc540), 0x0e }, { CCI_REG8(0xc541), 0x0b },
1464 { CCI_REG8(0xc542), 0x18 }, { CCI_REG8(0xc543), 0x12 },
1465 { CCI_REG8(0xc544), 0x0e }, { CCI_REG8(0xc545), 0x0b },
1466 { CCI_REG8(0xc546), 0x18 }, { CCI_REG8(0xc547), 0x12 },
1467 { CCI_REG8(0xc548), 0x0e }, { CCI_REG8(0xc549), 0x0b },
1468 { CCI_REG8(0x3701), 0x18 }, { CCI_REG8(0x3702), 0x38 },
1469 { CCI_REG8(0x3703), 0x72 }, { CCI_REG8(0x3708), 0x26 },
1470 { CCI_REG8(0x3709), 0xe6 }, { CCI_REG8(0x3a1d), 0x18 },
1471 { CCI_REG8(0x3a1e), 0x18 }, { CCI_REG8(0x3a21), 0x18 },
1472 { CCI_REG8(0x3a22), 0x18 }, { CCI_REG8(0x39fb), 0x18 },
1473 { CCI_REG8(0x39fc), 0x18 }, { CCI_REG8(0x39fd), 0x18 },
1474 { CCI_REG8(0x39fe), 0x18 }, { CCI_REG8(0xc44a), 0x08 },
1475 { CCI_REG8(0xc44c), 0x08 }, { CCI_REG8(0xc5e8), 0x0a },
1476 { CCI_REG8(0xc5ea), 0x0a }, { CCI_REG8(0x391d), 0x54 },
1477 { CCI_REG8(0x391e), 0xca }, { CCI_REG8(0x3991), 0x0c },
1478 { CCI_REG8(0x399d), 0x0c }, { CCI_REG8(0x3744), 0x24 },
1479 { CCI_REG8(0x374b), 0x0c }, { CCI_REG8(0x3be7), 0x1e },
1480 { CCI_REG8(0x3be8), 0x26 }, { CCI_REG8(0x3a50), 0x14 },
1481 { CCI_REG8(0x3a54), 0x14 }, { CCI_REG8(0x3add), 0x1f },
1482 { CCI_REG8(0x3adf), 0x24 }, { CCI_REG8(0x3aef), 0x1f },
1483 { CCI_REG8(0x3af0), 0x24 }, { CCI_REG8(0xc57f), 0x30 },
1484 { CCI_REG8(0xc580), 0x30 }, { CCI_REG8(0xc581), 0x30 },
1485 { CCI_REG8(0xc582), 0x30 }, { CCI_REG8(0xc583), 0x30 },
1486 { CCI_REG8(0xc584), 0x30 }, { CCI_REG8(0xc585), 0x30 },
1487 { CCI_REG8(0xc586), 0x30 }, { CCI_REG8(0xc587), 0x30 },
1488 { CCI_REG8(0xc588), 0x30 }, { CCI_REG8(0xc589), 0x30 },
1489 { CCI_REG8(0xc58a), 0x30 }, { CCI_REG8(0xc58b), 0x30 },
1490 { CCI_REG8(0xc58c), 0x30 }, { CCI_REG8(0xc58d), 0x30 },
1491 { CCI_REG8(0xc58e), 0x30 }, { CCI_REG8(0xc58f), 0x30 },
1492 { CCI_REG8(0xc590), 0x30 }, { CCI_REG8(0xc591), 0x30 },
1493 { CCI_REG8(0xc592), 0x30 }, { CCI_REG8(0xc598), 0x30 },
1494 { CCI_REG8(0xc599), 0x30 }, { CCI_REG8(0xc59a), 0x30 },
1495 { CCI_REG8(0xc59b), 0x30 }, { CCI_REG8(0xc59c), 0x30 },
1496 { CCI_REG8(0xc59d), 0x30 }, { CCI_REG8(0xc59e), 0x30 },
1497 { CCI_REG8(0xc59f), 0x30 }, { CCI_REG8(0xc5a0), 0x30 },
1498 { CCI_REG8(0xc5a1), 0x30 }, { CCI_REG8(0xc5a2), 0x30 },
1499 { CCI_REG8(0xc5a3), 0x30 }, { CCI_REG8(0xc5a4), 0x30 },
1500 { CCI_REG8(0xc5a5), 0x30 }, { CCI_REG8(0xc5a6), 0x30 },
1501 { CCI_REG8(0xc5a7), 0x30 }, { CCI_REG8(0xc5a8), 0x30 },
1502 { CCI_REG8(0xc5a9), 0x30 }, { CCI_REG8(0xc5aa), 0x30 },
1503 { CCI_REG8(0xc5ab), 0x30 }, { CCI_REG8(0xc5b1), 0x38 },
1504 { CCI_REG8(0xc5b2), 0x38 }, { CCI_REG8(0xc5b3), 0x38 },
1505 { CCI_REG8(0xc5b4), 0x38 }, { CCI_REG8(0xc5b5), 0x38 },
1506 { CCI_REG8(0xc5b6), 0x38 }, { CCI_REG8(0xc5b7), 0x38 },
1507 { CCI_REG8(0xc5b8), 0x38 }, { CCI_REG8(0xc5b9), 0x38 },
1508 { CCI_REG8(0xc5ba), 0x38 }, { CCI_REG8(0xc5bb), 0x38 },
1509 { CCI_REG8(0xc5bc), 0x38 }, { CCI_REG8(0xc5bd), 0x38 },
1510 { CCI_REG8(0xc5be), 0x38 }, { CCI_REG8(0xc5bf), 0x38 },
1511 { CCI_REG8(0xc5c0), 0x38 }, { CCI_REG8(0xc5c1), 0x38 },
1512 { CCI_REG8(0xc5c2), 0x38 }, { CCI_REG8(0xc5c3), 0x38 },
1513 { CCI_REG8(0xc5c4), 0x38 }, { CCI_REG8(0xc5ca), 0x38 },
1514 { CCI_REG8(0xc5cb), 0x38 }, { CCI_REG8(0xc5cc), 0x38 },
1515 { CCI_REG8(0xc5cd), 0x38 }, { CCI_REG8(0xc5ce), 0x38 },
1516 { CCI_REG8(0xc5cf), 0x38 }, { CCI_REG8(0xc5d0), 0x38 },
1517 { CCI_REG8(0xc5d1), 0x38 }, { CCI_REG8(0xc5d2), 0x38 },
1518 { CCI_REG8(0xc5d3), 0x38 }, { CCI_REG8(0xc5d4), 0x38 },
1519 { CCI_REG8(0xc5d5), 0x38 }, { CCI_REG8(0xc5d6), 0x38 },
1520 { CCI_REG8(0xc5d7), 0x38 }, { CCI_REG8(0xc5d8), 0x38 },
1521 { CCI_REG8(0xc5d9), 0x38 }, { CCI_REG8(0xc5da), 0x38 },
1522 { CCI_REG8(0xc5db), 0x38 }, { CCI_REG8(0xc5dc), 0x38 },
1523 { CCI_REG8(0xc5dd), 0x38 }, { CCI_REG8(0x3a60), 0x68 },
1524 { CCI_REG8(0x3a6f), 0x68 }, { CCI_REG8(0x3a5e), 0xdc },
1525 { CCI_REG8(0x3a6d), 0xdc }, { CCI_REG8(0x3aed), 0x6e },
1526 { CCI_REG8(0x3af1), 0x73 }, { CCI_REG8(0x3992), 0x02 },
1527 { CCI_REG8(0x399e), 0x02 }, { CCI_REG8(0x371d), 0x17 },
1528 { CCI_REG8(0x371f), 0x08 }, { CCI_REG8(0x3721), 0xc9 },
1529 { CCI_REG8(0x401e), 0x00 }, { CCI_REG8(0x401f), 0xf8 },
1530 { CCI_REG8(0x3642), 0x00 }, { CCI_REG8(0x3641), 0x7f },
1531 { CCI_REG8(0x3ac5), 0x0c }, { CCI_REG8(0x3ac6), 0x09 },
1532 { CCI_REG8(0x3ac7), 0x06 }, { CCI_REG8(0x3ac8), 0x02 },
1533 { CCI_REG8(0x3ac9), 0x0c }, { CCI_REG8(0x3aca), 0x09 },
1534 { CCI_REG8(0x3acb), 0x06 }, { CCI_REG8(0x3acc), 0x02 },
1535 { CCI_REG8(0x3acd), 0x0c }, { CCI_REG8(0x3ace), 0x09 },
1536 { CCI_REG8(0x3acf), 0x07 }, { CCI_REG8(0x3ad0), 0x04 },
1537 { CCI_REG8(0x3ad1), 0x0c }, { CCI_REG8(0x3ad2), 0x09 },
1538 { CCI_REG8(0x3ad3), 0x07 }, { CCI_REG8(0x3ad4), 0x04 },
1539 { CCI_REG8(0xc483), 0x0c }, { CCI_REG8(0xc484), 0x0c },
1540 { CCI_REG8(0xc485), 0x0c }, { CCI_REG8(0xc486), 0x0c },
1541 { CCI_REG8(0x3a2f), 0x0c }, { CCI_REG8(0x3a30), 0x09 },
1542 { CCI_REG8(0x3a31), 0x06 }, { CCI_REG8(0x3a32), 0x02 },
1543 { CCI_REG8(0x3a34), 0x0c }, { CCI_REG8(0x3a35), 0x09 },
1544 { CCI_REG8(0x3a36), 0x07 }, { CCI_REG8(0x3a37), 0x04 },
1545 { CCI_REG8(0x3a43), 0x0c }, { CCI_REG8(0x3a44), 0x09 },
1546 { CCI_REG8(0x3a45), 0x06 }, { CCI_REG8(0x3a46), 0x02 },
1547 { CCI_REG8(0x3a48), 0x0c }, { CCI_REG8(0x3a49), 0x09 },
1548 { CCI_REG8(0x3a4a), 0x07 }, { CCI_REG8(0x3a4b), 0x04 },
1549 { CCI_REG8(0xc487), 0x0c }, { CCI_REG8(0xc488), 0x0c },
1550 { CCI_REG8(0xc489), 0x0c }, { CCI_REG8(0xc48a), 0x0c },
1551 { CCI_REG8(0x3645), 0xbd }, { CCI_REG8(0x373f), 0x00 },
1552 { CCI_REG8(0x374f), 0x10 }, { CCI_REG8(0x3743), 0xc6 },
1553 { CCI_REG8(0x3717), 0x82 }, { CCI_REG8(0x3732), 0x07 },
1554 { CCI_REG8(0x3731), 0x16 }, { CCI_REG8(0x3730), 0x16 },
1555 { CCI_REG8(0x3828), 0x07 }, { CCI_REG8(0x3714), 0x68 },
1556 { CCI_REG8(0x371d), 0x02 }, { CCI_REG8(0x371f), 0x02 },
1557 { CCI_REG8(0x37e0), 0x00 }, { CCI_REG8(0x37e1), 0x03 },
1558 { CCI_REG8(0x37e2), 0x07 }, { CCI_REG8(0x3734), 0x3e },
1559 { CCI_REG8(0x3736), 0x02 }, { CCI_REG8(0x37e4), 0x36 },
1560 { CCI_REG8(0x37e9), 0x1c }, { CCI_REG8(0x37ea), 0x01 },
1561 { CCI_REG8(0x37eb), 0x0a }, { CCI_REG8(0x37ec), 0x1c },
1562 { CCI_REG8(0x37ed), 0x01 }, { CCI_REG8(0x37ee), 0x36 },
1563 { CCI_REG8(0x373b), 0x1c }, { CCI_REG8(0x373c), 0x02 },
1564 { CCI_REG8(0x37bb), 0x1c }, { CCI_REG8(0x37bc), 0x02 },
1565 { CCI_REG8(0x37b8), 0x0c }, { CCI_REG8(0x371c), 0x01 },
1566 { CCI_REG8(0x371e), 0x11 }, { CCI_REG8(0x371d), 0x01 },
1567 { CCI_REG8(0x371f), 0x01 }, { CCI_REG8(0x3721), 0x01 },
1568 { CCI_REG8(0x3725), 0x12 }, { CCI_REG8(0x37e3), 0x06 },
1569 { CCI_REG8(0x37dd), 0x86 }, { CCI_REG8(0x37db), 0x0a },
1570 { CCI_REG8(0x37dc), 0x14 }, { CCI_REG8(0x3727), 0x20 },
1571 { CCI_REG8(0x37b2), 0x80 }, { CCI_REG8(0x37da), 0x04 },
1572 { CCI_REG8(0x37df), 0x01 }, { CCI_REG8(0x3731), 0x11 },
1573 { CCI_REG8(0x37dd), 0x86 }, { CCI_REG8(0x37df), 0x01 },
1574 { CCI_REG8(0x37da), 0x03 }, { CCI_REG8(0x37b2), 0x80 },
1575 { CCI_REG8(0x3727), 0x20 }, { CCI_REG8(0x4883), 0x26 },
1576 { CCI_REG8(0x488b), 0x88 }, { CCI_REG8(0x3d85), 0x1f },
1577 { CCI_REG8(0x3d81), 0x01 }, { CCI_REG8(0x3d84), 0x40 },
1578 { CCI_REG8(0x3d88), 0x00 }, { CCI_REG8(0x3d89), 0x00 },
1579 { CCI_REG8(0x3d8a), 0x0b }, { CCI_REG8(0x3d8b), 0xff },
1580 { CCI_REG8(0x4d00), 0x05 }, { CCI_REG8(0x4d01), 0xc4 },
1581 { CCI_REG8(0x4d02), 0xa3 }, { CCI_REG8(0x4d03), 0x8c },
1582 { CCI_REG8(0x4d04), 0xfb }, { CCI_REG8(0x4d05), 0xed },
1583 { CCI_REG8(0x4010), 0x28 }, { CCI_REG8(0x4030), 0x00 },
1584 { CCI_REG8(0x4031), 0x00 }, { CCI_REG8(0x4032), 0x00 },
1585 { CCI_REG8(0x4033), 0x00 }, { CCI_REG8(0x4034), 0x00 },
1586 { CCI_REG8(0x4035), 0x00 }, { CCI_REG8(0x4036), 0x00 },
1587 { CCI_REG8(0x4037), 0x00 }, { CCI_REG8(0x4040), 0x00 },
1588 { CCI_REG8(0x4041), 0x00 }, { CCI_REG8(0x4042), 0x00 },
1589 { CCI_REG8(0x4043), 0x00 }, { CCI_REG8(0x4044), 0x00 },
1590 { CCI_REG8(0x4045), 0x00 }, { CCI_REG8(0x4046), 0x00 },
1591 { CCI_REG8(0x4047), 0x00 }, { CCI_REG8(0x3400), 0x00 },
1592 { CCI_REG8(0x3421), 0x23 }, { CCI_REG8(0x3422), 0xfc },
1593 { CCI_REG8(0x3423), 0x07 }, { CCI_REG8(0x3424), 0x01 },
1594 { CCI_REG8(0x3425), 0x04 }, { CCI_REG8(0x3426), 0x50 },
1595 { CCI_REG8(0x3427), 0x55 }, { CCI_REG8(0x3428), 0x15 },
1596 { CCI_REG8(0x3429), 0x00 }, { CCI_REG8(0x3025), 0x03 },
1597 { CCI_REG8(0x3053), 0x00 }, { CCI_REG8(0x3054), 0x00 },
1598 { CCI_REG8(0x3055), 0x00 }, { CCI_REG8(0x3056), 0x00 },
1599 { CCI_REG8(0x3057), 0x00 }, { CCI_REG8(0x3058), 0x00 },
1600 { CCI_REG8(0x305c), 0x00 }, { CCI_REG8(0x340c), 0x1f },
1601 { CCI_REG8(0x340d), 0x00 }, { CCI_REG8(0x3501), 0x01 },
1602 { CCI_REG8(0x3542), 0x48 }, { CCI_REG8(0x3582), 0x24 },
1603 { CCI_REG8(0x3015), 0xf1 }, { CCI_REG8(0x3018), 0xf2 },
1604 { CCI_REG8(0x301c), 0xf2 }, { CCI_REG8(0x301d), 0xf6 },
1605 { CCI_REG8(0x301e), 0xf1 }, { CCI_REG8(0x0100), 0x01 },
1606 { CCI_REG8(0xfff9), 0x08 }, { CCI_REG8(0x3900), 0xcd },
1607 { CCI_REG8(0x3901), 0xcd }, { CCI_REG8(0x3902), 0xcd },
1608 { CCI_REG8(0x3903), 0xcd }, { CCI_REG8(0x3904), 0xcd },
1609 { CCI_REG8(0x3905), 0xcd }, { CCI_REG8(0x3906), 0xcd },
1610 { CCI_REG8(0x3907), 0xcd }, { CCI_REG8(0x3908), 0xcd },
1611 { CCI_REG8(0x3909), 0xcd }, { CCI_REG8(0x390a), 0xcd },
1612 { CCI_REG8(0x390b), 0xcd }, { CCI_REG8(0x390c), 0xcd },
1613 { CCI_REG8(0x390d), 0xcd }, { CCI_REG8(0x390e), 0xcd },
1614 { CCI_REG8(0x390f), 0xcd }, { CCI_REG8(0x3910), 0xcd },
1615 { CCI_REG8(0x3911), 0xcd }, { CCI_REG8(0x3912), 0xcd },
1616 { CCI_REG8(0x3913), 0xcd }, { CCI_REG8(0x3914), 0xcd },
1617 { CCI_REG8(0x3915), 0xcd }, { CCI_REG8(0x3916), 0xcd },
1618 { CCI_REG8(0x3917), 0xcd }, { CCI_REG8(0x3918), 0xcd },
1619 { CCI_REG8(0x3919), 0xcd }, { CCI_REG8(0x391a), 0xcd },
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1834 { CCI_REG8(0x3ac7), 0x40 }, { CCI_REG8(0x3ac8), 0x40 },
1835 { CCI_REG8(0x3ac9), 0x40 }, { CCI_REG8(0x3aca), 0x40 },
1836 { CCI_REG8(0x3acb), 0x40 }, { CCI_REG8(0x3acc), 0x40 },
1837 { CCI_REG8(0x3acd), 0x40 }, { CCI_REG8(0x3ace), 0x40 },
1838 { CCI_REG8(0x3acf), 0x40 }, { CCI_REG8(0x3ad0), 0x40 },
1839 { CCI_REG8(0x3ad1), 0x40 }, { CCI_REG8(0x3ad2), 0x40 },
1840 { CCI_REG8(0x3ad3), 0x40 }, { CCI_REG8(0x3ad4), 0x40 },
1841 { CCI_REG8(0x3ad5), 0x40 }, { CCI_REG8(0x3ad6), 0x40 },
1842 { CCI_REG8(0x3ad7), 0x40 }, { CCI_REG8(0x3ad8), 0x40 },
1843 { CCI_REG8(0x3ad9), 0x40 }, { CCI_REG8(0x3ada), 0x40 },
1844 { CCI_REG8(0x3adb), 0x40 }, { CCI_REG8(0x3adc), 0x40 },
1845 { CCI_REG8(0x3add), 0x40 }, { CCI_REG8(0x3ade), 0x40 },
1846 { CCI_REG8(0x3adf), 0x40 }, { CCI_REG8(0x3ae0), 0x40 },
1847 { CCI_REG8(0x3ae1), 0x40 }, { CCI_REG8(0x3ae2), 0x40 },
1848 { CCI_REG8(0x3ae3), 0x40 }, { CCI_REG8(0x3ae4), 0x40 },
1849 { CCI_REG8(0x3ae5), 0x40 }, { CCI_REG8(0x3ae6), 0x40 },
1850 { CCI_REG8(0x3ae7), 0x40 }, { CCI_REG8(0x3ae8), 0x40 },
1851 { CCI_REG8(0x3ae9), 0x40 }, { CCI_REG8(0x3aea), 0x40 },
1852 { CCI_REG8(0x3aeb), 0x40 }, { CCI_REG8(0x3aec), 0x40 },
1853 { CCI_REG8(0x3aed), 0x40 }, { CCI_REG8(0x3aee), 0x40 },
1854 { CCI_REG8(0x3aef), 0xcd }, { CCI_REG8(0x3af0), 0xcd },
1855 { CCI_REG8(0x3af1), 0xcd }, { CCI_REG8(0x3af2), 0xcd },
1856 { CCI_REG8(0x3af3), 0xcd }, { CCI_REG8(0x3af4), 0xcd },
1857 { CCI_REG8(0x3af5), 0xcd }, { CCI_REG8(0x3af6), 0xcd },
1858 { CCI_REG8(0x3af7), 0xcd }, { CCI_REG8(0x3af8), 0xcd },
1859 { CCI_REG8(0x3af9), 0xcd }, { CCI_REG8(0x3afa), 0xcd },
1860 { CCI_REG8(0x3afb), 0xcd }, { CCI_REG8(0x3afc), 0xcd },
1861 { CCI_REG8(0x3afd), 0xcd }, { CCI_REG8(0x3afe), 0xcd },
1862 { CCI_REG8(0x3aff), 0xcd }, { CCI_REG8(0x3b00), 0xcd },
1863 { CCI_REG8(0x3b01), 0xcd }, { CCI_REG8(0x3b02), 0xcd },
1864 { CCI_REG8(0x3b03), 0xcd }, { CCI_REG8(0x3b04), 0xcd },
1865 { CCI_REG8(0x3b05), 0xcd }, { CCI_REG8(0x3b06), 0xcd },
1866 { CCI_REG8(0x3b07), 0xcd }, { CCI_REG8(0x3b08), 0xcd },
1867 { CCI_REG8(0x3b09), 0xcd }, { CCI_REG8(0x3b0a), 0xcd },
1868 { CCI_REG8(0x3b0b), 0xcd }, { CCI_REG8(0x3b0c), 0xcd },
1869 { CCI_REG8(0x3b0d), 0xcd }, { CCI_REG8(0x3b0e), 0xcd },
1870 { CCI_REG8(0x3b0f), 0xcd }, { CCI_REG8(0x3b10), 0xcd },
1871 { CCI_REG8(0x3b11), 0xcd }, { CCI_REG8(0x3b12), 0xcd },
1872 { CCI_REG8(0x3b13), 0xcd }, { CCI_REG8(0x3b14), 0xcd },
1873 { CCI_REG8(0x3b15), 0xcd }, { CCI_REG8(0x3b16), 0xcd },
1874 { CCI_REG8(0x3b17), 0xcd }, { CCI_REG8(0x3b18), 0xcd },
1875 { CCI_REG8(0x3b19), 0xcd }, { CCI_REG8(0x3b1a), 0xcd },
1876 { CCI_REG8(0x3b1b), 0xcd }, { CCI_REG8(0x3b1c), 0xcd },
1877 { CCI_REG8(0x3b1d), 0xcd }, { CCI_REG8(0x3b1e), 0xcd },
1878 { CCI_REG8(0x3b1f), 0xcd }, { CCI_REG8(0x3b20), 0xcd },
1879 { CCI_REG8(0x3b21), 0xcd }, { CCI_REG8(0x3b22), 0xcd },
1880 { CCI_REG8(0x3b23), 0xcd }, { CCI_REG8(0x3b24), 0xcd },
1881 { CCI_REG8(0x3b25), 0xcd }, { CCI_REG8(0x3b26), 0xcd },
1882 { CCI_REG8(0x3b27), 0xcd }, { CCI_REG8(0x3b28), 0xcd },
1883 { CCI_REG8(0x3b29), 0xcd }, { CCI_REG8(0x3b2a), 0xcd },
1884 { CCI_REG8(0x3b2b), 0xcd }, { CCI_REG8(0x3b2c), 0xcd },
1885 { CCI_REG8(0x3b2d), 0xcd }, { CCI_REG8(0x3b2e), 0xcd },
1886 { CCI_REG8(0x3b2f), 0xcd }, { CCI_REG8(0x3b30), 0xcd },
1887 { CCI_REG8(0x3b31), 0xcd }, { CCI_REG8(0x3b32), 0xcd },
1888 { CCI_REG8(0x3b33), 0xcd }, { CCI_REG8(0x3b34), 0xcd },
1889 { CCI_REG8(0x3b35), 0xcd }, { CCI_REG8(0x3b36), 0xcd },
1890 { CCI_REG8(0x3b37), 0xcd }, { CCI_REG8(0x3b38), 0xcd },
1891 { CCI_REG8(0x3b39), 0xcd }, { CCI_REG8(0x3b3a), 0xcd },
1892 { CCI_REG8(0x3b3b), 0xcd }, { CCI_REG8(0x3b3c), 0xcd },
1893 { CCI_REG8(0x3b3d), 0xcd }, { CCI_REG8(0x3b3e), 0xcd },
1894 { CCI_REG8(0x3b3f), 0xcd }, { CCI_REG8(0x3b40), 0xcd },
1895 { CCI_REG8(0x3b41), 0xcd }, { CCI_REG8(0x3b42), 0xcd },
1896 { CCI_REG8(0x3b43), 0xcd }, { CCI_REG8(0x3b44), 0xcd },
1897 { CCI_REG8(0x3b45), 0xcd }, { CCI_REG8(0x3b46), 0xcd },
1898 { CCI_REG8(0x3b47), 0xcd }, { CCI_REG8(0x3b48), 0xcd },
1899 { CCI_REG8(0x3b49), 0xcd }, { CCI_REG8(0x3b4a), 0xcd },
1900 { CCI_REG8(0x3b4b), 0xcd }, { CCI_REG8(0x3b4c), 0xcd },
1901 { CCI_REG8(0x3b4d), 0xcd }, { CCI_REG8(0x3b4e), 0xcd },
1902 { CCI_REG8(0x3b4f), 0xcd }, { CCI_REG8(0x3b50), 0xcd },
1903 { CCI_REG8(0x3b51), 0xcd }, { CCI_REG8(0x3b52), 0xcd },
1904 { CCI_REG8(0x3b53), 0xcd }, { CCI_REG8(0x3b54), 0xcd },
1905 { CCI_REG8(0x3b55), 0xcd }, { CCI_REG8(0x3b56), 0xcd },
1906 { CCI_REG8(0x3b57), 0xcd }, { CCI_REG8(0x3b58), 0xcd },
1907 { CCI_REG8(0x3b59), 0xcd }, { CCI_REG8(0x3b5a), 0xcd },
1908 { CCI_REG8(0x3b5b), 0xcd }, { CCI_REG8(0x3b5c), 0xcd },
1909 { CCI_REG8(0x3b5d), 0xcd }, { CCI_REG8(0x3b5e), 0xcd },
1910 { CCI_REG8(0x3b5f), 0xcd }, { CCI_REG8(0x3b60), 0xcd },
1911 { CCI_REG8(0x3b61), 0xcd }, { CCI_REG8(0x3b62), 0xcd },
1912 { CCI_REG8(0x3b63), 0xcd }, { CCI_REG8(0x3b64), 0xcd },
1913 { CCI_REG8(0x3b65), 0xcd }, { CCI_REG8(0x3b66), 0xcd },
1914 { CCI_REG8(0x3b67), 0xcd }, { CCI_REG8(0x3b68), 0xcd },
1915 { CCI_REG8(0x3b69), 0xcd }, { CCI_REG8(0x3b6a), 0xcd },
1916 { CCI_REG8(0x3b6b), 0xcd }, { CCI_REG8(0x3b6c), 0xcd },
1917 { CCI_REG8(0x3b6d), 0xcd }, { CCI_REG8(0x3b6e), 0xcd },
1918 { CCI_REG8(0x3b6f), 0xcd }, { CCI_REG8(0x3b70), 0xcd },
1919 { CCI_REG8(0x3b71), 0xcd }, { CCI_REG8(0x3b72), 0xcd },
1920 { CCI_REG8(0x3b73), 0xcd }, { CCI_REG8(0x3b74), 0xcd },
1921 { CCI_REG8(0x3b75), 0xcd }, { CCI_REG8(0x3b76), 0xcd },
1922 { CCI_REG8(0x3b77), 0xcd }, { CCI_REG8(0x3b78), 0xcd },
1923 { CCI_REG8(0x3b79), 0xcd }, { CCI_REG8(0x3b7a), 0xcd },
1924 { CCI_REG8(0x3b7b), 0xcd }, { CCI_REG8(0x3b7c), 0xcd },
1925 { CCI_REG8(0x3b7d), 0xcd }, { CCI_REG8(0x3b7e), 0xcd },
1926 { CCI_REG8(0x3b7f), 0xcd }, { CCI_REG8(0x3b80), 0xcd },
1927 { CCI_REG8(0x3b81), 0xcd }, { CCI_REG8(0x3b82), 0xcd },
1928 { CCI_REG8(0x3b83), 0xcd }, { CCI_REG8(0x3b84), 0xcd },
1929 { CCI_REG8(0x3b85), 0xcd }, { CCI_REG8(0x3b86), 0xcd },
1930 { CCI_REG8(0x3b87), 0xcd }, { CCI_REG8(0x3b88), 0xcd },
1931 { CCI_REG8(0x3b89), 0xcd }, { CCI_REG8(0x3b8a), 0xcd },
1932 { CCI_REG8(0x3b8b), 0xcd }, { CCI_REG8(0x3b8c), 0xcd },
1933 { CCI_REG8(0x3b8d), 0xcd }, { CCI_REG8(0x3b8e), 0xcd },
1934 { CCI_REG8(0x3b8f), 0xcd }, { CCI_REG8(0x3b90), 0xcd },
1935 { CCI_REG8(0x3b91), 0xcd }, { CCI_REG8(0x3b92), 0xcd },
1936 { CCI_REG8(0x3b93), 0xcd }, { CCI_REG8(0x3b94), 0xcd },
1937 { CCI_REG8(0x3b95), 0xcd }, { CCI_REG8(0x3b96), 0xcd },
1938 { CCI_REG8(0x3b97), 0xcd }, { CCI_REG8(0x3b98), 0xcd },
1939 { CCI_REG8(0x3b99), 0xcd }, { CCI_REG8(0x3b9a), 0xcd },
1940 { CCI_REG8(0x3b9b), 0xcd }, { CCI_REG8(0x3b9c), 0xcd },
1941 { CCI_REG8(0x3b9d), 0xcd }, { CCI_REG8(0x3b9e), 0xcd },
1942 { CCI_REG8(0x3b9f), 0xcd }, { CCI_REG8(0x3ba0), 0xcd },
1943 { CCI_REG8(0x3ba1), 0xcd }, { CCI_REG8(0x3ba2), 0xcd },
1944 { CCI_REG8(0x3ba3), 0xcd }, { CCI_REG8(0x3ba4), 0xcd },
1945 { CCI_REG8(0x3ba5), 0xcd }, { CCI_REG8(0x3ba6), 0xcd },
1946 { CCI_REG8(0x3ba7), 0xcd }, { CCI_REG8(0x3ba8), 0xcd },
1947 { CCI_REG8(0x3ba9), 0xcd }, { CCI_REG8(0x3baa), 0xcd },
1948 { CCI_REG8(0x3bab), 0xcd }, { CCI_REG8(0x3bac), 0xcd },
1949 { CCI_REG8(0x3bad), 0xcd }, { CCI_REG8(0x3bae), 0xcd },
1950 { CCI_REG8(0x3baf), 0xcd }, { CCI_REG8(0x3bb0), 0xcd },
1951 { CCI_REG8(0x3bb1), 0xcd }, { CCI_REG8(0x3bb2), 0xcd },
1952 { CCI_REG8(0x3bb3), 0xcd }, { CCI_REG8(0x3bb4), 0xcd },
1953 { CCI_REG8(0x3bb5), 0xcd }, { CCI_REG8(0x3bb6), 0xcd },
1954 { CCI_REG8(0x3bb7), 0xcd }, { CCI_REG8(0x3bb8), 0xcd },
1955 { CCI_REG8(0x3bb9), 0xcd }, { CCI_REG8(0x3bba), 0xcd },
1956 { CCI_REG8(0x3bbb), 0xcd }, { CCI_REG8(0x3bbc), 0xcd },
1957 { CCI_REG8(0x3bbd), 0xcd }, { CCI_REG8(0x3bbe), 0xcd },
1958 { CCI_REG8(0x3bbf), 0xcd }, { CCI_REG8(0x3bc0), 0xcd },
1959 { CCI_REG8(0x3bc1), 0xcd }, { CCI_REG8(0x3bc2), 0xcd },
1960 { CCI_REG8(0x3bc3), 0xcd }, { CCI_REG8(0x3bc4), 0xcd },
1961 { CCI_REG8(0x3bc5), 0xcd }, { CCI_REG8(0x3bc6), 0xcd },
1962 { CCI_REG8(0x3bc7), 0xcd }, { CCI_REG8(0x3bc8), 0xcd },
1963 { CCI_REG8(0x3bc9), 0xcd }, { CCI_REG8(0x3bca), 0xcd },
1964 { CCI_REG8(0x3bcb), 0xcd }, { CCI_REG8(0x3bcc), 0xcd },
1965 { CCI_REG8(0x3bcd), 0xcd }, { CCI_REG8(0x3bce), 0xcd },
1966 { CCI_REG8(0x3bcf), 0xcd }, { CCI_REG8(0x3bd0), 0xcd },
1967 { CCI_REG8(0x3bd1), 0xcd }, { CCI_REG8(0x3bd2), 0xcd },
1968 { CCI_REG8(0x3bd3), 0xcd }, { CCI_REG8(0x3bd4), 0xcd },
1969 { CCI_REG8(0x3bd5), 0xcd }, { CCI_REG8(0x3bd6), 0xcd },
1970 { CCI_REG8(0x3bd7), 0xcd }, { CCI_REG8(0x3bd8), 0xcd },
1971 { CCI_REG8(0x3bd9), 0xcd }, { CCI_REG8(0x3bda), 0xcd },
1972 { CCI_REG8(0x3bdb), 0xcd }, { CCI_REG8(0x3bdc), 0xcd },
1973 { CCI_REG8(0x3bdd), 0xcd }, { CCI_REG8(0x3bde), 0xcd },
1974 { CCI_REG8(0x3bdf), 0xcd }, { CCI_REG8(0x3be0), 0xcd },
1975 { CCI_REG8(0x3be1), 0xcd }, { CCI_REG8(0x3be2), 0xcd },
1976 { CCI_REG8(0x3be3), 0xcd }, { CCI_REG8(0x3be4), 0xcd },
1977 { CCI_REG8(0x3be5), 0xcd }, { CCI_REG8(0x3be6), 0xcd },
1978 { CCI_REG8(0x3be7), 0xcd }, { CCI_REG8(0x3be8), 0xcd },
1979 { CCI_REG8(0x3be9), 0xcd }, { CCI_REG8(0x3bea), 0xcd },
1980 { CCI_REG8(0x3beb), 0xcd }, { CCI_REG8(0x3bec), 0xcd },
1981 { CCI_REG8(0x3bed), 0xcd }, { CCI_REG8(0x3bee), 0xcd },
1982 { CCI_REG8(0x3bef), 0xcd }, { CCI_REG8(0x3bf0), 0xcd },
1983 { CCI_REG8(0x3bf1), 0xcd }, { CCI_REG8(0x3bf2), 0xcd },
1984 { CCI_REG8(0x3bf3), 0xcd }, { CCI_REG8(0x3bf4), 0xcd },
1985 { CCI_REG8(0x3bf5), 0xcd }, { CCI_REG8(0x3bf6), 0xcd },
1986 { CCI_REG8(0x3bf7), 0xcd }, { CCI_REG8(0x3bf8), 0xcd },
1987 { CCI_REG8(0x3bf9), 0xcd }, { CCI_REG8(0x3bfa), 0xcd },
1988 { CCI_REG8(0x3bfb), 0xcd }, { CCI_REG8(0x3bfc), 0xcd },
1989 { CCI_REG8(0x3bfd), 0xcd }, { CCI_REG8(0x3bfe), 0xcd },
1990 { CCI_REG8(0x3bff), 0xcd }, { CCI_REG8(0x3c00), 0xcd },
1991 { CCI_REG8(0x3c01), 0xcd }, { CCI_REG8(0x3c02), 0xcd },
1992 { CCI_REG8(0x3c03), 0xcd }, { CCI_REG8(0x3c04), 0xcd },
1993 { CCI_REG8(0x3c05), 0xcd }, { CCI_REG8(0x3c06), 0xcd },
1994 { CCI_REG8(0x3c07), 0xcd }, { CCI_REG8(0x3c08), 0xcd },
1995 { CCI_REG8(0x3c09), 0xcd }, { CCI_REG8(0x3c0a), 0xcd },
1996 { CCI_REG8(0x3c0b), 0xcd }, { CCI_REG8(0x3c0c), 0xcd },
1997 { CCI_REG8(0x3c0d), 0xcd }, { CCI_REG8(0x3c0e), 0xcd },
1998 { CCI_REG8(0x3c0f), 0xcd }, { CCI_REG8(0x3c10), 0xcd },
1999 { CCI_REG8(0x3c11), 0xcd }, { CCI_REG8(0x3c12), 0xcd },
2000 { CCI_REG8(0x3c13), 0xcd }, { CCI_REG8(0x3c14), 0xcd },
2001 { CCI_REG8(0x3c15), 0xcd }, { CCI_REG8(0x3c16), 0xcd },
2002 { CCI_REG8(0x3c17), 0xcd }, { CCI_REG8(0x3c18), 0xcd },
2003 { CCI_REG8(0x3c19), 0xcd }, { CCI_REG8(0x3c1a), 0xcd },
2004 { CCI_REG8(0x3c1b), 0xcd }, { CCI_REG8(0x3c1c), 0xcd },
2005 { CCI_REG8(0x3c1d), 0xcd }, { CCI_REG8(0x3c1e), 0xcd },
2006 { CCI_REG8(0x3c1f), 0xcd }, { CCI_REG8(0x3c20), 0xcd },
2007 { CCI_REG8(0x3c21), 0xcd }, { CCI_REG8(0x3c22), 0xcd },
2008 { CCI_REG8(0x3c23), 0xcd }, { CCI_REG8(0x3c24), 0xcd },
2009 { CCI_REG8(0x3c25), 0xcd }, { CCI_REG8(0x3c26), 0xcd },
2010 { CCI_REG8(0x3c27), 0xcd }, { CCI_REG8(0x3c28), 0xcd },
2011 { CCI_REG8(0x3c29), 0xcd }, { CCI_REG8(0x3c2a), 0xcd },
2012 { CCI_REG8(0x3c2b), 0xcd }, { CCI_REG8(0x3c2c), 0xcd },
2013 { CCI_REG8(0x3c2d), 0xcd }, { CCI_REG8(0x3c2e), 0xcd },
2014 { CCI_REG8(0x3c2f), 0xcd }, { CCI_REG8(0x3c30), 0xcd },
2015 { CCI_REG8(0x3c31), 0xcd }, { CCI_REG8(0x3c32), 0xcd },
2016 { CCI_REG8(0x3c33), 0xcd }, { CCI_REG8(0x3c34), 0xcd },
2017 { CCI_REG8(0x3c35), 0xcd }, { CCI_REG8(0x3c36), 0xcd },
2018 { CCI_REG8(0x3c37), 0xcd }, { CCI_REG8(0x3c38), 0xcd },
2019 { CCI_REG8(0x3c39), 0xcd }, { CCI_REG8(0x3c3a), 0xcd },
2020 { CCI_REG8(0x3c3b), 0xcd }, { CCI_REG8(0x3c3c), 0xcd },
2021 { CCI_REG8(0x3c3d), 0xcd }, { CCI_REG8(0x3c3e), 0xcd },
2022 { CCI_REG8(0x3c3f), 0xcd }, { CCI_REG8(0x3c40), 0xcd },
2023 { CCI_REG8(0x3c41), 0xcd }, { CCI_REG8(0x3c42), 0xcd },
2024 { CCI_REG8(0x3c43), 0xcd }, { CCI_REG8(0x3c44), 0xcd },
2025 { CCI_REG8(0x3c45), 0xcd }, { CCI_REG8(0x3c46), 0xcd },
2026 { CCI_REG8(0x3c47), 0xcd }, { CCI_REG8(0x3c48), 0xcd },
2027 { CCI_REG8(0x3c49), 0xcd }, { CCI_REG8(0x3c4a), 0xcd },
2028 { CCI_REG8(0x3c4b), 0xcd }, { CCI_REG8(0x3c4c), 0xcd },
2029 { CCI_REG8(0x3c4d), 0xcd }, { CCI_REG8(0x3c4e), 0xcd },
2030 { CCI_REG8(0x3c4f), 0xcd }, { CCI_REG8(0x3c50), 0xcd },
2031 { CCI_REG8(0x3c51), 0xcd }, { CCI_REG8(0x3c52), 0xcd },
2032 { CCI_REG8(0x3c53), 0xcd }, { CCI_REG8(0x3c54), 0xcd },
2033 { CCI_REG8(0x3c55), 0xcd }, { CCI_REG8(0x3c56), 0xcd },
2034 { CCI_REG8(0x3c57), 0xcd }, { CCI_REG8(0x3c58), 0xcd },
2035 { CCI_REG8(0x3c59), 0xcd }, { CCI_REG8(0x3c5a), 0xcd },
2036 { CCI_REG8(0x3c5b), 0xcd }, { CCI_REG8(0x3c5c), 0xcd },
2037 { CCI_REG8(0x3c5d), 0xcd }, { CCI_REG8(0x3c5e), 0xcd },
2038 { CCI_REG8(0x3c5f), 0xcd }, { CCI_REG8(0x3c60), 0xcd },
2039 { CCI_REG8(0x3c61), 0xcd }, { CCI_REG8(0x3c62), 0xcd },
2040 { CCI_REG8(0x3c63), 0xcd }, { CCI_REG8(0x3c64), 0xcd },
2041 { CCI_REG8(0x3c65), 0xcd }, { CCI_REG8(0x3c66), 0xcd },
2042 { CCI_REG8(0x3c67), 0xcd }, { CCI_REG8(0x3c68), 0xcd },
2043 { CCI_REG8(0x3c69), 0xcd }, { CCI_REG8(0x3c6a), 0xcd },
2044 { CCI_REG8(0x3c6b), 0xcd }, { CCI_REG8(0x3c6c), 0xcd },
2045 { CCI_REG8(0x3c6d), 0xcd }, { CCI_REG8(0x3c6e), 0xcd },
2046 { CCI_REG8(0x3c6f), 0xcd }, { CCI_REG8(0x3c70), 0xcd },
2047 { CCI_REG8(0x3c71), 0xcd }, { CCI_REG8(0x3c72), 0xcd },
2048 { CCI_REG8(0x3c73), 0xcd }, { CCI_REG8(0x3c74), 0xcd },
2049 { CCI_REG8(0x3c75), 0xcd }, { CCI_REG8(0x3c76), 0xcd },
2050 { CCI_REG8(0x3c77), 0xcd }, { CCI_REG8(0x3c78), 0xcd },
2051 { CCI_REG8(0x3c79), 0xcd }, { CCI_REG8(0x3c7a), 0xcd },
2052 { CCI_REG8(0x3c7b), 0xcd }, { CCI_REG8(0x3c7c), 0xcd },
2053 { CCI_REG8(0x3c7d), 0xcd }, { CCI_REG8(0x3c7e), 0xcd },
2054 { CCI_REG8(0x3c7f), 0xcd }, { CCI_REG8(0x3c80), 0xcd },
2055 { CCI_REG8(0x3c81), 0xcd }, { CCI_REG8(0x3c82), 0xcd },
2056 { CCI_REG8(0x3c83), 0xcd }, { CCI_REG8(0x3c84), 0xcd },
2057 { CCI_REG8(0x3c85), 0xcd }, { CCI_REG8(0x3c86), 0xcd },
2058 { CCI_REG8(0x3c87), 0xcd }, { CCI_REG8(0x3c88), 0xcd },
2059 { CCI_REG8(0x3c89), 0xcd }, { CCI_REG8(0x3c8a), 0xcd },
2060 { CCI_REG8(0x3c8b), 0xcd }, { CCI_REG8(0x3c8c), 0xcd },
2061 { CCI_REG8(0x3c8d), 0xcd }, { CCI_REG8(0x3c8e), 0xcd },
2062 { CCI_REG8(0x3c8f), 0xcd }, { CCI_REG8(0x3c90), 0xcd },
2063 { CCI_REG8(0x3c91), 0xcd }, { CCI_REG8(0x3c92), 0xcd },
2064 { CCI_REG8(0x3c93), 0xcd }, { CCI_REG8(0x3c94), 0xcd },
2065 { CCI_REG8(0x3c95), 0xcd }, { CCI_REG8(0x3c96), 0xcd },
2066 { CCI_REG8(0x3c97), 0xcd }, { CCI_REG8(0x3c98), 0xcd },
2067 { CCI_REG8(0x3c99), 0xcd }, { CCI_REG8(0x3c9a), 0xcd },
2068 { CCI_REG8(0x3c9b), 0xcd }, { CCI_REG8(0x3c9c), 0xcd },
2069 { CCI_REG8(0x3c9d), 0xcd }, { CCI_REG8(0x3c9e), 0xcd },
2070 { CCI_REG8(0x3c9f), 0xcd }, { CCI_REG8(0x3ca0), 0xcd },
2071 { CCI_REG8(0x3ca1), 0xcd }, { CCI_REG8(0x3ca2), 0xcd },
2072 { CCI_REG8(0x3ca3), 0xcd }, { CCI_REG8(0x3ca4), 0xcd },
2073 { CCI_REG8(0x3ca5), 0xcd }, { CCI_REG8(0x3ca6), 0xcd },
2074 { CCI_REG8(0x3ca7), 0xcd }, { CCI_REG8(0x3ca8), 0xcd },
2075 { CCI_REG8(0x3ca9), 0xcd }, { CCI_REG8(0x3caa), 0xcd },
2076 { CCI_REG8(0x3cab), 0xcd }, { CCI_REG8(0x3cac), 0xcd },
2077 { CCI_REG8(0x3cad), 0xcd }, { CCI_REG8(0x3cae), 0xcd },
2078 { CCI_REG8(0x3caf), 0xcd }, { CCI_REG8(0x3cb0), 0xcd },
2079 { CCI_REG8(0x3cb1), 0x40 }, { CCI_REG8(0x3cb2), 0x40 },
2080 { CCI_REG8(0x3cb3), 0x40 }, { CCI_REG8(0x3cb4), 0x40 },
2081 { CCI_REG8(0x3cb5), 0x40 }, { CCI_REG8(0x3cb6), 0x40 },
2082 { CCI_REG8(0x3cb7), 0x40 }, { CCI_REG8(0x3cb8), 0x40 },
2083 { CCI_REG8(0x3cb9), 0x40 }, { CCI_REG8(0x3cba), 0x40 },
2084 { CCI_REG8(0x3cbb), 0x40 }, { CCI_REG8(0x3cbc), 0x40 },
2085 { CCI_REG8(0x3cbd), 0x40 }, { CCI_REG8(0x3cbe), 0x40 },
2086 { CCI_REG8(0x3cbf), 0x40 }, { CCI_REG8(0x3cc0), 0x40 },
2087 { CCI_REG8(0x3cc1), 0x40 }, { CCI_REG8(0x3cc2), 0x40 },
2088 { CCI_REG8(0x3cc3), 0x40 }, { CCI_REG8(0x3cc4), 0x40 },
2089 { CCI_REG8(0x3cc5), 0x40 }, { CCI_REG8(0x3cc6), 0x40 },
2090 { CCI_REG8(0x3cc7), 0x40 }, { CCI_REG8(0x3cc8), 0x40 },
2091 { CCI_REG8(0x3cc9), 0x40 }, { CCI_REG8(0x3cca), 0x40 },
2092 { CCI_REG8(0x3ccb), 0x40 }, { CCI_REG8(0x3ccc), 0x40 },
2093 { CCI_REG8(0x3ccd), 0x40 }, { CCI_REG8(0x3cce), 0x40 },
2094 { CCI_REG8(0x3ccf), 0x40 }, { CCI_REG8(0x3cd0), 0x40 },
2095 { CCI_REG8(0x3cd1), 0x40 }, { CCI_REG8(0x3cd2), 0x40 },
2096 { CCI_REG8(0x3cd3), 0x40 }, { CCI_REG8(0x3cd4), 0x40 },
2097 { CCI_REG8(0x3cd5), 0x40 }, { CCI_REG8(0x3cd6), 0x40 },
2098 { CCI_REG8(0x3cd7), 0x40 }, { CCI_REG8(0x3cd8), 0x40 },
2099 { CCI_REG8(0x3cd9), 0x40 }, { CCI_REG8(0x3cda), 0x40 },
2100 { CCI_REG8(0x3cdb), 0x40 }, { CCI_REG8(0x3cdc), 0x40 },
2101 { CCI_REG8(0x3cdd), 0x40 }, { CCI_REG8(0x3cde), 0x40 },
2102 { CCI_REG8(0x3cdf), 0x40 }, { CCI_REG8(0x3ce0), 0x40 },
2103 { CCI_REG8(0x3ce1), 0x40 }, { CCI_REG8(0x3ce2), 0x40 },
2104 { CCI_REG8(0x3ce3), 0x40 }, { CCI_REG8(0x3ce4), 0x40 },
2105 { CCI_REG8(0x3ce5), 0x40 }, { CCI_REG8(0x3ce6), 0x40 },
2106 { CCI_REG8(0x3ce7), 0x40 }, { CCI_REG8(0x3ce8), 0x40 },
2107 { CCI_REG8(0x3ce9), 0x40 }, { CCI_REG8(0x3cea), 0x40 },
2108 { CCI_REG8(0x3ceb), 0x40 }, { CCI_REG8(0x3cec), 0x40 },
2109 { CCI_REG8(0x3ced), 0x40 }, { CCI_REG8(0x3cee), 0x40 },
2110 { CCI_REG8(0x3cef), 0x40 }, { CCI_REG8(0x3cf0), 0x40 },
2111 { CCI_REG8(0x3cf1), 0x40 }, { CCI_REG8(0x3cf2), 0x40 },
2112 { CCI_REG8(0x3cf3), 0x40 }, { CCI_REG8(0x3cf4), 0x40 },
2113 { CCI_REG8(0x3cf5), 0x40 }, { CCI_REG8(0x3cf6), 0x40 },
2114 { CCI_REG8(0x3cf7), 0x40 }, { CCI_REG8(0x3cf8), 0x40 },
2115 { CCI_REG8(0x3cf9), 0x40 }, { CCI_REG8(0x3cfa), 0x40 },
2116 { CCI_REG8(0x3cfb), 0x40 }, { CCI_REG8(0x3cfc), 0x40 },
2117 { CCI_REG8(0x3cfd), 0x40 }, { CCI_REG8(0x3cfe), 0x40 },
2118 { CCI_REG8(0x3cff), 0x40 }, { CCI_REG8(0x3d00), 0x40 },
2119 { CCI_REG8(0x3d01), 0x40 }, { CCI_REG8(0x3d02), 0x40 },
2120 { CCI_REG8(0x3d03), 0x40 }, { CCI_REG8(0x3d04), 0x40 },
2121 { CCI_REG8(0x3d05), 0x40 }, { CCI_REG8(0x3d06), 0x40 },
2122 { CCI_REG8(0x3d07), 0x40 }, { CCI_REG8(0x3d08), 0x40 },
2123 { CCI_REG8(0x3d09), 0x40 }, { CCI_REG8(0x3d0a), 0x40 },
2124 { CCI_REG8(0x3d0b), 0xcd }, { CCI_REG8(0x3d0c), 0xcd },
2125 { CCI_REG8(0x3d0d), 0xcd }, { CCI_REG8(0x3d0e), 0xcd },
2126 { CCI_REG8(0x3d0f), 0xcd }, { CCI_REG8(0x3d10), 0xcd },
2127 { CCI_REG8(0x3d11), 0xcd }, { CCI_REG8(0x3d12), 0xcd },
2128 { CCI_REG8(0x3d13), 0xcd }, { CCI_REG8(0x3d14), 0xcd },
2129 { CCI_REG8(0x3d15), 0xcd }, { CCI_REG8(0x3d16), 0xcd },
2130 { CCI_REG8(0x3d17), 0xcd }, { CCI_REG8(0x3d18), 0xcd },
2131 { CCI_REG8(0x3d19), 0xcd }, { CCI_REG8(0x3d1a), 0xcd },
2132 { CCI_REG8(0x3d1b), 0xcd }, { CCI_REG8(0x3d1c), 0xcd },
2133 { CCI_REG8(0x3d1d), 0xcd }, { CCI_REG8(0x3d1e), 0xcd },
2134 { CCI_REG8(0x3d1f), 0xcd }, { CCI_REG8(0x3d20), 0xcd },
2135 { CCI_REG8(0x3d21), 0xcd }, { CCI_REG8(0x3d22), 0xcd },
2136 { CCI_REG8(0x3d23), 0xcd }, { CCI_REG8(0x3d24), 0xcd },
2137 { CCI_REG8(0x3d25), 0xcd }, { CCI_REG8(0x3d26), 0xcd },
2138 { CCI_REG8(0x3d27), 0xcd }, { CCI_REG8(0x3d28), 0xcd },
2139 { CCI_REG8(0x3d29), 0xcd }, { CCI_REG8(0x3d2a), 0xcd },
2140 { CCI_REG8(0x3d2b), 0xcd }, { CCI_REG8(0x3d2c), 0xcd },
2141 { CCI_REG8(0x3d2d), 0xcd }, { CCI_REG8(0x3d2e), 0xcd },
2142 { CCI_REG8(0x3d2f), 0xcd }, { CCI_REG8(0x3d30), 0xcd },
2143 { CCI_REG8(0x3d31), 0xcd }, { CCI_REG8(0x3d32), 0xcd },
2144 { CCI_REG8(0x3d33), 0xcd }, { CCI_REG8(0x3d34), 0xcd },
2145 { CCI_REG8(0x3d35), 0xcd }, { CCI_REG8(0x3d36), 0xcd },
2146 { CCI_REG8(0x3d37), 0xcd }, { CCI_REG8(0x3d38), 0xcd },
2147 { CCI_REG8(0x3d39), 0xcd }, { CCI_REG8(0x3d3a), 0xcd },
2148 { CCI_REG8(0x3d3b), 0xcd }, { CCI_REG8(0x3d3c), 0xcd },
2149 { CCI_REG8(0x3d3d), 0xcd }, { CCI_REG8(0x3d3e), 0xcd },
2150 { CCI_REG8(0x3d3f), 0xcd }, { CCI_REG8(0x3d40), 0xcd },
2151 { CCI_REG8(0x3d41), 0xcd }, { CCI_REG8(0x3d42), 0xcd },
2152 { CCI_REG8(0x3d43), 0xcd }, { CCI_REG8(0x3d44), 0xcd },
2153 { CCI_REG8(0x3d45), 0xcd }, { CCI_REG8(0x3d46), 0xcd },
2154 { CCI_REG8(0x3d47), 0xcd }, { CCI_REG8(0x3d48), 0xcd },
2155 { CCI_REG8(0x3d49), 0xcd }, { CCI_REG8(0x3d4a), 0xcd },
2156 { CCI_REG8(0x3d4b), 0xcd }, { CCI_REG8(0x3d4c), 0xcd },
2157 { CCI_REG8(0x3d4d), 0xcd }, { CCI_REG8(0x3d4e), 0xcd },
2158 { CCI_REG8(0x3d4f), 0xcd }, { CCI_REG8(0x3d50), 0xcd },
2159 { CCI_REG8(0x3d51), 0xcd }, { CCI_REG8(0x3d52), 0xcd },
2160 { CCI_REG8(0x3d53), 0xcd }, { CCI_REG8(0x3d54), 0xcd },
2161 { CCI_REG8(0x3d55), 0xcd }, { CCI_REG8(0x3d56), 0xcd },
2162 { CCI_REG8(0x3d57), 0xcd }, { CCI_REG8(0x3d58), 0xcd },
2163 { CCI_REG8(0x3d59), 0xcd }, { CCI_REG8(0x3d5a), 0xcd },
2164 { CCI_REG8(0x3d5b), 0xcd }, { CCI_REG8(0x3d5c), 0xcd },
2165 { CCI_REG8(0x3d5d), 0xcd }, { CCI_REG8(0x3d5e), 0xcd },
2166 { CCI_REG8(0x3d5f), 0xcd }, { CCI_REG8(0x3d60), 0xcd },
2167 { CCI_REG8(0x3d61), 0xcd }, { CCI_REG8(0x3d62), 0xcd },
2168 { CCI_REG8(0x3d63), 0xcd }, { CCI_REG8(0x3d64), 0xcd },
2169 { CCI_REG8(0x3d65), 0x40 }, { CCI_REG8(0x3d66), 0x40 },
2170 { CCI_REG8(0x3d67), 0x40 }, { CCI_REG8(0x3d68), 0x40 },
2171 { CCI_REG8(0x3d69), 0x40 }, { CCI_REG8(0x3d6a), 0x40 },
2172 { CCI_REG8(0x3d6b), 0x40 }, { CCI_REG8(0x3d6c), 0x40 },
2173 { CCI_REG8(0x3d6d), 0x40 }, { CCI_REG8(0x3d6e), 0x40 },
2174 { CCI_REG8(0x3d6f), 0x40 }, { CCI_REG8(0x3d70), 0x40 },
2175 { CCI_REG8(0x3d71), 0x40 }, { CCI_REG8(0x3d72), 0x40 },
2176 { CCI_REG8(0x3d73), 0x40 }, { CCI_REG8(0x3d74), 0x40 },
2177 { CCI_REG8(0x3d75), 0x40 }, { CCI_REG8(0x3d76), 0x40 },
2178 { CCI_REG8(0x3d77), 0x40 }, { CCI_REG8(0x3d78), 0x40 },
2179 { CCI_REG8(0x3d79), 0x40 }, { CCI_REG8(0x3d7a), 0x40 },
2180 { CCI_REG8(0x3d7b), 0x40 }, { CCI_REG8(0x3d7c), 0x40 },
2181 { CCI_REG8(0x3d7d), 0x40 }, { CCI_REG8(0x3d7e), 0x40 },
2182 { CCI_REG8(0x3d7f), 0x40 }, { CCI_REG8(0x3d80), 0x40 },
2183 { CCI_REG8(0x3d81), 0x40 }, { CCI_REG8(0x3d82), 0x40 },
2184 { CCI_REG8(0x3d83), 0x40 }, { CCI_REG8(0x3d84), 0x40 },
2185 { CCI_REG8(0x3d85), 0x40 }, { CCI_REG8(0x3d86), 0x40 },
2186 { CCI_REG8(0x3d87), 0x40 }, { CCI_REG8(0x3d88), 0x40 },
2187 { CCI_REG8(0x3d89), 0x40 }, { CCI_REG8(0x3d8a), 0x40 },
2188 { CCI_REG8(0x3d8b), 0x40 }, { CCI_REG8(0x3d8c), 0x40 },
2189 { CCI_REG8(0x3d8d), 0x40 }, { CCI_REG8(0x3d8e), 0x40 },
2190 { CCI_REG8(0x3d8f), 0x40 }, { CCI_REG8(0x3d90), 0x40 },
2191 { CCI_REG8(0x3d91), 0x40 }, { CCI_REG8(0x3d92), 0x40 },
2192 { CCI_REG8(0x3d93), 0x40 }, { CCI_REG8(0x3d94), 0x40 },
2193 { CCI_REG8(0x3d95), 0x40 }, { CCI_REG8(0x3d96), 0x40 },
2194 { CCI_REG8(0x3d97), 0x40 }, { CCI_REG8(0x3d98), 0x40 },
2195 { CCI_REG8(0x3d99), 0x40 }, { CCI_REG8(0x3d9a), 0x40 },
2196 { CCI_REG8(0x3d9b), 0x40 }, { CCI_REG8(0x3d9c), 0x40 },
2197 { CCI_REG8(0x3d9d), 0x40 }, { CCI_REG8(0x3d9e), 0x40 },
2198 { CCI_REG8(0x3d9f), 0x40 }, { CCI_REG8(0x3da0), 0x40 },
2199 { CCI_REG8(0x3da1), 0x40 }, { CCI_REG8(0x3da2), 0x40 },
2200 { CCI_REG8(0x3da3), 0x40 }, { CCI_REG8(0x3da4), 0x40 },
2201 { CCI_REG8(0x3da5), 0x40 }, { CCI_REG8(0x3da6), 0x40 },
2202 { CCI_REG8(0x3da7), 0x40 }, { CCI_REG8(0x3da8), 0x40 },
2203 { CCI_REG8(0x3da9), 0x40 }, { CCI_REG8(0x3daa), 0x40 },
2204 { CCI_REG8(0x3dab), 0x40 }, { CCI_REG8(0x3dac), 0x40 },
2205 { CCI_REG8(0x3dad), 0x40 }, { CCI_REG8(0x3dae), 0x40 },
2206 { CCI_REG8(0x3daf), 0x40 }, { CCI_REG8(0x3db0), 0x40 },
2207 { CCI_REG8(0x3db1), 0x40 }, { CCI_REG8(0x3db2), 0x40 },
2208 { CCI_REG8(0x3db3), 0x40 }, { CCI_REG8(0x3db4), 0x40 },
2209 { CCI_REG8(0x3db5), 0x40 }, { CCI_REG8(0x3db6), 0x40 },
2210 { CCI_REG8(0x3db7), 0x40 }, { CCI_REG8(0x3db8), 0x40 },
2211 { CCI_REG8(0x3db9), 0x40 }, { CCI_REG8(0x3dba), 0x40 },
2212 { CCI_REG8(0x3dbb), 0x40 }, { CCI_REG8(0x3dbc), 0x40 },
2213 { CCI_REG8(0x3dbd), 0x40 }, { CCI_REG8(0x3dbe), 0x40 },
2214 { CCI_REG8(0x3dbf), 0xcd }, { CCI_REG8(0x3dc0), 0xcd },
2215 { CCI_REG8(0x3dc1), 0xcd }, { CCI_REG8(0x3dc2), 0xcd },
2216 { CCI_REG8(0x3dc3), 0xcd }, { CCI_REG8(0x3dc4), 0xcd },
2217 { CCI_REG8(0x3dc5), 0xcd }, { CCI_REG8(0x3dc6), 0xcd },
2218 { CCI_REG8(0x3dc7), 0xcd }, { CCI_REG8(0x3dc8), 0xcd },
2219 { CCI_REG8(0x3dc9), 0xcd }, { CCI_REG8(0x3dca), 0xcd },
2220 { CCI_REG8(0x3dcb), 0xcd }, { CCI_REG8(0x3dcc), 0xcd },
2221 { CCI_REG8(0x3dcd), 0xcd }, { CCI_REG8(0x3dce), 0xcd },
2222 { CCI_REG8(0x3dcf), 0xcd }, { CCI_REG8(0x3dd0), 0xcd },
2223 { CCI_REG8(0x3dd1), 0xcd }, { CCI_REG8(0x3dd2), 0xcd },
2224 { CCI_REG8(0x3dd3), 0xcd }, { CCI_REG8(0x3dd4), 0xcd },
2225 { CCI_REG8(0x3dd5), 0xcd }, { CCI_REG8(0x3dd6), 0xcd },
2226 { CCI_REG8(0x3dd7), 0xcd }, { CCI_REG8(0x3dd8), 0xcd },
2227 { CCI_REG8(0x3dd9), 0xcd }, { CCI_REG8(0x3dda), 0xcd },
2228 { CCI_REG8(0x3ddb), 0xcd }, { CCI_REG8(0x3ddc), 0xcd },
2229 { CCI_REG8(0x3ddd), 0xcd }, { CCI_REG8(0x3dde), 0xcd },
2230 { CCI_REG8(0x3ddf), 0xcd }, { CCI_REG8(0x3de0), 0xcd },
2231 { CCI_REG8(0x3de1), 0xcd }, { CCI_REG8(0x3de2), 0xcd },
2232 { CCI_REG8(0x3de3), 0xcd }, { CCI_REG8(0x3de4), 0xcd },
2233 { CCI_REG8(0x3de5), 0xcd }, { CCI_REG8(0x3de6), 0xcd },
2234 { CCI_REG8(0x3de7), 0xcd }, { CCI_REG8(0x3de8), 0xcd },
2235 { CCI_REG8(0x3de9), 0xcd }, { CCI_REG8(0x3dea), 0xcd },
2236 { CCI_REG8(0x3deb), 0xcd }, { CCI_REG8(0x3dec), 0xcd },
2237 { CCI_REG8(0x3ded), 0xcd }, { CCI_REG8(0x3dee), 0xcd },
2238 { CCI_REG8(0x3def), 0xcd }, { CCI_REG8(0x3df0), 0xcd },
2239 { CCI_REG8(0x3df1), 0xcd }, { CCI_REG8(0x3df2), 0xcd },
2240 { CCI_REG8(0x3df3), 0xcd }, { CCI_REG8(0x3df4), 0xcd },
2241 { CCI_REG8(0x3df5), 0xcd }, { CCI_REG8(0x3df6), 0xcd },
2242 { CCI_REG8(0x3df7), 0xcd }, { CCI_REG8(0x3df8), 0xcd },
2243 { CCI_REG8(0x3df9), 0xcd }, { CCI_REG8(0x3dfa), 0xcd },
2244 { CCI_REG8(0x3dfb), 0xcd }, { CCI_REG8(0x3dfc), 0xcd },
2245 { CCI_REG8(0x3dfd), 0xcd }, { CCI_REG8(0x3dfe), 0xcd },
2246 { CCI_REG8(0x3dff), 0xcd }, { CCI_REG8(0x3e00), 0xcd },
2247 { CCI_REG8(0x3e01), 0xcd }, { CCI_REG8(0x3e02), 0xcd },
2248 { CCI_REG8(0x3e03), 0xcd }, { CCI_REG8(0x3e04), 0xcd },
2249 { CCI_REG8(0x3e05), 0xcd }, { CCI_REG8(0x3e06), 0xcd },
2250 { CCI_REG8(0x3e07), 0xcd }, { CCI_REG8(0x3e08), 0xcd },
2251 { CCI_REG8(0x3e09), 0xcd }, { CCI_REG8(0x3e0a), 0xcd },
2252 { CCI_REG8(0x3e0b), 0xcd }, { CCI_REG8(0x3e0c), 0xcd },
2253 { CCI_REG8(0x3e0d), 0xcd }, { CCI_REG8(0x3e0e), 0xcd },
2254 { CCI_REG8(0x3e0f), 0xcd }, { CCI_REG8(0x3e10), 0xcd },
2255 { CCI_REG8(0x3e11), 0xcd }, { CCI_REG8(0x3e12), 0xcd },
2256 { CCI_REG8(0x3e13), 0xcd }, { CCI_REG8(0x3e14), 0xcd },
2257 { CCI_REG8(0x3e15), 0xcd }, { CCI_REG8(0x3e16), 0xcd },
2258 { CCI_REG8(0x3e17), 0xcd }, { CCI_REG8(0x3e18), 0xcd },
2259 { CCI_REG8(0x3e19), 0xcd }, { CCI_REG8(0x3e1a), 0xcd },
2260 { CCI_REG8(0x3e1b), 0xcd }, { CCI_REG8(0x3e1c), 0xcd },
2261 { CCI_REG8(0x3e1d), 0xcd }, { CCI_REG8(0x3e1e), 0xcd },
2262 { CCI_REG8(0x3e1f), 0xcd }, { CCI_REG8(0x3e20), 0xcd },
2263 { CCI_REG8(0x3e21), 0xcd }, { CCI_REG8(0x3e22), 0xcd },
2264 { CCI_REG8(0x3e23), 0xcd }, { CCI_REG8(0x3e24), 0xcd },
2265 { CCI_REG8(0x3e25), 0xcd }, { CCI_REG8(0x3e26), 0xcd },
2266 { CCI_REG8(0x3e27), 0xcd }, { CCI_REG8(0x3e28), 0xcd },
2267 { CCI_REG8(0x3e29), 0xcd }, { CCI_REG8(0x3e2a), 0xcd },
2268 { CCI_REG8(0x3e2b), 0xcd }, { CCI_REG8(0x3e2c), 0xcd },
2269 { CCI_REG8(0x3e2d), 0xcd }, { CCI_REG8(0x3e2e), 0xcd },
2270 { CCI_REG8(0x3e2f), 0xcd }, { CCI_REG8(0x3e30), 0xcd },
2271 { CCI_REG8(0x3e31), 0xcd }, { CCI_REG8(0x3e32), 0xcd },
2272 { CCI_REG8(0x3e33), 0xcd }, { CCI_REG8(0x3e34), 0xcd },
2273 { CCI_REG8(0x3e35), 0xcd }, { CCI_REG8(0x3e36), 0xcd },
2274 { CCI_REG8(0x3e37), 0xcd }, { CCI_REG8(0x3e38), 0xcd },
2275 { CCI_REG8(0x3e39), 0xcd }, { CCI_REG8(0x3e3a), 0xcd },
2276 { CCI_REG8(0x3e3b), 0xcd }, { CCI_REG8(0x3e3c), 0xcd },
2277 { CCI_REG8(0x3e3d), 0xcd }, { CCI_REG8(0x3e3e), 0xcd },
2278 { CCI_REG8(0x3e3f), 0xcd }, { CCI_REG8(0x3e40), 0xcd },
2279 { CCI_REG8(0x3e41), 0xcd }, { CCI_REG8(0x3e42), 0xcd },
2280 { CCI_REG8(0x3e43), 0xcd }, { CCI_REG8(0x3e44), 0xcd },
2281 { CCI_REG8(0x3e45), 0xcd }, { CCI_REG8(0x3e46), 0xcd },
2282 { CCI_REG8(0x3e47), 0xcd }, { CCI_REG8(0x3e48), 0xcd },
2283 { CCI_REG8(0x3e49), 0xcd }, { CCI_REG8(0x3e4a), 0xcd },
2284 { CCI_REG8(0x3e4b), 0xcd }, { CCI_REG8(0x3e4c), 0xcd },
2285 { CCI_REG8(0x3e4d), 0xcd }, { CCI_REG8(0x3e4e), 0xcd },
2286 { CCI_REG8(0x3e4f), 0xcd }, { CCI_REG8(0x3e50), 0xcd },
2287 { CCI_REG8(0x3e51), 0xcd }, { CCI_REG8(0x3e52), 0xcd },
2288 { CCI_REG8(0x3e53), 0xcd }, { CCI_REG8(0x3e54), 0xcd },
2289 { CCI_REG8(0x3e55), 0xcd }, { CCI_REG8(0x3e56), 0xcd },
2290 { CCI_REG8(0x3e57), 0xcd }, { CCI_REG8(0x3e58), 0xcd },
2291 { CCI_REG8(0x3e59), 0xcd }, { CCI_REG8(0x3e5a), 0xcd },
2292 { CCI_REG8(0x3e5b), 0xcd }, { CCI_REG8(0x3e5c), 0xcd },
2293 { CCI_REG8(0x3e5d), 0xcd }, { CCI_REG8(0x3e5e), 0xcd },
2294 { CCI_REG8(0x3e5f), 0xcd }, { CCI_REG8(0x3e60), 0xcd },
2295 { CCI_REG8(0x3e61), 0xcd }, { CCI_REG8(0x3e62), 0xcd },
2296 { CCI_REG8(0x3e63), 0xcd }, { CCI_REG8(0x3e64), 0xcd },
2297 { CCI_REG8(0x3e65), 0xcd }, { CCI_REG8(0x3e66), 0xcd },
2298 { CCI_REG8(0x3e67), 0xcd }, { CCI_REG8(0x3e68), 0xcd },
2299 { CCI_REG8(0x3e69), 0xcd }, { CCI_REG8(0x3e6a), 0xcd },
2300 { CCI_REG8(0x3e6b), 0xcd }, { CCI_REG8(0x3e6c), 0xcd },
2301 { CCI_REG8(0x3e6d), 0xcd }, { CCI_REG8(0x3e6e), 0xcd },
2302 { CCI_REG8(0x3e6f), 0xcd }, { CCI_REG8(0x3e70), 0xcd },
2303 { CCI_REG8(0x3e71), 0xcd }, { CCI_REG8(0x3e72), 0xcd },
2304 { CCI_REG8(0x3e73), 0xcd }, { CCI_REG8(0x3e74), 0xcd },
2305 { CCI_REG8(0x3e75), 0xcd }, { CCI_REG8(0x3e76), 0xcd },
2306 { CCI_REG8(0x3e77), 0xcd }, { CCI_REG8(0x3e78), 0xcd },
2307 { CCI_REG8(0x3e79), 0xcd }, { CCI_REG8(0x3e7a), 0xcd },
2308 { CCI_REG8(0x3e7b), 0xcd }, { CCI_REG8(0x3e7c), 0xcd },
2309 { CCI_REG8(0x3e7d), 0xcd }, { CCI_REG8(0x3e7e), 0xcd },
2310 { CCI_REG8(0x3e7f), 0xcd }, { CCI_REG8(0x3e80), 0xcd },
2311 { CCI_REG8(0x3e81), 0xcd }, { CCI_REG8(0x3e82), 0xcd },
2312 { CCI_REG8(0x3e83), 0xcd }, { CCI_REG8(0x3e84), 0xcd },
2313 { CCI_REG8(0x3e85), 0xcd }, { CCI_REG8(0x3e86), 0xcd },
2314 { CCI_REG8(0x3e87), 0xcd }, { CCI_REG8(0x3e88), 0xcd },
2315 { CCI_REG8(0x3e89), 0xcd }, { CCI_REG8(0x3e8a), 0xcd },
2316 { CCI_REG8(0x3e8b), 0xcd }, { CCI_REG8(0x3e8c), 0xcd },
2317 { CCI_REG8(0x3e8d), 0xcd }, { CCI_REG8(0x3e8e), 0xcd },
2318 { CCI_REG8(0x3e8f), 0xcd }, { CCI_REG8(0x3e90), 0xcd },
2319 { CCI_REG8(0x3e91), 0xcd }, { CCI_REG8(0x3e92), 0xcd },
2320 { CCI_REG8(0x3e93), 0xcd }, { CCI_REG8(0x3e94), 0xcd },
2321 { CCI_REG8(0x3e95), 0xcd }, { CCI_REG8(0x3e96), 0xcd },
2322 { CCI_REG8(0x3e97), 0xcd }, { CCI_REG8(0x3e98), 0xcd },
2323 { CCI_REG8(0x3e99), 0xcd }, { CCI_REG8(0x3e9a), 0xcd },
2324 { CCI_REG8(0x3e9b), 0xcd }, { CCI_REG8(0x3e9c), 0xcd },
2325 { CCI_REG8(0x3e9d), 0xcd }, { CCI_REG8(0x3e9e), 0xcd },
2326 { CCI_REG8(0x3e9f), 0xcd }, { CCI_REG8(0xfff9), 0x06 },
2327 { CCI_REG8(0xc03f), 0x01 }, { CCI_REG8(0xc03e), 0x08 },
2328 { CCI_REG8(0xc02c), 0xff }, { CCI_REG8(0xc005), 0x06 },
2329 { CCI_REG8(0xc006), 0x30 }, { CCI_REG8(0xc007), 0xc0 },
2330 { CCI_REG8(0xc027), 0x01 }, { CCI_REG8(0x30c0), 0x05 },
2331 { CCI_REG8(0x30c1), 0x9f }, { CCI_REG8(0x30c2), 0x06 },
2332 { CCI_REG8(0x30c3), 0x5f }, { CCI_REG8(0x30c4), 0x80 },
2333 { CCI_REG8(0x30c5), 0x08 }, { CCI_REG8(0x30c6), 0x39 },
2334 { CCI_REG8(0x30c7), 0x00 }, { CCI_REG8(0xc046), 0x20 },
2335 { CCI_REG8(0xc043), 0x01 }, { CCI_REG8(0xc04b), 0x01 },
2336 { CCI_REG8(0x0102), 0x01 }, { CCI_REG8(0x0100), 0x00 },
2337 { CCI_REG8(0x0102), 0x00 }, { CCI_REG8(0x3015), 0xf0 },
2338 { CCI_REG8(0x3018), 0xf0 }, { CCI_REG8(0x301c), 0xf0 },
2339 { CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 }
2340};
2341
2342static const struct cci_reg_sequence ov64a40_9248x6944[] = {
2343 { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 },
2344 { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a },
2345 { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 },
2346 { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 },
2347 { CCI_REG8(0x5001), 0x21 }
2348};
2349
2350static const struct cci_reg_sequence ov64a40_8000x6000[] = {
2351 { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 },
2352 { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a },
2353 { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 },
2354 { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 },
2355 { CCI_REG8(0x5001), 0x21 }
2356};
2357
2358static const struct cci_reg_sequence ov64a40_4624_3472[] = {
2359 { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 },
2360 { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e },
2361 { CCI_REG8(0x3712), 0x50 }, { CCI_REG8(0x3822), 0x00 },
2362 { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x08 },
2363 { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x02 },
2364 { CCI_REG8(0x384d), 0xba }, { CCI_REG8(0x3852), 0x00 },
2365 { CCI_REG8(0x3856), 0x08 }, { CCI_REG8(0x3857), 0x08 },
2366 { CCI_REG8(0x3858), 0x10 }, { CCI_REG8(0x3859), 0x10 },
2367 { CCI_REG8(0x4016), 0x0f }, { CCI_REG8(0x4018), 0x03 },
2368 { CCI_REG8(0x4504), 0x1e }, { CCI_REG8(0x4523), 0x41 },
2369 { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x12 },
2370 { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4915), 0x02 },
2371 { CCI_REG8(0x4916), 0x1d }, { CCI_REG8(0x4a15), 0x02 },
2372 { CCI_REG8(0x4a16), 0x1d }, { CCI_REG8(0x3703), 0x72 },
2373 { CCI_REG8(0x3709), 0xe6 }, { CCI_REG8(0x3a60), 0x68 },
2374 { CCI_REG8(0x3a6f), 0x68 }, { CCI_REG8(0x3a5e), 0xdc },
2375 { CCI_REG8(0x3a6d), 0xdc }, { CCI_REG8(0x3721), 0xc9 },
2376 { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 },
2377 { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 },
2378 { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 },
2379 { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b },
2380 { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 },
2381 { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b },
2382 { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 },
2383 { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b },
2384 { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x481b), 0x35 },
2385 { CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x3400), 0x00 },
2386 { CCI_REG8(0x3421), 0x23 }, { CCI_REG8(0x3422), 0xfc },
2387 { CCI_REG8(0x3423), 0x07 }, { CCI_REG8(0x3424), 0x01 },
2388 { CCI_REG8(0x3425), 0x04 }, { CCI_REG8(0x3426), 0x50 },
2389 { CCI_REG8(0x3427), 0x55 }, { CCI_REG8(0x3428), 0x15 },
2390 { CCI_REG8(0x3429), 0x00 }, { CCI_REG8(0x3025), 0x03 },
2391 { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x0305), 0x98 },
2392 { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 },
2393 { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },
2394 { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },
2395 { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 }
2396};
2397
2398static const struct cci_reg_sequence ov64a40_3840x2160[] = {
2399 { CCI_REG8(0x034a), 0x05 }, { CCI_REG8(0x034b), 0x05 },
2400 { CCI_REG8(0x3504), 0x08 }, { CCI_REG8(0x360d), 0x82 },
2401 { CCI_REG8(0x368a), 0x2e }, { CCI_REG8(0x3712), 0x50 },
2402 { CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3827), 0x40 },
2403 { CCI_REG8(0x383d), 0x08 }, { CCI_REG8(0x383f), 0x00 },
2404 { CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0xba },
2405 { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x08 },
2406 { CCI_REG8(0x3857), 0x08 }, { CCI_REG8(0x3858), 0x10 },
2407 { CCI_REG8(0x3859), 0x10 }, { CCI_REG8(0x4016), 0x0f },
2408 { CCI_REG8(0x4018), 0x03 }, { CCI_REG8(0x4504), 0x1e },
2409 { CCI_REG8(0x4523), 0x41 }, { CCI_REG8(0x45c0), 0x01 },
2410 { CCI_REG8(0x4641), 0x12 }, { CCI_REG8(0x4643), 0x0c },
2411 { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d },
2412 { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d },
2413 { CCI_REG8(0x3703), 0x72 }, { CCI_REG8(0x3709), 0xe6 },
2414 { CCI_REG8(0x3a60), 0x68 }, { CCI_REG8(0x3a6f), 0x68 },
2415 { CCI_REG8(0x3a5e), 0xdc }, { CCI_REG8(0x3a6d), 0xdc },
2416 { CCI_REG8(0x3721), 0xc9 }, { CCI_REG8(0x5250), 0x06 },
2417 { CCI_REG8(0x527a), 0x00 }, { CCI_REG8(0x527b), 0x65 },
2418 { CCI_REG8(0x527c), 0x00 }, { CCI_REG8(0x527d), 0x82 },
2419 { CCI_REG8(0x5280), 0x24 }, { CCI_REG8(0x5281), 0x40 },
2420 { CCI_REG8(0x5282), 0x1b }, { CCI_REG8(0x5283), 0x40 },
2421 { CCI_REG8(0x5284), 0x24 }, { CCI_REG8(0x5285), 0x40 },
2422 { CCI_REG8(0x5286), 0x1b }, { CCI_REG8(0x5287), 0x40 },
2423 { CCI_REG8(0x5200), 0x24 }, { CCI_REG8(0x5201), 0x40 },
2424 { CCI_REG8(0x5202), 0x1b }, { CCI_REG8(0x5203), 0x40 },
2425 { CCI_REG8(0x481b), 0x35 }, { CCI_REG8(0x4862), 0x25 },
2426 { CCI_REG8(0x3400), 0x00 }, { CCI_REG8(0x3421), 0x23 },
2427 { CCI_REG8(0x3422), 0xfc }, { CCI_REG8(0x3423), 0x07 },
2428 { CCI_REG8(0x3424), 0x01 }, { CCI_REG8(0x3425), 0x04 },
2429 { CCI_REG8(0x3426), 0x50 }, { CCI_REG8(0x3427), 0x55 },
2430 { CCI_REG8(0x3428), 0x15 }, { CCI_REG8(0x3429), 0x00 },
2431 { CCI_REG8(0x3025), 0x03 }, { CCI_REG8(0x5250), 0x06 },
2432 { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 },
2433 { CCI_REG8(0x0345), 0x90 }, { CCI_REG8(0x0307), 0x01 },
2434 { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },
2435 { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },
2436 { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 },
2437 { CCI_REG8(0x5000), 0x01 }
2438};
2439
2440static const struct cci_reg_sequence ov64a40_2312_1736[] = {
2441 { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 },
2442 { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e },
2443 { CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 },
2444 { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 },
2445 { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 },
2446 { CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 },
2447 { CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 },
2448 { CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 },
2449 { CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 },
2450 { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 },
2451 { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 },
2452 { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b },
2453 { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d },
2454 { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d },
2455 { CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 },
2456 { CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 },
2457 { CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a },
2458 { CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 },
2459 { CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 },
2460 { CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 },
2461 { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 },
2462 { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 },
2463 { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 },
2464 { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b },
2465 { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 },
2466 { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b },
2467 { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 },
2468 { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b },
2469 { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 },
2470 { CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 },
2471 { CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 },
2472 { CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 },
2473 { CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 },
2474 { CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 },
2475 { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 },
2476 { CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 },
2477 { CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 },
2478 { CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 },
2479 { CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 },
2480 { CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e },
2481 { CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 },
2482 { CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 },
2483 { CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 },
2484 { CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 },
2485 { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 },
2486 { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },
2487 { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },
2488 { CCI_REG8(0x480C), 0x92 }
2489};
2490
2491static const struct cci_reg_sequence ov64a40_1920x1080[] = {
2492 { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 },
2493 { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e },
2494 { CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 },
2495 { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 },
2496 { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 },
2497 { CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 },
2498 { CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 },
2499 { CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 },
2500 { CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 },
2501 { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 },
2502 { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 },
2503 { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b },
2504 { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d },
2505 { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d },
2506 { CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 },
2507 { CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 },
2508 { CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a },
2509 { CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 },
2510 { CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 },
2511 { CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 },
2512 { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 },
2513 { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 },
2514 { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 },
2515 { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b },
2516 { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 },
2517 { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b },
2518 { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 },
2519 { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b },
2520 { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 },
2521 { CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 },
2522 { CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 },
2523 { CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 },
2524 { CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 },
2525 { CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 },
2526 { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 },
2527 { CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 },
2528 { CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 },
2529 { CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 },
2530 { CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 },
2531 { CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e },
2532 { CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 },
2533 { CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 },
2534 { CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 },
2535 { CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 },
2536 { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 },
2537 { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },
2538 { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },
2539 { CCI_REG8(0x480C), 0x92 }
2540};
2541
2542/* 456MHz MIPI link frequency with 24MHz input clock. */
2543static const struct cci_reg_sequence ov64a40_pll_config[] = {
2544 { OV64A40_PLL1_PRE_DIV0, 0x88 },
2545 { OV64A40_PLL1_PRE_DIV, 0x02 },
2546 { OV64A40_PLL1_MULTIPLIER, 0x0098 },
2547 { OV64A40_PLL1_M_DIV, 0x01 },
2548 { OV64A40_PLL2_SEL_BAK_SA1, 0x00 },
2549 { OV64A40_PLL2_PRE_DIV, 0x12 },
2550 { OV64A40_PLL2_MULTIPLIER, 0x0190 },
2551 { OV64A40_PLL2_PRE_DIV0, 0xd7 },
2552 { OV64A40_PLL2_DIVSP, 0x00 },
2553 { OV64A40_PLL2_DIVDAC, 0x00 },
2554 { OV64A40_PLL2_DACPREDIV, 0x00 }
2555};
2556
2557struct ov64a40_reglist {
2558 unsigned int num_regs;
2559 const struct cci_reg_sequence *regvals;
2560};
2561
2562struct ov64a40_subsampling {
2563 unsigned int x_odd_inc;
2564 unsigned int x_even_inc;
2565 unsigned int y_odd_inc;
2566 unsigned int y_even_inc;
2567 bool vbin;
2568 bool hbin;
2569};
2570
2571static struct ov64a40_mode {
2572 unsigned int width;
2573 unsigned int height;
2574 struct ov64a40_timings {
2575 unsigned int vts;
2576 unsigned int ppl;
2577 } timings_default[OV64A40_NUM_LINK_FREQ];
2578 const struct ov64a40_reglist reglist;
2579 struct v4l2_rect analogue_crop;
2580 struct v4l2_rect digital_crop;
2581 struct ov64a40_subsampling subsampling;
2582} ov64a40_modes[] = {
2583 /* Full resolution */
2584 {
2585 .width = 9248,
2586 .height = 6944,
2587 .timings_default = {
2588 /* 2.6 FPS */
2589 [OV64A40_LINK_FREQ_456M_ID] = {
2590 .vts = 7072,
2591 .ppl = 4072,
2592 },
2593 /* 2 FPS */
2594 [OV64A40_LINK_FREQ_360M_ID] = {
2595 .vts = 7072,
2596 .ppl = 5248,
2597 },
2598 },
2599 .reglist = {
2600 .num_regs = ARRAY_SIZE(ov64a40_9248x6944),
2601 .regvals = ov64a40_9248x6944,
2602 },
2603 .analogue_crop = {
2604 .left = 0,
2605 .top = 0,
2606 .width = 9280,
2607 .height = 6976,
2608 },
2609 .digital_crop = {
2610 .left = 17,
2611 .top = 16,
2612 .width = 9248,
2613 .height = 6944,
2614 },
2615 .subsampling = {
2616 .x_odd_inc = 1,
2617 .x_even_inc = 1,
2618 .y_odd_inc = 1,
2619 .y_even_inc = 1,
2620 .vbin = false,
2621 .hbin = false,
2622 },
2623 },
2624 /* Analogue crop + digital crop */
2625 {
2626 .width = 8000,
2627 .height = 6000,
2628 .timings_default = {
2629 /* 3.0 FPS */
2630 [OV64A40_LINK_FREQ_456M_ID] = {
2631 .vts = 6400,
2632 .ppl = 3848,
2633 },
2634 /* 2.5 FPS */
2635 [OV64A40_LINK_FREQ_360M_ID] = {
2636 .vts = 6304,
2637 .ppl = 4736,
2638 },
2639 },
2640 .reglist = {
2641 .num_regs = ARRAY_SIZE(ov64a40_8000x6000),
2642 .regvals = ov64a40_8000x6000,
2643 },
2644 .analogue_crop = {
2645 .left = 624,
2646 .top = 472,
2647 .width = 8048,
2648 .height = 6032,
2649 },
2650 .digital_crop = {
2651 .left = 17,
2652 .top = 16,
2653 .width = 8000,
2654 .height = 6000,
2655 },
2656 .subsampling = {
2657 .x_odd_inc = 1,
2658 .x_even_inc = 1,
2659 .y_odd_inc = 1,
2660 .y_even_inc = 1,
2661 .vbin = false,
2662 .hbin = false,
2663 },
2664 },
2665 /* 2x2 downscaled */
2666 {
2667 .width = 4624,
2668 .height = 3472,
2669 .timings_default = {
2670 /* 10 FPS */
2671 [OV64A40_LINK_FREQ_456M_ID] = {
2672 .vts = 3533,
2673 .ppl = 2112,
2674 },
2675 /* 7 FPS */
2676 [OV64A40_LINK_FREQ_360M_ID] = {
2677 .vts = 3939,
2678 .ppl = 2720,
2679 },
2680 },
2681 .reglist = {
2682 .num_regs = ARRAY_SIZE(ov64a40_4624_3472),
2683 .regvals = ov64a40_4624_3472,
2684 },
2685 .analogue_crop = {
2686 .left = 0,
2687 .top = 0,
2688 .width = 9280,
2689 .height = 6976,
2690 },
2691 .digital_crop = {
2692 .left = 9,
2693 .top = 8,
2694 .width = 4624,
2695 .height = 3472,
2696 },
2697 .subsampling = {
2698 .x_odd_inc = 3,
2699 .x_even_inc = 1,
2700 .y_odd_inc = 1,
2701 .y_even_inc = 1,
2702 .vbin = true,
2703 .hbin = false,
2704 },
2705 },
2706 /* Analogue crop + 2x2 downscale + digital crop */
2707 {
2708 .width = 3840,
2709 .height = 2160,
2710 .timings_default = {
2711 /* 20 FPS */
2712 [OV64A40_LINK_FREQ_456M_ID] = {
2713 .vts = 2218,
2714 .ppl = 1690,
2715 },
2716 /* 15 FPS */
2717 [OV64A40_LINK_FREQ_360M_ID] = {
2718 .vts = 2270,
2719 .ppl = 2202,
2720 },
2721 },
2722 .reglist = {
2723 .num_regs = ARRAY_SIZE(ov64a40_3840x2160),
2724 .regvals = ov64a40_3840x2160,
2725 },
2726 .analogue_crop = {
2727 .left = 784,
2728 .top = 1312,
2729 .width = 7712,
2730 .height = 4352,
2731 },
2732 .digital_crop = {
2733 .left = 9,
2734 .top = 8,
2735 .width = 3840,
2736 .height = 2160,
2737 },
2738 .subsampling = {
2739 .x_odd_inc = 3,
2740 .x_even_inc = 1,
2741 .y_odd_inc = 1,
2742 .y_even_inc = 1,
2743 .vbin = true,
2744 .hbin = false,
2745 },
2746 },
2747 /* 4x4 downscaled */
2748 {
2749 .width = 2312,
2750 .height = 1736,
2751 .timings_default = {
2752 /* 30 FPS */
2753 [OV64A40_LINK_FREQ_456M_ID] = {
2754 .vts = 1998,
2755 .ppl = 1248,
2756 },
2757 /* 25 FPS */
2758 [OV64A40_LINK_FREQ_360M_ID] = {
2759 .vts = 1994,
2760 .ppl = 1504,
2761 },
2762 },
2763 .reglist = {
2764 .num_regs = ARRAY_SIZE(ov64a40_2312_1736),
2765 .regvals = ov64a40_2312_1736,
2766 },
2767 .analogue_crop = {
2768 .left = 0,
2769 .top = 0,
2770 .width = 9280,
2771 .height = 6976,
2772 },
2773 .digital_crop = {
2774 .left = 5,
2775 .top = 4,
2776 .width = 2312,
2777 .height = 1736,
2778 },
2779 .subsampling = {
2780 .x_odd_inc = 3,
2781 .x_even_inc = 1,
2782 .y_odd_inc = 3,
2783 .y_even_inc = 1,
2784 .vbin = true,
2785 .hbin = true,
2786 },
2787 },
2788 /* Analogue crop + 4x4 downscale + digital crop */
2789 {
2790 .width = 1920,
2791 .height = 1080,
2792 .timings_default = {
2793 /* 60 FPS */
2794 [OV64A40_LINK_FREQ_456M_ID] = {
2795 .vts = 1397,
2796 .ppl = 880,
2797 },
2798 /* 45 FPS */
2799 [OV64A40_LINK_FREQ_360M_ID] = {
2800 .vts = 1216,
2801 .ppl = 1360,
2802 },
2803 },
2804 .reglist = {
2805 .num_regs = ARRAY_SIZE(ov64a40_1920x1080),
2806 .regvals = ov64a40_1920x1080,
2807 },
2808 .analogue_crop = {
2809 .left = 784,
2810 .top = 1312,
2811 .width = 7712,
2812 .height = 4352,
2813 },
2814 .digital_crop = {
2815 .left = 7,
2816 .top = 6,
2817 .width = 1920,
2818 .height = 1080,
2819 },
2820 .subsampling = {
2821 .x_odd_inc = 3,
2822 .x_even_inc = 1,
2823 .y_odd_inc = 3,
2824 .y_even_inc = 1,
2825 .vbin = true,
2826 .hbin = true,
2827 },
2828 },
2829};
2830
2831struct ov64a40 {
2832 struct device *dev;
2833
2834 struct v4l2_subdev sd;
2835 struct media_pad pad;
2836
2837 struct regmap *cci;
2838
2839 struct ov64a40_mode *mode;
2840
2841 struct clk *xclk;
2842
2843 struct gpio_desc *reset_gpio;
2844 struct regulator_bulk_data supplies[ARRAY_SIZE(ov64a40_supply_names)];
2845
2846 s64 *link_frequencies;
2847 unsigned int num_link_frequencies;
2848
2849 struct v4l2_ctrl_handler ctrl_handler;
2850 struct v4l2_ctrl *exposure;
2851 struct v4l2_ctrl *link_freq;
2852 struct v4l2_ctrl *vblank;
2853 struct v4l2_ctrl *hblank;
2854 struct v4l2_ctrl *vflip;
2855 struct v4l2_ctrl *hflip;
2856};
2857
2858static inline struct ov64a40 *sd_to_ov64a40(struct v4l2_subdev *sd)
2859{
2860 return container_of_const(sd, struct ov64a40, sd);
2861}
2862
2863static const struct ov64a40_timings *
2864ov64a40_get_timings(struct ov64a40 *ov64a40, unsigned int link_freq_index)
2865{
2866 s64 link_freq = ov64a40->link_frequencies[link_freq_index];
2867 unsigned int timings_index = link_freq == OV64A40_LINK_FREQ_360M
2868 ? OV64A40_LINK_FREQ_360M_ID
2869 : OV64A40_LINK_FREQ_456M_ID;
2870
2871 return &ov64a40->mode->timings_default[timings_index];
2872}
2873
2874static int ov64a40_program_geometry(struct ov64a40 *ov64a40)
2875{
2876 struct ov64a40_mode *mode = ov64a40->mode;
2877 struct v4l2_rect *anacrop = &mode->analogue_crop;
2878 struct v4l2_rect *digicrop = &mode->digital_crop;
2879 const struct ov64a40_timings *timings;
2880 int ret = 0;
2881
2882 /* Analogue crop. */
2883 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL0,
2884 val: anacrop->left, err: &ret);
2885 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL2,
2886 val: anacrop->top, err: &ret);
2887 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL4,
2888 val: anacrop->width + anacrop->left - 1, err: &ret);
2889 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL6,
2890 val: anacrop->height + anacrop->top - 1, err: &ret);
2891
2892 /* ISP windowing. */
2893 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL10,
2894 val: digicrop->left, err: &ret);
2895 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL12,
2896 val: digicrop->top, err: &ret);
2897 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL8,
2898 val: digicrop->width, err: &ret);
2899 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRLA,
2900 val: digicrop->height, err: &ret);
2901
2902 /* Total timings. */
2903 timings = ov64a40_get_timings(ov64a40, link_freq_index: ov64a40->link_freq->cur.val);
2904 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRLC, val: timings->ppl, err: &ret);
2905 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRLE, val: timings->vts, err: &ret);
2906
2907 return ret;
2908}
2909
2910static int ov64a40_program_subsampling(struct ov64a40 *ov64a40)
2911{
2912 struct ov64a40_subsampling *subsampling = &ov64a40->mode->subsampling;
2913 int ret = 0;
2914
2915 /* Skipping configuration */
2916 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL14,
2917 OV64A40_SKIPPING_CONFIG(subsampling->x_odd_inc,
2918 subsampling->x_even_inc), err: &ret);
2919 cci_write(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL15,
2920 OV64A40_SKIPPING_CONFIG(subsampling->y_odd_inc,
2921 subsampling->y_even_inc), err: &ret);
2922
2923 /* Binning configuration */
2924 cci_update_bits(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL_20,
2925 OV64A40_TIMING_CTRL_20_VBIN,
2926 val: subsampling->vbin ? OV64A40_TIMING_CTRL_20_VBIN : 0,
2927 err: &ret);
2928 cci_update_bits(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL_21,
2929 OV64A40_TIMING_CTRL_21_HBIN_CONF,
2930 val: subsampling->hbin ?
2931 OV64A40_TIMING_CTRL_21_HBIN_CONF : 0, err: &ret);
2932
2933 return ret;
2934}
2935
2936static int ov64a40_start_streaming(struct ov64a40 *ov64a40,
2937 struct v4l2_subdev_state *state)
2938{
2939 const struct ov64a40_reglist *reglist = &ov64a40->mode->reglist;
2940 const struct ov64a40_timings *timings;
2941 unsigned long delay;
2942 int ret;
2943
2944 ret = pm_runtime_resume_and_get(dev: ov64a40->dev);
2945 if (ret < 0)
2946 return ret;
2947
2948 ret = cci_multi_reg_write(map: ov64a40->cci, regs: ov64a40_init,
2949 ARRAY_SIZE(ov64a40_init), NULL);
2950 if (ret)
2951 goto error_power_off;
2952
2953 ret = cci_multi_reg_write(map: ov64a40->cci, regs: reglist->regvals,
2954 num_regs: reglist->num_regs, NULL);
2955 if (ret)
2956 goto error_power_off;
2957
2958 ret = ov64a40_program_geometry(ov64a40);
2959 if (ret)
2960 goto error_power_off;
2961
2962 ret = ov64a40_program_subsampling(ov64a40);
2963 if (ret)
2964 goto error_power_off;
2965
2966 ret = __v4l2_ctrl_handler_setup(hdl: &ov64a40->ctrl_handler);
2967 if (ret)
2968 goto error_power_off;
2969
2970 ret = cci_write(map: ov64a40->cci, OV64A40_REG_SMIA,
2971 OV64A40_REG_SMIA_STREAMING, NULL);
2972 if (ret)
2973 goto error_power_off;
2974
2975 /* Link frequency and flips cannot change while streaming. */
2976 __v4l2_ctrl_grab(ctrl: ov64a40->link_freq, grabbed: true);
2977 __v4l2_ctrl_grab(ctrl: ov64a40->vflip, grabbed: true);
2978 __v4l2_ctrl_grab(ctrl: ov64a40->hflip, grabbed: true);
2979
2980 /* delay: max(4096 xclk pulses, 150usec) + exposure time */
2981 timings = ov64a40_get_timings(ov64a40, link_freq_index: ov64a40->link_freq->cur.val);
2982 delay = DIV_ROUND_UP(4096, OV64A40_XCLK_FREQ / 1000 / 1000);
2983 delay = max(delay, 150ul);
2984
2985 /* The sensor has an internal x4 multiplier on the line length. */
2986 delay += DIV_ROUND_UP(timings->ppl * 4 * ov64a40->exposure->cur.val,
2987 OV64A40_PIXEL_RATE / 1000 / 1000);
2988 fsleep(usecs: delay);
2989
2990 return 0;
2991
2992error_power_off:
2993 pm_runtime_mark_last_busy(dev: ov64a40->dev);
2994 pm_runtime_put_autosuspend(dev: ov64a40->dev);
2995
2996 return ret;
2997}
2998
2999static int ov64a40_stop_streaming(struct ov64a40 *ov64a40,
3000 struct v4l2_subdev_state *state)
3001{
3002 cci_update_bits(map: ov64a40->cci, OV64A40_REG_SMIA, BIT(0), val: 0, NULL);
3003 pm_runtime_mark_last_busy(dev: ov64a40->dev);
3004 pm_runtime_put_autosuspend(dev: ov64a40->dev);
3005
3006 __v4l2_ctrl_grab(ctrl: ov64a40->link_freq, grabbed: false);
3007 __v4l2_ctrl_grab(ctrl: ov64a40->vflip, grabbed: false);
3008 __v4l2_ctrl_grab(ctrl: ov64a40->hflip, grabbed: false);
3009
3010 return 0;
3011}
3012
3013static int ov64a40_set_stream(struct v4l2_subdev *sd, int enable)
3014{
3015 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3016 struct v4l2_subdev_state *state;
3017 int ret;
3018
3019 state = v4l2_subdev_lock_and_get_active_state(sd);
3020 if (enable)
3021 ret = ov64a40_start_streaming(ov64a40, state);
3022 else
3023 ret = ov64a40_stop_streaming(ov64a40, state);
3024 v4l2_subdev_unlock_state(state);
3025
3026 return ret;
3027}
3028
3029static const struct v4l2_subdev_video_ops ov64a40_video_ops = {
3030 .s_stream = ov64a40_set_stream,
3031};
3032
3033static u32 ov64a40_mbus_code(struct ov64a40 *ov64a40)
3034{
3035 unsigned int index = ov64a40->hflip->val << 1 | ov64a40->vflip->val;
3036
3037 return ov64a40_mbus_codes[index];
3038}
3039
3040static void ov64a40_update_pad_fmt(struct ov64a40 *ov64a40,
3041 struct ov64a40_mode *mode,
3042 struct v4l2_mbus_framefmt *fmt)
3043{
3044 fmt->code = ov64a40_mbus_code(ov64a40);
3045 fmt->width = mode->width;
3046 fmt->height = mode->height;
3047 fmt->field = V4L2_FIELD_NONE;
3048 fmt->colorspace = V4L2_COLORSPACE_RAW;
3049 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3050 fmt->xfer_func = V4L2_XFER_FUNC_NONE;
3051 fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
3052}
3053
3054static int ov64a40_init_state(struct v4l2_subdev *sd,
3055 struct v4l2_subdev_state *state)
3056{
3057 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3058 struct v4l2_mbus_framefmt *format;
3059 struct v4l2_rect *crop;
3060
3061 format = v4l2_subdev_state_get_format(state, 0);
3062 ov64a40_update_pad_fmt(ov64a40, mode: &ov64a40_modes[0], fmt: format);
3063
3064 crop = v4l2_subdev_state_get_crop(state, 0);
3065 crop->top = OV64A40_PIXEL_ARRAY_TOP;
3066 crop->left = OV64A40_PIXEL_ARRAY_LEFT;
3067 crop->width = OV64A40_PIXEL_ARRAY_WIDTH;
3068 crop->height = OV64A40_PIXEL_ARRAY_HEIGHT;
3069
3070 return 0;
3071}
3072
3073static int ov64a40_enum_mbus_code(struct v4l2_subdev *sd,
3074 struct v4l2_subdev_state *state,
3075 struct v4l2_subdev_mbus_code_enum *code)
3076{
3077 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3078
3079 if (code->index)
3080 return -EINVAL;
3081
3082 code->code = ov64a40_mbus_code(ov64a40);
3083
3084 return 0;
3085}
3086
3087static int ov64a40_enum_frame_size(struct v4l2_subdev *sd,
3088 struct v4l2_subdev_state *state,
3089 struct v4l2_subdev_frame_size_enum *fse)
3090{
3091 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3092 struct ov64a40_mode *mode;
3093 u32 code;
3094
3095 if (fse->index >= ARRAY_SIZE(ov64a40_modes))
3096 return -EINVAL;
3097
3098 code = ov64a40_mbus_code(ov64a40);
3099 if (fse->code != code)
3100 return -EINVAL;
3101
3102 mode = &ov64a40_modes[fse->index];
3103 fse->min_width = mode->width;
3104 fse->max_width = mode->width;
3105 fse->min_height = mode->height;
3106 fse->max_height = mode->height;
3107
3108 return 0;
3109}
3110
3111static int ov64a40_get_selection(struct v4l2_subdev *sd,
3112 struct v4l2_subdev_state *state,
3113 struct v4l2_subdev_selection *sel)
3114{
3115 switch (sel->target) {
3116 case V4L2_SEL_TGT_CROP:
3117 sel->r = *v4l2_subdev_state_get_crop(state, 0);
3118
3119 return 0;
3120
3121 case V4L2_SEL_TGT_NATIVE_SIZE:
3122 sel->r.top = 0;
3123 sel->r.left = 0;
3124 sel->r.width = OV64A40_NATIVE_WIDTH;
3125 sel->r.height = OV64A40_NATIVE_HEIGHT;
3126
3127 return 0;
3128
3129 case V4L2_SEL_TGT_CROP_DEFAULT:
3130 case V4L2_SEL_TGT_CROP_BOUNDS:
3131 sel->r.top = OV64A40_PIXEL_ARRAY_TOP;
3132 sel->r.left = OV64A40_PIXEL_ARRAY_LEFT;
3133 sel->r.width = OV64A40_PIXEL_ARRAY_WIDTH;
3134 sel->r.height = OV64A40_PIXEL_ARRAY_HEIGHT;
3135
3136 return 0;
3137 }
3138
3139 return -EINVAL;
3140}
3141
3142static int ov64a40_set_format(struct v4l2_subdev *sd,
3143 struct v4l2_subdev_state *state,
3144 struct v4l2_subdev_format *fmt)
3145{
3146 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3147 struct v4l2_mbus_framefmt *format;
3148 struct ov64a40_mode *mode;
3149
3150 mode = v4l2_find_nearest_size(ov64a40_modes,
3151 ARRAY_SIZE(ov64a40_modes),
3152 width, height,
3153 fmt->format.width, fmt->format.height);
3154
3155 ov64a40_update_pad_fmt(ov64a40, mode, fmt: &fmt->format);
3156
3157 format = v4l2_subdev_state_get_format(state, 0);
3158 if (ov64a40->mode == mode && format->code == fmt->format.code)
3159 return 0;
3160
3161 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
3162 const struct ov64a40_timings *timings;
3163 int vblank_max, vblank_def;
3164 int hblank_val;
3165 int exp_max;
3166
3167 ov64a40->mode = mode;
3168 *v4l2_subdev_state_get_crop(state, 0) = mode->analogue_crop;
3169
3170 /* Update control limits according to the new mode. */
3171 timings = ov64a40_get_timings(ov64a40,
3172 link_freq_index: ov64a40->link_freq->cur.val);
3173 vblank_max = OV64A40_VTS_MAX - mode->height;
3174 vblank_def = timings->vts - mode->height;
3175 __v4l2_ctrl_modify_range(ctrl: ov64a40->vblank, OV64A40_VBLANK_MIN,
3176 max: vblank_max, step: 1, def: vblank_def);
3177 __v4l2_ctrl_s_ctrl(ctrl: ov64a40->vblank, val: vblank_def);
3178
3179 exp_max = timings->vts - OV64A40_EXPOSURE_MARGIN;
3180 __v4l2_ctrl_modify_range(ctrl: ov64a40->exposure,
3181 OV64A40_EXPOSURE_MIN, max: exp_max,
3182 step: 1, OV64A40_EXPOSURE_MIN);
3183
3184 hblank_val = timings->ppl * 4 - mode->width;
3185 __v4l2_ctrl_modify_range(ctrl: ov64a40->hblank,
3186 min: hblank_val, max: hblank_val, step: 1, def: hblank_val);
3187 }
3188
3189 *format = fmt->format;
3190
3191 return 0;
3192}
3193
3194static const struct v4l2_subdev_pad_ops ov64a40_pad_ops = {
3195 .enum_mbus_code = ov64a40_enum_mbus_code,
3196 .enum_frame_size = ov64a40_enum_frame_size,
3197 .get_fmt = v4l2_subdev_get_fmt,
3198 .set_fmt = ov64a40_set_format,
3199 .get_selection = ov64a40_get_selection,
3200};
3201
3202static const struct v4l2_subdev_ops ov64a40_subdev_ops = {
3203 .video = &ov64a40_video_ops,
3204 .pad = &ov64a40_pad_ops,
3205};
3206
3207static const struct v4l2_subdev_internal_ops ov64a40_internal_ops = {
3208 .init_state = ov64a40_init_state,
3209};
3210
3211static int ov64a40_power_on(struct device *dev)
3212{
3213 struct v4l2_subdev *sd = dev_get_drvdata(dev);
3214 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3215 int ret;
3216
3217 ret = clk_prepare_enable(clk: ov64a40->xclk);
3218 if (ret)
3219 return ret;
3220
3221 ret = regulator_bulk_enable(ARRAY_SIZE(ov64a40_supply_names),
3222 consumers: ov64a40->supplies);
3223 if (ret) {
3224 clk_disable_unprepare(clk: ov64a40->xclk);
3225 dev_err(dev, "Failed to enable regulators: %d\n", ret);
3226 return ret;
3227 }
3228
3229 gpiod_set_value_cansleep(desc: ov64a40->reset_gpio, value: 0);
3230
3231 fsleep(usecs: 5000);
3232
3233 return 0;
3234}
3235
3236static int ov64a40_power_off(struct device *dev)
3237{
3238 struct v4l2_subdev *sd = dev_get_drvdata(dev);
3239 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3240
3241 gpiod_set_value_cansleep(desc: ov64a40->reset_gpio, value: 1);
3242 regulator_bulk_disable(ARRAY_SIZE(ov64a40_supply_names),
3243 consumers: ov64a40->supplies);
3244 clk_disable_unprepare(clk: ov64a40->xclk);
3245
3246 return 0;
3247}
3248
3249static int ov64a40_link_freq_config(struct ov64a40 *ov64a40, int link_freq_id)
3250{
3251 s64 link_frequency;
3252 int ret = 0;
3253
3254 /* Default 456MHz with 24MHz input clock. */
3255 cci_multi_reg_write(map: ov64a40->cci, regs: ov64a40_pll_config,
3256 ARRAY_SIZE(ov64a40_pll_config), err: &ret);
3257
3258 /* Decrease the PLL1 multiplier to obtain 360MHz mipi link frequency. */
3259 link_frequency = ov64a40->link_frequencies[link_freq_id];
3260 if (link_frequency == OV64A40_LINK_FREQ_360M)
3261 cci_write(map: ov64a40->cci, OV64A40_PLL1_MULTIPLIER, val: 0x0078, err: &ret);
3262
3263 return ret;
3264}
3265
3266static int ov64a40_set_ctrl(struct v4l2_ctrl *ctrl)
3267{
3268 struct ov64a40 *ov64a40 = container_of(ctrl->handler, struct ov64a40,
3269 ctrl_handler);
3270 int pm_status;
3271 int ret = 0;
3272
3273 if (ctrl->id == V4L2_CID_VBLANK) {
3274 int exp_max = ov64a40->mode->height + ctrl->val
3275 - OV64A40_EXPOSURE_MARGIN;
3276 int exp_val = min(ov64a40->exposure->cur.val, exp_max);
3277
3278 __v4l2_ctrl_modify_range(ctrl: ov64a40->exposure,
3279 min: ov64a40->exposure->minimum,
3280 max: exp_max, step: 1, def: exp_val);
3281 }
3282
3283 pm_status = pm_runtime_get_if_active(dev: ov64a40->dev);
3284 if (!pm_status)
3285 return 0;
3286
3287 switch (ctrl->id) {
3288 case V4L2_CID_EXPOSURE:
3289 ret = cci_write(map: ov64a40->cci, OV64A40_REG_MEC_LONG_EXPO,
3290 val: ctrl->val, NULL);
3291 break;
3292 case V4L2_CID_ANALOGUE_GAIN:
3293 ret = cci_write(map: ov64a40->cci, OV64A40_REG_MEC_LONG_GAIN,
3294 val: ctrl->val << 1, NULL);
3295 break;
3296 case V4L2_CID_VBLANK: {
3297 int vts = ctrl->val + ov64a40->mode->height;
3298
3299 cci_write(map: ov64a40->cci, OV64A40_REG_TIMINGS_VTS_LOW, val: vts, err: &ret);
3300 cci_write(map: ov64a40->cci, OV64A40_REG_TIMINGS_VTS_MID,
3301 val: (vts >> 8), err: &ret);
3302 cci_write(map: ov64a40->cci, OV64A40_REG_TIMINGS_VTS_HIGH,
3303 val: (vts >> 16), err: &ret);
3304 break;
3305 }
3306 case V4L2_CID_VFLIP:
3307 ret = cci_update_bits(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL_20,
3308 OV64A40_TIMING_CTRL_20_VFLIP,
3309 val: ctrl->val << 2,
3310 NULL);
3311 break;
3312 case V4L2_CID_HFLIP:
3313 ret = cci_update_bits(map: ov64a40->cci, OV64A40_REG_TIMING_CTRL_21,
3314 OV64A40_TIMING_CTRL_21_HFLIP,
3315 val: ctrl->val ? 0
3316 : OV64A40_TIMING_CTRL_21_HFLIP,
3317 NULL);
3318 break;
3319 case V4L2_CID_TEST_PATTERN:
3320 ret = cci_write(map: ov64a40->cci, OV64A40_REG_TEST_PATTERN,
3321 val: ov64a40_test_pattern_val[ctrl->val], NULL);
3322 break;
3323 case V4L2_CID_LINK_FREQ:
3324 ret = ov64a40_link_freq_config(ov64a40, link_freq_id: ctrl->val);
3325 break;
3326 default:
3327 dev_err(ov64a40->dev, "Unhandled control: %#x\n", ctrl->id);
3328 ret = -EINVAL;
3329 break;
3330 }
3331
3332 if (pm_status > 0) {
3333 pm_runtime_mark_last_busy(dev: ov64a40->dev);
3334 pm_runtime_put_autosuspend(dev: ov64a40->dev);
3335 }
3336
3337 return ret;
3338}
3339
3340static const struct v4l2_ctrl_ops ov64a40_ctrl_ops = {
3341 .s_ctrl = ov64a40_set_ctrl,
3342};
3343
3344static int ov64a40_init_controls(struct ov64a40 *ov64a40)
3345{
3346 int exp_max, hblank_val, vblank_max, vblank_def;
3347 struct v4l2_ctrl_handler *hdlr = &ov64a40->ctrl_handler;
3348 struct v4l2_fwnode_device_properties props;
3349 const struct ov64a40_timings *timings;
3350 int ret;
3351
3352 ret = v4l2_ctrl_handler_init(hdlr, 11);
3353 if (ret)
3354 return ret;
3355
3356 v4l2_ctrl_new_std(hdl: hdlr, ops: &ov64a40_ctrl_ops, V4L2_CID_PIXEL_RATE,
3357 OV64A40_PIXEL_RATE, OV64A40_PIXEL_RATE, step: 1,
3358 OV64A40_PIXEL_RATE);
3359
3360 ov64a40->link_freq =
3361 v4l2_ctrl_new_int_menu(hdl: hdlr, ops: &ov64a40_ctrl_ops,
3362 V4L2_CID_LINK_FREQ,
3363 max: ov64a40->num_link_frequencies - 1,
3364 def: 0, qmenu_int: ov64a40->link_frequencies);
3365
3366 v4l2_ctrl_new_std_menu_items(hdl: hdlr, ops: &ov64a40_ctrl_ops,
3367 V4L2_CID_TEST_PATTERN,
3368 ARRAY_SIZE(ov64a40_test_pattern_menu) - 1,
3369 mask: 0, def: 0, qmenu: ov64a40_test_pattern_menu);
3370
3371 timings = ov64a40_get_timings(ov64a40, link_freq_index: 0);
3372 exp_max = timings->vts - OV64A40_EXPOSURE_MARGIN;
3373 ov64a40->exposure = v4l2_ctrl_new_std(hdl: hdlr, ops: &ov64a40_ctrl_ops,
3374 V4L2_CID_EXPOSURE,
3375 OV64A40_EXPOSURE_MIN, max: exp_max, step: 1,
3376 OV64A40_EXPOSURE_MIN);
3377
3378 hblank_val = timings->ppl * 4 - ov64a40->mode->width;
3379 ov64a40->hblank = v4l2_ctrl_new_std(hdl: hdlr, ops: &ov64a40_ctrl_ops,
3380 V4L2_CID_HBLANK, min: hblank_val,
3381 max: hblank_val, step: 1, def: hblank_val);
3382 if (ov64a40->hblank)
3383 ov64a40->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
3384
3385 vblank_def = timings->vts - ov64a40->mode->height;
3386 vblank_max = OV64A40_VTS_MAX - ov64a40->mode->height;
3387 ov64a40->vblank = v4l2_ctrl_new_std(hdl: hdlr, ops: &ov64a40_ctrl_ops,
3388 V4L2_CID_VBLANK, OV64A40_VBLANK_MIN,
3389 max: vblank_max, step: 1, def: vblank_def);
3390
3391 v4l2_ctrl_new_std(hdl: hdlr, ops: &ov64a40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
3392 OV64A40_ANA_GAIN_MIN, OV64A40_ANA_GAIN_MAX, step: 1,
3393 OV64A40_ANA_GAIN_DEFAULT);
3394
3395 ov64a40->hflip = v4l2_ctrl_new_std(hdl: hdlr, ops: &ov64a40_ctrl_ops,
3396 V4L2_CID_HFLIP, min: 0, max: 1, step: 1, def: 0);
3397 if (ov64a40->hflip)
3398 ov64a40->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
3399
3400 ov64a40->vflip = v4l2_ctrl_new_std(hdl: hdlr, ops: &ov64a40_ctrl_ops,
3401 V4L2_CID_VFLIP, min: 0, max: 1, step: 1, def: 0);
3402 if (ov64a40->vflip)
3403 ov64a40->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
3404
3405 if (hdlr->error) {
3406 ret = hdlr->error;
3407 dev_err(ov64a40->dev, "control init failed: %d\n", ret);
3408 goto error_free_hdlr;
3409 }
3410
3411 ret = v4l2_fwnode_device_parse(dev: ov64a40->dev, props: &props);
3412 if (ret)
3413 goto error_free_hdlr;
3414
3415 ret = v4l2_ctrl_new_fwnode_properties(hdl: hdlr, ctrl_ops: &ov64a40_ctrl_ops,
3416 p: &props);
3417 if (ret)
3418 goto error_free_hdlr;
3419
3420 ov64a40->sd.ctrl_handler = hdlr;
3421
3422 return 0;
3423
3424error_free_hdlr:
3425 v4l2_ctrl_handler_free(hdl: hdlr);
3426 return ret;
3427}
3428
3429static int ov64a40_identify(struct ov64a40 *ov64a40)
3430{
3431 int ret;
3432 u64 id;
3433
3434 ret = cci_read(map: ov64a40->cci, OV64A40_REG_CHIP_ID, val: &id, NULL);
3435 if (ret) {
3436 dev_err(ov64a40->dev, "Failed to read chip id: %d\n", ret);
3437 return ret;
3438 }
3439
3440 if (id != OV64A40_CHIP_ID) {
3441 dev_err(ov64a40->dev, "chip id mismatch: %#llx\n", id);
3442 return -ENODEV;
3443 }
3444
3445 dev_dbg(ov64a40->dev, "OV64A40 chip identified: %#llx\n", id);
3446
3447 return 0;
3448}
3449
3450static int ov64a40_parse_dt(struct ov64a40 *ov64a40)
3451{
3452 struct v4l2_fwnode_endpoint v4l2_fwnode = {
3453 .bus_type = V4L2_MBUS_CSI2_DPHY
3454 };
3455 struct fwnode_handle *endpoint;
3456 unsigned int i;
3457 int ret;
3458
3459 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(ov64a40->dev),
3460 NULL);
3461 if (!endpoint) {
3462 dev_err(ov64a40->dev, "Failed to find endpoint\n");
3463 return -EINVAL;
3464 }
3465
3466 ret = v4l2_fwnode_endpoint_alloc_parse(fwnode: endpoint, vep: &v4l2_fwnode);
3467 fwnode_handle_put(fwnode: endpoint);
3468 if (ret) {
3469 dev_err(ov64a40->dev, "Failed to parse endpoint\n");
3470 return ret;
3471 }
3472
3473 if (v4l2_fwnode.bus.mipi_csi2.num_data_lanes != 2) {
3474 dev_err(ov64a40->dev, "Unsupported number of data lanes: %u\n",
3475 v4l2_fwnode.bus.mipi_csi2.num_data_lanes);
3476 v4l2_fwnode_endpoint_free(vep: &v4l2_fwnode);
3477 return -EINVAL;
3478 }
3479
3480 if (!v4l2_fwnode.nr_of_link_frequencies) {
3481 dev_warn(ov64a40->dev, "no link frequencies defined\n");
3482 v4l2_fwnode_endpoint_free(vep: &v4l2_fwnode);
3483 return -EINVAL;
3484 }
3485
3486 if (v4l2_fwnode.nr_of_link_frequencies > 2) {
3487 dev_warn(ov64a40->dev,
3488 "Unsupported number of link frequencies\n");
3489 v4l2_fwnode_endpoint_free(vep: &v4l2_fwnode);
3490 return -EINVAL;
3491 }
3492
3493 ov64a40->link_frequencies =
3494 devm_kcalloc(dev: ov64a40->dev, n: v4l2_fwnode.nr_of_link_frequencies,
3495 size: sizeof(v4l2_fwnode.link_frequencies[0]),
3496 GFP_KERNEL);
3497 if (!ov64a40->link_frequencies) {
3498 v4l2_fwnode_endpoint_free(vep: &v4l2_fwnode);
3499 return -ENOMEM;
3500 }
3501 ov64a40->num_link_frequencies = v4l2_fwnode.nr_of_link_frequencies;
3502
3503 for (i = 0; i < v4l2_fwnode.nr_of_link_frequencies; ++i) {
3504 if (v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_360M &&
3505 v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_456M) {
3506 dev_err(ov64a40->dev,
3507 "Unsupported link frequency %lld\n",
3508 v4l2_fwnode.link_frequencies[i]);
3509 v4l2_fwnode_endpoint_free(vep: &v4l2_fwnode);
3510 return -EINVAL;
3511 }
3512
3513 ov64a40->link_frequencies[i] = v4l2_fwnode.link_frequencies[i];
3514 }
3515
3516 v4l2_fwnode_endpoint_free(vep: &v4l2_fwnode);
3517
3518 return 0;
3519}
3520
3521static int ov64a40_get_regulators(struct ov64a40 *ov64a40)
3522{
3523 struct i2c_client *client = v4l2_get_subdevdata(sd: &ov64a40->sd);
3524 unsigned int i;
3525
3526 for (i = 0; i < ARRAY_SIZE(ov64a40_supply_names); i++)
3527 ov64a40->supplies[i].supply = ov64a40_supply_names[i];
3528
3529 return devm_regulator_bulk_get(dev: &client->dev,
3530 ARRAY_SIZE(ov64a40_supply_names),
3531 consumers: ov64a40->supplies);
3532}
3533
3534static int ov64a40_probe(struct i2c_client *client)
3535{
3536 struct ov64a40 *ov64a40;
3537 u32 xclk_freq;
3538 int ret;
3539
3540 ov64a40 = devm_kzalloc(dev: &client->dev, size: sizeof(*ov64a40), GFP_KERNEL);
3541 if (!ov64a40)
3542 return -ENOMEM;
3543
3544 ov64a40->dev = &client->dev;
3545 v4l2_i2c_subdev_init(sd: &ov64a40->sd, client, ops: &ov64a40_subdev_ops);
3546
3547 ov64a40->cci = devm_cci_regmap_init_i2c(client, reg_addr_bits: 16);
3548 if (IS_ERR(ptr: ov64a40->cci)) {
3549 dev_err(&client->dev, "Failed to initialize CCI\n");
3550 return PTR_ERR(ptr: ov64a40->cci);
3551 }
3552
3553 ov64a40->xclk = devm_clk_get(dev: &client->dev, NULL);
3554 if (IS_ERR(ptr: ov64a40->xclk))
3555 return dev_err_probe(dev: &client->dev, err: PTR_ERR(ptr: ov64a40->xclk),
3556 fmt: "Failed to get clock\n");
3557
3558 xclk_freq = clk_get_rate(clk: ov64a40->xclk);
3559 if (xclk_freq != OV64A40_XCLK_FREQ) {
3560 dev_err(&client->dev, "Unsupported xclk frequency %u\n",
3561 xclk_freq);
3562 return -EINVAL;
3563 }
3564
3565 ret = ov64a40_get_regulators(ov64a40);
3566 if (ret)
3567 return ret;
3568
3569 ov64a40->reset_gpio = devm_gpiod_get_optional(dev: &client->dev, con_id: "reset",
3570 flags: GPIOD_OUT_LOW);
3571 if (IS_ERR(ptr: ov64a40->reset_gpio))
3572 return dev_err_probe(dev: &client->dev, err: PTR_ERR(ptr: ov64a40->reset_gpio),
3573 fmt: "Failed to get reset gpio\n");
3574
3575 ret = ov64a40_parse_dt(ov64a40);
3576 if (ret)
3577 return ret;
3578
3579 ret = ov64a40_power_on(dev: &client->dev);
3580 if (ret)
3581 return ret;
3582
3583 ret = ov64a40_identify(ov64a40);
3584 if (ret)
3585 goto error_poweroff;
3586
3587 ov64a40->mode = &ov64a40_modes[0];
3588
3589 pm_runtime_set_active(dev: &client->dev);
3590 pm_runtime_get_noresume(dev: &client->dev);
3591 pm_runtime_enable(dev: &client->dev);
3592 pm_runtime_set_autosuspend_delay(dev: &client->dev, delay: 1000);
3593 pm_runtime_use_autosuspend(dev: &client->dev);
3594
3595 ret = ov64a40_init_controls(ov64a40);
3596 if (ret)
3597 goto error_poweroff;
3598
3599 /* Initialize subdev */
3600 ov64a40->sd.internal_ops = &ov64a40_internal_ops;
3601 ov64a40->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
3602 ov64a40->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
3603
3604 ov64a40->pad.flags = MEDIA_PAD_FL_SOURCE;
3605 ret = media_entity_pads_init(entity: &ov64a40->sd.entity, num_pads: 1, pads: &ov64a40->pad);
3606 if (ret) {
3607 dev_err(&client->dev, "failed to init entity pads: %d\n", ret);
3608 goto error_handler_free;
3609 }
3610
3611 ov64a40->sd.state_lock = ov64a40->ctrl_handler.lock;
3612 ret = v4l2_subdev_init_finalize(&ov64a40->sd);
3613 if (ret < 0) {
3614 dev_err(&client->dev, "subdev init error: %d\n", ret);
3615 goto error_media_entity;
3616 }
3617
3618 ret = v4l2_async_register_subdev_sensor(sd: &ov64a40->sd);
3619 if (ret < 0) {
3620 dev_err(&client->dev,
3621 "failed to register sensor sub-device: %d\n", ret);
3622 goto error_subdev_cleanup;
3623 }
3624
3625 pm_runtime_mark_last_busy(dev: &client->dev);
3626 pm_runtime_put_autosuspend(dev: &client->dev);
3627
3628 return 0;
3629
3630error_subdev_cleanup:
3631 v4l2_subdev_cleanup(sd: &ov64a40->sd);
3632error_media_entity:
3633 media_entity_cleanup(entity: &ov64a40->sd.entity);
3634error_handler_free:
3635 v4l2_ctrl_handler_free(hdl: ov64a40->sd.ctrl_handler);
3636error_poweroff:
3637 ov64a40_power_off(dev: &client->dev);
3638 pm_runtime_set_suspended(dev: &client->dev);
3639
3640 return ret;
3641}
3642
3643static void ov64a40_remove(struct i2c_client *client)
3644{
3645 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3646
3647 v4l2_async_unregister_subdev(sd);
3648 v4l2_subdev_cleanup(sd);
3649 media_entity_cleanup(entity: &sd->entity);
3650 v4l2_ctrl_handler_free(hdl: sd->ctrl_handler);
3651
3652 pm_runtime_disable(dev: &client->dev);
3653 if (!pm_runtime_status_suspended(dev: &client->dev))
3654 ov64a40_power_off(dev: &client->dev);
3655 pm_runtime_set_suspended(dev: &client->dev);
3656}
3657
3658static const struct of_device_id ov64a40_of_ids[] = {
3659 { .compatible = "ovti,ov64a40" },
3660 { /* sentinel */ }
3661};
3662MODULE_DEVICE_TABLE(of, ov64a40_of_ids);
3663
3664static const struct dev_pm_ops ov64a40_pm_ops = {
3665 SET_RUNTIME_PM_OPS(ov64a40_power_off, ov64a40_power_on, NULL)
3666};
3667
3668static struct i2c_driver ov64a40_i2c_driver = {
3669 .driver = {
3670 .name = "ov64a40",
3671 .of_match_table = ov64a40_of_ids,
3672 .pm = &ov64a40_pm_ops,
3673 },
3674 .probe = ov64a40_probe,
3675 .remove = ov64a40_remove,
3676};
3677
3678module_i2c_driver(ov64a40_i2c_driver);
3679
3680MODULE_AUTHOR("Jacopo Mondi <jacopo.mondi@ideasonboard.com>");
3681MODULE_DESCRIPTION("OmniVision OV64A40 sensor driver");
3682MODULE_LICENSE("GPL");
3683

source code of linux/drivers/media/i2c/ov64a40.c