1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * OmniVision OV96xx Camera Header File |
4 | * |
5 | * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com> |
6 | */ |
7 | |
8 | #ifndef __DRIVERS_MEDIA_VIDEO_OV9640_H__ |
9 | #define __DRIVERS_MEDIA_VIDEO_OV9640_H__ |
10 | |
11 | /* Register definitions */ |
12 | #define OV9640_GAIN 0x00 |
13 | #define OV9640_BLUE 0x01 |
14 | #define OV9640_RED 0x02 |
15 | #define OV9640_VFER 0x03 |
16 | #define OV9640_COM1 0x04 |
17 | #define OV9640_BAVE 0x05 |
18 | #define OV9640_GEAVE 0x06 |
19 | #define OV9640_RSID 0x07 |
20 | #define OV9640_RAVE 0x08 |
21 | #define OV9640_COM2 0x09 |
22 | #define OV9640_PID 0x0a |
23 | #define OV9640_VER 0x0b |
24 | #define OV9640_COM3 0x0c |
25 | #define OV9640_COM4 0x0d |
26 | #define OV9640_COM5 0x0e |
27 | #define OV9640_COM6 0x0f |
28 | #define OV9640_AECH 0x10 |
29 | #define OV9640_CLKRC 0x11 |
30 | #define OV9640_COM7 0x12 |
31 | #define OV9640_COM8 0x13 |
32 | #define OV9640_COM9 0x14 |
33 | #define OV9640_COM10 0x15 |
34 | /* 0x16 - RESERVED */ |
35 | #define OV9640_HSTART 0x17 |
36 | #define OV9640_HSTOP 0x18 |
37 | #define OV9640_VSTART 0x19 |
38 | #define OV9640_VSTOP 0x1a |
39 | #define OV9640_PSHFT 0x1b |
40 | #define OV9640_MIDH 0x1c |
41 | #define OV9640_MIDL 0x1d |
42 | #define OV9640_MVFP 0x1e |
43 | #define OV9640_LAEC 0x1f |
44 | #define OV9640_BOS 0x20 |
45 | #define OV9640_GBOS 0x21 |
46 | #define OV9640_GROS 0x22 |
47 | #define OV9640_ROS 0x23 |
48 | #define OV9640_AEW 0x24 |
49 | #define OV9640_AEB 0x25 |
50 | #define OV9640_VPT 0x26 |
51 | #define OV9640_BBIAS 0x27 |
52 | #define OV9640_GBBIAS 0x28 |
53 | /* 0x29 - RESERVED */ |
54 | #define OV9640_EXHCH 0x2a |
55 | #define OV9640_EXHCL 0x2b |
56 | #define OV9640_RBIAS 0x2c |
57 | #define OV9640_ADVFL 0x2d |
58 | #define OV9640_ADVFH 0x2e |
59 | #define OV9640_YAVE 0x2f |
60 | #define OV9640_HSYST 0x30 |
61 | #define OV9640_HSYEN 0x31 |
62 | #define OV9640_HREF 0x32 |
63 | #define OV9640_CHLF 0x33 |
64 | #define OV9640_ARBLM 0x34 |
65 | /* 0x35..0x36 - RESERVED */ |
66 | #define OV9640_ADC 0x37 |
67 | #define OV9640_ACOM 0x38 |
68 | #define OV9640_OFON 0x39 |
69 | #define OV9640_TSLB 0x3a |
70 | #define OV9640_COM11 0x3b |
71 | #define OV9640_COM12 0x3c |
72 | #define OV9640_COM13 0x3d |
73 | #define OV9640_COM14 0x3e |
74 | #define OV9640_EDGE 0x3f |
75 | #define OV9640_COM15 0x40 |
76 | #define OV9640_COM16 0x41 |
77 | #define OV9640_COM17 0x42 |
78 | /* 0x43..0x4e - RESERVED */ |
79 | #define OV9640_MTX1 0x4f |
80 | #define OV9640_MTX2 0x50 |
81 | #define OV9640_MTX3 0x51 |
82 | #define OV9640_MTX4 0x52 |
83 | #define OV9640_MTX5 0x53 |
84 | #define OV9640_MTX6 0x54 |
85 | #define OV9640_MTX7 0x55 |
86 | #define OV9640_MTX8 0x56 |
87 | #define OV9640_MTX9 0x57 |
88 | #define OV9640_MTXS 0x58 |
89 | /* 0x59..0x61 - RESERVED */ |
90 | #define OV9640_LCC1 0x62 |
91 | #define OV9640_LCC2 0x63 |
92 | #define OV9640_LCC3 0x64 |
93 | #define OV9640_LCC4 0x65 |
94 | #define OV9640_LCC5 0x66 |
95 | #define OV9640_MANU 0x67 |
96 | #define OV9640_MANV 0x68 |
97 | #define OV9640_HV 0x69 |
98 | #define OV9640_MBD 0x6a |
99 | #define OV9640_DBLV 0x6b |
100 | #define OV9640_GSP 0x6c /* ... till 0x7b */ |
101 | #define OV9640_GST 0x7c /* ... till 0x8a */ |
102 | |
103 | #define OV9640_CLKRC_DPLL_EN 0x80 |
104 | #define OV9640_CLKRC_DIRECT 0x40 |
105 | #define OV9640_CLKRC_DIV(x) ((x) & 0x3f) |
106 | |
107 | #define OV9640_PSHFT_VAL(x) ((x) & 0xff) |
108 | |
109 | #define OV9640_ACOM_2X_ANALOG 0x80 |
110 | #define OV9640_ACOM_RSVD 0x12 |
111 | |
112 | #define OV9640_MVFP_V 0x10 |
113 | #define OV9640_MVFP_H 0x20 |
114 | |
115 | #define OV9640_COM1_HREF_NOSKIP 0x00 |
116 | #define OV9640_COM1_HREF_2SKIP 0x04 |
117 | #define OV9640_COM1_HREF_3SKIP 0x08 |
118 | #define OV9640_COM1_QQFMT 0x20 |
119 | |
120 | #define OV9640_COM2_SSM 0x10 |
121 | |
122 | #define OV9640_COM3_VP 0x04 |
123 | |
124 | #define OV9640_COM4_QQ_VP 0x80 |
125 | #define OV9640_COM4_RSVD 0x40 |
126 | |
127 | #define OV9640_COM5_SYSCLK 0x80 |
128 | #define OV9640_COM5_LONGEXP 0x01 |
129 | |
130 | #define OV9640_COM6_OPT_BLC 0x40 |
131 | #define OV9640_COM6_ADBLC_BIAS 0x08 |
132 | #define OV9640_COM6_FMT_RST 0x82 |
133 | #define OV9640_COM6_ADBLC_OPTEN 0x01 |
134 | |
135 | #define OV9640_COM7_RAW_RGB 0x01 |
136 | #define OV9640_COM7_RGB 0x04 |
137 | #define OV9640_COM7_QCIF 0x08 |
138 | #define OV9640_COM7_QVGA 0x10 |
139 | #define OV9640_COM7_CIF 0x20 |
140 | #define OV9640_COM7_VGA 0x40 |
141 | #define OV9640_COM7_SCCB_RESET 0x80 |
142 | |
143 | #define OV9640_TSLB_YVYU_YUYV 0x04 |
144 | #define OV9640_TSLB_YUYV_UYVY 0x08 |
145 | |
146 | #define OV9640_COM12_YUV_AVG 0x04 |
147 | #define OV9640_COM12_RSVD 0x40 |
148 | |
149 | #define OV9640_COM13_GAMMA_NONE 0x00 |
150 | #define OV9640_COM13_GAMMA_Y 0x40 |
151 | #define OV9640_COM13_GAMMA_RAW 0x80 |
152 | #define OV9640_COM13_RGB_AVG 0x20 |
153 | #define OV9640_COM13_MATRIX_EN 0x10 |
154 | #define OV9640_COM13_Y_DELAY_EN 0x08 |
155 | #define OV9640_COM13_YUV_DLY(x) ((x) & 0x07) |
156 | |
157 | #define OV9640_COM15_OR_00FF 0x00 |
158 | #define OV9640_COM15_OR_01FE 0x40 |
159 | #define OV9640_COM15_OR_10F0 0xc0 |
160 | #define OV9640_COM15_RGB_NORM 0x00 |
161 | #define OV9640_COM15_RGB_565 0x10 |
162 | #define OV9640_COM15_RGB_555 0x30 |
163 | |
164 | #define OV9640_COM16_RB_AVG 0x01 |
165 | |
166 | /* IDs */ |
167 | #define OV9640_V2 0x9648 |
168 | #define OV9640_V3 0x9649 |
169 | #define VERSION(pid, ver) (((pid) << 8) | ((ver) & 0xFF)) |
170 | |
171 | /* supported resolutions */ |
172 | enum { |
173 | W_QQCIF = 88, |
174 | W_QQVGA = 160, |
175 | W_QCIF = 176, |
176 | W_QVGA = 320, |
177 | W_CIF = 352, |
178 | W_VGA = 640, |
179 | W_SXGA = 1280 |
180 | }; |
181 | #define H_SXGA 960 |
182 | |
183 | /* Misc. structures */ |
184 | struct ov9640_reg_alt { |
185 | u8 com7; |
186 | u8 com12; |
187 | u8 com13; |
188 | u8 com15; |
189 | }; |
190 | |
191 | struct ov9640_reg { |
192 | u8 reg; |
193 | u8 val; |
194 | }; |
195 | |
196 | struct ov9640_priv { |
197 | struct v4l2_subdev subdev; |
198 | struct v4l2_ctrl_handler hdl; |
199 | struct clk *clk; |
200 | struct gpio_desc *gpio_power; |
201 | struct gpio_desc *gpio_reset; |
202 | |
203 | int model; |
204 | int revision; |
205 | }; |
206 | |
207 | #endif /* __DRIVERS_MEDIA_VIDEO_OV9640_H__ */ |
208 | |