1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Driver for the Conexant CX23885 PCIe bridge |
4 | * |
5 | * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> |
6 | */ |
7 | |
8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
9 | |
10 | #include <linux/pci.h> |
11 | #include <linux/i2c.h> |
12 | #include <linux/kdev_t.h> |
13 | #include <linux/slab.h> |
14 | |
15 | #include <media/v4l2-device.h> |
16 | #include <media/v4l2-fh.h> |
17 | #include <media/v4l2-ctrls.h> |
18 | #include <media/tuner.h> |
19 | #include <media/tveeprom.h> |
20 | #include <media/videobuf2-dma-sg.h> |
21 | #include <media/videobuf2-dvb.h> |
22 | #include <media/rc-core.h> |
23 | |
24 | #include "cx23885-reg.h" |
25 | #include "media/drv-intf/cx2341x.h" |
26 | |
27 | #include <linux/mutex.h> |
28 | |
29 | #define CX23885_VERSION "0.0.4" |
30 | |
31 | #define UNSET (-1U) |
32 | |
33 | #define CX23885_MAXBOARDS 8 |
34 | |
35 | /* Max number of inputs by card */ |
36 | #define MAX_CX23885_INPUT 8 |
37 | #define INPUT(nr) (&cx23885_boards[dev->board].input[nr]) |
38 | |
39 | #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */ |
40 | |
41 | #define CX23885_BOARD_NOAUTO UNSET |
42 | #define CX23885_BOARD_UNKNOWN 0 |
43 | #define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1 |
44 | #define CX23885_BOARD_HAUPPAUGE_HVR1800 2 |
45 | #define CX23885_BOARD_HAUPPAUGE_HVR1250 3 |
46 | #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4 |
47 | #define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5 |
48 | #define CX23885_BOARD_HAUPPAUGE_HVR1500 6 |
49 | #define CX23885_BOARD_HAUPPAUGE_HVR1200 7 |
50 | #define CX23885_BOARD_HAUPPAUGE_HVR1700 8 |
51 | #define CX23885_BOARD_HAUPPAUGE_HVR1400 9 |
52 | #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10 |
53 | #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11 |
54 | #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12 |
55 | #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13 |
56 | #define CX23885_BOARD_TBS_6920 14 |
57 | #define CX23885_BOARD_TEVII_S470 15 |
58 | #define CX23885_BOARD_DVBWORLD_2005 16 |
59 | #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17 |
60 | #define CX23885_BOARD_HAUPPAUGE_HVR1270 18 |
61 | #define CX23885_BOARD_HAUPPAUGE_HVR1275 19 |
62 | #define CX23885_BOARD_HAUPPAUGE_HVR1255 20 |
63 | #define CX23885_BOARD_HAUPPAUGE_HVR1210 21 |
64 | #define CX23885_BOARD_MYGICA_X8506 22 |
65 | #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23 |
66 | #define CX23885_BOARD_HAUPPAUGE_HVR1850 24 |
67 | #define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25 |
68 | #define CX23885_BOARD_HAUPPAUGE_HVR1290 26 |
69 | #define CX23885_BOARD_MYGICA_X8558PRO 27 |
70 | #define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28 |
71 | #define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29 |
72 | #define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30 |
73 | #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31 |
74 | #define CX23885_BOARD_MPX885 32 |
75 | #define CX23885_BOARD_MYGICA_X8507 33 |
76 | #define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34 |
77 | #define CX23885_BOARD_TEVII_S471 35 |
78 | #define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36 |
79 | #define CX23885_BOARD_PROF_8000 37 |
80 | #define CX23885_BOARD_HAUPPAUGE_HVR4400 38 |
81 | #define CX23885_BOARD_AVERMEDIA_HC81R 39 |
82 | #define CX23885_BOARD_TBS_6981 40 |
83 | #define CX23885_BOARD_TBS_6980 41 |
84 | #define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42 |
85 | #define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43 |
86 | #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2 44 |
87 | #define CX23885_BOARD_DVBSKY_T9580 45 |
88 | #define CX23885_BOARD_DVBSKY_T980C 46 |
89 | #define CX23885_BOARD_DVBSKY_S950C 47 |
90 | #define CX23885_BOARD_TT_CT2_4500_CI 48 |
91 | #define CX23885_BOARD_DVBSKY_S950 49 |
92 | #define CX23885_BOARD_DVBSKY_S952 50 |
93 | #define CX23885_BOARD_DVBSKY_T982 51 |
94 | #define CX23885_BOARD_HAUPPAUGE_HVR5525 52 |
95 | #define CX23885_BOARD_HAUPPAUGE_STARBURST 53 |
96 | #define CX23885_BOARD_VIEWCAST_260E 54 |
97 | #define CX23885_BOARD_VIEWCAST_460E 55 |
98 | #define CX23885_BOARD_HAUPPAUGE_QUADHD_DVB 56 |
99 | #define CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC 57 |
100 | #define CX23885_BOARD_HAUPPAUGE_HVR1265_K4 58 |
101 | #define CX23885_BOARD_HAUPPAUGE_STARBURST2 59 |
102 | #define CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885 60 |
103 | #define CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885 61 |
104 | #define CX23885_BOARD_AVERMEDIA_CE310B 62 |
105 | |
106 | #define GPIO_0 0x00000001 |
107 | #define GPIO_1 0x00000002 |
108 | #define GPIO_2 0x00000004 |
109 | #define GPIO_3 0x00000008 |
110 | #define GPIO_4 0x00000010 |
111 | #define GPIO_5 0x00000020 |
112 | #define GPIO_6 0x00000040 |
113 | #define GPIO_7 0x00000080 |
114 | #define GPIO_8 0x00000100 |
115 | #define GPIO_9 0x00000200 |
116 | #define GPIO_10 0x00000400 |
117 | #define GPIO_11 0x00000800 |
118 | #define GPIO_12 0x00001000 |
119 | #define GPIO_13 0x00002000 |
120 | #define GPIO_14 0x00004000 |
121 | #define GPIO_15 0x00008000 |
122 | |
123 | /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */ |
124 | #define CX23885_NORMS (\ |
125 | V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \ |
126 | V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \ |
127 | V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \ |
128 | V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK) |
129 | |
130 | struct cx23885_fmt { |
131 | u32 fourcc; /* v4l2 format id */ |
132 | int depth; |
133 | int flags; |
134 | u32 cxformat; |
135 | }; |
136 | |
137 | struct cx23885_tvnorm { |
138 | char *name; |
139 | v4l2_std_id id; |
140 | u32 cxiformat; |
141 | u32 cxoformat; |
142 | }; |
143 | |
144 | enum cx23885_itype { |
145 | CX23885_VMUX_COMPOSITE1 = 1, |
146 | CX23885_VMUX_COMPOSITE2, |
147 | CX23885_VMUX_COMPOSITE3, |
148 | CX23885_VMUX_COMPOSITE4, |
149 | CX23885_VMUX_SVIDEO, |
150 | CX23885_VMUX_COMPONENT, |
151 | CX23885_VMUX_TELEVISION, |
152 | CX23885_VMUX_CABLE, |
153 | CX23885_VMUX_DVB, |
154 | CX23885_VMUX_DEBUG, |
155 | CX23885_RADIO, |
156 | }; |
157 | |
158 | enum cx23885_src_sel_type { |
159 | CX23885_SRC_SEL_EXT_656_VIDEO = 0, |
160 | CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO |
161 | }; |
162 | |
163 | struct cx23885_riscmem { |
164 | unsigned int size; |
165 | __le32 *cpu; |
166 | __le32 *jmp; |
167 | dma_addr_t dma; |
168 | }; |
169 | |
170 | /* buffer for one video frame */ |
171 | struct cx23885_buffer { |
172 | /* common v4l buffer stuff -- must be first */ |
173 | struct vb2_v4l2_buffer vb; |
174 | struct list_head queue; |
175 | |
176 | /* cx23885 specific */ |
177 | unsigned int bpl; |
178 | struct cx23885_riscmem risc; |
179 | struct cx23885_fmt *fmt; |
180 | u32 count; |
181 | }; |
182 | |
183 | struct cx23885_input { |
184 | enum cx23885_itype type; |
185 | unsigned int vmux; |
186 | unsigned int amux; |
187 | u32 gpio0, gpio1, gpio2, gpio3; |
188 | }; |
189 | |
190 | typedef enum { |
191 | CX23885_MPEG_UNDEFINED = 0, |
192 | CX23885_MPEG_DVB, |
193 | CX23885_ANALOG_VIDEO, |
194 | CX23885_MPEG_ENCODER, |
195 | } port_t; |
196 | |
197 | struct cx23885_board { |
198 | char *name; |
199 | port_t porta, portb, portc; |
200 | int num_fds_portb, num_fds_portc; |
201 | unsigned int tuner_type; |
202 | unsigned int radio_type; |
203 | unsigned char tuner_addr; |
204 | unsigned char radio_addr; |
205 | unsigned int tuner_bus; |
206 | |
207 | /* Vendors can and do run the PCIe bridge at different |
208 | * clock rates, driven physically by crystals on the PCBs. |
209 | * The core has to accommodate this. This allows the user |
210 | * to add new boards with new frequencys. The value is |
211 | * expressed in Hz. |
212 | * |
213 | * The core framework will default this value based on |
214 | * current designs, but it can vary. |
215 | */ |
216 | u32 clk_freq; |
217 | struct cx23885_input input[MAX_CX23885_INPUT]; |
218 | int ci_type; /* for NetUP */ |
219 | /* Force bottom field first during DMA (888 workaround) */ |
220 | u32 force_bff; |
221 | }; |
222 | |
223 | struct cx23885_subid { |
224 | u16 subvendor; |
225 | u16 subdevice; |
226 | u32 card; |
227 | }; |
228 | |
229 | struct cx23885_i2c { |
230 | struct cx23885_dev *dev; |
231 | |
232 | int nr; |
233 | |
234 | /* i2c i/o */ |
235 | struct i2c_adapter i2c_adap; |
236 | struct i2c_client i2c_client; |
237 | u32 i2c_rc; |
238 | |
239 | /* 885 registers used for raw address */ |
240 | u32 i2c_period; |
241 | u32 reg_ctrl; |
242 | u32 reg_stat; |
243 | u32 reg_addr; |
244 | u32 reg_rdata; |
245 | u32 reg_wdata; |
246 | }; |
247 | |
248 | struct cx23885_dmaqueue { |
249 | struct list_head active; |
250 | u32 count; |
251 | }; |
252 | |
253 | struct cx23885_tsport { |
254 | struct cx23885_dev *dev; |
255 | |
256 | unsigned nr; |
257 | int sram_chno; |
258 | |
259 | struct vb2_dvb_frontends frontends; |
260 | |
261 | /* dma queues */ |
262 | struct cx23885_dmaqueue mpegq; |
263 | u32 ts_packet_size; |
264 | u32 ts_packet_count; |
265 | |
266 | int width; |
267 | int height; |
268 | |
269 | spinlock_t slock; |
270 | |
271 | /* registers */ |
272 | u32 reg_gpcnt; |
273 | u32 reg_gpcnt_ctl; |
274 | u32 reg_dma_ctl; |
275 | u32 reg_lngth; |
276 | u32 reg_hw_sop_ctrl; |
277 | u32 reg_gen_ctrl; |
278 | u32 reg_bd_pkt_status; |
279 | u32 reg_sop_status; |
280 | u32 reg_fifo_ovfl_stat; |
281 | u32 reg_vld_misc; |
282 | u32 reg_ts_clk_en; |
283 | u32 reg_ts_int_msk; |
284 | u32 reg_ts_int_stat; |
285 | u32 reg_src_sel; |
286 | |
287 | /* Default register vals */ |
288 | int pci_irqmask; |
289 | u32 dma_ctl_val; |
290 | u32 ts_int_msk_val; |
291 | u32 gen_ctrl_val; |
292 | u32 ts_clk_en_val; |
293 | u32 src_sel_val; |
294 | u32 vld_misc_val; |
295 | u32 hw_sop_ctrl_val; |
296 | |
297 | /* Allow a single tsport to have multiple frontends */ |
298 | u32 num_frontends; |
299 | void (*gate_ctrl)(struct cx23885_tsport *port, int open); |
300 | void *port_priv; |
301 | |
302 | /* Workaround for a temp dvb_frontend that the tuner can attached to */ |
303 | struct dvb_frontend analog_fe; |
304 | |
305 | struct i2c_client *i2c_client_demod; |
306 | struct i2c_client *i2c_client_tuner; |
307 | struct i2c_client *i2c_client_sec; |
308 | struct i2c_client *i2c_client_ci; |
309 | |
310 | int (*set_frontend)(struct dvb_frontend *fe); |
311 | int (*fe_set_voltage)(struct dvb_frontend *fe, |
312 | enum fe_sec_voltage voltage); |
313 | }; |
314 | |
315 | struct cx23885_kernel_ir { |
316 | struct cx23885_dev *cx; |
317 | char *name; |
318 | char *phys; |
319 | |
320 | struct rc_dev *rc; |
321 | }; |
322 | |
323 | struct cx23885_audio_buffer { |
324 | unsigned int bpl; |
325 | struct cx23885_riscmem risc; |
326 | void *vaddr; |
327 | struct scatterlist *sglist; |
328 | int sglen; |
329 | unsigned long nr_pages; |
330 | }; |
331 | |
332 | struct cx23885_audio_dev { |
333 | struct cx23885_dev *dev; |
334 | |
335 | struct pci_dev *pci; |
336 | |
337 | struct snd_card *card; |
338 | |
339 | spinlock_t lock; |
340 | |
341 | atomic_t count; |
342 | |
343 | unsigned int dma_size; |
344 | unsigned int period_size; |
345 | unsigned int num_periods; |
346 | |
347 | struct cx23885_audio_buffer *buf; |
348 | |
349 | struct snd_pcm_substream *substream; |
350 | }; |
351 | |
352 | struct cx23885_dev { |
353 | atomic_t refcount; |
354 | struct v4l2_device v4l2_dev; |
355 | struct v4l2_ctrl_handler ctrl_handler; |
356 | |
357 | /* pci stuff */ |
358 | struct pci_dev *pci; |
359 | unsigned char pci_rev, pci_lat; |
360 | int pci_bus, pci_slot; |
361 | u32 __iomem *lmmio; |
362 | u8 __iomem *bmmio; |
363 | int pci_irqmask; |
364 | spinlock_t pci_irqmask_lock; /* protects mask reg too */ |
365 | int hwrevision; |
366 | |
367 | /* This valud is board specific and is used to configure the |
368 | * AV core so we see nice clean and stable video and audio. */ |
369 | u32 clk_freq; |
370 | |
371 | /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */ |
372 | struct cx23885_i2c i2c_bus[3]; |
373 | |
374 | int nr; |
375 | struct mutex lock; |
376 | struct mutex gpio_lock; |
377 | |
378 | /* board details */ |
379 | unsigned int board; |
380 | char name[32]; |
381 | |
382 | struct cx23885_tsport ts1, ts2; |
383 | |
384 | /* sram configuration */ |
385 | struct sram_channel *sram_channels; |
386 | |
387 | enum { |
388 | CX23885_BRIDGE_UNDEFINED = 0, |
389 | CX23885_BRIDGE_885 = 885, |
390 | CX23885_BRIDGE_887 = 887, |
391 | CX23885_BRIDGE_888 = 888, |
392 | } bridge; |
393 | |
394 | /* Analog video */ |
395 | unsigned int input; |
396 | unsigned int audinput; /* Selectable audio input */ |
397 | u32 tvaudio; |
398 | v4l2_std_id tvnorm; |
399 | unsigned int tuner_type; |
400 | unsigned char tuner_addr; |
401 | unsigned int tuner_bus; |
402 | unsigned int radio_type; |
403 | unsigned char radio_addr; |
404 | struct v4l2_subdev *sd_cx25840; |
405 | struct work_struct cx25840_work; |
406 | |
407 | /* Infrared */ |
408 | struct v4l2_subdev *sd_ir; |
409 | struct work_struct ir_rx_work; |
410 | unsigned long ir_rx_notifications; |
411 | struct work_struct ir_tx_work; |
412 | unsigned long ir_tx_notifications; |
413 | |
414 | struct cx23885_kernel_ir *kernel_ir; |
415 | atomic_t ir_input_stopping; |
416 | |
417 | /* V4l */ |
418 | u32 freq; |
419 | struct video_device *video_dev; |
420 | struct video_device *vbi_dev; |
421 | |
422 | /* video capture */ |
423 | struct cx23885_fmt *fmt; |
424 | unsigned int width, height; |
425 | unsigned field; |
426 | |
427 | struct cx23885_dmaqueue vidq; |
428 | struct vb2_queue vb2_vidq; |
429 | struct cx23885_dmaqueue vbiq; |
430 | struct vb2_queue vb2_vbiq; |
431 | |
432 | spinlock_t slock; |
433 | |
434 | /* MPEG Encoder ONLY settings */ |
435 | u32 cx23417_mailbox; |
436 | struct cx2341x_handler cxhdl; |
437 | struct video_device *v4l_device; |
438 | struct vb2_queue vb2_mpegq; |
439 | struct cx23885_tvnorm encodernorm; |
440 | |
441 | /* Analog raw audio */ |
442 | struct cx23885_audio_dev *audio_dev; |
443 | |
444 | /* Does the system require periodic DMA resets? */ |
445 | unsigned int need_dma_reset:1; |
446 | }; |
447 | |
448 | static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev) |
449 | { |
450 | return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev); |
451 | } |
452 | |
453 | #define call_all(dev, o, f, args...) \ |
454 | v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args) |
455 | |
456 | #define CX23885_HW_888_IR (1 << 0) |
457 | #define CX23885_HW_AV_CORE (1 << 1) |
458 | |
459 | #define call_hw(dev, grpid, o, f, args...) \ |
460 | v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args) |
461 | |
462 | extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw); |
463 | |
464 | #define SRAM_CH01 0 /* Video A */ |
465 | #define SRAM_CH02 1 /* VBI A */ |
466 | #define SRAM_CH03 2 /* Video B */ |
467 | #define SRAM_CH04 3 /* Transport via B */ |
468 | #define SRAM_CH05 4 /* VBI B */ |
469 | #define SRAM_CH06 5 /* Video C */ |
470 | #define SRAM_CH07 6 /* Transport via C */ |
471 | #define SRAM_CH08 7 /* Audio Internal A */ |
472 | #define SRAM_CH09 8 /* Audio Internal B */ |
473 | #define SRAM_CH10 9 /* Audio External */ |
474 | #define SRAM_CH11 10 /* COMB_3D_N */ |
475 | #define SRAM_CH12 11 /* Comb 3D N1 */ |
476 | #define SRAM_CH13 12 /* Comb 3D N2 */ |
477 | #define SRAM_CH14 13 /* MOE Vid */ |
478 | #define SRAM_CH15 14 /* MOE RSLT */ |
479 | |
480 | struct sram_channel { |
481 | char *name; |
482 | u32 cmds_start; |
483 | u32 ctrl_start; |
484 | u32 cdt; |
485 | u32 fifo_start; |
486 | u32 fifo_size; |
487 | u32 ptr1_reg; |
488 | u32 ptr2_reg; |
489 | u32 cnt1_reg; |
490 | u32 cnt2_reg; |
491 | u32 jumponly; |
492 | }; |
493 | |
494 | /* ----------------------------------------------------------- */ |
495 | |
496 | #define cx_read(reg) readl(dev->lmmio + ((reg)>>2)) |
497 | #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2)) |
498 | |
499 | #define cx_andor(reg, mask, value) \ |
500 | writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ |
501 | ((value) & (mask)), dev->lmmio+((reg)>>2)) |
502 | |
503 | #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) |
504 | #define cx_clear(reg, bit) cx_andor((reg), (bit), 0) |
505 | |
506 | /* ----------------------------------------------------------- */ |
507 | /* cx23885-core.c */ |
508 | |
509 | extern int cx23885_sram_channel_setup(struct cx23885_dev *dev, |
510 | struct sram_channel *ch, |
511 | unsigned int bpl, u32 risc); |
512 | |
513 | extern void cx23885_sram_channel_dump(struct cx23885_dev *dev, |
514 | struct sram_channel *ch); |
515 | |
516 | extern int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc, |
517 | struct scatterlist *sglist, |
518 | unsigned int top_offset, unsigned int bottom_offset, |
519 | unsigned int bpl, unsigned int padding, unsigned int lines); |
520 | |
521 | extern int cx23885_risc_vbibuffer(struct pci_dev *pci, |
522 | struct cx23885_riscmem *risc, struct scatterlist *sglist, |
523 | unsigned int top_offset, unsigned int bottom_offset, |
524 | unsigned int bpl, unsigned int padding, unsigned int lines); |
525 | |
526 | int cx23885_start_dma(struct cx23885_tsport *port, |
527 | struct cx23885_dmaqueue *q, |
528 | struct cx23885_buffer *buf); |
529 | void cx23885_cancel_buffers(struct cx23885_tsport *port); |
530 | |
531 | |
532 | extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask); |
533 | extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask); |
534 | extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask); |
535 | extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, |
536 | int asoutput); |
537 | |
538 | extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask); |
539 | extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask); |
540 | extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask); |
541 | extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask); |
542 | |
543 | /* ----------------------------------------------------------- */ |
544 | /* cx23885-cards.c */ |
545 | extern struct cx23885_board cx23885_boards[]; |
546 | extern const unsigned int cx23885_bcount; |
547 | |
548 | extern struct cx23885_subid cx23885_subids[]; |
549 | extern const unsigned int cx23885_idcount; |
550 | |
551 | extern int cx23885_tuner_callback(void *priv, int component, |
552 | int command, int arg); |
553 | extern void cx23885_card_list(struct cx23885_dev *dev); |
554 | extern int cx23885_ir_init(struct cx23885_dev *dev); |
555 | extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev); |
556 | extern void cx23885_ir_fini(struct cx23885_dev *dev); |
557 | extern void cx23885_gpio_setup(struct cx23885_dev *dev); |
558 | extern void cx23885_card_setup(struct cx23885_dev *dev); |
559 | extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev); |
560 | |
561 | extern int cx23885_dvb_register(struct cx23885_tsport *port); |
562 | extern int cx23885_dvb_unregister(struct cx23885_tsport *port); |
563 | |
564 | extern int cx23885_buf_prepare(struct cx23885_buffer *buf, |
565 | struct cx23885_tsport *port); |
566 | extern void cx23885_buf_queue(struct cx23885_tsport *port, |
567 | struct cx23885_buffer *buf); |
568 | extern void cx23885_free_buffer(struct cx23885_dev *dev, |
569 | struct cx23885_buffer *buf); |
570 | |
571 | /* ----------------------------------------------------------- */ |
572 | /* cx23885-video.c */ |
573 | /* Video */ |
574 | extern int cx23885_video_register(struct cx23885_dev *dev); |
575 | extern void cx23885_video_unregister(struct cx23885_dev *dev); |
576 | extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status); |
577 | extern void cx23885_video_wakeup(struct cx23885_dev *dev, |
578 | struct cx23885_dmaqueue *q, u32 count); |
579 | int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i); |
580 | int cx23885_set_input(struct file *file, void *priv, unsigned int i); |
581 | int cx23885_get_input(struct file *file, void *priv, unsigned int *i); |
582 | int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f); |
583 | int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm); |
584 | |
585 | /* ----------------------------------------------------------- */ |
586 | /* cx23885-vbi.c */ |
587 | extern int cx23885_vbi_fmt(struct file *file, void *priv, |
588 | struct v4l2_format *f); |
589 | extern void cx23885_vbi_timeout(unsigned long data); |
590 | extern const struct vb2_ops cx23885_vbi_qops; |
591 | extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status); |
592 | |
593 | /* cx23885-i2c.c */ |
594 | extern int cx23885_i2c_register(struct cx23885_i2c *bus); |
595 | extern int cx23885_i2c_unregister(struct cx23885_i2c *bus); |
596 | extern void cx23885_av_clk(struct cx23885_dev *dev, int enable); |
597 | |
598 | /* ----------------------------------------------------------- */ |
599 | /* cx23885-417.c */ |
600 | extern int cx23885_417_register(struct cx23885_dev *dev); |
601 | extern void cx23885_417_unregister(struct cx23885_dev *dev); |
602 | extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status); |
603 | extern void cx23885_417_check_encoder(struct cx23885_dev *dev); |
604 | extern void cx23885_mc417_init(struct cx23885_dev *dev); |
605 | extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value); |
606 | extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value); |
607 | extern int mc417_register_read(struct cx23885_dev *dev, |
608 | u16 address, u32 *value); |
609 | extern int mc417_register_write(struct cx23885_dev *dev, |
610 | u16 address, u32 value); |
611 | extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask); |
612 | extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask); |
613 | extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput); |
614 | |
615 | /* ----------------------------------------------------------- */ |
616 | /* cx23885-alsa.c */ |
617 | extern struct cx23885_audio_dev *cx23885_audio_register( |
618 | struct cx23885_dev *dev); |
619 | extern void cx23885_audio_unregister(struct cx23885_dev *dev); |
620 | extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask); |
621 | extern int cx23885_risc_databuffer(struct pci_dev *pci, |
622 | struct cx23885_riscmem *risc, |
623 | struct scatterlist *sglist, |
624 | unsigned int bpl, |
625 | unsigned int lines, |
626 | unsigned int lpi); |
627 | |
628 | /* ----------------------------------------------------------- */ |
629 | /* tv norms */ |
630 | |
631 | static inline unsigned int norm_maxh(v4l2_std_id norm) |
632 | { |
633 | return (norm & V4L2_STD_525_60) ? 480 : 576; |
634 | } |
635 | |