| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Driver for the Conexant CX25821 PCIe bridge |
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| 4 | * |
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| 5 | * Copyright (C) 2009 Conexant Systems Inc. |
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| 6 | * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __MEDUSA_REGISTERS__ |
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| 10 | #define __MEDUSA_REGISTERS__ |
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| 11 | |
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| 12 | /* Serial Slave Registers */ |
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| 13 | #define HOST_REGISTER1 0x0000 |
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| 14 | #define HOST_REGISTER2 0x0001 |
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| 15 | |
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| 16 | /* Chip Configuration Registers */ |
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| 17 | #define CHIP_CTRL 0x0100 |
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| 18 | #define AFE_AB_CTRL 0x0104 |
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| 19 | #define AFE_CD_CTRL 0x0108 |
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| 20 | #define AFE_EF_CTRL 0x010C |
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| 21 | #define AFE_GH_CTRL 0x0110 |
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| 22 | #define DENC_AB_CTRL 0x0114 |
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| 23 | #define BYP_AB_CTRL 0x0118 |
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| 24 | #define MON_A_CTRL 0x011C |
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| 25 | #define DISP_SEQ_A 0x0120 |
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| 26 | #define DISP_SEQ_B 0x0124 |
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| 27 | #define DISP_AB_CNT 0x0128 |
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| 28 | #define DISP_CD_CNT 0x012C |
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| 29 | #define DISP_EF_CNT 0x0130 |
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| 30 | #define DISP_GH_CNT 0x0134 |
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| 31 | #define DISP_IJ_CNT 0x0138 |
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| 32 | #define PIN_OE_CTRL 0x013C |
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| 33 | #define PIN_SPD_CTRL 0x0140 |
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| 34 | #define PIN_SPD_CTRL2 0x0144 |
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| 35 | #define IRQ_STAT_CTRL 0x0148 |
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| 36 | #define POWER_CTRL_AB 0x014C |
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| 37 | #define POWER_CTRL_CD 0x0150 |
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| 38 | #define POWER_CTRL_EF 0x0154 |
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| 39 | #define POWER_CTRL_GH 0x0158 |
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| 40 | #define TUNE_CTRL 0x015C |
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| 41 | #define BIAS_CTRL 0x0160 |
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| 42 | #define AFE_AB_DIAG_CTRL 0x0164 |
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| 43 | #define AFE_CD_DIAG_CTRL 0x0168 |
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| 44 | #define AFE_EF_DIAG_CTRL 0x016C |
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| 45 | #define AFE_GH_DIAG_CTRL 0x0170 |
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| 46 | #define PLL_AB_DIAG_CTRL 0x0174 |
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| 47 | #define PLL_CD_DIAG_CTRL 0x0178 |
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| 48 | #define PLL_EF_DIAG_CTRL 0x017C |
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| 49 | #define PLL_GH_DIAG_CTRL 0x0180 |
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| 50 | #define TEST_CTRL 0x0184 |
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| 51 | #define BIST_STAT 0x0188 |
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| 52 | #define BIST_STAT2 0x018C |
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| 53 | #define BIST_VID_PLL_AB_STAT 0x0190 |
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| 54 | #define BIST_VID_PLL_CD_STAT 0x0194 |
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| 55 | #define BIST_VID_PLL_EF_STAT 0x0198 |
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| 56 | #define BIST_VID_PLL_GH_STAT 0x019C |
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| 57 | #define DLL_DIAG_CTRL 0x01A0 |
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| 58 | #define DEV_CH_ID_CTRL 0x01A4 |
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| 59 | #define ABIST_CTRL_STATUS 0x01A8 |
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| 60 | #define ABIST_FREQ 0x01AC |
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| 61 | #define ABIST_GOERT_SHIFT 0x01B0 |
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| 62 | #define ABIST_COEF12 0x01B4 |
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| 63 | #define ABIST_COEF34 0x01B8 |
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| 64 | #define ABIST_COEF56 0x01BC |
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| 65 | #define ABIST_COEF7_SNR 0x01C0 |
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| 66 | #define ABIST_ADC_CAL 0x01C4 |
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| 67 | #define ABIST_BIN1_VGA0 0x01C8 |
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| 68 | #define ABIST_BIN2_VGA1 0x01CC |
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| 69 | #define ABIST_BIN3_VGA2 0x01D0 |
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| 70 | #define ABIST_BIN4_VGA3 0x01D4 |
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| 71 | #define ABIST_BIN5_VGA4 0x01D8 |
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| 72 | #define ABIST_BIN6_VGA5 0x01DC |
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| 73 | #define ABIST_BIN7_VGA6 0x01E0 |
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| 74 | #define ABIST_CLAMP_A 0x01E4 |
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| 75 | #define ABIST_CLAMP_B 0x01E8 |
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| 76 | #define ABIST_CLAMP_C 0x01EC |
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| 77 | #define ABIST_CLAMP_D 0x01F0 |
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| 78 | #define ABIST_CLAMP_E 0x01F4 |
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| 79 | #define ABIST_CLAMP_F 0x01F8 |
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| 80 | |
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| 81 | /* Digital Video Encoder A Registers */ |
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| 82 | #define DENC_A_REG_1 0x0200 |
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| 83 | #define DENC_A_REG_2 0x0204 |
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| 84 | #define DENC_A_REG_3 0x0208 |
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| 85 | #define DENC_A_REG_4 0x020C |
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| 86 | #define DENC_A_REG_5 0x0210 |
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| 87 | #define DENC_A_REG_6 0x0214 |
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| 88 | #define DENC_A_REG_7 0x0218 |
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| 89 | #define DENC_A_REG_8 0x021C |
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| 90 | |
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| 91 | /* Digital Video Encoder B Registers */ |
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| 92 | #define DENC_B_REG_1 0x0300 |
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| 93 | #define DENC_B_REG_2 0x0304 |
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| 94 | #define DENC_B_REG_3 0x0308 |
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| 95 | #define DENC_B_REG_4 0x030C |
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| 96 | #define DENC_B_REG_5 0x0310 |
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| 97 | #define DENC_B_REG_6 0x0314 |
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| 98 | #define DENC_B_REG_7 0x0318 |
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| 99 | #define DENC_B_REG_8 0x031C |
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| 100 | |
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| 101 | /* Video Decoder A Registers */ |
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| 102 | #define MODE_CTRL 0x1000 |
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| 103 | #define OUT_CTRL1 0x1004 |
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| 104 | #define OUT_CTRL_NS 0x1008 |
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| 105 | #define GEN_STAT 0x100C |
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| 106 | #define INT_STAT_MASK 0x1010 |
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| 107 | #define LUMA_CTRL 0x1014 |
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| 108 | #define CHROMA_CTRL 0x1018 |
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| 109 | #define CRUSH_CTRL 0x101C |
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| 110 | #define HORIZ_TIM_CTRL 0x1020 |
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| 111 | #define VERT_TIM_CTRL 0x1024 |
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| 112 | #define MISC_TIM_CTRL 0x1028 |
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| 113 | #define FIELD_COUNT 0x102C |
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| 114 | #define HSCALE_CTRL 0x1030 |
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| 115 | #define VSCALE_CTRL 0x1034 |
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| 116 | #define MAN_VGA_CTRL 0x1038 |
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| 117 | #define MAN_AGC_CTRL 0x103C |
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| 118 | #define DFE_CTRL1 0x1040 |
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| 119 | #define DFE_CTRL2 0x1044 |
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| 120 | #define DFE_CTRL3 0x1048 |
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| 121 | #define PLL_CTRL 0x104C |
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| 122 | #define PLL_CTRL_FAST 0x1050 |
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| 123 | #define HTL_CTRL 0x1054 |
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| 124 | #define SRC_CFG 0x1058 |
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| 125 | #define SC_STEP_SIZE 0x105C |
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| 126 | #define SC_CONVERGE_CTRL 0x1060 |
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| 127 | #define SC_LOOP_CTRL 0x1064 |
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| 128 | #define COMB_2D_HFS_CFG 0x1068 |
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| 129 | #define COMB_2D_HFD_CFG 0x106C |
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| 130 | #define COMB_2D_LF_CFG 0x1070 |
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| 131 | #define COMB_2D_BLEND 0x1074 |
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| 132 | #define COMB_MISC_CTRL 0x1078 |
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| 133 | #define COMB_FLAT_THRESH_CTRL 0x107C |
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| 134 | #define COMB_TEST 0x1080 |
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| 135 | #define BP_MISC_CTRL 0x1084 |
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| 136 | #define VCR_DET_CTRL 0x1088 |
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| 137 | #define NOISE_DET_CTRL 0x108C |
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| 138 | #define COMB_FLAT_NOISE_CTRL 0x1090 |
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| 139 | #define VERSION 0x11F8 |
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| 140 | #define SOFT_RST_CTRL 0x11FC |
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| 141 | |
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| 142 | /* Video Decoder B Registers */ |
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| 143 | #define VDEC_B_MODE_CTRL 0x1200 |
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| 144 | #define VDEC_B_OUT_CTRL1 0x1204 |
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| 145 | #define VDEC_B_OUT_CTRL_NS 0x1208 |
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| 146 | #define VDEC_B_GEN_STAT 0x120C |
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| 147 | #define VDEC_B_INT_STAT_MASK 0x1210 |
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| 148 | #define VDEC_B_LUMA_CTRL 0x1214 |
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| 149 | #define VDEC_B_CHROMA_CTRL 0x1218 |
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| 150 | #define VDEC_B_CRUSH_CTRL 0x121C |
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| 151 | #define VDEC_B_HORIZ_TIM_CTRL 0x1220 |
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| 152 | #define VDEC_B_VERT_TIM_CTRL 0x1224 |
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| 153 | #define VDEC_B_MISC_TIM_CTRL 0x1228 |
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| 154 | #define VDEC_B_FIELD_COUNT 0x122C |
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| 155 | #define VDEC_B_HSCALE_CTRL 0x1230 |
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| 156 | #define VDEC_B_VSCALE_CTRL 0x1234 |
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| 157 | #define VDEC_B_MAN_VGA_CTRL 0x1238 |
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| 158 | #define VDEC_B_MAN_AGC_CTRL 0x123C |
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| 159 | #define VDEC_B_DFE_CTRL1 0x1240 |
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| 160 | #define VDEC_B_DFE_CTRL2 0x1244 |
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| 161 | #define VDEC_B_DFE_CTRL3 0x1248 |
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| 162 | #define VDEC_B_PLL_CTRL 0x124C |
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| 163 | #define VDEC_B_PLL_CTRL_FAST 0x1250 |
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| 164 | #define VDEC_B_HTL_CTRL 0x1254 |
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| 165 | #define VDEC_B_SRC_CFG 0x1258 |
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| 166 | #define VDEC_B_SC_STEP_SIZE 0x125C |
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| 167 | #define VDEC_B_SC_CONVERGE_CTRL 0x1260 |
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| 168 | #define VDEC_B_SC_LOOP_CTRL 0x1264 |
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| 169 | #define VDEC_B_COMB_2D_HFS_CFG 0x1268 |
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| 170 | #define VDEC_B_COMB_2D_HFD_CFG 0x126C |
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| 171 | #define VDEC_B_COMB_2D_LF_CFG 0x1270 |
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| 172 | #define VDEC_B_COMB_2D_BLEND 0x1274 |
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| 173 | #define VDEC_B_COMB_MISC_CTRL 0x1278 |
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| 174 | #define VDEC_B_COMB_FLAT_THRESH_CTRL 0x127C |
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| 175 | #define VDEC_B_COMB_TEST 0x1280 |
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| 176 | #define VDEC_B_BP_MISC_CTRL 0x1284 |
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| 177 | #define VDEC_B_VCR_DET_CTRL 0x1288 |
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| 178 | #define VDEC_B_NOISE_DET_CTRL 0x128C |
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| 179 | #define VDEC_B_COMB_FLAT_NOISE_CTRL 0x1290 |
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| 180 | #define VDEC_B_VERSION 0x13F8 |
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| 181 | #define VDEC_B_SOFT_RST_CTRL 0x13FC |
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| 182 | |
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| 183 | /* Video Decoder C Registers */ |
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| 184 | #define VDEC_C_MODE_CTRL 0x1400 |
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| 185 | #define VDEC_C_OUT_CTRL1 0x1404 |
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| 186 | #define VDEC_C_OUT_CTRL_NS 0x1408 |
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| 187 | #define VDEC_C_GEN_STAT 0x140C |
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| 188 | #define VDEC_C_INT_STAT_MASK 0x1410 |
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| 189 | #define VDEC_C_LUMA_CTRL 0x1414 |
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| 190 | #define VDEC_C_CHROMA_CTRL 0x1418 |
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| 191 | #define VDEC_C_CRUSH_CTRL 0x141C |
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| 192 | #define VDEC_C_HORIZ_TIM_CTRL 0x1420 |
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| 193 | #define VDEC_C_VERT_TIM_CTRL 0x1424 |
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| 194 | #define VDEC_C_MISC_TIM_CTRL 0x1428 |
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| 195 | #define VDEC_C_FIELD_COUNT 0x142C |
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| 196 | #define VDEC_C_HSCALE_CTRL 0x1430 |
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| 197 | #define VDEC_C_VSCALE_CTRL 0x1434 |
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| 198 | #define VDEC_C_MAN_VGA_CTRL 0x1438 |
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| 199 | #define VDEC_C_MAN_AGC_CTRL 0x143C |
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| 200 | #define VDEC_C_DFE_CTRL1 0x1440 |
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| 201 | #define VDEC_C_DFE_CTRL2 0x1444 |
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| 202 | #define VDEC_C_DFE_CTRL3 0x1448 |
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| 203 | #define VDEC_C_PLL_CTRL 0x144C |
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| 204 | #define VDEC_C_PLL_CTRL_FAST 0x1450 |
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| 205 | #define VDEC_C_HTL_CTRL 0x1454 |
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| 206 | #define VDEC_C_SRC_CFG 0x1458 |
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| 207 | #define VDEC_C_SC_STEP_SIZE 0x145C |
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| 208 | #define VDEC_C_SC_CONVERGE_CTRL 0x1460 |
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| 209 | #define VDEC_C_SC_LOOP_CTRL 0x1464 |
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| 210 | #define VDEC_C_COMB_2D_HFS_CFG 0x1468 |
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| 211 | #define VDEC_C_COMB_2D_HFD_CFG 0x146C |
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| 212 | #define VDEC_C_COMB_2D_LF_CFG 0x1470 |
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| 213 | #define VDEC_C_COMB_2D_BLEND 0x1474 |
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| 214 | #define VDEC_C_COMB_MISC_CTRL 0x1478 |
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| 215 | #define VDEC_C_COMB_FLAT_THRESH_CTRL 0x147C |
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| 216 | #define VDEC_C_COMB_TEST 0x1480 |
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| 217 | #define VDEC_C_BP_MISC_CTRL 0x1484 |
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| 218 | #define VDEC_C_VCR_DET_CTRL 0x1488 |
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| 219 | #define VDEC_C_NOISE_DET_CTRL 0x148C |
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| 220 | #define VDEC_C_COMB_FLAT_NOISE_CTRL 0x1490 |
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| 221 | #define VDEC_C_VERSION 0x15F8 |
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| 222 | #define VDEC_C_SOFT_RST_CTRL 0x15FC |
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| 223 | |
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| 224 | /* Video Decoder D Registers */ |
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| 225 | #define VDEC_D_MODE_CTRL 0x1600 |
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| 226 | #define VDEC_D_OUT_CTRL1 0x1604 |
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| 227 | #define VDEC_D_OUT_CTRL_NS 0x1608 |
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| 228 | #define VDEC_D_GEN_STAT 0x160C |
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| 229 | #define VDEC_D_INT_STAT_MASK 0x1610 |
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| 230 | #define VDEC_D_LUMA_CTRL 0x1614 |
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| 231 | #define VDEC_D_CHROMA_CTRL 0x1618 |
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| 232 | #define VDEC_D_CRUSH_CTRL 0x161C |
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| 233 | #define VDEC_D_HORIZ_TIM_CTRL 0x1620 |
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| 234 | #define VDEC_D_VERT_TIM_CTRL 0x1624 |
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| 235 | #define VDEC_D_MISC_TIM_CTRL 0x1628 |
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| 236 | #define VDEC_D_FIELD_COUNT 0x162C |
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| 237 | #define VDEC_D_HSCALE_CTRL 0x1630 |
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| 238 | #define VDEC_D_VSCALE_CTRL 0x1634 |
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| 239 | #define VDEC_D_MAN_VGA_CTRL 0x1638 |
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| 240 | #define VDEC_D_MAN_AGC_CTRL 0x163C |
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| 241 | #define VDEC_D_DFE_CTRL1 0x1640 |
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| 242 | #define VDEC_D_DFE_CTRL2 0x1644 |
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| 243 | #define VDEC_D_DFE_CTRL3 0x1648 |
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| 244 | #define VDEC_D_PLL_CTRL 0x164C |
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| 245 | #define VDEC_D_PLL_CTRL_FAST 0x1650 |
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| 246 | #define VDEC_D_HTL_CTRL 0x1654 |
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| 247 | #define VDEC_D_SRC_CFG 0x1658 |
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| 248 | #define VDEC_D_SC_STEP_SIZE 0x165C |
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| 249 | #define VDEC_D_SC_CONVERGE_CTRL 0x1660 |
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| 250 | #define VDEC_D_SC_LOOP_CTRL 0x1664 |
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| 251 | #define VDEC_D_COMB_2D_HFS_CFG 0x1668 |
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| 252 | #define VDEC_D_COMB_2D_HFD_CFG 0x166C |
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| 253 | #define VDEC_D_COMB_2D_LF_CFG 0x1670 |
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| 254 | #define VDEC_D_COMB_2D_BLEND 0x1674 |
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| 255 | #define VDEC_D_COMB_MISC_CTRL 0x1678 |
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| 256 | #define VDEC_D_COMB_FLAT_THRESH_CTRL 0x167C |
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| 257 | #define VDEC_D_COMB_TEST 0x1680 |
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| 258 | #define VDEC_D_BP_MISC_CTRL 0x1684 |
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| 259 | #define VDEC_D_VCR_DET_CTRL 0x1688 |
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| 260 | #define VDEC_D_NOISE_DET_CTRL 0x168C |
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| 261 | #define VDEC_D_COMB_FLAT_NOISE_CTRL 0x1690 |
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| 262 | #define VDEC_D_VERSION 0x17F8 |
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| 263 | #define VDEC_D_SOFT_RST_CTRL 0x17FC |
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| 264 | |
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| 265 | /* Video Decoder E Registers */ |
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| 266 | #define VDEC_E_MODE_CTRL 0x1800 |
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| 267 | #define VDEC_E_OUT_CTRL1 0x1804 |
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| 268 | #define VDEC_E_OUT_CTRL_NS 0x1808 |
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| 269 | #define VDEC_E_GEN_STAT 0x180C |
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| 270 | #define VDEC_E_INT_STAT_MASK 0x1810 |
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| 271 | #define VDEC_E_LUMA_CTRL 0x1814 |
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| 272 | #define VDEC_E_CHROMA_CTRL 0x1818 |
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| 273 | #define VDEC_E_CRUSH_CTRL 0x181C |
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| 274 | #define VDEC_E_HORIZ_TIM_CTRL 0x1820 |
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| 275 | #define VDEC_E_VERT_TIM_CTRL 0x1824 |
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| 276 | #define VDEC_E_MISC_TIM_CTRL 0x1828 |
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| 277 | #define VDEC_E_FIELD_COUNT 0x182C |
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| 278 | #define VDEC_E_HSCALE_CTRL 0x1830 |
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| 279 | #define VDEC_E_VSCALE_CTRL 0x1834 |
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| 280 | #define VDEC_E_MAN_VGA_CTRL 0x1838 |
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| 281 | #define VDEC_E_MAN_AGC_CTRL 0x183C |
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| 282 | #define VDEC_E_DFE_CTRL1 0x1840 |
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| 283 | #define VDEC_E_DFE_CTRL2 0x1844 |
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| 284 | #define VDEC_E_DFE_CTRL3 0x1848 |
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| 285 | #define VDEC_E_PLL_CTRL 0x184C |
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| 286 | #define VDEC_E_PLL_CTRL_FAST 0x1850 |
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| 287 | #define VDEC_E_HTL_CTRL 0x1854 |
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| 288 | #define VDEC_E_SRC_CFG 0x1858 |
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| 289 | #define VDEC_E_SC_STEP_SIZE 0x185C |
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| 290 | #define VDEC_E_SC_CONVERGE_CTRL 0x1860 |
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| 291 | #define VDEC_E_SC_LOOP_CTRL 0x1864 |
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| 292 | #define VDEC_E_COMB_2D_HFS_CFG 0x1868 |
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| 293 | #define VDEC_E_COMB_2D_HFD_CFG 0x186C |
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| 294 | #define VDEC_E_COMB_2D_LF_CFG 0x1870 |
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| 295 | #define VDEC_E_COMB_2D_BLEND 0x1874 |
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| 296 | #define VDEC_E_COMB_MISC_CTRL 0x1878 |
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| 297 | #define VDEC_E_COMB_FLAT_THRESH_CTRL 0x187C |
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| 298 | #define VDEC_E_COMB_TEST 0x1880 |
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| 299 | #define VDEC_E_BP_MISC_CTRL 0x1884 |
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| 300 | #define VDEC_E_VCR_DET_CTRL 0x1888 |
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| 301 | #define VDEC_E_NOISE_DET_CTRL 0x188C |
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| 302 | #define VDEC_E_COMB_FLAT_NOISE_CTRL 0x1890 |
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| 303 | #define VDEC_E_VERSION 0x19F8 |
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| 304 | #define VDEC_E_SOFT_RST_CTRL 0x19FC |
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| 305 | |
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| 306 | /* Video Decoder F Registers */ |
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| 307 | #define VDEC_F_MODE_CTRL 0x1A00 |
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| 308 | #define VDEC_F_OUT_CTRL1 0x1A04 |
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| 309 | #define VDEC_F_OUT_CTRL_NS 0x1A08 |
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| 310 | #define VDEC_F_GEN_STAT 0x1A0C |
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| 311 | #define VDEC_F_INT_STAT_MASK 0x1A10 |
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| 312 | #define VDEC_F_LUMA_CTRL 0x1A14 |
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| 313 | #define VDEC_F_CHROMA_CTRL 0x1A18 |
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| 314 | #define VDEC_F_CRUSH_CTRL 0x1A1C |
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| 315 | #define VDEC_F_HORIZ_TIM_CTRL 0x1A20 |
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| 316 | #define VDEC_F_VERT_TIM_CTRL 0x1A24 |
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| 317 | #define VDEC_F_MISC_TIM_CTRL 0x1A28 |
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| 318 | #define VDEC_F_FIELD_COUNT 0x1A2C |
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| 319 | #define VDEC_F_HSCALE_CTRL 0x1A30 |
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| 320 | #define VDEC_F_VSCALE_CTRL 0x1A34 |
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| 321 | #define VDEC_F_MAN_VGA_CTRL 0x1A38 |
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| 322 | #define VDEC_F_MAN_AGC_CTRL 0x1A3C |
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| 323 | #define VDEC_F_DFE_CTRL1 0x1A40 |
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| 324 | #define VDEC_F_DFE_CTRL2 0x1A44 |
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| 325 | #define VDEC_F_DFE_CTRL3 0x1A48 |
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| 326 | #define VDEC_F_PLL_CTRL 0x1A4C |
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| 327 | #define VDEC_F_PLL_CTRL_FAST 0x1A50 |
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| 328 | #define VDEC_F_HTL_CTRL 0x1A54 |
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| 329 | #define VDEC_F_SRC_CFG 0x1A58 |
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| 330 | #define VDEC_F_SC_STEP_SIZE 0x1A5C |
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| 331 | #define VDEC_F_SC_CONVERGE_CTRL 0x1A60 |
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| 332 | #define VDEC_F_SC_LOOP_CTRL 0x1A64 |
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| 333 | #define VDEC_F_COMB_2D_HFS_CFG 0x1A68 |
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| 334 | #define VDEC_F_COMB_2D_HFD_CFG 0x1A6C |
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| 335 | #define VDEC_F_COMB_2D_LF_CFG 0x1A70 |
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| 336 | #define VDEC_F_COMB_2D_BLEND 0x1A74 |
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| 337 | #define VDEC_F_COMB_MISC_CTRL 0x1A78 |
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| 338 | #define VDEC_F_COMB_FLAT_THRESH_CTRL 0x1A7C |
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| 339 | #define VDEC_F_COMB_TEST 0x1A80 |
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| 340 | #define VDEC_F_BP_MISC_CTRL 0x1A84 |
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| 341 | #define VDEC_F_VCR_DET_CTRL 0x1A88 |
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| 342 | #define VDEC_F_NOISE_DET_CTRL 0x1A8C |
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| 343 | #define VDEC_F_COMB_FLAT_NOISE_CTRL 0x1A90 |
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| 344 | #define VDEC_F_VERSION 0x1BF8 |
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| 345 | #define VDEC_F_SOFT_RST_CTRL 0x1BFC |
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| 346 | |
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| 347 | /* Video Decoder G Registers */ |
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| 348 | #define VDEC_G_MODE_CTRL 0x1C00 |
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| 349 | #define VDEC_G_OUT_CTRL1 0x1C04 |
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| 350 | #define VDEC_G_OUT_CTRL_NS 0x1C08 |
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| 351 | #define VDEC_G_GEN_STAT 0x1C0C |
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| 352 | #define VDEC_G_INT_STAT_MASK 0x1C10 |
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| 353 | #define VDEC_G_LUMA_CTRL 0x1C14 |
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| 354 | #define VDEC_G_CHROMA_CTRL 0x1C18 |
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| 355 | #define VDEC_G_CRUSH_CTRL 0x1C1C |
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| 356 | #define VDEC_G_HORIZ_TIM_CTRL 0x1C20 |
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| 357 | #define VDEC_G_VERT_TIM_CTRL 0x1C24 |
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| 358 | #define VDEC_G_MISC_TIM_CTRL 0x1C28 |
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| 359 | #define VDEC_G_FIELD_COUNT 0x1C2C |
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| 360 | #define VDEC_G_HSCALE_CTRL 0x1C30 |
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| 361 | #define VDEC_G_VSCALE_CTRL 0x1C34 |
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| 362 | #define VDEC_G_MAN_VGA_CTRL 0x1C38 |
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| 363 | #define VDEC_G_MAN_AGC_CTRL 0x1C3C |
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| 364 | #define VDEC_G_DFE_CTRL1 0x1C40 |
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| 365 | #define VDEC_G_DFE_CTRL2 0x1C44 |
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| 366 | #define VDEC_G_DFE_CTRL3 0x1C48 |
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| 367 | #define VDEC_G_PLL_CTRL 0x1C4C |
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| 368 | #define VDEC_G_PLL_CTRL_FAST 0x1C50 |
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| 369 | #define VDEC_G_HTL_CTRL 0x1C54 |
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| 370 | #define VDEC_G_SRC_CFG 0x1C58 |
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| 371 | #define VDEC_G_SC_STEP_SIZE 0x1C5C |
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| 372 | #define VDEC_G_SC_CONVERGE_CTRL 0x1C60 |
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| 373 | #define VDEC_G_SC_LOOP_CTRL 0x1C64 |
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| 374 | #define VDEC_G_COMB_2D_HFS_CFG 0x1C68 |
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| 375 | #define VDEC_G_COMB_2D_HFD_CFG 0x1C6C |
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| 376 | #define VDEC_G_COMB_2D_LF_CFG 0x1C70 |
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| 377 | #define VDEC_G_COMB_2D_BLEND 0x1C74 |
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| 378 | #define VDEC_G_COMB_MISC_CTRL 0x1C78 |
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| 379 | #define VDEC_G_COMB_FLAT_THRESH_CTRL 0x1C7C |
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| 380 | #define VDEC_G_COMB_TEST 0x1C80 |
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| 381 | #define VDEC_G_BP_MISC_CTRL 0x1C84 |
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| 382 | #define VDEC_G_VCR_DET_CTRL 0x1C88 |
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| 383 | #define VDEC_G_NOISE_DET_CTRL 0x1C8C |
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| 384 | #define VDEC_G_COMB_FLAT_NOISE_CTRL 0x1C90 |
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| 385 | #define VDEC_G_VERSION 0x1DF8 |
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| 386 | #define VDEC_G_SOFT_RST_CTRL 0x1DFC |
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| 387 | |
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| 388 | /* Video Decoder H Registers */ |
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| 389 | #define VDEC_H_MODE_CTRL 0x1E00 |
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| 390 | #define VDEC_H_OUT_CTRL1 0x1E04 |
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| 391 | #define VDEC_H_OUT_CTRL_NS 0x1E08 |
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| 392 | #define VDEC_H_GEN_STAT 0x1E0C |
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| 393 | #define VDEC_H_INT_STAT_MASK 0x1E1E |
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| 394 | #define VDEC_H_LUMA_CTRL 0x1E14 |
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| 395 | #define VDEC_H_CHROMA_CTRL 0x1E18 |
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| 396 | #define VDEC_H_CRUSH_CTRL 0x1E1C |
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| 397 | #define VDEC_H_HORIZ_TIM_CTRL 0x1E20 |
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| 398 | #define VDEC_H_VERT_TIM_CTRL 0x1E24 |
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| 399 | #define VDEC_H_MISC_TIM_CTRL 0x1E28 |
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| 400 | #define VDEC_H_FIELD_COUNT 0x1E2C |
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| 401 | #define VDEC_H_HSCALE_CTRL 0x1E30 |
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| 402 | #define VDEC_H_VSCALE_CTRL 0x1E34 |
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| 403 | #define VDEC_H_MAN_VGA_CTRL 0x1E38 |
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| 404 | #define VDEC_H_MAN_AGC_CTRL 0x1E3C |
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| 405 | #define VDEC_H_DFE_CTRL1 0x1E40 |
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| 406 | #define VDEC_H_DFE_CTRL2 0x1E44 |
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| 407 | #define VDEC_H_DFE_CTRL3 0x1E48 |
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| 408 | #define VDEC_H_PLL_CTRL 0x1E4C |
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| 409 | #define VDEC_H_PLL_CTRL_FAST 0x1E50 |
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| 410 | #define VDEC_H_HTL_CTRL 0x1E54 |
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| 411 | #define VDEC_H_SRC_CFG 0x1E58 |
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| 412 | #define VDEC_H_SC_STEP_SIZE 0x1E5C |
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| 413 | #define VDEC_H_SC_CONVERGE_CTRL 0x1E60 |
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| 414 | #define VDEC_H_SC_LOOP_CTRL 0x1E64 |
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| 415 | #define VDEC_H_COMB_2D_HFS_CFG 0x1E68 |
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| 416 | #define VDEC_H_COMB_2D_HFD_CFG 0x1E6C |
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| 417 | #define VDEC_H_COMB_2D_LF_CFG 0x1E70 |
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| 418 | #define VDEC_H_COMB_2D_BLEND 0x1E74 |
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| 419 | #define VDEC_H_COMB_MISC_CTRL 0x1E78 |
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| 420 | #define VDEC_H_COMB_FLAT_THRESH_CTRL 0x1E7C |
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| 421 | #define VDEC_H_COMB_TEST 0x1E80 |
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| 422 | #define VDEC_H_BP_MISC_CTRL 0x1E84 |
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| 423 | #define VDEC_H_VCR_DET_CTRL 0x1E88 |
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| 424 | #define VDEC_H_NOISE_DET_CTRL 0x1E8C |
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| 425 | #define VDEC_H_COMB_FLAT_NOISE_CTRL 0x1E90 |
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| 426 | #define VDEC_H_VERSION 0x1FF8 |
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| 427 | #define VDEC_H_SOFT_RST_CTRL 0x1FFC |
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| 428 | |
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| 429 | /*****************************************************************************/ |
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| 430 | /* LUMA_CTRL register fields */ |
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| 431 | #define VDEC_A_BRITE_CTRL 0x1014 |
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| 432 | #define VDEC_A_CNTRST_CTRL 0x1015 |
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| 433 | #define VDEC_A_PEAK_SEL 0x1016 |
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| 434 | |
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| 435 | /*****************************************************************************/ |
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| 436 | /* CHROMA_CTRL register fields */ |
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| 437 | #define VDEC_A_USAT_CTRL 0x1018 |
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| 438 | #define VDEC_A_VSAT_CTRL 0x1019 |
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| 439 | #define VDEC_A_HUE_CTRL 0x101A |
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| 440 | |
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| 441 | #endif |
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| 442 | |
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