| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Driver for the Conexant CX25821 PCIe bridge |
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| 4 | * |
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| 5 | * Copyright (C) 2009 Conexant Systems Inc. |
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| 6 | * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __ATHENA_SRAM_H__ |
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| 10 | #define __ATHENA_SRAM_H__ |
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| 11 | |
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| 12 | /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */ |
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| 13 | #define VID_CMDS_SIZE 80 /* Video CMDS size in bytes */ |
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| 14 | #define AUDIO_CMDS_SIZE 80 /* AUDIO CMDS size in bytes */ |
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| 15 | #define MBIF_CMDS_SIZE 80 /* MBIF CMDS size in bytes */ |
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| 16 | |
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| 17 | /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */ |
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| 18 | #define VID_IQ_SIZE 64 /* VID instruction queue size in bytes */ |
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| 19 | #define MBIF_IQ_SIZE 64 |
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| 20 | #define AUDIO_IQ_SIZE 64 /* AUD instruction queue size in bytes */ |
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| 21 | |
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| 22 | #define VID_CDT_SIZE 64 /* VID cluster descriptor table size in bytes */ |
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| 23 | #define MBIF_CDT_SIZE 64 /* MBIF/HBI cluster descriptor table size in bytes */ |
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| 24 | #define AUDIO_CDT_SIZE 48 /* AUD cluster descriptor table size in bytes */ |
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| 25 | |
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| 26 | /* #define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM */ |
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| 27 | /* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */ |
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| 28 | |
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| 29 | /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */ |
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| 30 | /* #define MSI_DATA_SIZE = 64; // Reserved (MSI Data, RISC working stora */ |
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| 31 | |
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| 32 | #define VID_CLUSTER_SIZE 1440 /* VID cluster data line */ |
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| 33 | #define AUDIO_CLUSTER_SIZE 128 /* AUDIO cluster data line */ |
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| 34 | #define MBIF_CLUSTER_SIZE 1440 /* MBIF/HBI cluster data line */ |
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| 35 | |
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| 36 | /* #define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM */ |
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| 37 | /* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */ |
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| 38 | |
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| 39 | /* Receive SRAM */ |
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| 40 | #define RX_SRAM_START 0x10000 |
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| 41 | #define VID_A_DOWN_CMDS 0x10000 |
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| 42 | #define VID_B_DOWN_CMDS 0x10050 |
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| 43 | #define VID_C_DOWN_CMDS 0x100A0 |
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| 44 | #define VID_D_DOWN_CMDS 0x100F0 |
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| 45 | #define VID_E_DOWN_CMDS 0x10140 |
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| 46 | #define VID_F_DOWN_CMDS 0x10190 |
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| 47 | #define VID_G_DOWN_CMDS 0x101E0 |
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| 48 | #define VID_H_DOWN_CMDS 0x10230 |
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| 49 | #define VID_A_UP_CMDS 0x10280 |
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| 50 | #define VID_B_UP_CMDS 0x102D0 |
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| 51 | #define VID_C_UP_CMDS 0x10320 |
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| 52 | #define VID_D_UP_CMDS 0x10370 |
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| 53 | #define VID_E_UP_CMDS 0x103C0 |
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| 54 | #define VID_F_UP_CMDS 0x10410 |
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| 55 | #define VID_I_UP_CMDS 0x10460 |
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| 56 | #define VID_J_UP_CMDS 0x104B0 |
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| 57 | #define AUD_A_DOWN_CMDS 0x10500 |
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| 58 | #define AUD_B_DOWN_CMDS 0x10550 |
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| 59 | #define AUD_C_DOWN_CMDS 0x105A0 |
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| 60 | #define AUD_D_DOWN_CMDS 0x105F0 |
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| 61 | #define AUD_A_UP_CMDS 0x10640 |
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| 62 | #define AUD_B_UP_CMDS 0x10690 |
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| 63 | #define AUD_C_UP_CMDS 0x106E0 |
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| 64 | #define AUD_E_UP_CMDS 0x10730 |
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| 65 | #define MBIF_A_DOWN_CMDS 0x10780 |
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| 66 | #define MBIF_B_DOWN_CMDS 0x107D0 |
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| 67 | #define DMA_SCRATCH_PAD 0x10820 /* Scratch pad area from 0x10820 to 0x10B40 */ |
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| 68 | |
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| 69 | /* #define RX_SRAM_POOL_START = 0x105B0; */ |
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| 70 | |
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| 71 | #define VID_A_IQ 0x11000 |
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| 72 | #define VID_B_IQ 0x11040 |
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| 73 | #define VID_C_IQ 0x11080 |
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| 74 | #define VID_D_IQ 0x110C0 |
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| 75 | #define VID_E_IQ 0x11100 |
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| 76 | #define VID_F_IQ 0x11140 |
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| 77 | #define VID_G_IQ 0x11180 |
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| 78 | #define VID_H_IQ 0x111C0 |
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| 79 | #define VID_I_IQ 0x11200 |
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| 80 | #define VID_J_IQ 0x11240 |
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| 81 | #define AUD_A_IQ 0x11280 |
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| 82 | #define AUD_B_IQ 0x112C0 |
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| 83 | #define AUD_C_IQ 0x11300 |
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| 84 | #define AUD_D_IQ 0x11340 |
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| 85 | #define AUD_E_IQ 0x11380 |
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| 86 | #define MBIF_A_IQ 0x11000 |
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| 87 | #define MBIF_B_IQ 0x110C0 |
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| 88 | |
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| 89 | #define VID_A_CDT 0x10C00 |
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| 90 | #define VID_B_CDT 0x10C40 |
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| 91 | #define VID_C_CDT 0x10C80 |
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| 92 | #define VID_D_CDT 0x10CC0 |
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| 93 | #define VID_E_CDT 0x10D00 |
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| 94 | #define VID_F_CDT 0x10D40 |
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| 95 | #define VID_G_CDT 0x10D80 |
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| 96 | #define VID_H_CDT 0x10DC0 |
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| 97 | #define VID_I_CDT 0x10E00 |
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| 98 | #define VID_J_CDT 0x10E40 |
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| 99 | #define AUD_A_CDT 0x10E80 |
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| 100 | #define AUD_B_CDT 0x10EB0 |
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| 101 | #define AUD_C_CDT 0x10EE0 |
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| 102 | #define AUD_D_CDT 0x10F10 |
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| 103 | #define AUD_E_CDT 0x10F40 |
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| 104 | #define MBIF_A_CDT 0x10C00 |
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| 105 | #define MBIF_B_CDT 0x10CC0 |
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| 106 | |
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| 107 | /* Cluster Buffer for RX */ |
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| 108 | #define VID_A_UP_CLUSTER_1 0x11400 |
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| 109 | #define VID_A_UP_CLUSTER_2 0x119A0 |
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| 110 | #define VID_A_UP_CLUSTER_3 0x11F40 |
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| 111 | #define VID_A_UP_CLUSTER_4 0x124E0 |
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| 112 | |
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| 113 | #define VID_B_UP_CLUSTER_1 0x12A80 |
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| 114 | #define VID_B_UP_CLUSTER_2 0x13020 |
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| 115 | #define VID_B_UP_CLUSTER_3 0x135C0 |
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| 116 | #define VID_B_UP_CLUSTER_4 0x13B60 |
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| 117 | |
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| 118 | #define VID_C_UP_CLUSTER_1 0x14100 |
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| 119 | #define VID_C_UP_CLUSTER_2 0x146A0 |
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| 120 | #define VID_C_UP_CLUSTER_3 0x14C40 |
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| 121 | #define VID_C_UP_CLUSTER_4 0x151E0 |
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| 122 | |
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| 123 | #define VID_D_UP_CLUSTER_1 0x15780 |
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| 124 | #define VID_D_UP_CLUSTER_2 0x15D20 |
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| 125 | #define VID_D_UP_CLUSTER_3 0x162C0 |
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| 126 | #define VID_D_UP_CLUSTER_4 0x16860 |
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| 127 | |
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| 128 | #define VID_E_UP_CLUSTER_1 0x16E00 |
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| 129 | #define VID_E_UP_CLUSTER_2 0x173A0 |
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| 130 | #define VID_E_UP_CLUSTER_3 0x17940 |
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| 131 | #define VID_E_UP_CLUSTER_4 0x17EE0 |
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| 132 | |
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| 133 | #define VID_F_UP_CLUSTER_1 0x18480 |
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| 134 | #define VID_F_UP_CLUSTER_2 0x18A20 |
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| 135 | #define VID_F_UP_CLUSTER_3 0x18FC0 |
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| 136 | #define VID_F_UP_CLUSTER_4 0x19560 |
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| 137 | |
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| 138 | #define VID_I_UP_CLUSTER_1 0x19B00 |
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| 139 | #define VID_I_UP_CLUSTER_2 0x1A0A0 |
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| 140 | #define VID_I_UP_CLUSTER_3 0x1A640 |
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| 141 | #define VID_I_UP_CLUSTER_4 0x1ABE0 |
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| 142 | |
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| 143 | #define VID_J_UP_CLUSTER_1 0x1B180 |
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| 144 | #define VID_J_UP_CLUSTER_2 0x1B720 |
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| 145 | #define VID_J_UP_CLUSTER_3 0x1BCC0 |
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| 146 | #define VID_J_UP_CLUSTER_4 0x1C260 |
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| 147 | |
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| 148 | #define AUD_A_UP_CLUSTER_1 0x1C800 |
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| 149 | #define AUD_A_UP_CLUSTER_2 0x1C880 |
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| 150 | #define AUD_A_UP_CLUSTER_3 0x1C900 |
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| 151 | |
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| 152 | #define AUD_B_UP_CLUSTER_1 0x1C980 |
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| 153 | #define AUD_B_UP_CLUSTER_2 0x1CA00 |
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| 154 | #define AUD_B_UP_CLUSTER_3 0x1CA80 |
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| 155 | |
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| 156 | #define AUD_C_UP_CLUSTER_1 0x1CB00 |
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| 157 | #define AUD_C_UP_CLUSTER_2 0x1CB80 |
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| 158 | #define AUD_C_UP_CLUSTER_3 0x1CC00 |
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| 159 | |
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| 160 | #define AUD_E_UP_CLUSTER_1 0x1CC80 |
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| 161 | #define AUD_E_UP_CLUSTER_2 0x1CD00 |
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| 162 | #define AUD_E_UP_CLUSTER_3 0x1CD80 |
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| 163 | |
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| 164 | #define RX_SRAM_POOL_FREE 0x1CE00 |
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| 165 | #define RX_SRAM_END 0x1D000 |
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| 166 | |
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| 167 | /* Free Receive SRAM 144 Bytes */ |
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| 168 | |
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| 169 | /* Transmit SRAM */ |
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| 170 | #define TX_SRAM_POOL_START 0x00000 |
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| 171 | |
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| 172 | #define VID_A_DOWN_CLUSTER_1 0x00040 |
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| 173 | #define VID_A_DOWN_CLUSTER_2 0x005E0 |
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| 174 | #define VID_A_DOWN_CLUSTER_3 0x00B80 |
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| 175 | #define VID_A_DOWN_CLUSTER_4 0x01120 |
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| 176 | |
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| 177 | #define VID_B_DOWN_CLUSTER_1 0x016C0 |
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| 178 | #define VID_B_DOWN_CLUSTER_2 0x01C60 |
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| 179 | #define VID_B_DOWN_CLUSTER_3 0x02200 |
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| 180 | #define VID_B_DOWN_CLUSTER_4 0x027A0 |
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| 181 | |
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| 182 | #define VID_C_DOWN_CLUSTER_1 0x02D40 |
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| 183 | #define VID_C_DOWN_CLUSTER_2 0x032E0 |
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| 184 | #define VID_C_DOWN_CLUSTER_3 0x03880 |
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| 185 | #define VID_C_DOWN_CLUSTER_4 0x03E20 |
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| 186 | |
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| 187 | #define VID_D_DOWN_CLUSTER_1 0x043C0 |
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| 188 | #define VID_D_DOWN_CLUSTER_2 0x04960 |
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| 189 | #define VID_D_DOWN_CLUSTER_3 0x04F00 |
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| 190 | #define VID_D_DOWN_CLUSTER_4 0x054A0 |
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| 191 | |
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| 192 | #define VID_E_DOWN_CLUSTER_1 0x05a40 |
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| 193 | #define VID_E_DOWN_CLUSTER_2 0x05FE0 |
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| 194 | #define VID_E_DOWN_CLUSTER_3 0x06580 |
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| 195 | #define VID_E_DOWN_CLUSTER_4 0x06B20 |
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| 196 | |
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| 197 | #define VID_F_DOWN_CLUSTER_1 0x070C0 |
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| 198 | #define VID_F_DOWN_CLUSTER_2 0x07660 |
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| 199 | #define VID_F_DOWN_CLUSTER_3 0x07C00 |
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| 200 | #define VID_F_DOWN_CLUSTER_4 0x081A0 |
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| 201 | |
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| 202 | #define VID_G_DOWN_CLUSTER_1 0x08740 |
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| 203 | #define VID_G_DOWN_CLUSTER_2 0x08CE0 |
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| 204 | #define VID_G_DOWN_CLUSTER_3 0x09280 |
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| 205 | #define VID_G_DOWN_CLUSTER_4 0x09820 |
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| 206 | |
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| 207 | #define VID_H_DOWN_CLUSTER_1 0x09DC0 |
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| 208 | #define VID_H_DOWN_CLUSTER_2 0x0A360 |
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| 209 | #define VID_H_DOWN_CLUSTER_3 0x0A900 |
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| 210 | #define VID_H_DOWN_CLUSTER_4 0x0AEA0 |
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| 211 | |
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| 212 | #define AUD_A_DOWN_CLUSTER_1 0x0B500 |
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| 213 | #define AUD_A_DOWN_CLUSTER_2 0x0B580 |
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| 214 | #define AUD_A_DOWN_CLUSTER_3 0x0B600 |
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| 215 | |
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| 216 | #define AUD_B_DOWN_CLUSTER_1 0x0B680 |
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| 217 | #define AUD_B_DOWN_CLUSTER_2 0x0B700 |
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| 218 | #define AUD_B_DOWN_CLUSTER_3 0x0B780 |
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| 219 | |
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| 220 | #define AUD_C_DOWN_CLUSTER_1 0x0B800 |
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| 221 | #define AUD_C_DOWN_CLUSTER_2 0x0B880 |
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| 222 | #define AUD_C_DOWN_CLUSTER_3 0x0B900 |
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| 223 | |
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| 224 | #define AUD_D_DOWN_CLUSTER_1 0x0B980 |
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| 225 | #define AUD_D_DOWN_CLUSTER_2 0x0BA00 |
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| 226 | #define AUD_D_DOWN_CLUSTER_3 0x0BA80 |
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| 227 | |
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| 228 | #define TX_SRAM_POOL_FREE 0x0BB00 |
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| 229 | #define TX_SRAM_END 0x0C000 |
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| 230 | |
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| 231 | #define BYTES_TO_DWORDS(bcount) ((bcount) >> 2) |
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| 232 | #define BYTES_TO_QWORDS(bcount) ((bcount) >> 3) |
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| 233 | #define BYTES_TO_OWORDS(bcount) ((bcount) >> 4) |
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| 234 | |
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| 235 | #define VID_IQ_SIZE_DW BYTES_TO_DWORDS(VID_IQ_SIZE) |
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| 236 | #define VID_CDT_SIZE_QW BYTES_TO_QWORDS(VID_CDT_SIZE) |
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| 237 | #define VID_CLUSTER_SIZE_OW BYTES_TO_OWORDS(VID_CLUSTER_SIZE) |
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| 238 | |
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| 239 | #define AUDIO_IQ_SIZE_DW BYTES_TO_DWORDS(AUDIO_IQ_SIZE) |
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| 240 | #define AUDIO_CDT_SIZE_QW BYTES_TO_QWORDS(AUDIO_CDT_SIZE) |
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| 241 | #define AUDIO_CLUSTER_SIZE_QW BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE) |
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| 242 | |
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| 243 | #define MBIF_IQ_SIZE_DW BYTES_TO_DWORDS(MBIF_IQ_SIZE) |
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| 244 | #define MBIF_CDT_SIZE_QW BYTES_TO_QWORDS(MBIF_CDT_SIZE) |
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| 245 | #define MBIF_CLUSTER_SIZE_OW BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE) |
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| 246 | |
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| 247 | #endif |
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| 248 | |
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