| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * ddbridge-regs.h: Digital Devices PCIe bridge driver |
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| 4 | * |
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| 5 | * Copyright (C) 2010-2017 Digital Devices GmbH |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __DDBRIDGE_REGS_H__ |
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| 9 | #define __DDBRIDGE_REGS_H__ |
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| 10 | |
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| 11 | /* ------------------------------------------------------------------------- */ |
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| 12 | /* SPI Controller */ |
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| 13 | |
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| 14 | #define SPI_CONTROL 0x10 |
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| 15 | #define SPI_DATA 0x14 |
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| 16 | |
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| 17 | /* ------------------------------------------------------------------------- */ |
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| 18 | /* GPIO */ |
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| 19 | |
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| 20 | #define GPIO_OUTPUT 0x20 |
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| 21 | #define GPIO_INPUT 0x24 |
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| 22 | #define GPIO_DIRECTION 0x28 |
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| 23 | |
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| 24 | /* ------------------------------------------------------------------------- */ |
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| 25 | |
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| 26 | #define BOARD_CONTROL 0x30 |
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| 27 | |
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| 28 | /* ------------------------------------------------------------------------- */ |
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| 29 | |
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| 30 | /* Interrupt controller |
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| 31 | * How many MSI's are available depends on HW (Min 2 max 8) |
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| 32 | * How many are usable also depends on Host platform |
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| 33 | */ |
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| 34 | |
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| 35 | #define INTERRUPT_BASE (0x40) |
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| 36 | |
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| 37 | #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00) |
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| 38 | #define MSI1_ENABLE (INTERRUPT_BASE + 0x04) |
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| 39 | #define MSI2_ENABLE (INTERRUPT_BASE + 0x08) |
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| 40 | #define MSI3_ENABLE (INTERRUPT_BASE + 0x0C) |
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| 41 | #define MSI4_ENABLE (INTERRUPT_BASE + 0x10) |
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| 42 | #define MSI5_ENABLE (INTERRUPT_BASE + 0x14) |
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| 43 | #define MSI6_ENABLE (INTERRUPT_BASE + 0x18) |
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| 44 | #define MSI7_ENABLE (INTERRUPT_BASE + 0x1C) |
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| 45 | |
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| 46 | #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) |
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| 47 | #define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) |
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| 48 | |
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| 49 | /* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */ |
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| 50 | #define TEMPMON_BASE (0x1c0) |
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| 51 | #define TEMPMON_CONTROL (TEMPMON_BASE + 0x00) |
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| 52 | |
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| 53 | #define TEMPMON_CONTROL_AUTOSCAN (0x00000002) |
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| 54 | #define TEMPMON_CONTROL_INTENABLE (0x00000004) |
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| 55 | #define TEMPMON_CONTROL_OVERTEMP (0x00008000) |
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| 56 | |
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| 57 | /* SHORT Temperature in Celsius x 256 */ |
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| 58 | #define TEMPMON_SENSOR0 (TEMPMON_BASE + 0x04) |
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| 59 | #define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08) |
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| 60 | |
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| 61 | #define TEMPMON_FANCONTROL (TEMPMON_BASE + 0x10) |
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| 62 | |
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| 63 | /* ------------------------------------------------------------------------- */ |
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| 64 | /* I2C Master Controller */ |
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| 65 | |
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| 66 | #define I2C_COMMAND (0x00) |
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| 67 | #define I2C_TIMING (0x04) |
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| 68 | #define I2C_TASKLENGTH (0x08) /* High read, low write */ |
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| 69 | #define I2C_TASKADDRESS (0x0C) /* High read, low write */ |
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| 70 | #define I2C_MONITOR (0x1C) |
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| 71 | |
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| 72 | #define I2C_SPEED_400 (0x04030404) |
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| 73 | #define I2C_SPEED_100 (0x13121313) |
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| 74 | |
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| 75 | /* ------------------------------------------------------------------------- */ |
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| 76 | /* DMA Controller */ |
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| 77 | |
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| 78 | #define DMA_BASE_WRITE (0x100) |
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| 79 | #define DMA_BASE_READ (0x140) |
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| 80 | |
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| 81 | #define TS_CONTROL(_io) ((_io)->regs + 0x00) |
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| 82 | #define TS_CONTROL2(_io) ((_io)->regs + 0x04) |
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| 83 | |
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| 84 | /* ------------------------------------------------------------------------- */ |
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| 85 | /* DMA Buffer */ |
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| 86 | |
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| 87 | #define DMA_BUFFER_CONTROL(_dma) ((_dma)->regs + 0x00) |
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| 88 | #define DMA_BUFFER_ACK(_dma) ((_dma)->regs + 0x04) |
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| 89 | #define DMA_BUFFER_CURRENT(_dma) ((_dma)->regs + 0x08) |
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| 90 | #define DMA_BUFFER_SIZE(_dma) ((_dma)->regs + 0x0c) |
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| 91 | |
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| 92 | /* ------------------------------------------------------------------------- */ |
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| 93 | /* CI Interface (only CI-Bridge) */ |
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| 94 | |
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| 95 | #define CI_BASE (0x400) |
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| 96 | #define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00) |
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| 97 | |
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| 98 | #define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04) |
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| 99 | #define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08) |
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| 100 | #define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c) |
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| 101 | #define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10) |
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| 102 | |
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| 103 | #define CI_RESET_CAM (0x00000001) |
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| 104 | #define CI_POWER_ON (0x00000002) |
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| 105 | #define CI_ENABLE (0x00000004) |
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| 106 | #define CI_BYPASS_DISABLE (0x00000010) |
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| 107 | |
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| 108 | #define CI_CAM_READY (0x00010000) |
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| 109 | #define CI_CAM_DETECT (0x00020000) |
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| 110 | #define CI_READY (0x80000000) |
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| 111 | |
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| 112 | #define CI_READ_CMD (0x40000000) |
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| 113 | #define CI_WRITE_CMD (0x80000000) |
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| 114 | |
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| 115 | #define CI_BUFFER_BASE (0x3000) |
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| 116 | #define CI_BUFFER_SIZE (0x0800) |
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| 117 | |
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| 118 | #define CI_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE) |
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| 119 | |
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| 120 | /* ------------------------------------------------------------------------- */ |
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| 121 | /* LNB commands (mxl5xx / Max S8) */ |
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| 122 | |
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| 123 | #define LNB_BASE (0x400) |
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| 124 | #define LNB_CONTROL(i) (LNB_BASE + (i) * 0x20 + 0x00) |
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| 125 | |
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| 126 | #define LNB_CMD (7ULL << 0) |
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| 127 | #define LNB_CMD_NOP 0 |
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| 128 | #define LNB_CMD_INIT 1 |
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| 129 | #define LNB_CMD_LOW 3 |
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| 130 | #define LNB_CMD_HIGH 4 |
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| 131 | #define LNB_CMD_OFF 5 |
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| 132 | #define LNB_CMD_DISEQC 6 |
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| 133 | |
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| 134 | #define LNB_BUSY BIT_ULL(4) |
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| 135 | #define LNB_TONE BIT_ULL(15) |
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| 136 | |
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| 137 | #define LNB_BUF_LEVEL(i) (LNB_BASE + (i) * 0x20 + 0x10) |
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| 138 | #define LNB_BUF_WRITE(i) (LNB_BASE + (i) * 0x20 + 0x14) |
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| 139 | |
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| 140 | #endif /* __DDBRIDGE_REGS_H__ */ |
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| 141 | |
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