| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | interrupt handling |
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| 4 | Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com> |
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| 5 | Copyright (C) 2004 Chris Kennedy <c@groovy.org> |
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| 6 | Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl> |
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| 7 | |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef IVTV_IRQ_H |
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| 11 | #define IVTV_IRQ_H |
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| 12 | |
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| 13 | #define IVTV_IRQ_ENC_START_CAP BIT(31) |
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| 14 | #define IVTV_IRQ_ENC_EOS BIT(30) |
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| 15 | #define IVTV_IRQ_ENC_VBI_CAP BIT(29) |
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| 16 | #define IVTV_IRQ_ENC_VIM_RST BIT(28) |
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| 17 | #define IVTV_IRQ_ENC_DMA_COMPLETE BIT(27) |
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| 18 | #define IVTV_IRQ_ENC_PIO_COMPLETE BIT(25) |
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| 19 | #define IVTV_IRQ_DEC_AUD_MODE_CHG BIT(24) |
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| 20 | #define IVTV_IRQ_DEC_DATA_REQ BIT(22) |
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| 21 | #define IVTV_IRQ_DEC_DMA_COMPLETE BIT(20) |
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| 22 | #define IVTV_IRQ_DEC_VBI_RE_INSERT BIT(19) |
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| 23 | #define IVTV_IRQ_DMA_ERR BIT(18) |
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| 24 | #define IVTV_IRQ_DMA_WRITE BIT(17) |
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| 25 | #define IVTV_IRQ_DMA_READ BIT(16) |
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| 26 | #define IVTV_IRQ_DEC_VSYNC BIT(10) |
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| 27 | |
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| 28 | /* IRQ Masks */ |
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| 29 | #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\ |
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| 30 | IVTV_IRQ_DMA_READ|IVTV_IRQ_ENC_PIO_COMPLETE) |
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| 31 | |
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| 32 | #define IVTV_IRQ_MASK_CAPTURE (IVTV_IRQ_ENC_START_CAP | IVTV_IRQ_ENC_EOS) |
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| 33 | #define IVTV_IRQ_MASK_DECODE (IVTV_IRQ_DEC_DATA_REQ|IVTV_IRQ_DEC_AUD_MODE_CHG) |
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| 34 | |
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| 35 | irqreturn_t ivtv_irq_handler(int irq, void *dev_id); |
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| 36 | |
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| 37 | void ivtv_irq_work_handler(struct kthread_work *work); |
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| 38 | void ivtv_dma_stream_dec_prepare(struct ivtv_stream *s, u32 offset, int lock); |
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| 39 | void ivtv_unfinished_dma(struct timer_list *t); |
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| 40 | |
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| 41 | #endif |
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| 42 | |
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