| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* DMA controller registers */ |
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| 3 | #define REG8_1(a0) ((const u16[8]) { a0, a0 + 1, a0 + 2, a0 + 3, \ |
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| 4 | a0 + 4, a0 + 5, a0 + 6, a0 + 7}) |
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| 5 | #define REG8_2(a0) ((const u16[8]) { a0, a0 + 2, a0 + 4, a0 + 6, \ |
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| 6 | a0 + 8, a0 + 0xa, a0 + 0xc, a0 + 0xe}) |
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| 7 | #define REG8_8(a0) ((const u16[8]) { a0, a0 + 8, a0 + 0x10, a0 + 0x18, \ |
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| 8 | a0 + 0x20, a0 + 0x28, a0 + 0x30, \ |
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| 9 | a0 + 0x38}) |
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| 10 | #define INT_STATUS 0x00 |
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| 11 | #define PB_STATUS 0x01 |
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| 12 | #define DMA_CMD 0x02 |
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| 13 | #define VIDEO_FIFO_STATUS 0x03 |
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| 14 | #define VIDEO_CHANNEL_ID 0x04 |
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| 15 | #define VIDEO_PARSER_STATUS 0x05 |
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| 16 | #define SYS_SOFT_RST 0x06 |
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| 17 | #define DMA_PAGE_TABLE0_ADDR ((const u16[8]) { 0x08, 0xd0, 0xd2, 0xd4, \ |
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| 18 | 0xd6, 0xd8, 0xda, 0xdc }) |
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| 19 | #define DMA_PAGE_TABLE1_ADDR ((const u16[8]) { 0x09, 0xd1, 0xd3, 0xd5, \ |
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| 20 | 0xd7, 0xd9, 0xdb, 0xdd }) |
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| 21 | #define DMA_CHANNEL_ENABLE 0x0a |
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| 22 | #define DMA_CONFIG 0x0b |
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| 23 | #define DMA_TIMER_INTERVAL 0x0c |
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| 24 | #define DMA_CHANNEL_TIMEOUT 0x0d |
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| 25 | #define VDMA_CHANNEL_CONFIG REG8_1(0x10) |
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| 26 | #define ADMA_P_ADDR REG8_2(0x18) |
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| 27 | #define ADMA_B_ADDR REG8_2(0x19) |
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| 28 | #define DMA10_P_ADDR 0x28 |
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| 29 | #define DMA10_B_ADDR 0x29 |
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| 30 | #define VIDEO_CONTROL1 0x2a |
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| 31 | #define VIDEO_CONTROL2 0x2b |
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| 32 | #define AUDIO_CONTROL1 0x2c |
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| 33 | #define AUDIO_CONTROL2 0x2d |
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| 34 | #define PHASE_REF 0x2e |
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| 35 | #define GPIO_REG 0x2f |
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| 36 | #define INTL_HBAR_CTRL REG8_1(0x30) |
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| 37 | #define AUDIO_CONTROL3 0x38 |
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| 38 | #define VIDEO_FIELD_CTRL REG8_1(0x39) |
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| 39 | #define HSCALER_CTRL REG8_1(0x42) |
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| 40 | #define VIDEO_SIZE REG8_1(0x4A) |
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| 41 | #define VIDEO_SIZE_F2 REG8_1(0x52) |
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| 42 | #define MD_CONF REG8_1(0x60) |
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| 43 | #define MD_INIT REG8_1(0x68) |
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| 44 | #define MD_MAP0 REG8_1(0x70) |
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| 45 | #define VDMA_P_ADDR REG8_8(0x80) /* not used in DMA SG mode */ |
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| 46 | #define VDMA_WHP REG8_8(0x81) |
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| 47 | #define VDMA_B_ADDR REG8_8(0x82) |
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| 48 | #define VDMA_F2_P_ADDR REG8_8(0x84) |
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| 49 | #define VDMA_F2_WHP REG8_8(0x85) |
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| 50 | #define VDMA_F2_B_ADDR REG8_8(0x86) |
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| 51 | #define EP_REG_ADDR 0xfe |
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| 52 | #define EP_REG_DATA 0xff |
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| 53 | |
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| 54 | /* Video decoder registers */ |
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| 55 | #define VDREG8(a0) ((const u16[8]) { \ |
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| 56 | a0 + 0x000, a0 + 0x010, a0 + 0x020, a0 + 0x030, \ |
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| 57 | a0 + 0x100, a0 + 0x110, a0 + 0x120, a0 + 0x130}) |
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| 58 | #define VIDSTAT VDREG8(0x100) |
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| 59 | #define BRIGHT VDREG8(0x101) |
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| 60 | #define CONTRAST VDREG8(0x102) |
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| 61 | #define SHARPNESS VDREG8(0x103) |
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| 62 | #define SAT_U VDREG8(0x104) |
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| 63 | #define SAT_V VDREG8(0x105) |
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| 64 | #define HUE VDREG8(0x106) |
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| 65 | #define CROP_HI VDREG8(0x107) |
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| 66 | #define VDELAY_LO VDREG8(0x108) |
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| 67 | #define VACTIVE_LO VDREG8(0x109) |
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| 68 | #define HDELAY_LO VDREG8(0x10a) |
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| 69 | #define HACTIVE_LO VDREG8(0x10b) |
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| 70 | #define MVSN VDREG8(0x10c) |
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| 71 | #define STATUS2 VDREG8(0x10d) |
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| 72 | #define SDT VDREG8(0x10e) |
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| 73 | #define SDT_EN VDREG8(0x10f) |
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| 74 | |
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| 75 | #define VSCALE_LO VDREG8(0x144) |
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| 76 | #define SCALE_HI VDREG8(0x145) |
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| 77 | #define HSCALE_LO VDREG8(0x146) |
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| 78 | #define F2CROP_HI VDREG8(0x147) |
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| 79 | #define F2VDELAY_LO VDREG8(0x148) |
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| 80 | #define F2VACTIVE_LO VDREG8(0x149) |
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| 81 | #define F2HDELAY_LO VDREG8(0x14a) |
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| 82 | #define F2HACTIVE_LO VDREG8(0x14b) |
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| 83 | #define F2VSCALE_LO VDREG8(0x14c) |
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| 84 | #define F2SCALE_HI VDREG8(0x14d) |
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| 85 | #define F2HSCALE_LO VDREG8(0x14e) |
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| 86 | #define F2CNT VDREG8(0x14f) |
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| 87 | |
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| 88 | #define VDREG2(a0) ((const u16[2]) { a0, a0 + 0x100 }) |
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| 89 | #define SRST VDREG2(0x180) |
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| 90 | #define ACNTL VDREG2(0x181) |
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| 91 | #define ACNTL2 VDREG2(0x182) |
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| 92 | #define CNTRL1 VDREG2(0x183) |
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| 93 | #define CKHY VDREG2(0x184) |
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| 94 | #define SHCOR VDREG2(0x185) |
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| 95 | #define CORING VDREG2(0x186) |
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| 96 | #define CLMPG VDREG2(0x187) |
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| 97 | #define IAGC VDREG2(0x188) |
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| 98 | #define VCTRL1 VDREG2(0x18f) |
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| 99 | #define MISC1 VDREG2(0x194) |
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| 100 | #define LOOP VDREG2(0x195) |
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| 101 | #define MISC2 VDREG2(0x196) |
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| 102 | |
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| 103 | #define CLMD VDREG2(0x197) |
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| 104 | #define ANPWRDOWN VDREG2(0x1ce) |
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| 105 | #define AIGAIN ((const u16[8]) { 0x1d0, 0x1d1, 0x1d2, 0x1d3, \ |
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| 106 | 0x2d0, 0x2d1, 0x2d2, 0x2d3 }) |
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| 107 | |
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| 108 | #define SYS_MODE_DMA_SHIFT 13 |
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| 109 | #define AUDIO_DMA_SIZE_SHIFT 19 |
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| 110 | #define AUDIO_DMA_SIZE_MIN SZ_512 |
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| 111 | #define AUDIO_DMA_SIZE_MAX SZ_4K |
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| 112 | #define AUDIO_DMA_SIZE_MASK (SZ_8K - 1) |
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| 113 | |
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| 114 | #define DMA_CMD_ENABLE BIT(31) |
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| 115 | #define INT_STATUS_DMA_TOUT BIT(17) |
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| 116 | #define TW686X_VIDSTAT_HLOCK BIT(6) |
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| 117 | #define TW686X_VIDSTAT_VDLOSS BIT(7) |
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| 118 | |
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| 119 | #define TW686X_STD_NTSC_M 0 |
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| 120 | #define TW686X_STD_PAL 1 |
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| 121 | #define TW686X_STD_SECAM 2 |
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| 122 | #define TW686X_STD_NTSC_443 3 |
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| 123 | #define TW686X_STD_PAL_M 4 |
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| 124 | #define TW686X_STD_PAL_CN 5 |
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| 125 | #define TW686X_STD_PAL_60 6 |
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| 126 | |
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| 127 | #define TW686X_FIELD_MODE 0x3 |
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| 128 | #define TW686X_FRAME_MODE 0x2 |
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| 129 | /* 0x1 is reserved */ |
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| 130 | #define TW686X_SG_MODE 0x0 |
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| 131 | |
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| 132 | #define TW686X_FIFO_ERROR(x) (x & ~(0xff)) |
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| 133 | |
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