1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Zoran ZR36060 basic configuration functions - header file
4 *
5 * Copyright (C) 2002 Laurent Pinchart <laurent.pinchart@skynet.be>
6 */
7
8#ifndef ZR36060_H
9#define ZR36060_H
10
11#include "videocodec.h"
12
13/* data stored for each zoran jpeg codec chip */
14struct zr36060 {
15 char name[32];
16 int num;
17 /* io datastructure */
18 struct videocodec *codec;
19 // last coder status
20 __u8 status;
21 // actual coder setup
22 int mode;
23
24 __u16 width;
25 __u16 height;
26
27 __u16 bitrate_ctrl;
28
29 __u32 total_code_vol;
30 __u32 real_code_vol;
31 __u16 max_block_vol;
32
33 __u8 h_samp_ratio[8];
34 __u8 v_samp_ratio[8];
35 __u16 scalefact;
36 __u16 dri;
37
38 /* app/com marker data */
39 struct jpeg_app_marker app;
40 struct jpeg_com_marker com;
41};
42
43/* ZR36060 register addresses */
44#define ZR060_LOAD 0x000
45#define ZR060_CFSR 0x001
46#define ZR060_CIR 0x002
47#define ZR060_CMR 0x003
48#define ZR060_MBZ 0x004
49#define ZR060_MBCVR 0x005
50#define ZR060_MER 0x006
51#define ZR060_IMR 0x007
52#define ZR060_ISR 0x008
53#define ZR060_TCV_NET_HI 0x009
54#define ZR060_TCV_NET_MH 0x00a
55#define ZR060_TCV_NET_ML 0x00b
56#define ZR060_TCV_NET_LO 0x00c
57#define ZR060_TCV_DATA_HI 0x00d
58#define ZR060_TCV_DATA_MH 0x00e
59#define ZR060_TCV_DATA_ML 0x00f
60#define ZR060_TCV_DATA_LO 0x010
61#define ZR060_SF_HI 0x011
62#define ZR060_SF_LO 0x012
63#define ZR060_AF_HI 0x013
64#define ZR060_AF_M 0x014
65#define ZR060_AF_LO 0x015
66#define ZR060_ACV_HI 0x016
67#define ZR060_ACV_MH 0x017
68#define ZR060_ACV_ML 0x018
69#define ZR060_ACV_LO 0x019
70#define ZR060_ACT_HI 0x01a
71#define ZR060_ACT_MH 0x01b
72#define ZR060_ACT_ML 0x01c
73#define ZR060_ACT_LO 0x01d
74#define ZR060_ACV_TURN_HI 0x01e
75#define ZR060_ACV_TURN_MH 0x01f
76#define ZR060_ACV_TURN_ML 0x020
77#define ZR060_ACV_TURN_LO 0x021
78#define ZR060_IDR_DEV 0x022
79#define ZR060_IDR_REV 0x023
80#define ZR060_TCR_HI 0x024
81#define ZR060_TCR_LO 0x025
82#define ZR060_VCR 0x030
83#define ZR060_VPR 0x031
84#define ZR060_SR 0x032
85#define ZR060_BCR_Y 0x033
86#define ZR060_BCR_U 0x034
87#define ZR060_BCR_V 0x035
88#define ZR060_SGR_VTOTAL_HI 0x036
89#define ZR060_SGR_VTOTAL_LO 0x037
90#define ZR060_SGR_HTOTAL_HI 0x038
91#define ZR060_SGR_HTOTAL_LO 0x039
92#define ZR060_SGR_VSYNC 0x03a
93#define ZR060_SGR_HSYNC 0x03b
94#define ZR060_SGR_BVSTART 0x03c
95#define ZR060_SGR_BHSTART 0x03d
96#define ZR060_SGR_BVEND_HI 0x03e
97#define ZR060_SGR_BVEND_LO 0x03f
98#define ZR060_SGR_BHEND_HI 0x040
99#define ZR060_SGR_BHEND_LO 0x041
100#define ZR060_AAR_VSTART_HI 0x042
101#define ZR060_AAR_VSTART_LO 0x043
102#define ZR060_AAR_VEND_HI 0x044
103#define ZR060_AAR_VEND_LO 0x045
104#define ZR060_AAR_HSTART_HI 0x046
105#define ZR060_AAR_HSTART_LO 0x047
106#define ZR060_AAR_HEND_HI 0x048
107#define ZR060_AAR_HEND_LO 0x049
108#define ZR060_SWR_VSTART_HI 0x04a
109#define ZR060_SWR_VSTART_LO 0x04b
110#define ZR060_SWR_VEND_HI 0x04c
111#define ZR060_SWR_VEND_LO 0x04d
112#define ZR060_SWR_HSTART_HI 0x04e
113#define ZR060_SWR_HSTART_LO 0x04f
114#define ZR060_SWR_HEND_HI 0x050
115#define ZR060_SWR_HEND_LO 0x051
116
117#define ZR060_SOF_IDX 0x060
118#define ZR060_SOS_IDX 0x07a
119#define ZR060_DRI_IDX 0x0c0
120#define ZR060_DQT_IDX 0x0cc
121#define ZR060_DHT_IDX 0x1d4
122#define ZR060_APP_IDX 0x380
123#define ZR060_COM_IDX 0x3c0
124
125/* ZR36060 LOAD register bits */
126
127#define ZR060_LOAD_LOAD BIT(7)
128#define ZR060_LOAD_SYNC_RST BIT(0)
129
130/* ZR36060 Code FIFO Status register bits */
131
132#define ZR060_CFSR_BUSY BIT(7)
133#define ZR060_CFSR_C_BUSY BIT(2)
134#define ZR060_CFSR_CFIFO (3 << 0)
135
136/* ZR36060 Code Interface register */
137
138#define ZR060_CIR_CODE16 BIT(7)
139#define ZR060_CIR_ENDIAN BIT(6)
140#define ZR060_CIR_CFIS BIT(2)
141#define ZR060_CIR_CODE_MSTR BIT(0)
142
143/* ZR36060 Codec Mode register */
144
145#define ZR060_CMR_COMP BIT(7)
146#define ZR060_CMR_ATP BIT(6)
147#define ZR060_CMR_PASS2 BIT(5)
148#define ZR060_CMR_TLM BIT(4)
149#define ZR060_CMR_BRB BIT(2)
150#define ZR060_CMR_FSF BIT(1)
151
152/* ZR36060 Markers Enable register */
153
154#define ZR060_MER_APP BIT(7)
155#define ZR060_MER_COM BIT(6)
156#define ZR060_MER_DRI BIT(5)
157#define ZR060_MER_DQT BIT(4)
158#define ZR060_MER_DHT BIT(3)
159
160/* ZR36060 Interrupt Mask register */
161
162#define ZR060_IMR_EOAV BIT(3)
163#define ZR060_IMR_EOI BIT(2)
164#define ZR060_IMR_END BIT(1)
165#define ZR060_IMR_DATA_ERR BIT(0)
166
167/* ZR36060 Interrupt Status register */
168
169#define ZR060_ISR_PRO_CNT (3 << 6)
170#define ZR060_ISR_EOAV BIT(3)
171#define ZR060_ISR_EOI BIT(2)
172#define ZR060_ISR_END BIT(1)
173#define ZR060_ISR_DATA_ERR BIT(0)
174
175/* ZR36060 Video Control register */
176
177#define ZR060_VCR_VIDEO8 BIT(7)
178#define ZR060_VCR_RANGE BIT(6)
179#define ZR060_VCR_FI_DET BIT(3)
180#define ZR060_VCR_FI_VEDGE BIT(2)
181#define ZR060_VCR_FI_EXT BIT(1)
182#define ZR060_VCR_SYNC_MSTR BIT(0)
183
184/* ZR36060 Video Polarity register */
185
186#define ZR060_VPR_VCLK_POL BIT(7)
187#define ZR060_VPR_P_VAL_POL BIT(6)
188#define ZR060_VPR_POE_POL BIT(5)
189#define ZR060_VPR_S_IMG_POL BIT(4)
190#define ZR060_VPR_BL_POL BIT(3)
191#define ZR060_VPR_FI_POL BIT(2)
192#define ZR060_VPR_HS_POL BIT(1)
193#define ZR060_VPR_VS_POL BIT(0)
194
195/* ZR36060 Scaling register */
196
197#define ZR060_SR_V_SCALE BIT(2)
198#define ZR060_SR_H_SCALE2 BIT(0)
199#define ZR060_SR_H_SCALE4 (2 << 0)
200
201int zr36060_init_module(void);
202void zr36060_cleanup_module(void);
203#endif /*fndef ZR36060_H */
204

source code of linux/drivers/media/pci/zoran/zr36060.h