| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Register definitions for the Atmel Image Sensor Interface. |
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| 4 | * |
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| 5 | * Copyright (C) 2011 Atmel Corporation |
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| 6 | * Josh Wu, <josh.wu@atmel.com> |
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| 7 | * |
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| 8 | * Based on previous work by Lars Haring, <lars.haring@atmel.com> |
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| 9 | * and Sedji Gaouaou |
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| 10 | */ |
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| 11 | #ifndef __ATMEL_ISI_H__ |
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| 12 | #define __ATMEL_ISI_H__ |
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| 13 | |
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| 14 | #include <linux/types.h> |
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| 15 | |
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| 16 | /* ISI_V2 register offsets */ |
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| 17 | #define ISI_CFG1 0x0000 |
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| 18 | #define ISI_CFG2 0x0004 |
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| 19 | #define ISI_PSIZE 0x0008 |
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| 20 | #define ISI_PDECF 0x000c |
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| 21 | #define ISI_Y2R_SET0 0x0010 |
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| 22 | #define ISI_Y2R_SET1 0x0014 |
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| 23 | #define ISI_R2Y_SET0 0x0018 |
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| 24 | #define ISI_R2Y_SET1 0x001C |
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| 25 | #define ISI_R2Y_SET2 0x0020 |
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| 26 | #define ISI_CTRL 0x0024 |
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| 27 | #define ISI_STATUS 0x0028 |
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| 28 | #define ISI_INTEN 0x002C |
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| 29 | #define ISI_INTDIS 0x0030 |
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| 30 | #define ISI_INTMASK 0x0034 |
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| 31 | #define ISI_DMA_CHER 0x0038 |
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| 32 | #define ISI_DMA_CHDR 0x003C |
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| 33 | #define ISI_DMA_CHSR 0x0040 |
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| 34 | #define ISI_DMA_P_ADDR 0x0044 |
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| 35 | #define ISI_DMA_P_CTRL 0x0048 |
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| 36 | #define ISI_DMA_P_DSCR 0x004C |
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| 37 | #define ISI_DMA_C_ADDR 0x0050 |
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| 38 | #define ISI_DMA_C_CTRL 0x0054 |
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| 39 | #define ISI_DMA_C_DSCR 0x0058 |
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| 40 | |
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| 41 | /* Bitfields in CFG1 */ |
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| 42 | #define ISI_CFG1_HSYNC_POL_ACTIVE_LOW (1 << 2) |
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| 43 | #define ISI_CFG1_VSYNC_POL_ACTIVE_LOW (1 << 3) |
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| 44 | #define ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING (1 << 4) |
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| 45 | #define ISI_CFG1_EMB_SYNC (1 << 6) |
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| 46 | #define ISI_CFG1_CRC_SYNC (1 << 7) |
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| 47 | /* Constants for FRATE(ISI_V2) */ |
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| 48 | #define ISI_CFG1_FRATE_CAPTURE_ALL (0 << 8) |
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| 49 | #define ISI_CFG1_FRATE_DIV_2 (1 << 8) |
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| 50 | #define ISI_CFG1_FRATE_DIV_3 (2 << 8) |
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| 51 | #define ISI_CFG1_FRATE_DIV_4 (3 << 8) |
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| 52 | #define ISI_CFG1_FRATE_DIV_5 (4 << 8) |
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| 53 | #define ISI_CFG1_FRATE_DIV_6 (5 << 8) |
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| 54 | #define ISI_CFG1_FRATE_DIV_7 (6 << 8) |
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| 55 | #define ISI_CFG1_FRATE_DIV_8 (7 << 8) |
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| 56 | #define ISI_CFG1_FRATE_DIV_MASK (7 << 8) |
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| 57 | #define ISI_CFG1_DISCR (1 << 11) |
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| 58 | #define ISI_CFG1_FULL_MODE (1 << 12) |
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| 59 | /* Definition for THMASK(ISI_V2) */ |
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| 60 | #define ISI_CFG1_THMASK_BEATS_4 (0 << 13) |
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| 61 | #define ISI_CFG1_THMASK_BEATS_8 (1 << 13) |
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| 62 | #define ISI_CFG1_THMASK_BEATS_16 (2 << 13) |
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| 63 | |
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| 64 | /* Bitfields in CFG2 */ |
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| 65 | #define ISI_CFG2_GS_MODE_2_PIXEL (0 << 11) |
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| 66 | #define ISI_CFG2_GS_MODE_1_PIXEL (1 << 11) |
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| 67 | #define ISI_CFG2_GRAYSCALE (1 << 13) |
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| 68 | #define ISI_CFG2_COL_SPACE_YCbCr (0 << 15) |
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| 69 | #define ISI_CFG2_COL_SPACE_RGB (1 << 15) |
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| 70 | /* Constants for YCC_SWAP(ISI_V2) */ |
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| 71 | #define ISI_CFG2_YCC_SWAP_DEFAULT (0 << 28) |
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| 72 | #define ISI_CFG2_YCC_SWAP_MODE_1 (1 << 28) |
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| 73 | #define ISI_CFG2_YCC_SWAP_MODE_2 (2 << 28) |
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| 74 | #define ISI_CFG2_YCC_SWAP_MODE_3 (3 << 28) |
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| 75 | #define ISI_CFG2_YCC_SWAP_MODE_MASK (3 << 28) |
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| 76 | #define ISI_CFG2_IM_VSIZE_OFFSET 0 |
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| 77 | #define ISI_CFG2_IM_HSIZE_OFFSET 16 |
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| 78 | #define ISI_CFG2_IM_VSIZE_MASK (0x7FF << ISI_CFG2_IM_VSIZE_OFFSET) |
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| 79 | #define ISI_CFG2_IM_HSIZE_MASK (0x7FF << ISI_CFG2_IM_HSIZE_OFFSET) |
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| 80 | |
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| 81 | /* Bitfields in PSIZE */ |
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| 82 | #define ISI_PSIZE_PREV_VSIZE_OFFSET 0 |
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| 83 | #define ISI_PSIZE_PREV_HSIZE_OFFSET 16 |
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| 84 | #define ISI_PSIZE_PREV_VSIZE_MASK (0x3FF << ISI_PSIZE_PREV_VSIZE_OFFSET) |
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| 85 | #define ISI_PSIZE_PREV_HSIZE_MASK (0x3FF << ISI_PSIZE_PREV_HSIZE_OFFSET) |
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| 86 | |
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| 87 | /* Bitfields in PDECF */ |
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| 88 | #define ISI_PDECF_DEC_FACTOR_MASK (0xFF << 0) |
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| 89 | #define ISI_PDECF_NO_SAMPLING (16) |
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| 90 | |
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| 91 | /* Bitfields in CTRL */ |
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| 92 | /* Also using in SR(ISI_V2) */ |
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| 93 | #define ISI_CTRL_EN (1 << 0) |
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| 94 | #define ISI_CTRL_CDC (1 << 8) |
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| 95 | /* Also using in SR/IER/IDR/IMR(ISI_V2) */ |
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| 96 | #define ISI_CTRL_DIS (1 << 1) |
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| 97 | #define ISI_CTRL_SRST (1 << 2) |
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| 98 | |
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| 99 | /* Bitfields in SR */ |
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| 100 | #define ISI_SR_SIP (1 << 19) |
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| 101 | /* Also using in SR/IER/IDR/IMR */ |
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| 102 | #define ISI_SR_VSYNC (1 << 10) |
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| 103 | #define ISI_SR_PXFR_DONE (1 << 16) |
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| 104 | #define ISI_SR_CXFR_DONE (1 << 17) |
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| 105 | #define ISI_SR_P_OVR (1 << 24) |
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| 106 | #define ISI_SR_C_OVR (1 << 25) |
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| 107 | #define ISI_SR_CRC_ERR (1 << 26) |
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| 108 | #define ISI_SR_FR_OVR (1 << 27) |
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| 109 | |
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| 110 | /* Bitfields in DMA_C_CTRL & in DMA_P_CTRL */ |
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| 111 | #define ISI_DMA_CTRL_FETCH (1 << 0) |
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| 112 | #define ISI_DMA_CTRL_WB (1 << 1) |
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| 113 | #define ISI_DMA_CTRL_IEN (1 << 2) |
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| 114 | #define ISI_DMA_CTRL_DONE (1 << 3) |
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| 115 | |
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| 116 | /* Bitfields in DMA_CHSR/CHER/CHDR */ |
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| 117 | #define ISI_DMA_CHSR_P_CH (1 << 0) |
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| 118 | #define ISI_DMA_CHSR_C_CH (1 << 1) |
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| 119 | |
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| 120 | /* Definition for isi_platform_data */ |
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| 121 | #define ISI_DATAWIDTH_8 0x01 |
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| 122 | #define ISI_DATAWIDTH_10 0x02 |
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| 123 | |
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| 124 | struct isi_platform_data { |
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| 125 | u8 has_emb_sync; |
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| 126 | u8 hsync_act_low; |
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| 127 | u8 vsync_act_low; |
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| 128 | u8 pclk_act_falling; |
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| 129 | u8 full_mode; |
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| 130 | u32 data_width_flags; |
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| 131 | /* Using for ISI_CFG1 */ |
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| 132 | u32 frate; |
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| 133 | }; |
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| 134 | |
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| 135 | #endif /* __ATMEL_ISI_H__ */ |
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| 136 | |
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