1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Marvell camera core structures. |
4 | * |
5 | * Copyright 2011 Jonathan Corbet corbet@lwn.net |
6 | */ |
7 | #ifndef _MCAM_CORE_H |
8 | #define _MCAM_CORE_H |
9 | |
10 | #include <linux/list.h> |
11 | #include <linux/clk-provider.h> |
12 | #include <media/v4l2-common.h> |
13 | #include <media/v4l2-ctrls.h> |
14 | #include <media/v4l2-dev.h> |
15 | #include <media/videobuf2-v4l2.h> |
16 | |
17 | /* |
18 | * Create our own symbols for the supported buffer modes, but, for now, |
19 | * base them entirely on which videobuf2 options have been selected. |
20 | */ |
21 | #if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC) |
22 | #define MCAM_MODE_VMALLOC 1 |
23 | #endif |
24 | |
25 | #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG) |
26 | #define MCAM_MODE_DMA_CONTIG 1 |
27 | #endif |
28 | |
29 | #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG) |
30 | #define MCAM_MODE_DMA_SG 1 |
31 | #endif |
32 | |
33 | #if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \ |
34 | !defined(MCAM_MODE_DMA_SG) |
35 | #error One of the vb2 buffer modes must be selected in the config |
36 | #endif |
37 | |
38 | |
39 | enum mcam_state { |
40 | S_NOTREADY, /* Not yet initialized */ |
41 | S_IDLE, /* Just hanging around */ |
42 | S_FLAKED, /* Some sort of problem */ |
43 | S_STREAMING, /* Streaming data */ |
44 | S_BUFWAIT /* streaming requested but no buffers yet */ |
45 | }; |
46 | #define MAX_DMA_BUFS 3 |
47 | |
48 | /* |
49 | * Different platforms work best with different buffer modes, so we |
50 | * let the platform pick. |
51 | */ |
52 | enum mcam_buffer_mode { |
53 | B_vmalloc = 0, |
54 | B_DMA_contig = 1, |
55 | B_DMA_sg = 2 |
56 | }; |
57 | |
58 | enum mcam_chip_id { |
59 | MCAM_CAFE, |
60 | MCAM_ARMADA610, |
61 | }; |
62 | |
63 | /* |
64 | * Is a given buffer mode supported by the current kernel configuration? |
65 | */ |
66 | static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode) |
67 | { |
68 | switch (mode) { |
69 | #ifdef MCAM_MODE_VMALLOC |
70 | case B_vmalloc: |
71 | #endif |
72 | #ifdef MCAM_MODE_DMA_CONTIG |
73 | case B_DMA_contig: |
74 | #endif |
75 | #ifdef MCAM_MODE_DMA_SG |
76 | case B_DMA_sg: |
77 | #endif |
78 | return 1; |
79 | default: |
80 | return 0; |
81 | } |
82 | } |
83 | |
84 | /* |
85 | * Basic frame states |
86 | */ |
87 | struct mcam_frame_state { |
88 | unsigned int frames; |
89 | unsigned int singles; |
90 | unsigned int delivered; |
91 | }; |
92 | |
93 | #define NR_MCAM_CLK 3 |
94 | |
95 | /* |
96 | * A description of one of our devices. |
97 | * Locking: controlled by s_mutex. Certain fields, however, require |
98 | * the dev_lock spinlock; they are marked as such by comments. |
99 | * dev_lock is also required for access to device registers. |
100 | */ |
101 | struct mcam_camera { |
102 | /* |
103 | * These fields should be set by the platform code prior to |
104 | * calling mcam_register(). |
105 | */ |
106 | unsigned char __iomem *regs; |
107 | unsigned regs_size; /* size in bytes of the register space */ |
108 | spinlock_t dev_lock; |
109 | struct device *dev; /* For messages, dma alloc */ |
110 | enum mcam_chip_id chip_id; |
111 | enum mcam_buffer_mode buffer_mode; |
112 | |
113 | int mclk_src; /* which clock source the mclk derives from */ |
114 | int mclk_div; /* Clock Divider Value for MCLK */ |
115 | |
116 | enum v4l2_mbus_type bus_type; |
117 | /* MIPI support */ |
118 | /* The dphy config value, allocated in board file |
119 | * dphy[0]: DPHY3 |
120 | * dphy[1]: DPHY5 |
121 | * dphy[2]: DPHY6 |
122 | */ |
123 | int *dphy; |
124 | bool mipi_enabled; /* flag whether mipi is enabled already */ |
125 | int lane; /* lane number */ |
126 | |
127 | /* clock tree support */ |
128 | struct clk *clk[NR_MCAM_CLK]; |
129 | struct clk_hw mclk_hw; |
130 | struct clk *mclk; |
131 | |
132 | /* |
133 | * Callbacks from the core to the platform code. |
134 | */ |
135 | int (*plat_power_up) (struct mcam_camera *cam); |
136 | void (*plat_power_down) (struct mcam_camera *cam); |
137 | void (*calc_dphy) (struct mcam_camera *cam); |
138 | |
139 | /* |
140 | * Everything below here is private to the mcam core and |
141 | * should not be touched by the platform code. |
142 | */ |
143 | struct v4l2_device v4l2_dev; |
144 | struct v4l2_ctrl_handler ctrl_handler; |
145 | enum mcam_state state; |
146 | unsigned long flags; /* Buffer status, mainly (dev_lock) */ |
147 | |
148 | struct mcam_frame_state frame_state; /* Frame state counter */ |
149 | /* |
150 | * Subsystem structures. |
151 | */ |
152 | struct video_device vdev; |
153 | struct v4l2_async_notifier notifier; |
154 | struct v4l2_subdev *sensor; |
155 | |
156 | /* Videobuf2 stuff */ |
157 | struct vb2_queue vb_queue; |
158 | struct list_head buffers; /* Available frames */ |
159 | |
160 | unsigned int nbufs; /* How many are alloc'd */ |
161 | int next_buf; /* Next to consume (dev_lock) */ |
162 | |
163 | char bus_info[32]; /* querycap bus_info */ |
164 | |
165 | /* DMA buffers - vmalloc mode */ |
166 | #ifdef MCAM_MODE_VMALLOC |
167 | unsigned int dma_buf_size; /* allocated size */ |
168 | void *dma_bufs[MAX_DMA_BUFS]; /* Internal buffer addresses */ |
169 | dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */ |
170 | struct tasklet_struct s_tasklet; |
171 | #endif |
172 | unsigned int sequence; /* Frame sequence number */ |
173 | unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */ |
174 | |
175 | /* DMA buffers - DMA modes */ |
176 | struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS]; |
177 | |
178 | /* Mode-specific ops, set at open time */ |
179 | void (*dma_setup)(struct mcam_camera *cam); |
180 | void (*frame_complete)(struct mcam_camera *cam, int frame); |
181 | |
182 | /* Current operating parameters */ |
183 | struct v4l2_pix_format pix_format; |
184 | u32 mbus_code; |
185 | |
186 | /* Locks */ |
187 | struct mutex s_mutex; /* Access to this structure */ |
188 | }; |
189 | |
190 | |
191 | /* |
192 | * Register I/O functions. These are here because the platform code |
193 | * may legitimately need to mess with the register space. |
194 | */ |
195 | /* |
196 | * Device register I/O |
197 | */ |
198 | static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg, |
199 | unsigned int val) |
200 | { |
201 | iowrite32(val, cam->regs + reg); |
202 | } |
203 | |
204 | static inline unsigned int mcam_reg_read(struct mcam_camera *cam, |
205 | unsigned int reg) |
206 | { |
207 | return ioread32(cam->regs + reg); |
208 | } |
209 | |
210 | |
211 | static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg, |
212 | unsigned int val, unsigned int mask) |
213 | { |
214 | unsigned int v = mcam_reg_read(cam, reg); |
215 | |
216 | v = (v & ~mask) | (val & mask); |
217 | mcam_reg_write(cam, reg, val: v); |
218 | } |
219 | |
220 | static inline void mcam_reg_clear_bit(struct mcam_camera *cam, |
221 | unsigned int reg, unsigned int val) |
222 | { |
223 | mcam_reg_write_mask(cam, reg, val: 0, mask: val); |
224 | } |
225 | |
226 | static inline void mcam_reg_set_bit(struct mcam_camera *cam, |
227 | unsigned int reg, unsigned int val) |
228 | { |
229 | mcam_reg_write_mask(cam, reg, val, mask: val); |
230 | } |
231 | |
232 | /* |
233 | * Functions for use by platform code. |
234 | */ |
235 | int mccic_register(struct mcam_camera *cam); |
236 | int mccic_irq(struct mcam_camera *cam, unsigned int irqs); |
237 | void mccic_shutdown(struct mcam_camera *cam); |
238 | void mccic_suspend(struct mcam_camera *cam); |
239 | int mccic_resume(struct mcam_camera *cam); |
240 | |
241 | /* |
242 | * Register definitions for the m88alp01 camera interface. Offsets in bytes |
243 | * as given in the spec. |
244 | */ |
245 | #define REG_Y0BAR 0x00 |
246 | #define REG_Y1BAR 0x04 |
247 | #define REG_Y2BAR 0x08 |
248 | #define REG_U0BAR 0x0c |
249 | #define REG_U1BAR 0x10 |
250 | #define REG_U2BAR 0x14 |
251 | #define REG_V0BAR 0x18 |
252 | #define REG_V1BAR 0x1C |
253 | #define REG_V2BAR 0x20 |
254 | |
255 | /* |
256 | * register definitions for MIPI support |
257 | */ |
258 | #define REG_CSI2_CTRL0 0x100 |
259 | #define CSI2_C0_MIPI_EN (0x1 << 0) |
260 | #define CSI2_C0_ACT_LANE(n) ((n-1) << 1) |
261 | #define REG_CSI2_DPHY3 0x12c |
262 | #define REG_CSI2_DPHY5 0x134 |
263 | #define REG_CSI2_DPHY6 0x138 |
264 | |
265 | /* ... */ |
266 | |
267 | #define REG_IMGPITCH 0x24 /* Image pitch register */ |
268 | #define IMGP_YP_SHFT 2 /* Y pitch params */ |
269 | #define IMGP_YP_MASK 0x00003ffc /* Y pitch field */ |
270 | #define IMGP_UVP_SHFT 18 /* UV pitch (planar) */ |
271 | #define IMGP_UVP_MASK 0x3ffc0000 |
272 | #define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */ |
273 | #define IRQ_EOF0 0x00000001 /* End of frame 0 */ |
274 | #define IRQ_EOF1 0x00000002 /* End of frame 1 */ |
275 | #define IRQ_EOF2 0x00000004 /* End of frame 2 */ |
276 | #define IRQ_SOF0 0x00000008 /* Start of frame 0 */ |
277 | #define IRQ_SOF1 0x00000010 /* Start of frame 1 */ |
278 | #define IRQ_SOF2 0x00000020 /* Start of frame 2 */ |
279 | #define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */ |
280 | #define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */ |
281 | #define IRQ_TWSIR 0x00020000 /* TWSI read */ |
282 | #define IRQ_TWSIE 0x00040000 /* TWSI error */ |
283 | #define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE) |
284 | #define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2) |
285 | #define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW) |
286 | #define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */ |
287 | #define REG_IRQSTAT 0x30 /* IRQ status / clear */ |
288 | |
289 | #define REG_IMGSIZE 0x34 /* Image size */ |
290 | #define IMGSZ_V_MASK 0x1fff0000 |
291 | #define IMGSZ_V_SHIFT 16 |
292 | #define IMGSZ_H_MASK 0x00003fff |
293 | #define REG_IMGOFFSET 0x38 /* IMage offset */ |
294 | |
295 | #define REG_CTRL0 0x3c /* Control 0 */ |
296 | #define C0_ENABLE 0x00000001 /* Makes the whole thing go */ |
297 | |
298 | /* Mask for all the format bits */ |
299 | #define C0_DF_MASK 0x00fffffc /* Bits 2-23 */ |
300 | |
301 | /* RGB ordering */ |
302 | #define C0_RGB4_RGBX 0x00000000 |
303 | #define C0_RGB4_XRGB 0x00000004 |
304 | #define C0_RGB4_BGRX 0x00000008 |
305 | #define C0_RGB4_XBGR 0x0000000c |
306 | #define C0_RGB5_RGGB 0x00000000 |
307 | #define C0_RGB5_GRBG 0x00000004 |
308 | #define C0_RGB5_GBRG 0x00000008 |
309 | #define C0_RGB5_BGGR 0x0000000c |
310 | |
311 | /* Spec has two fields for DIN and DOUT, but they must match, so |
312 | combine them here. */ |
313 | #define C0_DF_YUV 0x00000000 /* Data is YUV */ |
314 | #define C0_DF_RGB 0x000000a0 /* ... RGB */ |
315 | #define C0_DF_BAYER 0x00000140 /* ... Bayer */ |
316 | /* 8-8-8 must be missing from the below - ask */ |
317 | #define C0_RGBF_565 0x00000000 |
318 | #define C0_RGBF_444 0x00000800 |
319 | #define C0_RGB_BGR 0x00001000 /* Blue comes first */ |
320 | #define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */ |
321 | #define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */ |
322 | #define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */ |
323 | /* Think that 420 packed must be 111 - ask */ |
324 | #define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */ |
325 | #define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */ |
326 | #define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */ |
327 | #define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */ |
328 | #define C0_YUVE_NOSWAP 0x00000000 /* no bytes swapping */ |
329 | #define C0_YUVE_SWAP13 0x00010000 /* swap byte 1 and 3 */ |
330 | #define C0_YUVE_SWAP24 0x00020000 /* swap byte 2 and 4 */ |
331 | #define C0_YUVE_SWAP1324 0x00030000 /* swap bytes 1&3 and 2&4 */ |
332 | /* Bayer bits 18,19 if needed */ |
333 | #define C0_EOF_VSYNC 0x00400000 /* Generate EOF by VSYNC */ |
334 | #define C0_VEDGE_CTRL 0x00800000 /* Detect falling edge of VSYNC */ |
335 | #define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */ |
336 | #define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */ |
337 | #define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */ |
338 | #define C0_DOWNSCALE 0x08000000 /* Enable downscaler */ |
339 | /* SIFMODE */ |
340 | #define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */ |
341 | #define C0_SOF_NOSYNC 0x40000000 /* Use inband active signaling */ |
342 | #define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */ |
343 | |
344 | /* Bits below C1_444ALPHA are not present in Cafe */ |
345 | #define REG_CTRL1 0x40 /* Control 1 */ |
346 | #define C1_CLKGATE 0x00000001 /* Sensor clock gate */ |
347 | #define C1_DESC_ENA 0x00000100 /* DMA descriptor enable */ |
348 | #define C1_DESC_3WORD 0x00000200 /* Three-word descriptors used */ |
349 | #define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */ |
350 | #define C1_ALPHA_SHFT 20 |
351 | #define C1_DMAB32 0x00000000 /* 32-byte DMA burst */ |
352 | #define C1_DMAB16 0x02000000 /* 16-byte DMA burst */ |
353 | #define C1_DMAB64 0x04000000 /* 64-byte DMA burst */ |
354 | #define C1_DMAB_MASK 0x06000000 |
355 | #define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */ |
356 | #define C1_PWRDWN 0x10000000 /* Power down */ |
357 | |
358 | #define REG_CLKCTRL 0x88 /* Clock control */ |
359 | #define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */ |
360 | |
361 | /* This appears to be a Cafe-only register */ |
362 | #define REG_UBAR 0xc4 /* Upper base address register */ |
363 | |
364 | /* Armada 610 DMA descriptor registers */ |
365 | #define REG_DMA_DESC_Y 0x200 |
366 | #define REG_DMA_DESC_U 0x204 |
367 | #define REG_DMA_DESC_V 0x208 |
368 | #define REG_DESC_LEN_Y 0x20c /* Lengths are in bytes */ |
369 | #define REG_DESC_LEN_U 0x210 |
370 | #define REG_DESC_LEN_V 0x214 |
371 | |
372 | /* |
373 | * Useful stuff that probably belongs somewhere global. |
374 | */ |
375 | #define VGA_WIDTH 640 |
376 | #define VGA_HEIGHT 480 |
377 | |
378 | #endif /* _MCAM_CORE_H */ |
379 | |