| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Register definition header for NPCM video driver |
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| 4 | * |
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| 5 | * Copyright (C) 2022 Nuvoton Technologies |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _NPCM_REGS_H |
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| 9 | #define _NPCM_REGS_H |
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| 10 | |
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| 11 | /* VCD Registers */ |
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| 12 | #define VCD_DIFF_TBL 0x0000 |
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| 13 | #define VCD_FBA_ADR 0x8000 |
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| 14 | #define VCD_FBB_ADR 0x8004 |
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| 15 | |
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| 16 | #define VCD_FB_LP 0x8008 |
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| 17 | #define VCD_FBA_LP GENMASK(15, 0) |
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| 18 | #define VCD_FBB_LP GENMASK(31, 16) |
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| 19 | |
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| 20 | #define VCD_CAP_RES 0x800c |
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| 21 | #define VCD_CAP_RES_VERT_RES GENMASK(10, 0) |
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| 22 | #define VCD_CAP_RES_HOR_RES GENMASK(26, 16) |
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| 23 | |
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| 24 | #define VCD_MODE 0x8014 |
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| 25 | #define VCD_MODE_VCDE BIT(0) |
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| 26 | #define VCD_MODE_CM565 BIT(1) |
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| 27 | #define VCD_MODE_IDBC BIT(3) |
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| 28 | #define VCD_MODE_KVM_BW_SET BIT(16) |
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| 29 | |
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| 30 | #define VCD_CMD 0x8018 |
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| 31 | #define VCD_CMD_GO BIT(0) |
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| 32 | #define VCD_CMD_RST BIT(1) |
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| 33 | #define VCD_CMD_OPERATION GENMASK(6, 4) |
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| 34 | #define VCD_CMD_OPERATION_CAPTURE 0 |
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| 35 | #define VCD_CMD_OPERATION_COMPARE 2 |
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| 36 | |
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| 37 | #define VCD_STAT 0x801c |
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| 38 | #define VCD_STAT_DONE BIT(0) |
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| 39 | #define VCD_STAT_IFOT BIT(2) |
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| 40 | #define VCD_STAT_IFOR BIT(3) |
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| 41 | #define VCD_STAT_VHT_CHG BIT(5) |
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| 42 | #define VCD_STAT_HAC_CHG BIT(8) |
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| 43 | #define VCD_STAT_BUSY BIT(30) |
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| 44 | #define VCD_STAT_CLEAR 0x3fff |
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| 45 | |
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| 46 | #define VCD_INTE 0x8020 |
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| 47 | #define VCD_INTE_DONE_IE BIT(0) |
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| 48 | #define VCD_INTE_IFOT_IE BIT(2) |
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| 49 | #define VCD_INTE_IFOR_IE BIT(3) |
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| 50 | #define VCD_INTE_VHT_IE BIT(5) |
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| 51 | #define VCD_INTE_HAC_IE BIT(8) |
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| 52 | |
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| 53 | #define VCD_RCHG 0x8028 |
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| 54 | #define VCD_RCHG_IG_CHG0 GENMASK(2, 0) |
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| 55 | #define VCD_RCHG_TIM_PRSCL GENMASK(12, 9) |
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| 56 | |
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| 57 | #define VCD_VER_HI_TIM 0x8044 |
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| 58 | #define VCD_VER_HI_TIME GENMASK(23, 0) |
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| 59 | |
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| 60 | #define VCD_VER_HI_LST 0x8048 |
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| 61 | #define VCD_VER_HI_LAST GENMASK(23, 0) |
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| 62 | |
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| 63 | #define VCD_HOR_AC_TIM 0x804c |
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| 64 | #define VCD_HOR_AC_TIME GENMASK(13, 0) |
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| 65 | |
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| 66 | #define VCD_HOR_AC_LST 0x8050 |
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| 67 | #define VCD_HOR_AC_LAST GENMASK(13, 0) |
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| 68 | |
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| 69 | #define VCD_FIFO 0x805c |
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| 70 | #define VCD_FIFO_TH 0x100350ff |
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| 71 | |
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| 72 | #define VCD_FB_SIZE 0x500000 /* support up to 1920 x 1200 */ |
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| 73 | #define VCD_KVM_BW_PCLK 120000000UL |
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| 74 | #define VCD_TIMEOUT_US 300000 |
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| 75 | |
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| 76 | /* ECE Registers */ |
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| 77 | #define ECE_DDA_CTRL 0x0000 |
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| 78 | #define ECE_DDA_CTRL_ECEEN BIT(0) |
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| 79 | #define ECE_DDA_CTRL_INTEN BIT(8) |
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| 80 | |
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| 81 | #define ECE_DDA_STS 0x0004 |
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| 82 | #define ECE_DDA_STS_CDREADY BIT(8) |
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| 83 | #define ECE_DDA_STS_ACDRDY BIT(10) |
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| 84 | |
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| 85 | #define ECE_FBR_BA 0x0008 |
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| 86 | #define ECE_ED_BA 0x000c |
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| 87 | #define ECE_RECT_XY 0x0010 |
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| 88 | |
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| 89 | #define ECE_RECT_DIMEN 0x0014 |
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| 90 | #define ECE_RECT_DIMEN_WR GENMASK(10, 0) |
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| 91 | #define ECE_RECT_DIMEN_WLTR GENMASK(14, 11) |
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| 92 | #define ECE_RECT_DIMEN_HR GENMASK(26, 16) |
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| 93 | #define ECE_RECT_DIMEN_HLTR GENMASK(30, 27) |
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| 94 | |
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| 95 | #define ECE_RESOL 0x001c |
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| 96 | #define ECE_RESOL_FB_LP_512 0 |
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| 97 | #define ECE_RESOL_FB_LP_1024 1 |
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| 98 | #define ECE_RESOL_FB_LP_2048 2 |
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| 99 | #define ECE_RESOL_FB_LP_2560 3 |
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| 100 | #define ECE_RESOL_FB_LP_4096 4 |
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| 101 | |
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| 102 | #define ECE_HEX_CTRL 0x0040 |
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| 103 | #define ECE_HEX_CTRL_ENCDIS BIT(0) |
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| 104 | #define ECE_HEX_CTRL_ENC_GAP GENMASK(12, 8) |
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| 105 | |
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| 106 | #define ECE_HEX_RECT_OFFSET 0x0048 |
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| 107 | #define ECE_HEX_RECT_OFFSET_MASK GENMASK(22, 0) |
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| 108 | |
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| 109 | #define ECE_TILE_W 16 |
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| 110 | #define ECE_TILE_H 16 |
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| 111 | #define ECE_POLL_TIMEOUT_US 300000 |
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| 112 | |
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| 113 | /* GCR Registers */ |
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| 114 | #define INTCR 0x3c |
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| 115 | #define INTCR_GFXIFDIS GENMASK(9, 8) |
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| 116 | #define INTCR_DEHS BIT(27) |
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| 117 | |
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| 118 | #define INTCR2 0x60 |
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| 119 | #define INTCR2_GIRST2 BIT(2) |
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| 120 | #define INTCR2_GIHCRST BIT(5) |
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| 121 | #define INTCR2_GIVCRST BIT(6) |
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| 122 | |
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| 123 | /* GFXI Register */ |
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| 124 | #define DISPST 0x00 |
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| 125 | #define DISPST_HSCROFF BIT(1) |
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| 126 | #define DISPST_MGAMODE BIT(7) |
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| 127 | |
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| 128 | #define HVCNTL 0x10 |
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| 129 | #define HVCNTL_MASK GENMASK(7, 0) |
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| 130 | |
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| 131 | #define HVCNTH 0x14 |
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| 132 | #define HVCNTH_MASK GENMASK(2, 0) |
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| 133 | |
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| 134 | #define VVCNTL 0x20 |
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| 135 | #define VVCNTL_MASK GENMASK(7, 0) |
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| 136 | |
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| 137 | #define VVCNTH 0x24 |
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| 138 | #define VVCNTH_MASK GENMASK(2, 0) |
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| 139 | |
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| 140 | #define GPLLINDIV 0x40 |
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| 141 | #define GPLLINDIV_MASK GENMASK(5, 0) |
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| 142 | #define GPLLINDIV_GPLLFBDV8 BIT(7) |
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| 143 | |
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| 144 | #define GPLLFBDIV 0x44 |
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| 145 | #define GPLLFBDIV_MASK GENMASK(7, 0) |
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| 146 | |
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| 147 | #define GPLLST 0x48 |
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| 148 | #define GPLLST_PLLOTDIV1 GENMASK(2, 0) |
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| 149 | #define GPLLST_PLLOTDIV2 GENMASK(5, 3) |
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| 150 | #define GPLLST_GPLLFBDV109 GENMASK(7, 6) |
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| 151 | |
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| 152 | #endif /* _NPCM_REGS_H */ |
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| 153 | |
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