| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * TI AM437x Image Sensor Interface Registers |
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| 4 | * |
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| 5 | * Copyright (C) 2013 - 2014 Texas Instruments, Inc. |
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| 6 | * |
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| 7 | * Benoit Parrot <bparrot@ti.com> |
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| 8 | * Lad, Prabhakar <prabhakar.csengg@gmail.com> |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef AM437X_VPFE_REGS_H |
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| 12 | #define AM437X_VPFE_REGS_H |
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| 13 | |
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| 14 | /* VPFE module register offset */ |
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| 15 | #define VPFE_REVISION 0x0 |
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| 16 | #define VPFE_PCR 0x4 |
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| 17 | #define VPFE_SYNMODE 0x8 |
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| 18 | #define VPFE_HD_VD_WID 0xc |
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| 19 | #define VPFE_PIX_LINES 0x10 |
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| 20 | #define VPFE_HORZ_INFO 0x14 |
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| 21 | #define VPFE_VERT_START 0x18 |
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| 22 | #define VPFE_VERT_LINES 0x1c |
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| 23 | #define VPFE_CULLING 0x20 |
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| 24 | #define VPFE_HSIZE_OFF 0x24 |
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| 25 | #define VPFE_SDOFST 0x28 |
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| 26 | #define VPFE_SDR_ADDR 0x2c |
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| 27 | #define VPFE_CLAMP 0x30 |
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| 28 | #define VPFE_DCSUB 0x34 |
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| 29 | #define VPFE_COLPTN 0x38 |
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| 30 | #define VPFE_BLKCMP 0x3c |
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| 31 | #define VPFE_VDINT 0x48 |
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| 32 | #define VPFE_ALAW 0x4c |
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| 33 | #define VPFE_REC656IF 0x50 |
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| 34 | #define VPFE_CCDCFG 0x54 |
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| 35 | #define VPFE_DMA_CNTL 0x98 |
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| 36 | #define VPFE_SYSCONFIG 0x104 |
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| 37 | #define VPFE_CONFIG 0x108 |
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| 38 | #define VPFE_IRQ_EOI 0x110 |
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| 39 | #define VPFE_IRQ_STS_RAW 0x114 |
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| 40 | #define VPFE_IRQ_STS 0x118 |
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| 41 | #define VPFE_IRQ_EN_SET 0x11c |
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| 42 | #define VPFE_IRQ_EN_CLR 0x120 |
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| 43 | #define VPFE_REG_END 0x124 |
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| 44 | |
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| 45 | /* Define bit fields within selected registers */ |
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| 46 | #define VPFE_FID_POL_MASK 1 |
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| 47 | #define VPFE_FID_POL_SHIFT 4 |
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| 48 | #define VPFE_HD_POL_MASK 1 |
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| 49 | #define VPFE_HD_POL_SHIFT 3 |
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| 50 | #define VPFE_VD_POL_MASK 1 |
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| 51 | #define VPFE_VD_POL_SHIFT 2 |
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| 52 | #define VPFE_HSIZE_OFF_MASK 0xffffffe0 |
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| 53 | #define VPFE_32BYTE_ALIGN_VAL 31 |
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| 54 | #define VPFE_FRM_FMT_MASK 0x1 |
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| 55 | #define VPFE_FRM_FMT_SHIFT 7 |
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| 56 | #define VPFE_DATA_SZ_MASK 7 |
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| 57 | #define VPFE_DATA_SZ_SHIFT 8 |
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| 58 | #define VPFE_PIX_FMT_MASK 3 |
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| 59 | #define VPFE_PIX_FMT_SHIFT 12 |
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| 60 | #define VPFE_VP2SDR_DISABLE 0xfffbffff |
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| 61 | #define VPFE_WEN_ENABLE BIT(17) |
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| 62 | #define VPFE_SDR2RSZ_DISABLE 0xfff7ffff |
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| 63 | #define VPFE_VDHDEN_ENABLE BIT(16) |
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| 64 | #define VPFE_LPF_ENABLE BIT(14) |
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| 65 | #define VPFE_ALAW_ENABLE BIT(3) |
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| 66 | #define VPFE_ALAW_GAMMA_WD_MASK 7 |
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| 67 | #define VPFE_BLK_CLAMP_ENABLE BIT(31) |
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| 68 | #define VPFE_BLK_SGAIN_MASK 0x1f |
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| 69 | #define VPFE_BLK_ST_PXL_MASK 0x7fff |
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| 70 | #define VPFE_BLK_ST_PXL_SHIFT 10 |
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| 71 | #define VPFE_BLK_SAMPLE_LN_MASK 7 |
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| 72 | #define VPFE_BLK_SAMPLE_LN_SHIFT 28 |
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| 73 | #define VPFE_BLK_SAMPLE_LINE_MASK 7 |
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| 74 | #define VPFE_BLK_SAMPLE_LINE_SHIFT 25 |
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| 75 | #define VPFE_BLK_DC_SUB_MASK 0x03fff |
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| 76 | #define VPFE_BLK_COMP_MASK 0xff |
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| 77 | #define VPFE_BLK_COMP_GB_COMP_SHIFT 8 |
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| 78 | #define VPFE_BLK_COMP_GR_COMP_SHIFT 16 |
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| 79 | #define VPFE_BLK_COMP_R_COMP_SHIFT 24 |
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| 80 | #define VPFE_LATCH_ON_VSYNC_DISABLE BIT(15) |
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| 81 | #define VPFE_DATA_PACK_ENABLE BIT(11) |
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| 82 | #define VPFE_HORZ_INFO_SPH_SHIFT 16 |
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| 83 | #define VPFE_VERT_START_SLV0_SHIFT 16 |
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| 84 | #define VPFE_VDINT_VDINT0_SHIFT 16 |
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| 85 | #define VPFE_VDINT_VDINT1_MASK 0xffff |
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| 86 | #define VPFE_PPC_RAW 1 |
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| 87 | #define VPFE_DCSUB_DEFAULT_VAL 0 |
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| 88 | #define VPFE_CLAMP_DEFAULT_VAL 0 |
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| 89 | #define VPFE_COLPTN_VAL 0xbb11bb11 |
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| 90 | #define VPFE_TWO_BYTES_PER_PIXEL 2 |
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| 91 | #define VPFE_INTERLACED_IMAGE_INVERT 0x4b6d |
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| 92 | #define VPFE_INTERLACED_NO_IMAGE_INVERT 0x0249 |
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| 93 | #define VPFE_PROGRESSIVE_IMAGE_INVERT 0x4000 |
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| 94 | #define VPFE_PROGRESSIVE_NO_IMAGE_INVERT 0 |
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| 95 | #define VPFE_INTERLACED_HEIGHT_SHIFT 1 |
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| 96 | #define VPFE_SYN_MODE_INPMOD_SHIFT 12 |
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| 97 | #define VPFE_SYN_MODE_INPMOD_MASK 3 |
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| 98 | #define VPFE_SYN_MODE_8BITS (7 << 8) |
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| 99 | #define VPFE_SYN_MODE_10BITS (6 << 8) |
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| 100 | #define VPFE_SYN_MODE_11BITS (5 << 8) |
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| 101 | #define VPFE_SYN_MODE_12BITS (4 << 8) |
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| 102 | #define VPFE_SYN_MODE_13BITS (3 << 8) |
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| 103 | #define VPFE_SYN_MODE_14BITS (2 << 8) |
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| 104 | #define VPFE_SYN_MODE_15BITS (1 << 8) |
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| 105 | #define VPFE_SYN_MODE_16BITS (0 << 8) |
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| 106 | #define VPFE_SYN_FLDMODE_MASK 1 |
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| 107 | #define VPFE_SYN_FLDMODE_SHIFT 7 |
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| 108 | #define VPFE_REC656IF_BT656_EN 3 |
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| 109 | #define VPFE_SYN_MODE_VD_POL_NEGATIVE BIT(2) |
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| 110 | #define VPFE_CCDCFG_Y8POS_SHIFT 11 |
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| 111 | #define VPFE_CCDCFG_BW656_10BIT BIT(5) |
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| 112 | #define VPFE_SDOFST_FIELD_INTERLEAVED 0x249 |
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| 113 | #define VPFE_NO_CULLING 0xffff00ff |
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| 114 | #define VPFE_VDINT0 BIT(0) |
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| 115 | #define VPFE_VDINT1 BIT(1) |
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| 116 | #define VPFE_VDINT2 BIT(2) |
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| 117 | #define VPFE_DMA_CNTL_OVERFLOW BIT(31) |
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| 118 | |
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| 119 | #define VPFE_CONFIG_PCLK_INV_SHIFT 0 |
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| 120 | #define VPFE_CONFIG_PCLK_INV_MASK 1 |
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| 121 | #define VPFE_CONFIG_PCLK_INV_NOT_INV 0 |
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| 122 | #define VPFE_CONFIG_PCLK_INV_INV 1 |
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| 123 | #define VPFE_CONFIG_EN_SHIFT 1 |
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| 124 | #define VPFE_CONFIG_EN_MASK 2 |
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| 125 | #define VPFE_CONFIG_EN_DISABLE 0 |
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| 126 | #define VPFE_CONFIG_EN_ENABLE 1 |
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| 127 | #define VPFE_CONFIG_ST_SHIFT 2 |
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| 128 | #define VPFE_CONFIG_ST_MASK 4 |
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| 129 | #define VPFE_CONFIG_ST_OCP_ACTIVE 0 |
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| 130 | #define VPFE_CONFIG_ST_OCP_STANDBY 1 |
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| 131 | |
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| 132 | #endif /* AM437X_VPFE_REGS_H */ |
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| 133 | |
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