| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * isph3a.h |
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| 4 | * |
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| 5 | * TI OMAP3 ISP - H3A AF module |
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| 6 | * |
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| 7 | * Copyright (C) 2010 Nokia Corporation |
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| 8 | * Copyright (C) 2009 Texas Instruments, Inc. |
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| 9 | * |
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| 10 | * Contacts: David Cohen <dacohen@gmail.com> |
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| 11 | * Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
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| 12 | * Sakari Ailus <sakari.ailus@iki.fi> |
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| 13 | */ |
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| 14 | |
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| 15 | #ifndef OMAP3_ISP_H3A_H |
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| 16 | #define OMAP3_ISP_H3A_H |
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| 17 | |
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| 18 | #include <linux/omap3isp.h> |
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| 19 | |
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| 20 | /* |
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| 21 | * ---------- |
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| 22 | * -H3A AEWB- |
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| 23 | * ---------- |
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| 24 | */ |
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| 25 | |
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| 26 | #define AEWB_PACKET_SIZE 16 |
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| 27 | #define AEWB_SATURATION_LIMIT 0x3ff |
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| 28 | |
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| 29 | /* Flags for changed registers */ |
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| 30 | #define PCR_CHNG (1 << 0) |
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| 31 | #define AEWWIN1_CHNG (1 << 1) |
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| 32 | #define AEWINSTART_CHNG (1 << 2) |
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| 33 | #define AEWINBLK_CHNG (1 << 3) |
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| 34 | #define AEWSUBWIN_CHNG (1 << 4) |
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| 35 | #define PRV_WBDGAIN_CHNG (1 << 5) |
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| 36 | #define PRV_WBGAIN_CHNG (1 << 6) |
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| 37 | |
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| 38 | /* ISPH3A REGISTERS bits */ |
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| 39 | #define ISPH3A_PCR_AF_EN (1 << 0) |
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| 40 | #define ISPH3A_PCR_AF_ALAW_EN (1 << 1) |
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| 41 | #define ISPH3A_PCR_AF_MED_EN (1 << 2) |
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| 42 | #define ISPH3A_PCR_AF_BUSY (1 << 15) |
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| 43 | #define ISPH3A_PCR_AEW_EN (1 << 16) |
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| 44 | #define ISPH3A_PCR_AEW_ALAW_EN (1 << 17) |
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| 45 | #define ISPH3A_PCR_AEW_BUSY (1 << 18) |
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| 46 | #define ISPH3A_PCR_AEW_MASK (ISPH3A_PCR_AEW_ALAW_EN | \ |
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| 47 | ISPH3A_PCR_AEW_AVE2LMT_MASK) |
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| 48 | |
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| 49 | /* |
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| 50 | * -------- |
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| 51 | * -H3A AF- |
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| 52 | * -------- |
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| 53 | */ |
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| 54 | |
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| 55 | /* Peripheral Revision */ |
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| 56 | #define AFPID 0x0 |
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| 57 | |
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| 58 | #define AFCOEF_OFFSET 0x00000004 /* COEF base address */ |
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| 59 | |
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| 60 | /* PCR fields */ |
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| 61 | #define AF_BUSYAF (1 << 15) |
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| 62 | #define AF_FVMODE (1 << 14) |
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| 63 | #define AF_RGBPOS (0x7 << 11) |
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| 64 | #define AF_MED_TH (0xFF << 3) |
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| 65 | #define AF_MED_EN (1 << 2) |
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| 66 | #define AF_ALAW_EN (1 << 1) |
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| 67 | #define AF_EN (1 << 0) |
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| 68 | #define AF_PCR_MASK (AF_FVMODE | AF_RGBPOS | AF_MED_TH | \ |
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| 69 | AF_MED_EN | AF_ALAW_EN) |
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| 70 | |
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| 71 | /* AFPAX1 fields */ |
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| 72 | #define AF_PAXW (0x7F << 16) |
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| 73 | #define AF_PAXH 0x7F |
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| 74 | |
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| 75 | /* AFPAX2 fields */ |
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| 76 | #define AF_AFINCV (0xF << 13) |
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| 77 | #define AF_PAXVC (0x7F << 6) |
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| 78 | #define AF_PAXHC 0x3F |
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| 79 | |
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| 80 | /* AFPAXSTART fields */ |
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| 81 | #define AF_PAXSH (0xFFF<<16) |
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| 82 | #define AF_PAXSV 0xFFF |
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| 83 | |
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| 84 | /* COEFFICIENT MASK */ |
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| 85 | #define AF_COEF_MASK0 0xFFF |
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| 86 | #define AF_COEF_MASK1 (0xFFF<<16) |
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| 87 | |
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| 88 | /* BIT SHIFTS */ |
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| 89 | #define AF_RGBPOS_SHIFT 11 |
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| 90 | #define AF_MED_TH_SHIFT 3 |
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| 91 | #define AF_PAXW_SHIFT 16 |
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| 92 | #define AF_LINE_INCR_SHIFT 13 |
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| 93 | #define AF_VT_COUNT_SHIFT 6 |
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| 94 | #define AF_HZ_START_SHIFT 16 |
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| 95 | #define AF_COEF_SHIFT 16 |
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| 96 | |
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| 97 | /* Init and cleanup functions */ |
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| 98 | int omap3isp_h3a_aewb_init(struct isp_device *isp); |
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| 99 | int omap3isp_h3a_af_init(struct isp_device *isp); |
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| 100 | |
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| 101 | void omap3isp_h3a_aewb_cleanup(struct isp_device *isp); |
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| 102 | void omap3isp_h3a_af_cleanup(struct isp_device *isp); |
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| 103 | |
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| 104 | #endif /* OMAP3_ISP_H3A_H */ |
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| 105 | |
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