1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR |
4 | * |
5 | * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com> |
6 | * |
7 | * Special thanks to Fintek for providing hardware and spec sheets. |
8 | * This driver is based upon the nuvoton, ite and ene drivers for |
9 | * similar hardware. |
10 | */ |
11 | |
12 | #include <linux/spinlock.h> |
13 | #include <linux/ioctl.h> |
14 | |
15 | /* platform driver name to register */ |
16 | #define FINTEK_DRIVER_NAME "fintek-cir" |
17 | #define FINTEK_DESCRIPTION "Fintek LPC SuperIO Consumer IR Transceiver" |
18 | #define VENDOR_ID_FINTEK 0x1934 |
19 | |
20 | |
21 | /* debugging module parameter */ |
22 | static int debug; |
23 | |
24 | #define fit_pr(level, text, ...) \ |
25 | printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__) |
26 | |
27 | #define fit_dbg(text, ...) \ |
28 | if (debug) \ |
29 | printk(KERN_DEBUG \ |
30 | KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) |
31 | |
32 | #define fit_dbg_verbose(text, ...) \ |
33 | if (debug > 1) \ |
34 | printk(KERN_DEBUG \ |
35 | KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) |
36 | |
37 | #define fit_dbg_wake(text, ...) \ |
38 | if (debug > 2) \ |
39 | printk(KERN_DEBUG \ |
40 | KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) |
41 | |
42 | |
43 | #define TX_BUF_LEN 256 |
44 | #define RX_BUF_LEN 32 |
45 | |
46 | struct fintek_dev { |
47 | struct pnp_dev *pdev; |
48 | struct rc_dev *rdev; |
49 | |
50 | spinlock_t fintek_lock; |
51 | |
52 | /* for rx */ |
53 | u8 buf[RX_BUF_LEN]; |
54 | unsigned int pkts; |
55 | |
56 | struct { |
57 | spinlock_t lock; |
58 | u8 buf[TX_BUF_LEN]; |
59 | unsigned int buf_count; |
60 | unsigned int cur_buf_num; |
61 | wait_queue_head_t queue; |
62 | } tx; |
63 | |
64 | /* Config register index/data port pair */ |
65 | u32 cr_ip; |
66 | u32 cr_dp; |
67 | |
68 | /* hardware I/O settings */ |
69 | unsigned long cir_addr; |
70 | int cir_irq; |
71 | int cir_port_len; |
72 | |
73 | /* hardware id */ |
74 | u8 chip_major; |
75 | u8 chip_minor; |
76 | u16 chip_vendor; |
77 | u8 logical_dev_cir; |
78 | |
79 | /* hardware features */ |
80 | bool hw_learning_capable; |
81 | bool hw_tx_capable; |
82 | |
83 | /* rx settings */ |
84 | bool learning_enabled; |
85 | bool carrier_detect_enabled; |
86 | |
87 | enum { |
88 | = 0, |
89 | SUBCMD, |
90 | CMD_DATA, |
91 | PARSE_IRDATA, |
92 | } parser_state; |
93 | |
94 | u8 cmd, rem; |
95 | |
96 | /* carrier period = 1 / frequency */ |
97 | u32 carrier; |
98 | }; |
99 | |
100 | /* buffer packet constants, largely identical to mceusb.c */ |
101 | #define BUF_PULSE_BIT 0x80 |
102 | #define BUF_LEN_MASK 0x1f |
103 | #define BUF_SAMPLE_MASK 0x7f |
104 | |
105 | #define BUF_COMMAND_HEADER 0x9f |
106 | #define BUF_COMMAND_MASK 0xe0 |
107 | #define BUF_COMMAND_NULL 0x00 |
108 | #define 0xff |
109 | #define BUF_CMD_G_REVISION 0x0b |
110 | #define BUF_CMD_S_CARRIER 0x06 |
111 | #define BUF_CMD_S_TIMEOUT 0x0c |
112 | #define BUF_CMD_SIG_END 0x01 |
113 | #define BUF_CMD_S_TXMASK 0x08 |
114 | #define BUF_CMD_S_RXSENSOR 0x14 |
115 | #define BUF_RSP_PULSE_COUNT 0x15 |
116 | |
117 | #define CIR_SAMPLE_PERIOD 50 |
118 | |
119 | /* |
120 | * Configuration Register: |
121 | * Index Port |
122 | * Data Port |
123 | */ |
124 | #define CR_INDEX_PORT 0x2e |
125 | #define CR_DATA_PORT 0x2f |
126 | |
127 | /* Possible alternate values, depends on how the chip is wired */ |
128 | #define CR_INDEX_PORT2 0x4e |
129 | #define CR_DATA_PORT2 0x4f |
130 | |
131 | /* |
132 | * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is |
133 | * active. 1 = 0x4e, 0 = 0x2e |
134 | */ |
135 | #define PORT_SEL_PORT_4E_EN 0x10 |
136 | |
137 | /* Extended Function Mode enable/disable magic values */ |
138 | #define CONFIG_REG_ENABLE 0x87 |
139 | #define CONFIG_REG_DISABLE 0xaa |
140 | |
141 | /* Chip IDs found in CR_CHIP_ID_{HI,LO} */ |
142 | #define CHIP_ID_HIGH_F71809U 0x04 |
143 | #define CHIP_ID_LOW_F71809U 0x08 |
144 | |
145 | /* |
146 | * Global control regs we need to care about: |
147 | * Global Control def. |
148 | * Register name addr val. */ |
149 | #define GCR_SOFTWARE_RESET 0x02 /* 0x00 */ |
150 | #define GCR_LOGICAL_DEV_NO 0x07 /* 0x00 */ |
151 | #define GCR_CHIP_ID_HI 0x20 /* 0x04 */ |
152 | #define GCR_CHIP_ID_LO 0x21 /* 0x08 */ |
153 | #define GCR_VENDOR_ID_HI 0x23 /* 0x19 */ |
154 | #define GCR_VENDOR_ID_LO 0x24 /* 0x34 */ |
155 | #define GCR_CONFIG_PORT_SEL 0x25 /* 0x01 */ |
156 | #define GCR_KBMOUSE_WAKEUP 0x27 |
157 | |
158 | #define LOGICAL_DEV_DISABLE 0x00 |
159 | #define LOGICAL_DEV_ENABLE 0x01 |
160 | |
161 | /* Logical device number of the CIR function */ |
162 | #define LOGICAL_DEV_CIR_REV1 0x05 |
163 | #define LOGICAL_DEV_CIR_REV2 0x08 |
164 | |
165 | /* CIR Logical Device (LDN 0x08) config registers */ |
166 | #define CIR_CR_COMMAND_INDEX 0x04 |
167 | #define CIR_CR_IRCS 0x05 /* Before host writes command to IR, host |
168 | must set to 1. When host finshes write |
169 | command to IR, host must clear to 0. */ |
170 | #define CIR_CR_COMMAND_DATA 0x06 /* Host read or write command data */ |
171 | #define CIR_CR_CLASS 0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx, |
172 | 0x33 = rx + 1 tx */ |
173 | #define CIR_CR_DEV_EN 0x30 /* bit0 = 1 enables CIR */ |
174 | #define CIR_CR_BASE_ADDR_HI 0x60 /* MSB of CIR IO base addr */ |
175 | #define CIR_CR_BASE_ADDR_LO 0x61 /* LSB of CIR IO base addr */ |
176 | #define CIR_CR_IRQ_SEL 0x70 /* bits3-0 store CIR IRQ */ |
177 | #define CIR_CR_PSOUT_STATUS 0xf1 |
178 | #define CIR_CR_WAKE_KEY3_ADDR 0xf8 |
179 | #define CIR_CR_WAKE_KEY3_CODE 0xf9 |
180 | #define CIR_CR_WAKE_KEY3_DC 0xfa |
181 | #define CIR_CR_WAKE_CONTROL 0xfb |
182 | #define CIR_CR_WAKE_KEY12_ADDR 0xfc |
183 | #define CIR_CR_WAKE_KEY4_ADDR 0xfd |
184 | #define CIR_CR_WAKE_KEY5_ADDR 0xfe |
185 | |
186 | #define CLASS_RX_ONLY 0xff |
187 | #define CLASS_RX_2TX 0x66 |
188 | #define CLASS_RX_1TX 0x33 |
189 | |
190 | /* CIR device registers */ |
191 | #define CIR_STATUS 0x00 |
192 | #define CIR_RX_DATA 0x01 |
193 | #define CIR_TX_CONTROL 0x02 |
194 | #define CIR_TX_DATA 0x03 |
195 | #define CIR_CONTROL 0x04 |
196 | |
197 | /* Bits to enable CIR wake */ |
198 | #define LOGICAL_DEV_ACPI 0x01 |
199 | #define LDEV_ACPI_WAKE_EN_REG 0xe8 |
200 | #define ACPI_WAKE_EN_CIR_BIT 0x04 |
201 | |
202 | #define LDEV_ACPI_PME_EN_REG 0xf0 |
203 | #define LDEV_ACPI_PME_CLR_REG 0xf1 |
204 | #define ACPI_PME_CIR_BIT 0x02 |
205 | |
206 | #define LDEV_ACPI_STATE_REG 0xf4 |
207 | #define ACPI_STATE_CIR_BIT 0x20 |
208 | |
209 | /* |
210 | * CIR status register (0x00): |
211 | * 7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable) |
212 | * 3 - TX_FINISH (1 when TX finished, write 1 to clear) |
213 | * 2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear) |
214 | * 1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear) |
215 | * 0 - RX_RECEIVE (1 on RX receive, write 1 to clear) |
216 | */ |
217 | #define CIR_STATUS_IRQ_EN 0x80 |
218 | #define CIR_STATUS_TX_FINISH 0x08 |
219 | #define CIR_STATUS_TX_UNDERRUN 0x04 |
220 | #define CIR_STATUS_RX_TIMEOUT 0x02 |
221 | #define CIR_STATUS_RX_RECEIVE 0x01 |
222 | #define CIR_STATUS_IRQ_MASK 0x0f |
223 | |
224 | /* |
225 | * CIR TX control register (0x02): |
226 | * 7 - TX_START (1 to indicate TX start, auto-cleared when done) |
227 | * 6 - TX_END (1 to indicate TX data written to TX fifo) |
228 | */ |
229 | #define CIR_TX_CONTROL_TX_START 0x80 |
230 | #define CIR_TX_CONTROL_TX_END 0x40 |
231 | |
232 | |