| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR |
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| 4 | * |
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| 5 | * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> |
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| 6 | * Copyright (C) 2009 Nuvoton PS Team |
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| 7 | * |
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| 8 | * Special thanks to Nuvoton for providing hardware, spec sheets and |
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| 9 | * sample code upon which portions of this driver are based. Indirect |
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| 10 | * thanks also to Maxim Levitsky, whose ene_ir driver this driver is |
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| 11 | * modeled after. |
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| 12 | */ |
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| 13 | |
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| 14 | #include <linux/spinlock.h> |
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| 15 | #include <linux/ioctl.h> |
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| 16 | |
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| 17 | /* platform driver name to register */ |
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| 18 | #define NVT_DRIVER_NAME "nuvoton-cir" |
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| 19 | |
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| 20 | /* debugging module parameter */ |
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| 21 | static int debug; |
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| 22 | |
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| 23 | |
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| 24 | #define nvt_dbg(text, ...) \ |
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| 25 | if (debug) \ |
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| 26 | printk(KERN_DEBUG \ |
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| 27 | KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) |
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| 28 | |
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| 29 | #define nvt_dbg_verbose(text, ...) \ |
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| 30 | if (debug > 1) \ |
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| 31 | printk(KERN_DEBUG \ |
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| 32 | KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) |
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| 33 | |
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| 34 | #define nvt_dbg_wake(text, ...) \ |
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| 35 | if (debug > 2) \ |
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| 36 | printk(KERN_DEBUG \ |
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| 37 | KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) |
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| 38 | |
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| 39 | |
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| 40 | #define RX_BUF_LEN 32 |
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| 41 | |
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| 42 | #define SIO_ID_MASK 0xfff0 |
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| 43 | |
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| 44 | enum nvt_chip_ver { |
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| 45 | NVT_UNKNOWN = 0, |
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| 46 | NVT_W83667HG = 0xa510, |
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| 47 | NVT_6775F = 0xb470, |
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| 48 | NVT_6776F = 0xc330, |
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| 49 | NVT_6779D = 0xc560, |
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| 50 | NVT_INVALID = 0xffff, |
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| 51 | }; |
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| 52 | |
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| 53 | struct nvt_chip { |
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| 54 | const char *name; |
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| 55 | enum nvt_chip_ver chip_ver; |
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| 56 | }; |
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| 57 | |
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| 58 | struct nvt_dev { |
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| 59 | struct rc_dev *rdev; |
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| 60 | |
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| 61 | spinlock_t lock; |
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| 62 | |
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| 63 | /* for rx */ |
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| 64 | u8 buf[RX_BUF_LEN]; |
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| 65 | unsigned int pkts; |
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| 66 | |
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| 67 | /* EFER Config register index/data pair */ |
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| 68 | u32 cr_efir; |
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| 69 | u32 cr_efdr; |
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| 70 | |
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| 71 | /* hardware I/O settings */ |
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| 72 | unsigned long cir_addr; |
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| 73 | unsigned long cir_wake_addr; |
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| 74 | int cir_irq; |
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| 75 | |
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| 76 | enum nvt_chip_ver chip_ver; |
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| 77 | /* hardware id */ |
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| 78 | u8 chip_major; |
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| 79 | u8 chip_minor; |
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| 80 | |
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| 81 | /* carrier period = 1 / frequency */ |
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| 82 | u32 carrier; |
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| 83 | }; |
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| 84 | |
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| 85 | /* buffer packet constants */ |
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| 86 | #define BUF_PULSE_BIT 0x80 |
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| 87 | #define BUF_LEN_MASK 0x7f |
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| 88 | #define BUF_REPEAT_BYTE 0x70 |
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| 89 | #define BUF_REPEAT_MASK 0xf0 |
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| 90 | |
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| 91 | /* CIR settings */ |
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| 92 | |
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| 93 | /* total length of CIR and CIR WAKE */ |
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| 94 | #define CIR_IOREG_LENGTH 0x0f |
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| 95 | |
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| 96 | /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */ |
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| 97 | #define CIR_RX_LIMIT_COUNT (IR_DEFAULT_TIMEOUT / SAMPLE_PERIOD) |
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| 98 | |
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| 99 | /* CIR Regs */ |
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| 100 | #define CIR_IRCON 0x00 |
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| 101 | #define CIR_IRSTS 0x01 |
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| 102 | #define CIR_IREN 0x02 |
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| 103 | #define CIR_RXFCONT 0x03 |
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| 104 | #define CIR_CP 0x04 |
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| 105 | #define CIR_CC 0x05 |
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| 106 | #define CIR_SLCH 0x06 |
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| 107 | #define CIR_SLCL 0x07 |
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| 108 | #define CIR_FIFOCON 0x08 |
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| 109 | #define CIR_IRFIFOSTS 0x09 |
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| 110 | #define CIR_SRXFIFO 0x0a |
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| 111 | #define CIR_TXFCONT 0x0b |
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| 112 | #define CIR_STXFIFO 0x0c |
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| 113 | #define CIR_FCCH 0x0d |
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| 114 | #define CIR_FCCL 0x0e |
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| 115 | #define CIR_IRFSM 0x0f |
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| 116 | |
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| 117 | /* CIR IRCON settings */ |
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| 118 | #define CIR_IRCON_RECV 0x80 |
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| 119 | #define CIR_IRCON_WIREN 0x40 |
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| 120 | #define CIR_IRCON_TXEN 0x20 |
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| 121 | #define CIR_IRCON_RXEN 0x10 |
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| 122 | #define CIR_IRCON_WRXINV 0x08 |
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| 123 | #define CIR_IRCON_RXINV 0x04 |
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| 124 | |
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| 125 | #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00 |
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| 126 | #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01 |
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| 127 | #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02 |
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| 128 | #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03 |
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| 129 | |
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| 130 | /* FIXME: make this a runtime option */ |
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| 131 | /* select sample period as 50us */ |
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| 132 | #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 |
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| 133 | |
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| 134 | /* CIR IRSTS settings */ |
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| 135 | #define CIR_IRSTS_RDR 0x80 |
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| 136 | #define CIR_IRSTS_RTR 0x40 |
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| 137 | #define CIR_IRSTS_PE 0x20 |
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| 138 | #define CIR_IRSTS_RFO 0x10 |
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| 139 | #define CIR_IRSTS_TE 0x08 |
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| 140 | #define CIR_IRSTS_TTR 0x04 |
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| 141 | #define CIR_IRSTS_TFU 0x02 |
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| 142 | #define CIR_IRSTS_GH 0x01 |
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| 143 | |
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| 144 | /* CIR IREN settings */ |
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| 145 | #define CIR_IREN_RDR 0x80 |
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| 146 | #define CIR_IREN_RTR 0x40 |
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| 147 | #define CIR_IREN_PE 0x20 |
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| 148 | #define CIR_IREN_RFO 0x10 |
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| 149 | #define CIR_IREN_TE 0x08 |
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| 150 | #define CIR_IREN_TTR 0x04 |
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| 151 | #define CIR_IREN_TFU 0x02 |
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| 152 | #define CIR_IREN_GH 0x01 |
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| 153 | |
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| 154 | /* CIR FIFOCON settings */ |
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| 155 | #define CIR_FIFOCON_TXFIFOCLR 0x80 |
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| 156 | |
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| 157 | #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00 |
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| 158 | #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10 |
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| 159 | #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20 |
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| 160 | #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30 |
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| 161 | |
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| 162 | /* FIXME: make this a runtime option */ |
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| 163 | /* select TX trigger level as 16 */ |
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| 164 | #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16 |
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| 165 | |
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| 166 | #define CIR_FIFOCON_RXFIFOCLR 0x08 |
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| 167 | |
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| 168 | #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00 |
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| 169 | #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01 |
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| 170 | #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02 |
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| 171 | #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03 |
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| 172 | |
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| 173 | /* FIXME: make this a runtime option */ |
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| 174 | /* select RX trigger level as 24 */ |
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| 175 | #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24 |
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| 176 | |
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| 177 | /* CIR IRFIFOSTS settings */ |
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| 178 | #define CIR_IRFIFOSTS_IR_PENDING 0x80 |
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| 179 | #define CIR_IRFIFOSTS_RX_GS 0x40 |
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| 180 | #define CIR_IRFIFOSTS_RX_FTA 0x20 |
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| 181 | #define CIR_IRFIFOSTS_RX_EMPTY 0x10 |
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| 182 | #define CIR_IRFIFOSTS_RX_FULL 0x08 |
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| 183 | #define CIR_IRFIFOSTS_TX_FTA 0x04 |
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| 184 | #define CIR_IRFIFOSTS_TX_EMPTY 0x02 |
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| 185 | #define CIR_IRFIFOSTS_TX_FULL 0x01 |
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| 186 | |
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| 187 | |
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| 188 | /* CIR WAKE UP Regs */ |
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| 189 | #define CIR_WAKE_IRCON 0x00 |
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| 190 | #define CIR_WAKE_IRSTS 0x01 |
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| 191 | #define CIR_WAKE_IREN 0x02 |
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| 192 | #define CIR_WAKE_FIFO_CMP_DEEP 0x03 |
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| 193 | #define CIR_WAKE_FIFO_CMP_TOL 0x04 |
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| 194 | #define CIR_WAKE_FIFO_COUNT 0x05 |
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| 195 | #define CIR_WAKE_SLCH 0x06 |
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| 196 | #define CIR_WAKE_SLCL 0x07 |
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| 197 | #define CIR_WAKE_FIFOCON 0x08 |
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| 198 | #define CIR_WAKE_SRXFSTS 0x09 |
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| 199 | #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a |
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| 200 | #define CIR_WAKE_WR_FIFO_DATA 0x0b |
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| 201 | #define CIR_WAKE_RD_FIFO_ONLY 0x0c |
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| 202 | #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d |
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| 203 | #define CIR_WAKE_FIFO_IGNORE 0x0e |
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| 204 | #define CIR_WAKE_IRFSM 0x0f |
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| 205 | |
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| 206 | /* CIR WAKE UP IRCON settings */ |
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| 207 | #define CIR_WAKE_IRCON_DEC_RST 0x80 |
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| 208 | #define CIR_WAKE_IRCON_MODE1 0x40 |
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| 209 | #define CIR_WAKE_IRCON_MODE0 0x20 |
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| 210 | #define CIR_WAKE_IRCON_RXEN 0x10 |
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| 211 | #define CIR_WAKE_IRCON_R 0x08 |
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| 212 | #define CIR_WAKE_IRCON_RXINV 0x04 |
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| 213 | |
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| 214 | /* FIXME/jarod: make this a runtime option */ |
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| 215 | /* select a same sample period like cir register */ |
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| 216 | #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 |
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| 217 | |
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| 218 | /* CIR WAKE IRSTS Bits */ |
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| 219 | #define CIR_WAKE_IRSTS_RDR 0x80 |
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| 220 | #define CIR_WAKE_IRSTS_RTR 0x40 |
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| 221 | #define CIR_WAKE_IRSTS_PE 0x20 |
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| 222 | #define CIR_WAKE_IRSTS_RFO 0x10 |
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| 223 | #define CIR_WAKE_IRSTS_GH 0x08 |
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| 224 | #define CIR_WAKE_IRSTS_IR_PENDING 0x01 |
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| 225 | |
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| 226 | /* CIR WAKE UP IREN Bits */ |
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| 227 | #define CIR_WAKE_IREN_RDR 0x80 |
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| 228 | #define CIR_WAKE_IREN_RTR 0x40 |
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| 229 | #define CIR_WAKE_IREN_PE 0x20 |
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| 230 | #define CIR_WAKE_IREN_RFO 0x10 |
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| 231 | #define CIR_WAKE_IREN_GH 0x08 |
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| 232 | |
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| 233 | /* CIR WAKE FIFOCON settings */ |
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| 234 | #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08 |
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| 235 | |
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| 236 | #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00 |
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| 237 | #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01 |
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| 238 | #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02 |
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| 239 | #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03 |
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| 240 | |
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| 241 | /* FIXME: make this a runtime option */ |
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| 242 | /* select WAKE UP RX trigger level as 67 */ |
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| 243 | #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 |
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| 244 | |
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| 245 | /* CIR WAKE SRXFSTS settings */ |
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| 246 | #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80 |
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| 247 | #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40 |
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| 248 | #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20 |
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| 249 | #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10 |
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| 250 | |
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| 251 | /* |
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| 252 | * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes |
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| 253 | * the system comparing only 65 bytes (fails with this set to 67) |
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| 254 | */ |
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| 255 | #define CIR_WAKE_FIFO_CMP_BYTES 65 |
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| 256 | /* CIR Wake byte comparison tolerance */ |
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| 257 | #define CIR_WAKE_CMP_TOLERANCE 5 |
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| 258 | |
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| 259 | /* |
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| 260 | * Extended Function Enable Registers: |
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| 261 | * Extended Function Index Register |
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| 262 | * Extended Function Data Register |
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| 263 | */ |
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| 264 | #define CR_EFIR 0x2e |
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| 265 | #define CR_EFDR 0x2f |
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| 266 | |
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| 267 | /* Possible alternate EFER values, depends on how the chip is wired */ |
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| 268 | #define CR_EFIR2 0x4e |
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| 269 | #define CR_EFDR2 0x4f |
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| 270 | |
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| 271 | /* Extended Function Mode enable/disable magic values */ |
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| 272 | #define EFER_EFM_ENABLE 0x87 |
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| 273 | #define EFER_EFM_DISABLE 0xaa |
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| 274 | |
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| 275 | /* Config regs we need to care about */ |
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| 276 | #define CR_SOFTWARE_RESET 0x02 |
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| 277 | #define CR_LOGICAL_DEV_SEL 0x07 |
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| 278 | #define CR_CHIP_ID_HI 0x20 |
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| 279 | #define CR_CHIP_ID_LO 0x21 |
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| 280 | #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */ |
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| 281 | #define CR_OUTPUT_PIN_SEL 0x27 |
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| 282 | #define CR_MULTIFUNC_PIN_SEL 0x2c |
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| 283 | #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */ |
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| 284 | /* next three regs valid for both the CIR and CIR_WAKE logical devices */ |
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| 285 | #define CR_CIR_BASE_ADDR_HI 0x60 |
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| 286 | #define CR_CIR_BASE_ADDR_LO 0x61 |
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| 287 | #define CR_CIR_IRQ_RSRC 0x70 |
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| 288 | /* next three regs valid only for ACPI logical dev */ |
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| 289 | #define CR_ACPI_CIR_WAKE 0xe0 |
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| 290 | #define CR_ACPI_IRQ_EVENTS 0xf6 |
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| 291 | #define CR_ACPI_IRQ_EVENTS2 0xf7 |
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| 292 | |
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| 293 | /* Logical devices that we need to care about */ |
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| 294 | #define LOGICAL_DEV_LPT 0x01 |
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| 295 | #define LOGICAL_DEV_CIR 0x06 |
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| 296 | #define LOGICAL_DEV_ACPI 0x0a |
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| 297 | #define LOGICAL_DEV_CIR_WAKE 0x0e |
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| 298 | |
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| 299 | #define LOGICAL_DEV_DISABLE 0x00 |
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| 300 | #define LOGICAL_DEV_ENABLE 0x01 |
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| 301 | |
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| 302 | #define CIR_WAKE_ENABLE_BIT 0x08 |
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| 303 | #define PME_INTR_CIR_PASS_BIT 0x08 |
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| 304 | |
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| 305 | /* w83677hg CIR pin config */ |
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| 306 | #define OUTPUT_PIN_SEL_MASK 0xbc |
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| 307 | #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */ |
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| 308 | #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */ |
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| 309 | |
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| 310 | /* w83667hg CIR pin config */ |
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| 311 | #define MULTIFUNC_PIN_SEL_MASK 0x1f |
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| 312 | #define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */ |
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| 313 | #define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */ |
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| 314 | |
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| 315 | /* MCE CIR signal length, related on sample period */ |
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| 316 | |
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| 317 | /* MCE CIR controller signal length: about 43ms |
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| 318 | * 43ms / 50us (sample period) * 0.85 (inaccuracy) |
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| 319 | */ |
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| 320 | #define CONTROLLER_BUF_LEN_MIN 830 |
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| 321 | |
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| 322 | /* MCE CIR keyboard signal length: about 26ms |
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| 323 | * 26ms / 50us (sample period) * 0.85 (inaccuracy) |
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| 324 | */ |
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| 325 | #define KEYBOARD_BUF_LEN_MAX 650 |
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| 326 | #define KEYBOARD_BUF_LEN_MIN 610 |
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| 327 | |
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| 328 | /* MCE CIR mouse signal length: about 24ms |
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| 329 | * 24ms / 50us (sample period) * 0.85 (inaccuracy) |
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| 330 | */ |
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| 331 | #define MOUSE_BUF_LEN_MIN 565 |
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| 332 | |
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| 333 | #define CIR_SAMPLE_PERIOD 50 |
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| 334 | #define CIR_SAMPLE_LOW_INACCURACY 0.85 |
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| 335 | |
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| 336 | /* MAX silence time that driver will sent to lirc */ |
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| 337 | #define MAX_SILENCE_TIME 60000 |
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| 338 | |
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| 339 | #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100 |
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| 340 | #define SAMPLE_PERIOD 100 |
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| 341 | |
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| 342 | #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50 |
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| 343 | #define SAMPLE_PERIOD 50 |
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| 344 | |
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| 345 | #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25 |
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| 346 | #define SAMPLE_PERIOD 25 |
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| 347 | |
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| 348 | #else |
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| 349 | #define SAMPLE_PERIOD 1 |
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| 350 | #endif |
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| 351 | |
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| 352 | /* as VISTA MCE definition, valid carrier value */ |
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| 353 | #define MAX_CARRIER 60000 |
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| 354 | #define MIN_CARRIER 30000 |
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| 355 | |
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| 356 | /* max wakeup sequence length */ |
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| 357 | #define WAKEUP_MAX_SIZE 65 |
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| 358 | |
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