1 | /* |
2 | MaxLinear MXL5005S VSB/QAM/DVBT tuner driver |
3 | |
4 | Copyright (C) 2008 MaxLinear |
5 | Copyright (C) 2006 Steven Toth <stoth@linuxtv.org> |
6 | Functions: |
7 | mxl5005s_reset() |
8 | mxl5005s_writereg() |
9 | mxl5005s_writeregs() |
10 | mxl5005s_init() |
11 | mxl5005s_reconfigure() |
12 | mxl5005s_AssignTunerMode() |
13 | mxl5005s_set_params() |
14 | mxl5005s_get_frequency() |
15 | mxl5005s_get_bandwidth() |
16 | mxl5005s_release() |
17 | mxl5005s_attach() |
18 | |
19 | Copyright (C) 2008 Realtek |
20 | Copyright (C) 2008 Jan Hoogenraad |
21 | Functions: |
22 | mxl5005s_SetRfFreqHz() |
23 | |
24 | This program is free software; you can redistribute it and/or modify |
25 | it under the terms of the GNU General Public License as published by |
26 | the Free Software Foundation; either version 2 of the License, or |
27 | (at your option) any later version. |
28 | |
29 | This program is distributed in the hope that it will be useful, |
30 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
31 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
32 | GNU General Public License for more details. |
33 | |
34 | You should have received a copy of the GNU General Public License |
35 | along with this program; if not, write to the Free Software |
36 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
37 | |
38 | */ |
39 | |
40 | /* |
41 | History of this driver (Steven Toth): |
42 | I was given a public release of a linux driver that included |
43 | support for the MaxLinear MXL5005S silicon tuner. Analysis of |
44 | the tuner driver showed clearly three things. |
45 | |
46 | 1. The tuner driver didn't support the LinuxTV tuner API |
47 | so the code Realtek added had to be removed. |
48 | |
49 | 2. A significant amount of the driver is reference driver code |
50 | from MaxLinear, I felt it was important to identify and |
51 | preserve this. |
52 | |
53 | 3. New code has to be added to interface correctly with the |
54 | LinuxTV API, as a regular kernel module. |
55 | |
56 | Other than the reference driver enum's, I've clearly marked |
57 | sections of the code and retained the copyright of the |
58 | respective owners. |
59 | */ |
60 | #include <linux/kernel.h> |
61 | #include <linux/init.h> |
62 | #include <linux/module.h> |
63 | #include <linux/string.h> |
64 | #include <linux/slab.h> |
65 | #include <linux/delay.h> |
66 | #include <media/dvb_frontend.h> |
67 | #include "mxl5005s.h" |
68 | |
69 | static int debug; |
70 | |
71 | #define dprintk(level, arg...) do { \ |
72 | if (level <= debug) \ |
73 | printk(arg); \ |
74 | } while (0) |
75 | |
76 | #define TUNER_REGS_NUM 104 |
77 | #define INITCTRL_NUM 40 |
78 | |
79 | #ifdef _MXL_PRODUCTION |
80 | #define CHCTRL_NUM 39 |
81 | #else |
82 | #define CHCTRL_NUM 36 |
83 | #endif |
84 | |
85 | #define MXLCTRL_NUM 189 |
86 | #define MASTER_CONTROL_ADDR 9 |
87 | |
88 | /* Enumeration of Master Control Register State */ |
89 | enum master_control_state { |
90 | MC_LOAD_START = 1, |
91 | MC_POWER_DOWN, |
92 | MC_SYNTH_RESET, |
93 | MC_SEQ_OFF |
94 | }; |
95 | |
96 | /* Enumeration of MXL5005 Tuner Modulation Type */ |
97 | enum { |
98 | MXL_DEFAULT_MODULATION = 0, |
99 | MXL_DVBT, |
100 | MXL_ATSC, |
101 | MXL_QAM, |
102 | MXL_ANALOG_CABLE, |
103 | MXL_ANALOG_OTA |
104 | }; |
105 | |
106 | /* MXL5005 Tuner Register Struct */ |
107 | struct TunerReg { |
108 | u16 Reg_Num; /* Tuner Register Address */ |
109 | u16 Reg_Val; /* Current sw programmed value waiting to be written */ |
110 | }; |
111 | |
112 | enum { |
113 | /* Initialization Control Names */ |
114 | DN_IQTN_AMP_CUT = 1, /* 1 */ |
115 | BB_MODE, /* 2 */ |
116 | BB_BUF, /* 3 */ |
117 | BB_BUF_OA, /* 4 */ |
118 | BB_ALPF_BANDSELECT, /* 5 */ |
119 | BB_IQSWAP, /* 6 */ |
120 | BB_DLPF_BANDSEL, /* 7 */ |
121 | RFSYN_CHP_GAIN, /* 8 */ |
122 | RFSYN_EN_CHP_HIGAIN, /* 9 */ |
123 | AGC_IF, /* 10 */ |
124 | AGC_RF, /* 11 */ |
125 | IF_DIVVAL, /* 12 */ |
126 | IF_VCO_BIAS, /* 13 */ |
127 | CHCAL_INT_MOD_IF, /* 14 */ |
128 | CHCAL_FRAC_MOD_IF, /* 15 */ |
129 | DRV_RES_SEL, /* 16 */ |
130 | I_DRIVER, /* 17 */ |
131 | EN_AAF, /* 18 */ |
132 | EN_3P, /* 19 */ |
133 | EN_AUX_3P, /* 20 */ |
134 | SEL_AAF_BAND, /* 21 */ |
135 | SEQ_ENCLK16_CLK_OUT, /* 22 */ |
136 | SEQ_SEL4_16B, /* 23 */ |
137 | XTAL_CAPSELECT, /* 24 */ |
138 | IF_SEL_DBL, /* 25 */ |
139 | RFSYN_R_DIV, /* 26 */ |
140 | SEQ_EXTSYNTHCALIF, /* 27 */ |
141 | SEQ_EXTDCCAL, /* 28 */ |
142 | , /* 29 */ |
143 | RFA_ENCLKRFAGC, /* 30 */ |
144 | , /* 31 */ |
145 | , /* 32 */ |
146 | , /* 33 */ |
147 | RFA_FLR, /* 34 */ |
148 | RFA_CEIL, /* 35 */ |
149 | SEQ_EXTIQFSMPULSE, /* 36 */ |
150 | OVERRIDE_1, /* 37 */ |
151 | BB_INITSTATE_DLPF_TUNE, /* 38 */ |
152 | TG_R_DIV, /* 39 */ |
153 | EN_CHP_LIN_B, /* 40 */ |
154 | |
155 | /* Channel Change Control Names */ |
156 | DN_POLY = 51, /* 51 */ |
157 | DN_RFGAIN, /* 52 */ |
158 | DN_CAP_RFLPF, /* 53 */ |
159 | DN_EN_VHFUHFBAR, /* 54 */ |
160 | DN_GAIN_ADJUST, /* 55 */ |
161 | DN_IQTNBUF_AMP, /* 56 */ |
162 | DN_IQTNGNBFBIAS_BST, /* 57 */ |
163 | RFSYN_EN_OUTMUX, /* 58 */ |
164 | RFSYN_SEL_VCO_OUT, /* 59 */ |
165 | RFSYN_SEL_VCO_HI, /* 60 */ |
166 | RFSYN_SEL_DIVM, /* 61 */ |
167 | RFSYN_RF_DIV_BIAS, /* 62 */ |
168 | DN_SEL_FREQ, /* 63 */ |
169 | RFSYN_VCO_BIAS, /* 64 */ |
170 | CHCAL_INT_MOD_RF, /* 65 */ |
171 | CHCAL_FRAC_MOD_RF, /* 66 */ |
172 | RFSYN_LPF_R, /* 67 */ |
173 | CHCAL_EN_INT_RF, /* 68 */ |
174 | TG_LO_DIVVAL, /* 69 */ |
175 | TG_LO_SELVAL, /* 70 */ |
176 | TG_DIV_VAL, /* 71 */ |
177 | TG_VCO_BIAS, /* 72 */ |
178 | SEQ_EXTPOWERUP, /* 73 */ |
179 | OVERRIDE_2, /* 74 */ |
180 | OVERRIDE_3, /* 75 */ |
181 | OVERRIDE_4, /* 76 */ |
182 | SEQ_FSM_PULSE, /* 77 */ |
183 | GPIO_4B, /* 78 */ |
184 | GPIO_3B, /* 79 */ |
185 | GPIO_4, /* 80 */ |
186 | GPIO_3, /* 81 */ |
187 | GPIO_1B, /* 82 */ |
188 | DAC_A_ENABLE, /* 83 */ |
189 | DAC_B_ENABLE, /* 84 */ |
190 | DAC_DIN_A, /* 85 */ |
191 | DAC_DIN_B, /* 86 */ |
192 | #ifdef _MXL_PRODUCTION |
193 | RFSYN_EN_DIV, /* 87 */ |
194 | RFSYN_DIVM, /* 88 */ |
195 | DN_BYPASS_AGC_I2C /* 89 */ |
196 | #endif |
197 | }; |
198 | |
199 | /* |
200 | * The following context is source code provided by MaxLinear. |
201 | * MaxLinear source code - Common_MXL.h (?) |
202 | */ |
203 | |
204 | /* Constants */ |
205 | #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 |
206 | #define MXL5005S_LATCH_BYTE 0xfe |
207 | |
208 | /* Register address, MSB, and LSB */ |
209 | #define MXL5005S_BB_IQSWAP_ADDR 59 |
210 | #define MXL5005S_BB_IQSWAP_MSB 0 |
211 | #define MXL5005S_BB_IQSWAP_LSB 0 |
212 | |
213 | #define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 |
214 | #define MXL5005S_BB_DLPF_BANDSEL_MSB 4 |
215 | #define MXL5005S_BB_DLPF_BANDSEL_LSB 3 |
216 | |
217 | /* Standard modes */ |
218 | enum { |
219 | MXL5005S_STANDARD_DVBT, |
220 | MXL5005S_STANDARD_ATSC, |
221 | }; |
222 | #define MXL5005S_STANDARD_MODE_NUM 2 |
223 | |
224 | /* Bandwidth modes */ |
225 | enum { |
226 | MXL5005S_BANDWIDTH_6MHZ = 6000000, |
227 | MXL5005S_BANDWIDTH_7MHZ = 7000000, |
228 | MXL5005S_BANDWIDTH_8MHZ = 8000000, |
229 | }; |
230 | #define MXL5005S_BANDWIDTH_MODE_NUM 3 |
231 | |
232 | /* MXL5005 Tuner Control Struct */ |
233 | struct TunerControl { |
234 | u16 Ctrl_Num; /* Control Number */ |
235 | u16 size; /* Number of bits to represent Value */ |
236 | u16 addr[25]; /* Array of Tuner Register Address for each bit pos */ |
237 | u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */ |
238 | u16 val[25]; /* Binary representation of Value */ |
239 | }; |
240 | |
241 | /* MXL5005 Tuner Struct */ |
242 | struct mxl5005s_state { |
243 | u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ |
244 | u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ |
245 | u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ |
246 | u32 IF_OUT; /* Desired IF Out Frequency */ |
247 | u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ |
248 | u32 RF_IN; /* RF Input Frequency */ |
249 | u32 Fxtal; /* XTAL Frequency */ |
250 | u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ |
251 | u16 TOP; /* Value: take over point */ |
252 | u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */ |
253 | u8 DIV_OUT; /* 4MHz or 16MHz */ |
254 | u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ |
255 | u8 ; /* 0: disable RSSI; 1: enable RSSI */ |
256 | |
257 | /* Modulation Type; */ |
258 | /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ |
259 | u8 Mod_Type; |
260 | |
261 | /* Tracking Filter Type */ |
262 | /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ |
263 | u8 TF_Type; |
264 | |
265 | /* Calculated Settings */ |
266 | u32 RF_LO; /* Synth RF LO Frequency */ |
267 | u32 IF_LO; /* Synth IF LO Frequency */ |
268 | u32 TG_LO; /* Synth TG_LO Frequency */ |
269 | |
270 | /* Pointers to ControlName Arrays */ |
271 | u16 Init_Ctrl_Num; /* Number of INIT Control Names */ |
272 | struct TunerControl |
273 | Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ |
274 | |
275 | u16 CH_Ctrl_Num; /* Number of CH Control Names */ |
276 | struct TunerControl |
277 | CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ |
278 | |
279 | u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ |
280 | struct TunerControl |
281 | MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ |
282 | |
283 | /* Pointer to Tuner Register Array */ |
284 | u16 TunerRegs_Num; /* Number of Tuner Registers */ |
285 | struct TunerReg |
286 | TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ |
287 | |
288 | /* Linux driver framework specific */ |
289 | struct mxl5005s_config *config; |
290 | struct dvb_frontend *frontend; |
291 | struct i2c_adapter *i2c; |
292 | |
293 | /* Cache values */ |
294 | u32 current_mode; |
295 | |
296 | }; |
297 | |
298 | static u16 MXL_GetMasterControl(u8 *MasterReg, int state); |
299 | static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); |
300 | static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); |
301 | static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, |
302 | u8 bitVal); |
303 | static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, |
304 | u8 *RegVal, int *count); |
305 | static u32 MXL_Ceiling(u32 value, u32 resolution); |
306 | static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); |
307 | static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, |
308 | u32 value, u16 controlGroup); |
309 | static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); |
310 | static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, |
311 | u8 *RegVal, int *count); |
312 | static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); |
313 | static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); |
314 | static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); |
315 | static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, |
316 | u8 *RegVal, int *count); |
317 | static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, |
318 | u8 *datatable, u8 len); |
319 | static u16 MXL_IFSynthInit(struct dvb_frontend *fe); |
320 | static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, |
321 | u32 bandwidth); |
322 | static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, |
323 | u32 bandwidth); |
324 | |
325 | /* ---------------------------------------------------------------- |
326 | * Begin: Custom code salvaged from the Realtek driver. |
327 | * Copyright (C) 2008 Realtek |
328 | * Copyright (C) 2008 Jan Hoogenraad |
329 | * This code is placed under the terms of the GNU General Public License |
330 | * |
331 | * Released by Realtek under GPLv2. |
332 | * Thanks to Realtek for a lot of support we received ! |
333 | * |
334 | * Revision: 080314 - original version |
335 | */ |
336 | |
337 | static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) |
338 | { |
339 | struct mxl5005s_state *state = fe->tuner_priv; |
340 | unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; |
341 | unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; |
342 | int TableLen; |
343 | |
344 | u32 IfDivval = 0; |
345 | unsigned char MasterControlByte; |
346 | |
347 | dprintk(1, "%s() freq=%ld\n" , __func__, RfFreqHz); |
348 | |
349 | /* Set MxL5005S tuner RF frequency according to example code. */ |
350 | |
351 | /* Tuner RF frequency setting stage 0 */ |
352 | MXL_GetMasterControl(MasterReg: ByteTable, state: MC_SYNTH_RESET); |
353 | AddrTable[0] = MASTER_CONTROL_ADDR; |
354 | ByteTable[0] |= state->config->AgcMasterByte; |
355 | |
356 | mxl5005s_writeregs(fe, addrtable: AddrTable, datatable: ByteTable, len: 1); |
357 | |
358 | /* Tuner RF frequency setting stage 1 */ |
359 | MXL_TuneRF(fe, RF_Freq: RfFreqHz); |
360 | |
361 | MXL_ControlRead(fe, controlNum: IF_DIVVAL, value: &IfDivval); |
362 | |
363 | MXL_ControlWrite(fe, ControlNum: SEQ_FSM_PULSE, value: 0); |
364 | MXL_ControlWrite(fe, ControlNum: SEQ_EXTPOWERUP, value: 1); |
365 | MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 8); |
366 | MXL_GetCHRegister(fe, RegNum: AddrTable, RegVal: ByteTable, count: &TableLen); |
367 | |
368 | MXL_GetMasterControl(MasterReg: &MasterControlByte, state: MC_LOAD_START); |
369 | AddrTable[TableLen] = MASTER_CONTROL_ADDR ; |
370 | ByteTable[TableLen] = MasterControlByte | |
371 | state->config->AgcMasterByte; |
372 | TableLen += 1; |
373 | |
374 | mxl5005s_writeregs(fe, addrtable: AddrTable, datatable: ByteTable, len: TableLen); |
375 | |
376 | /* Wait 30 ms. */ |
377 | msleep(msecs: 150); |
378 | |
379 | /* Tuner RF frequency setting stage 2 */ |
380 | MXL_ControlWrite(fe, ControlNum: SEQ_FSM_PULSE, value: 1); |
381 | MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: IfDivval); |
382 | MXL_GetCHRegister_ZeroIF(fe, RegNum: AddrTable, RegVal: ByteTable, count: &TableLen); |
383 | |
384 | MXL_GetMasterControl(MasterReg: &MasterControlByte, state: MC_LOAD_START); |
385 | AddrTable[TableLen] = MASTER_CONTROL_ADDR ; |
386 | ByteTable[TableLen] = MasterControlByte | |
387 | state->config->AgcMasterByte ; |
388 | TableLen += 1; |
389 | |
390 | mxl5005s_writeregs(fe, addrtable: AddrTable, datatable: ByteTable, len: TableLen); |
391 | |
392 | msleep(msecs: 100); |
393 | |
394 | return 0; |
395 | } |
396 | /* End: Custom code taken from the Realtek driver */ |
397 | |
398 | /* ---------------------------------------------------------------- |
399 | * Begin: Reference driver code found in the Realtek driver. |
400 | * Copyright (C) 2008 MaxLinear |
401 | */ |
402 | static u16 MXL5005_RegisterInit(struct dvb_frontend *fe) |
403 | { |
404 | struct mxl5005s_state *state = fe->tuner_priv; |
405 | state->TunerRegs_Num = TUNER_REGS_NUM ; |
406 | |
407 | state->TunerRegs[0].Reg_Num = 9 ; |
408 | state->TunerRegs[0].Reg_Val = 0x40 ; |
409 | |
410 | state->TunerRegs[1].Reg_Num = 11 ; |
411 | state->TunerRegs[1].Reg_Val = 0x19 ; |
412 | |
413 | state->TunerRegs[2].Reg_Num = 12 ; |
414 | state->TunerRegs[2].Reg_Val = 0x60 ; |
415 | |
416 | state->TunerRegs[3].Reg_Num = 13 ; |
417 | state->TunerRegs[3].Reg_Val = 0x00 ; |
418 | |
419 | state->TunerRegs[4].Reg_Num = 14 ; |
420 | state->TunerRegs[4].Reg_Val = 0x00 ; |
421 | |
422 | state->TunerRegs[5].Reg_Num = 15 ; |
423 | state->TunerRegs[5].Reg_Val = 0xC0 ; |
424 | |
425 | state->TunerRegs[6].Reg_Num = 16 ; |
426 | state->TunerRegs[6].Reg_Val = 0x00 ; |
427 | |
428 | state->TunerRegs[7].Reg_Num = 17 ; |
429 | state->TunerRegs[7].Reg_Val = 0x00 ; |
430 | |
431 | state->TunerRegs[8].Reg_Num = 18 ; |
432 | state->TunerRegs[8].Reg_Val = 0x00 ; |
433 | |
434 | state->TunerRegs[9].Reg_Num = 19 ; |
435 | state->TunerRegs[9].Reg_Val = 0x34 ; |
436 | |
437 | state->TunerRegs[10].Reg_Num = 21 ; |
438 | state->TunerRegs[10].Reg_Val = 0x00 ; |
439 | |
440 | state->TunerRegs[11].Reg_Num = 22 ; |
441 | state->TunerRegs[11].Reg_Val = 0x6B ; |
442 | |
443 | state->TunerRegs[12].Reg_Num = 23 ; |
444 | state->TunerRegs[12].Reg_Val = 0x35 ; |
445 | |
446 | state->TunerRegs[13].Reg_Num = 24 ; |
447 | state->TunerRegs[13].Reg_Val = 0x70 ; |
448 | |
449 | state->TunerRegs[14].Reg_Num = 25 ; |
450 | state->TunerRegs[14].Reg_Val = 0x3E ; |
451 | |
452 | state->TunerRegs[15].Reg_Num = 26 ; |
453 | state->TunerRegs[15].Reg_Val = 0x82 ; |
454 | |
455 | state->TunerRegs[16].Reg_Num = 31 ; |
456 | state->TunerRegs[16].Reg_Val = 0x00 ; |
457 | |
458 | state->TunerRegs[17].Reg_Num = 32 ; |
459 | state->TunerRegs[17].Reg_Val = 0x40 ; |
460 | |
461 | state->TunerRegs[18].Reg_Num = 33 ; |
462 | state->TunerRegs[18].Reg_Val = 0x53 ; |
463 | |
464 | state->TunerRegs[19].Reg_Num = 34 ; |
465 | state->TunerRegs[19].Reg_Val = 0x81 ; |
466 | |
467 | state->TunerRegs[20].Reg_Num = 35 ; |
468 | state->TunerRegs[20].Reg_Val = 0xC9 ; |
469 | |
470 | state->TunerRegs[21].Reg_Num = 36 ; |
471 | state->TunerRegs[21].Reg_Val = 0x01 ; |
472 | |
473 | state->TunerRegs[22].Reg_Num = 37 ; |
474 | state->TunerRegs[22].Reg_Val = 0x00 ; |
475 | |
476 | state->TunerRegs[23].Reg_Num = 41 ; |
477 | state->TunerRegs[23].Reg_Val = 0x00 ; |
478 | |
479 | state->TunerRegs[24].Reg_Num = 42 ; |
480 | state->TunerRegs[24].Reg_Val = 0xF8 ; |
481 | |
482 | state->TunerRegs[25].Reg_Num = 43 ; |
483 | state->TunerRegs[25].Reg_Val = 0x43 ; |
484 | |
485 | state->TunerRegs[26].Reg_Num = 44 ; |
486 | state->TunerRegs[26].Reg_Val = 0x20 ; |
487 | |
488 | state->TunerRegs[27].Reg_Num = 45 ; |
489 | state->TunerRegs[27].Reg_Val = 0x80 ; |
490 | |
491 | state->TunerRegs[28].Reg_Num = 46 ; |
492 | state->TunerRegs[28].Reg_Val = 0x88 ; |
493 | |
494 | state->TunerRegs[29].Reg_Num = 47 ; |
495 | state->TunerRegs[29].Reg_Val = 0x86 ; |
496 | |
497 | state->TunerRegs[30].Reg_Num = 48 ; |
498 | state->TunerRegs[30].Reg_Val = 0x00 ; |
499 | |
500 | state->TunerRegs[31].Reg_Num = 49 ; |
501 | state->TunerRegs[31].Reg_Val = 0x00 ; |
502 | |
503 | state->TunerRegs[32].Reg_Num = 53 ; |
504 | state->TunerRegs[32].Reg_Val = 0x94 ; |
505 | |
506 | state->TunerRegs[33].Reg_Num = 54 ; |
507 | state->TunerRegs[33].Reg_Val = 0xFA ; |
508 | |
509 | state->TunerRegs[34].Reg_Num = 55 ; |
510 | state->TunerRegs[34].Reg_Val = 0x92 ; |
511 | |
512 | state->TunerRegs[35].Reg_Num = 56 ; |
513 | state->TunerRegs[35].Reg_Val = 0x80 ; |
514 | |
515 | state->TunerRegs[36].Reg_Num = 57 ; |
516 | state->TunerRegs[36].Reg_Val = 0x41 ; |
517 | |
518 | state->TunerRegs[37].Reg_Num = 58 ; |
519 | state->TunerRegs[37].Reg_Val = 0xDB ; |
520 | |
521 | state->TunerRegs[38].Reg_Num = 59 ; |
522 | state->TunerRegs[38].Reg_Val = 0x00 ; |
523 | |
524 | state->TunerRegs[39].Reg_Num = 60 ; |
525 | state->TunerRegs[39].Reg_Val = 0x00 ; |
526 | |
527 | state->TunerRegs[40].Reg_Num = 61 ; |
528 | state->TunerRegs[40].Reg_Val = 0x00 ; |
529 | |
530 | state->TunerRegs[41].Reg_Num = 62 ; |
531 | state->TunerRegs[41].Reg_Val = 0x00 ; |
532 | |
533 | state->TunerRegs[42].Reg_Num = 65 ; |
534 | state->TunerRegs[42].Reg_Val = 0xF8 ; |
535 | |
536 | state->TunerRegs[43].Reg_Num = 66 ; |
537 | state->TunerRegs[43].Reg_Val = 0xE4 ; |
538 | |
539 | state->TunerRegs[44].Reg_Num = 67 ; |
540 | state->TunerRegs[44].Reg_Val = 0x90 ; |
541 | |
542 | state->TunerRegs[45].Reg_Num = 68 ; |
543 | state->TunerRegs[45].Reg_Val = 0xC0 ; |
544 | |
545 | state->TunerRegs[46].Reg_Num = 69 ; |
546 | state->TunerRegs[46].Reg_Val = 0x01 ; |
547 | |
548 | state->TunerRegs[47].Reg_Num = 70 ; |
549 | state->TunerRegs[47].Reg_Val = 0x50 ; |
550 | |
551 | state->TunerRegs[48].Reg_Num = 71 ; |
552 | state->TunerRegs[48].Reg_Val = 0x06 ; |
553 | |
554 | state->TunerRegs[49].Reg_Num = 72 ; |
555 | state->TunerRegs[49].Reg_Val = 0x00 ; |
556 | |
557 | state->TunerRegs[50].Reg_Num = 73 ; |
558 | state->TunerRegs[50].Reg_Val = 0x20 ; |
559 | |
560 | state->TunerRegs[51].Reg_Num = 76 ; |
561 | state->TunerRegs[51].Reg_Val = 0xBB ; |
562 | |
563 | state->TunerRegs[52].Reg_Num = 77 ; |
564 | state->TunerRegs[52].Reg_Val = 0x13 ; |
565 | |
566 | state->TunerRegs[53].Reg_Num = 81 ; |
567 | state->TunerRegs[53].Reg_Val = 0x04 ; |
568 | |
569 | state->TunerRegs[54].Reg_Num = 82 ; |
570 | state->TunerRegs[54].Reg_Val = 0x75 ; |
571 | |
572 | state->TunerRegs[55].Reg_Num = 83 ; |
573 | state->TunerRegs[55].Reg_Val = 0x00 ; |
574 | |
575 | state->TunerRegs[56].Reg_Num = 84 ; |
576 | state->TunerRegs[56].Reg_Val = 0x00 ; |
577 | |
578 | state->TunerRegs[57].Reg_Num = 85 ; |
579 | state->TunerRegs[57].Reg_Val = 0x00 ; |
580 | |
581 | state->TunerRegs[58].Reg_Num = 91 ; |
582 | state->TunerRegs[58].Reg_Val = 0x70 ; |
583 | |
584 | state->TunerRegs[59].Reg_Num = 92 ; |
585 | state->TunerRegs[59].Reg_Val = 0x00 ; |
586 | |
587 | state->TunerRegs[60].Reg_Num = 93 ; |
588 | state->TunerRegs[60].Reg_Val = 0x00 ; |
589 | |
590 | state->TunerRegs[61].Reg_Num = 94 ; |
591 | state->TunerRegs[61].Reg_Val = 0x00 ; |
592 | |
593 | state->TunerRegs[62].Reg_Num = 95 ; |
594 | state->TunerRegs[62].Reg_Val = 0x0C ; |
595 | |
596 | state->TunerRegs[63].Reg_Num = 96 ; |
597 | state->TunerRegs[63].Reg_Val = 0x00 ; |
598 | |
599 | state->TunerRegs[64].Reg_Num = 97 ; |
600 | state->TunerRegs[64].Reg_Val = 0x00 ; |
601 | |
602 | state->TunerRegs[65].Reg_Num = 98 ; |
603 | state->TunerRegs[65].Reg_Val = 0xE2 ; |
604 | |
605 | state->TunerRegs[66].Reg_Num = 99 ; |
606 | state->TunerRegs[66].Reg_Val = 0x00 ; |
607 | |
608 | state->TunerRegs[67].Reg_Num = 100 ; |
609 | state->TunerRegs[67].Reg_Val = 0x00 ; |
610 | |
611 | state->TunerRegs[68].Reg_Num = 101 ; |
612 | state->TunerRegs[68].Reg_Val = 0x12 ; |
613 | |
614 | state->TunerRegs[69].Reg_Num = 102 ; |
615 | state->TunerRegs[69].Reg_Val = 0x80 ; |
616 | |
617 | state->TunerRegs[70].Reg_Num = 103 ; |
618 | state->TunerRegs[70].Reg_Val = 0x32 ; |
619 | |
620 | state->TunerRegs[71].Reg_Num = 104 ; |
621 | state->TunerRegs[71].Reg_Val = 0xB4 ; |
622 | |
623 | state->TunerRegs[72].Reg_Num = 105 ; |
624 | state->TunerRegs[72].Reg_Val = 0x60 ; |
625 | |
626 | state->TunerRegs[73].Reg_Num = 106 ; |
627 | state->TunerRegs[73].Reg_Val = 0x83 ; |
628 | |
629 | state->TunerRegs[74].Reg_Num = 107 ; |
630 | state->TunerRegs[74].Reg_Val = 0x84 ; |
631 | |
632 | state->TunerRegs[75].Reg_Num = 108 ; |
633 | state->TunerRegs[75].Reg_Val = 0x9C ; |
634 | |
635 | state->TunerRegs[76].Reg_Num = 109 ; |
636 | state->TunerRegs[76].Reg_Val = 0x02 ; |
637 | |
638 | state->TunerRegs[77].Reg_Num = 110 ; |
639 | state->TunerRegs[77].Reg_Val = 0x81 ; |
640 | |
641 | state->TunerRegs[78].Reg_Num = 111 ; |
642 | state->TunerRegs[78].Reg_Val = 0xC0 ; |
643 | |
644 | state->TunerRegs[79].Reg_Num = 112 ; |
645 | state->TunerRegs[79].Reg_Val = 0x10 ; |
646 | |
647 | state->TunerRegs[80].Reg_Num = 131 ; |
648 | state->TunerRegs[80].Reg_Val = 0x8A ; |
649 | |
650 | state->TunerRegs[81].Reg_Num = 132 ; |
651 | state->TunerRegs[81].Reg_Val = 0x10 ; |
652 | |
653 | state->TunerRegs[82].Reg_Num = 133 ; |
654 | state->TunerRegs[82].Reg_Val = 0x24 ; |
655 | |
656 | state->TunerRegs[83].Reg_Num = 134 ; |
657 | state->TunerRegs[83].Reg_Val = 0x00 ; |
658 | |
659 | state->TunerRegs[84].Reg_Num = 135 ; |
660 | state->TunerRegs[84].Reg_Val = 0x00 ; |
661 | |
662 | state->TunerRegs[85].Reg_Num = 136 ; |
663 | state->TunerRegs[85].Reg_Val = 0x7E ; |
664 | |
665 | state->TunerRegs[86].Reg_Num = 137 ; |
666 | state->TunerRegs[86].Reg_Val = 0x40 ; |
667 | |
668 | state->TunerRegs[87].Reg_Num = 138 ; |
669 | state->TunerRegs[87].Reg_Val = 0x38 ; |
670 | |
671 | state->TunerRegs[88].Reg_Num = 146 ; |
672 | state->TunerRegs[88].Reg_Val = 0xF6 ; |
673 | |
674 | state->TunerRegs[89].Reg_Num = 147 ; |
675 | state->TunerRegs[89].Reg_Val = 0x1A ; |
676 | |
677 | state->TunerRegs[90].Reg_Num = 148 ; |
678 | state->TunerRegs[90].Reg_Val = 0x62 ; |
679 | |
680 | state->TunerRegs[91].Reg_Num = 149 ; |
681 | state->TunerRegs[91].Reg_Val = 0x33 ; |
682 | |
683 | state->TunerRegs[92].Reg_Num = 150 ; |
684 | state->TunerRegs[92].Reg_Val = 0x80 ; |
685 | |
686 | state->TunerRegs[93].Reg_Num = 156 ; |
687 | state->TunerRegs[93].Reg_Val = 0x56 ; |
688 | |
689 | state->TunerRegs[94].Reg_Num = 157 ; |
690 | state->TunerRegs[94].Reg_Val = 0x17 ; |
691 | |
692 | state->TunerRegs[95].Reg_Num = 158 ; |
693 | state->TunerRegs[95].Reg_Val = 0xA9 ; |
694 | |
695 | state->TunerRegs[96].Reg_Num = 159 ; |
696 | state->TunerRegs[96].Reg_Val = 0x00 ; |
697 | |
698 | state->TunerRegs[97].Reg_Num = 160 ; |
699 | state->TunerRegs[97].Reg_Val = 0x00 ; |
700 | |
701 | state->TunerRegs[98].Reg_Num = 161 ; |
702 | state->TunerRegs[98].Reg_Val = 0x00 ; |
703 | |
704 | state->TunerRegs[99].Reg_Num = 162 ; |
705 | state->TunerRegs[99].Reg_Val = 0x40 ; |
706 | |
707 | state->TunerRegs[100].Reg_Num = 166 ; |
708 | state->TunerRegs[100].Reg_Val = 0xAE ; |
709 | |
710 | state->TunerRegs[101].Reg_Num = 167 ; |
711 | state->TunerRegs[101].Reg_Val = 0x1B ; |
712 | |
713 | state->TunerRegs[102].Reg_Num = 168 ; |
714 | state->TunerRegs[102].Reg_Val = 0xF2 ; |
715 | |
716 | state->TunerRegs[103].Reg_Num = 195 ; |
717 | state->TunerRegs[103].Reg_Val = 0x00 ; |
718 | |
719 | return 0 ; |
720 | } |
721 | |
722 | static u16 MXL5005_ControlInit(struct dvb_frontend *fe) |
723 | { |
724 | struct mxl5005s_state *state = fe->tuner_priv; |
725 | state->Init_Ctrl_Num = INITCTRL_NUM; |
726 | |
727 | state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; |
728 | state->Init_Ctrl[0].size = 1 ; |
729 | state->Init_Ctrl[0].addr[0] = 73; |
730 | state->Init_Ctrl[0].bit[0] = 7; |
731 | state->Init_Ctrl[0].val[0] = 0; |
732 | |
733 | state->Init_Ctrl[1].Ctrl_Num = BB_MODE ; |
734 | state->Init_Ctrl[1].size = 1 ; |
735 | state->Init_Ctrl[1].addr[0] = 53; |
736 | state->Init_Ctrl[1].bit[0] = 2; |
737 | state->Init_Ctrl[1].val[0] = 1; |
738 | |
739 | state->Init_Ctrl[2].Ctrl_Num = BB_BUF ; |
740 | state->Init_Ctrl[2].size = 2 ; |
741 | state->Init_Ctrl[2].addr[0] = 53; |
742 | state->Init_Ctrl[2].bit[0] = 1; |
743 | state->Init_Ctrl[2].val[0] = 0; |
744 | state->Init_Ctrl[2].addr[1] = 57; |
745 | state->Init_Ctrl[2].bit[1] = 0; |
746 | state->Init_Ctrl[2].val[1] = 1; |
747 | |
748 | state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; |
749 | state->Init_Ctrl[3].size = 1 ; |
750 | state->Init_Ctrl[3].addr[0] = 53; |
751 | state->Init_Ctrl[3].bit[0] = 0; |
752 | state->Init_Ctrl[3].val[0] = 0; |
753 | |
754 | state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; |
755 | state->Init_Ctrl[4].size = 3 ; |
756 | state->Init_Ctrl[4].addr[0] = 53; |
757 | state->Init_Ctrl[4].bit[0] = 5; |
758 | state->Init_Ctrl[4].val[0] = 0; |
759 | state->Init_Ctrl[4].addr[1] = 53; |
760 | state->Init_Ctrl[4].bit[1] = 6; |
761 | state->Init_Ctrl[4].val[1] = 0; |
762 | state->Init_Ctrl[4].addr[2] = 53; |
763 | state->Init_Ctrl[4].bit[2] = 7; |
764 | state->Init_Ctrl[4].val[2] = 1; |
765 | |
766 | state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; |
767 | state->Init_Ctrl[5].size = 1 ; |
768 | state->Init_Ctrl[5].addr[0] = 59; |
769 | state->Init_Ctrl[5].bit[0] = 0; |
770 | state->Init_Ctrl[5].val[0] = 0; |
771 | |
772 | state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; |
773 | state->Init_Ctrl[6].size = 2 ; |
774 | state->Init_Ctrl[6].addr[0] = 53; |
775 | state->Init_Ctrl[6].bit[0] = 3; |
776 | state->Init_Ctrl[6].val[0] = 0; |
777 | state->Init_Ctrl[6].addr[1] = 53; |
778 | state->Init_Ctrl[6].bit[1] = 4; |
779 | state->Init_Ctrl[6].val[1] = 1; |
780 | |
781 | state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; |
782 | state->Init_Ctrl[7].size = 4 ; |
783 | state->Init_Ctrl[7].addr[0] = 22; |
784 | state->Init_Ctrl[7].bit[0] = 4; |
785 | state->Init_Ctrl[7].val[0] = 0; |
786 | state->Init_Ctrl[7].addr[1] = 22; |
787 | state->Init_Ctrl[7].bit[1] = 5; |
788 | state->Init_Ctrl[7].val[1] = 1; |
789 | state->Init_Ctrl[7].addr[2] = 22; |
790 | state->Init_Ctrl[7].bit[2] = 6; |
791 | state->Init_Ctrl[7].val[2] = 1; |
792 | state->Init_Ctrl[7].addr[3] = 22; |
793 | state->Init_Ctrl[7].bit[3] = 7; |
794 | state->Init_Ctrl[7].val[3] = 0; |
795 | |
796 | state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; |
797 | state->Init_Ctrl[8].size = 1 ; |
798 | state->Init_Ctrl[8].addr[0] = 22; |
799 | state->Init_Ctrl[8].bit[0] = 2; |
800 | state->Init_Ctrl[8].val[0] = 0; |
801 | |
802 | state->Init_Ctrl[9].Ctrl_Num = AGC_IF ; |
803 | state->Init_Ctrl[9].size = 4 ; |
804 | state->Init_Ctrl[9].addr[0] = 76; |
805 | state->Init_Ctrl[9].bit[0] = 0; |
806 | state->Init_Ctrl[9].val[0] = 1; |
807 | state->Init_Ctrl[9].addr[1] = 76; |
808 | state->Init_Ctrl[9].bit[1] = 1; |
809 | state->Init_Ctrl[9].val[1] = 1; |
810 | state->Init_Ctrl[9].addr[2] = 76; |
811 | state->Init_Ctrl[9].bit[2] = 2; |
812 | state->Init_Ctrl[9].val[2] = 0; |
813 | state->Init_Ctrl[9].addr[3] = 76; |
814 | state->Init_Ctrl[9].bit[3] = 3; |
815 | state->Init_Ctrl[9].val[3] = 1; |
816 | |
817 | state->Init_Ctrl[10].Ctrl_Num = AGC_RF ; |
818 | state->Init_Ctrl[10].size = 4 ; |
819 | state->Init_Ctrl[10].addr[0] = 76; |
820 | state->Init_Ctrl[10].bit[0] = 4; |
821 | state->Init_Ctrl[10].val[0] = 1; |
822 | state->Init_Ctrl[10].addr[1] = 76; |
823 | state->Init_Ctrl[10].bit[1] = 5; |
824 | state->Init_Ctrl[10].val[1] = 1; |
825 | state->Init_Ctrl[10].addr[2] = 76; |
826 | state->Init_Ctrl[10].bit[2] = 6; |
827 | state->Init_Ctrl[10].val[2] = 0; |
828 | state->Init_Ctrl[10].addr[3] = 76; |
829 | state->Init_Ctrl[10].bit[3] = 7; |
830 | state->Init_Ctrl[10].val[3] = 1; |
831 | |
832 | state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; |
833 | state->Init_Ctrl[11].size = 5 ; |
834 | state->Init_Ctrl[11].addr[0] = 43; |
835 | state->Init_Ctrl[11].bit[0] = 3; |
836 | state->Init_Ctrl[11].val[0] = 0; |
837 | state->Init_Ctrl[11].addr[1] = 43; |
838 | state->Init_Ctrl[11].bit[1] = 4; |
839 | state->Init_Ctrl[11].val[1] = 0; |
840 | state->Init_Ctrl[11].addr[2] = 43; |
841 | state->Init_Ctrl[11].bit[2] = 5; |
842 | state->Init_Ctrl[11].val[2] = 0; |
843 | state->Init_Ctrl[11].addr[3] = 43; |
844 | state->Init_Ctrl[11].bit[3] = 6; |
845 | state->Init_Ctrl[11].val[3] = 1; |
846 | state->Init_Ctrl[11].addr[4] = 43; |
847 | state->Init_Ctrl[11].bit[4] = 7; |
848 | state->Init_Ctrl[11].val[4] = 0; |
849 | |
850 | state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; |
851 | state->Init_Ctrl[12].size = 6 ; |
852 | state->Init_Ctrl[12].addr[0] = 44; |
853 | state->Init_Ctrl[12].bit[0] = 2; |
854 | state->Init_Ctrl[12].val[0] = 0; |
855 | state->Init_Ctrl[12].addr[1] = 44; |
856 | state->Init_Ctrl[12].bit[1] = 3; |
857 | state->Init_Ctrl[12].val[1] = 0; |
858 | state->Init_Ctrl[12].addr[2] = 44; |
859 | state->Init_Ctrl[12].bit[2] = 4; |
860 | state->Init_Ctrl[12].val[2] = 0; |
861 | state->Init_Ctrl[12].addr[3] = 44; |
862 | state->Init_Ctrl[12].bit[3] = 5; |
863 | state->Init_Ctrl[12].val[3] = 1; |
864 | state->Init_Ctrl[12].addr[4] = 44; |
865 | state->Init_Ctrl[12].bit[4] = 6; |
866 | state->Init_Ctrl[12].val[4] = 0; |
867 | state->Init_Ctrl[12].addr[5] = 44; |
868 | state->Init_Ctrl[12].bit[5] = 7; |
869 | state->Init_Ctrl[12].val[5] = 0; |
870 | |
871 | state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; |
872 | state->Init_Ctrl[13].size = 7 ; |
873 | state->Init_Ctrl[13].addr[0] = 11; |
874 | state->Init_Ctrl[13].bit[0] = 0; |
875 | state->Init_Ctrl[13].val[0] = 1; |
876 | state->Init_Ctrl[13].addr[1] = 11; |
877 | state->Init_Ctrl[13].bit[1] = 1; |
878 | state->Init_Ctrl[13].val[1] = 0; |
879 | state->Init_Ctrl[13].addr[2] = 11; |
880 | state->Init_Ctrl[13].bit[2] = 2; |
881 | state->Init_Ctrl[13].val[2] = 0; |
882 | state->Init_Ctrl[13].addr[3] = 11; |
883 | state->Init_Ctrl[13].bit[3] = 3; |
884 | state->Init_Ctrl[13].val[3] = 1; |
885 | state->Init_Ctrl[13].addr[4] = 11; |
886 | state->Init_Ctrl[13].bit[4] = 4; |
887 | state->Init_Ctrl[13].val[4] = 1; |
888 | state->Init_Ctrl[13].addr[5] = 11; |
889 | state->Init_Ctrl[13].bit[5] = 5; |
890 | state->Init_Ctrl[13].val[5] = 0; |
891 | state->Init_Ctrl[13].addr[6] = 11; |
892 | state->Init_Ctrl[13].bit[6] = 6; |
893 | state->Init_Ctrl[13].val[6] = 0; |
894 | |
895 | state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; |
896 | state->Init_Ctrl[14].size = 16 ; |
897 | state->Init_Ctrl[14].addr[0] = 13; |
898 | state->Init_Ctrl[14].bit[0] = 0; |
899 | state->Init_Ctrl[14].val[0] = 0; |
900 | state->Init_Ctrl[14].addr[1] = 13; |
901 | state->Init_Ctrl[14].bit[1] = 1; |
902 | state->Init_Ctrl[14].val[1] = 0; |
903 | state->Init_Ctrl[14].addr[2] = 13; |
904 | state->Init_Ctrl[14].bit[2] = 2; |
905 | state->Init_Ctrl[14].val[2] = 0; |
906 | state->Init_Ctrl[14].addr[3] = 13; |
907 | state->Init_Ctrl[14].bit[3] = 3; |
908 | state->Init_Ctrl[14].val[3] = 0; |
909 | state->Init_Ctrl[14].addr[4] = 13; |
910 | state->Init_Ctrl[14].bit[4] = 4; |
911 | state->Init_Ctrl[14].val[4] = 0; |
912 | state->Init_Ctrl[14].addr[5] = 13; |
913 | state->Init_Ctrl[14].bit[5] = 5; |
914 | state->Init_Ctrl[14].val[5] = 0; |
915 | state->Init_Ctrl[14].addr[6] = 13; |
916 | state->Init_Ctrl[14].bit[6] = 6; |
917 | state->Init_Ctrl[14].val[6] = 0; |
918 | state->Init_Ctrl[14].addr[7] = 13; |
919 | state->Init_Ctrl[14].bit[7] = 7; |
920 | state->Init_Ctrl[14].val[7] = 0; |
921 | state->Init_Ctrl[14].addr[8] = 12; |
922 | state->Init_Ctrl[14].bit[8] = 0; |
923 | state->Init_Ctrl[14].val[8] = 0; |
924 | state->Init_Ctrl[14].addr[9] = 12; |
925 | state->Init_Ctrl[14].bit[9] = 1; |
926 | state->Init_Ctrl[14].val[9] = 0; |
927 | state->Init_Ctrl[14].addr[10] = 12; |
928 | state->Init_Ctrl[14].bit[10] = 2; |
929 | state->Init_Ctrl[14].val[10] = 0; |
930 | state->Init_Ctrl[14].addr[11] = 12; |
931 | state->Init_Ctrl[14].bit[11] = 3; |
932 | state->Init_Ctrl[14].val[11] = 0; |
933 | state->Init_Ctrl[14].addr[12] = 12; |
934 | state->Init_Ctrl[14].bit[12] = 4; |
935 | state->Init_Ctrl[14].val[12] = 0; |
936 | state->Init_Ctrl[14].addr[13] = 12; |
937 | state->Init_Ctrl[14].bit[13] = 5; |
938 | state->Init_Ctrl[14].val[13] = 1; |
939 | state->Init_Ctrl[14].addr[14] = 12; |
940 | state->Init_Ctrl[14].bit[14] = 6; |
941 | state->Init_Ctrl[14].val[14] = 1; |
942 | state->Init_Ctrl[14].addr[15] = 12; |
943 | state->Init_Ctrl[14].bit[15] = 7; |
944 | state->Init_Ctrl[14].val[15] = 0; |
945 | |
946 | state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; |
947 | state->Init_Ctrl[15].size = 3 ; |
948 | state->Init_Ctrl[15].addr[0] = 147; |
949 | state->Init_Ctrl[15].bit[0] = 2; |
950 | state->Init_Ctrl[15].val[0] = 0; |
951 | state->Init_Ctrl[15].addr[1] = 147; |
952 | state->Init_Ctrl[15].bit[1] = 3; |
953 | state->Init_Ctrl[15].val[1] = 1; |
954 | state->Init_Ctrl[15].addr[2] = 147; |
955 | state->Init_Ctrl[15].bit[2] = 4; |
956 | state->Init_Ctrl[15].val[2] = 1; |
957 | |
958 | state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; |
959 | state->Init_Ctrl[16].size = 2 ; |
960 | state->Init_Ctrl[16].addr[0] = 147; |
961 | state->Init_Ctrl[16].bit[0] = 0; |
962 | state->Init_Ctrl[16].val[0] = 0; |
963 | state->Init_Ctrl[16].addr[1] = 147; |
964 | state->Init_Ctrl[16].bit[1] = 1; |
965 | state->Init_Ctrl[16].val[1] = 1; |
966 | |
967 | state->Init_Ctrl[17].Ctrl_Num = EN_AAF ; |
968 | state->Init_Ctrl[17].size = 1 ; |
969 | state->Init_Ctrl[17].addr[0] = 147; |
970 | state->Init_Ctrl[17].bit[0] = 7; |
971 | state->Init_Ctrl[17].val[0] = 0; |
972 | |
973 | state->Init_Ctrl[18].Ctrl_Num = EN_3P ; |
974 | state->Init_Ctrl[18].size = 1 ; |
975 | state->Init_Ctrl[18].addr[0] = 147; |
976 | state->Init_Ctrl[18].bit[0] = 6; |
977 | state->Init_Ctrl[18].val[0] = 0; |
978 | |
979 | state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; |
980 | state->Init_Ctrl[19].size = 1 ; |
981 | state->Init_Ctrl[19].addr[0] = 156; |
982 | state->Init_Ctrl[19].bit[0] = 0; |
983 | state->Init_Ctrl[19].val[0] = 0; |
984 | |
985 | state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; |
986 | state->Init_Ctrl[20].size = 1 ; |
987 | state->Init_Ctrl[20].addr[0] = 147; |
988 | state->Init_Ctrl[20].bit[0] = 5; |
989 | state->Init_Ctrl[20].val[0] = 0; |
990 | |
991 | state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; |
992 | state->Init_Ctrl[21].size = 1 ; |
993 | state->Init_Ctrl[21].addr[0] = 137; |
994 | state->Init_Ctrl[21].bit[0] = 4; |
995 | state->Init_Ctrl[21].val[0] = 0; |
996 | |
997 | state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; |
998 | state->Init_Ctrl[22].size = 1 ; |
999 | state->Init_Ctrl[22].addr[0] = 137; |
1000 | state->Init_Ctrl[22].bit[0] = 7; |
1001 | state->Init_Ctrl[22].val[0] = 0; |
1002 | |
1003 | state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; |
1004 | state->Init_Ctrl[23].size = 1 ; |
1005 | state->Init_Ctrl[23].addr[0] = 91; |
1006 | state->Init_Ctrl[23].bit[0] = 5; |
1007 | state->Init_Ctrl[23].val[0] = 1; |
1008 | |
1009 | state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; |
1010 | state->Init_Ctrl[24].size = 1 ; |
1011 | state->Init_Ctrl[24].addr[0] = 43; |
1012 | state->Init_Ctrl[24].bit[0] = 0; |
1013 | state->Init_Ctrl[24].val[0] = 1; |
1014 | |
1015 | state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; |
1016 | state->Init_Ctrl[25].size = 2 ; |
1017 | state->Init_Ctrl[25].addr[0] = 22; |
1018 | state->Init_Ctrl[25].bit[0] = 0; |
1019 | state->Init_Ctrl[25].val[0] = 1; |
1020 | state->Init_Ctrl[25].addr[1] = 22; |
1021 | state->Init_Ctrl[25].bit[1] = 1; |
1022 | state->Init_Ctrl[25].val[1] = 1; |
1023 | |
1024 | state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; |
1025 | state->Init_Ctrl[26].size = 1 ; |
1026 | state->Init_Ctrl[26].addr[0] = 134; |
1027 | state->Init_Ctrl[26].bit[0] = 2; |
1028 | state->Init_Ctrl[26].val[0] = 0; |
1029 | |
1030 | state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; |
1031 | state->Init_Ctrl[27].size = 1 ; |
1032 | state->Init_Ctrl[27].addr[0] = 137; |
1033 | state->Init_Ctrl[27].bit[0] = 3; |
1034 | state->Init_Ctrl[27].val[0] = 0; |
1035 | |
1036 | state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; |
1037 | state->Init_Ctrl[28].size = 1 ; |
1038 | state->Init_Ctrl[28].addr[0] = 77; |
1039 | state->Init_Ctrl[28].bit[0] = 7; |
1040 | state->Init_Ctrl[28].val[0] = 0; |
1041 | |
1042 | state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; |
1043 | state->Init_Ctrl[29].size = 1 ; |
1044 | state->Init_Ctrl[29].addr[0] = 166; |
1045 | state->Init_Ctrl[29].bit[0] = 7; |
1046 | state->Init_Ctrl[29].val[0] = 1; |
1047 | |
1048 | state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; |
1049 | state->Init_Ctrl[30].size = 3 ; |
1050 | state->Init_Ctrl[30].addr[0] = 166; |
1051 | state->Init_Ctrl[30].bit[0] = 0; |
1052 | state->Init_Ctrl[30].val[0] = 0; |
1053 | state->Init_Ctrl[30].addr[1] = 166; |
1054 | state->Init_Ctrl[30].bit[1] = 1; |
1055 | state->Init_Ctrl[30].val[1] = 1; |
1056 | state->Init_Ctrl[30].addr[2] = 166; |
1057 | state->Init_Ctrl[30].bit[2] = 2; |
1058 | state->Init_Ctrl[30].val[2] = 1; |
1059 | |
1060 | state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; |
1061 | state->Init_Ctrl[31].size = 3 ; |
1062 | state->Init_Ctrl[31].addr[0] = 166; |
1063 | state->Init_Ctrl[31].bit[0] = 3; |
1064 | state->Init_Ctrl[31].val[0] = 1; |
1065 | state->Init_Ctrl[31].addr[1] = 166; |
1066 | state->Init_Ctrl[31].bit[1] = 4; |
1067 | state->Init_Ctrl[31].val[1] = 0; |
1068 | state->Init_Ctrl[31].addr[2] = 166; |
1069 | state->Init_Ctrl[31].bit[2] = 5; |
1070 | state->Init_Ctrl[31].val[2] = 1; |
1071 | |
1072 | state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; |
1073 | state->Init_Ctrl[32].size = 3 ; |
1074 | state->Init_Ctrl[32].addr[0] = 167; |
1075 | state->Init_Ctrl[32].bit[0] = 0; |
1076 | state->Init_Ctrl[32].val[0] = 1; |
1077 | state->Init_Ctrl[32].addr[1] = 167; |
1078 | state->Init_Ctrl[32].bit[1] = 1; |
1079 | state->Init_Ctrl[32].val[1] = 1; |
1080 | state->Init_Ctrl[32].addr[2] = 167; |
1081 | state->Init_Ctrl[32].bit[2] = 2; |
1082 | state->Init_Ctrl[32].val[2] = 0; |
1083 | |
1084 | state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; |
1085 | state->Init_Ctrl[33].size = 4 ; |
1086 | state->Init_Ctrl[33].addr[0] = 168; |
1087 | state->Init_Ctrl[33].bit[0] = 0; |
1088 | state->Init_Ctrl[33].val[0] = 0; |
1089 | state->Init_Ctrl[33].addr[1] = 168; |
1090 | state->Init_Ctrl[33].bit[1] = 1; |
1091 | state->Init_Ctrl[33].val[1] = 1; |
1092 | state->Init_Ctrl[33].addr[2] = 168; |
1093 | state->Init_Ctrl[33].bit[2] = 2; |
1094 | state->Init_Ctrl[33].val[2] = 0; |
1095 | state->Init_Ctrl[33].addr[3] = 168; |
1096 | state->Init_Ctrl[33].bit[3] = 3; |
1097 | state->Init_Ctrl[33].val[3] = 0; |
1098 | |
1099 | state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; |
1100 | state->Init_Ctrl[34].size = 4 ; |
1101 | state->Init_Ctrl[34].addr[0] = 168; |
1102 | state->Init_Ctrl[34].bit[0] = 4; |
1103 | state->Init_Ctrl[34].val[0] = 1; |
1104 | state->Init_Ctrl[34].addr[1] = 168; |
1105 | state->Init_Ctrl[34].bit[1] = 5; |
1106 | state->Init_Ctrl[34].val[1] = 1; |
1107 | state->Init_Ctrl[34].addr[2] = 168; |
1108 | state->Init_Ctrl[34].bit[2] = 6; |
1109 | state->Init_Ctrl[34].val[2] = 1; |
1110 | state->Init_Ctrl[34].addr[3] = 168; |
1111 | state->Init_Ctrl[34].bit[3] = 7; |
1112 | state->Init_Ctrl[34].val[3] = 1; |
1113 | |
1114 | state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; |
1115 | state->Init_Ctrl[35].size = 1 ; |
1116 | state->Init_Ctrl[35].addr[0] = 135; |
1117 | state->Init_Ctrl[35].bit[0] = 0; |
1118 | state->Init_Ctrl[35].val[0] = 0; |
1119 | |
1120 | state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; |
1121 | state->Init_Ctrl[36].size = 1 ; |
1122 | state->Init_Ctrl[36].addr[0] = 56; |
1123 | state->Init_Ctrl[36].bit[0] = 3; |
1124 | state->Init_Ctrl[36].val[0] = 0; |
1125 | |
1126 | state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; |
1127 | state->Init_Ctrl[37].size = 7 ; |
1128 | state->Init_Ctrl[37].addr[0] = 59; |
1129 | state->Init_Ctrl[37].bit[0] = 1; |
1130 | state->Init_Ctrl[37].val[0] = 0; |
1131 | state->Init_Ctrl[37].addr[1] = 59; |
1132 | state->Init_Ctrl[37].bit[1] = 2; |
1133 | state->Init_Ctrl[37].val[1] = 0; |
1134 | state->Init_Ctrl[37].addr[2] = 59; |
1135 | state->Init_Ctrl[37].bit[2] = 3; |
1136 | state->Init_Ctrl[37].val[2] = 0; |
1137 | state->Init_Ctrl[37].addr[3] = 59; |
1138 | state->Init_Ctrl[37].bit[3] = 4; |
1139 | state->Init_Ctrl[37].val[3] = 0; |
1140 | state->Init_Ctrl[37].addr[4] = 59; |
1141 | state->Init_Ctrl[37].bit[4] = 5; |
1142 | state->Init_Ctrl[37].val[4] = 0; |
1143 | state->Init_Ctrl[37].addr[5] = 59; |
1144 | state->Init_Ctrl[37].bit[5] = 6; |
1145 | state->Init_Ctrl[37].val[5] = 0; |
1146 | state->Init_Ctrl[37].addr[6] = 59; |
1147 | state->Init_Ctrl[37].bit[6] = 7; |
1148 | state->Init_Ctrl[37].val[6] = 0; |
1149 | |
1150 | state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; |
1151 | state->Init_Ctrl[38].size = 6 ; |
1152 | state->Init_Ctrl[38].addr[0] = 32; |
1153 | state->Init_Ctrl[38].bit[0] = 2; |
1154 | state->Init_Ctrl[38].val[0] = 0; |
1155 | state->Init_Ctrl[38].addr[1] = 32; |
1156 | state->Init_Ctrl[38].bit[1] = 3; |
1157 | state->Init_Ctrl[38].val[1] = 0; |
1158 | state->Init_Ctrl[38].addr[2] = 32; |
1159 | state->Init_Ctrl[38].bit[2] = 4; |
1160 | state->Init_Ctrl[38].val[2] = 0; |
1161 | state->Init_Ctrl[38].addr[3] = 32; |
1162 | state->Init_Ctrl[38].bit[3] = 5; |
1163 | state->Init_Ctrl[38].val[3] = 0; |
1164 | state->Init_Ctrl[38].addr[4] = 32; |
1165 | state->Init_Ctrl[38].bit[4] = 6; |
1166 | state->Init_Ctrl[38].val[4] = 1; |
1167 | state->Init_Ctrl[38].addr[5] = 32; |
1168 | state->Init_Ctrl[38].bit[5] = 7; |
1169 | state->Init_Ctrl[38].val[5] = 0; |
1170 | |
1171 | state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; |
1172 | state->Init_Ctrl[39].size = 1 ; |
1173 | state->Init_Ctrl[39].addr[0] = 25; |
1174 | state->Init_Ctrl[39].bit[0] = 3; |
1175 | state->Init_Ctrl[39].val[0] = 1; |
1176 | |
1177 | |
1178 | state->CH_Ctrl_Num = CHCTRL_NUM ; |
1179 | |
1180 | state->CH_Ctrl[0].Ctrl_Num = DN_POLY ; |
1181 | state->CH_Ctrl[0].size = 2 ; |
1182 | state->CH_Ctrl[0].addr[0] = 68; |
1183 | state->CH_Ctrl[0].bit[0] = 6; |
1184 | state->CH_Ctrl[0].val[0] = 1; |
1185 | state->CH_Ctrl[0].addr[1] = 68; |
1186 | state->CH_Ctrl[0].bit[1] = 7; |
1187 | state->CH_Ctrl[0].val[1] = 1; |
1188 | |
1189 | state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; |
1190 | state->CH_Ctrl[1].size = 2 ; |
1191 | state->CH_Ctrl[1].addr[0] = 70; |
1192 | state->CH_Ctrl[1].bit[0] = 6; |
1193 | state->CH_Ctrl[1].val[0] = 1; |
1194 | state->CH_Ctrl[1].addr[1] = 70; |
1195 | state->CH_Ctrl[1].bit[1] = 7; |
1196 | state->CH_Ctrl[1].val[1] = 0; |
1197 | |
1198 | state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; |
1199 | state->CH_Ctrl[2].size = 9 ; |
1200 | state->CH_Ctrl[2].addr[0] = 69; |
1201 | state->CH_Ctrl[2].bit[0] = 5; |
1202 | state->CH_Ctrl[2].val[0] = 0; |
1203 | state->CH_Ctrl[2].addr[1] = 69; |
1204 | state->CH_Ctrl[2].bit[1] = 6; |
1205 | state->CH_Ctrl[2].val[1] = 0; |
1206 | state->CH_Ctrl[2].addr[2] = 69; |
1207 | state->CH_Ctrl[2].bit[2] = 7; |
1208 | state->CH_Ctrl[2].val[2] = 0; |
1209 | state->CH_Ctrl[2].addr[3] = 68; |
1210 | state->CH_Ctrl[2].bit[3] = 0; |
1211 | state->CH_Ctrl[2].val[3] = 0; |
1212 | state->CH_Ctrl[2].addr[4] = 68; |
1213 | state->CH_Ctrl[2].bit[4] = 1; |
1214 | state->CH_Ctrl[2].val[4] = 0; |
1215 | state->CH_Ctrl[2].addr[5] = 68; |
1216 | state->CH_Ctrl[2].bit[5] = 2; |
1217 | state->CH_Ctrl[2].val[5] = 0; |
1218 | state->CH_Ctrl[2].addr[6] = 68; |
1219 | state->CH_Ctrl[2].bit[6] = 3; |
1220 | state->CH_Ctrl[2].val[6] = 0; |
1221 | state->CH_Ctrl[2].addr[7] = 68; |
1222 | state->CH_Ctrl[2].bit[7] = 4; |
1223 | state->CH_Ctrl[2].val[7] = 0; |
1224 | state->CH_Ctrl[2].addr[8] = 68; |
1225 | state->CH_Ctrl[2].bit[8] = 5; |
1226 | state->CH_Ctrl[2].val[8] = 0; |
1227 | |
1228 | state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; |
1229 | state->CH_Ctrl[3].size = 1 ; |
1230 | state->CH_Ctrl[3].addr[0] = 70; |
1231 | state->CH_Ctrl[3].bit[0] = 5; |
1232 | state->CH_Ctrl[3].val[0] = 0; |
1233 | |
1234 | state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; |
1235 | state->CH_Ctrl[4].size = 3 ; |
1236 | state->CH_Ctrl[4].addr[0] = 73; |
1237 | state->CH_Ctrl[4].bit[0] = 4; |
1238 | state->CH_Ctrl[4].val[0] = 0; |
1239 | state->CH_Ctrl[4].addr[1] = 73; |
1240 | state->CH_Ctrl[4].bit[1] = 5; |
1241 | state->CH_Ctrl[4].val[1] = 1; |
1242 | state->CH_Ctrl[4].addr[2] = 73; |
1243 | state->CH_Ctrl[4].bit[2] = 6; |
1244 | state->CH_Ctrl[4].val[2] = 0; |
1245 | |
1246 | state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; |
1247 | state->CH_Ctrl[5].size = 4 ; |
1248 | state->CH_Ctrl[5].addr[0] = 70; |
1249 | state->CH_Ctrl[5].bit[0] = 0; |
1250 | state->CH_Ctrl[5].val[0] = 0; |
1251 | state->CH_Ctrl[5].addr[1] = 70; |
1252 | state->CH_Ctrl[5].bit[1] = 1; |
1253 | state->CH_Ctrl[5].val[1] = 0; |
1254 | state->CH_Ctrl[5].addr[2] = 70; |
1255 | state->CH_Ctrl[5].bit[2] = 2; |
1256 | state->CH_Ctrl[5].val[2] = 0; |
1257 | state->CH_Ctrl[5].addr[3] = 70; |
1258 | state->CH_Ctrl[5].bit[3] = 3; |
1259 | state->CH_Ctrl[5].val[3] = 0; |
1260 | |
1261 | state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; |
1262 | state->CH_Ctrl[6].size = 1 ; |
1263 | state->CH_Ctrl[6].addr[0] = 70; |
1264 | state->CH_Ctrl[6].bit[0] = 4; |
1265 | state->CH_Ctrl[6].val[0] = 1; |
1266 | |
1267 | state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; |
1268 | state->CH_Ctrl[7].size = 1 ; |
1269 | state->CH_Ctrl[7].addr[0] = 111; |
1270 | state->CH_Ctrl[7].bit[0] = 4; |
1271 | state->CH_Ctrl[7].val[0] = 0; |
1272 | |
1273 | state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; |
1274 | state->CH_Ctrl[8].size = 1 ; |
1275 | state->CH_Ctrl[8].addr[0] = 111; |
1276 | state->CH_Ctrl[8].bit[0] = 7; |
1277 | state->CH_Ctrl[8].val[0] = 1; |
1278 | |
1279 | state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; |
1280 | state->CH_Ctrl[9].size = 1 ; |
1281 | state->CH_Ctrl[9].addr[0] = 111; |
1282 | state->CH_Ctrl[9].bit[0] = 6; |
1283 | state->CH_Ctrl[9].val[0] = 1; |
1284 | |
1285 | state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; |
1286 | state->CH_Ctrl[10].size = 1 ; |
1287 | state->CH_Ctrl[10].addr[0] = 111; |
1288 | state->CH_Ctrl[10].bit[0] = 5; |
1289 | state->CH_Ctrl[10].val[0] = 0; |
1290 | |
1291 | state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; |
1292 | state->CH_Ctrl[11].size = 2 ; |
1293 | state->CH_Ctrl[11].addr[0] = 110; |
1294 | state->CH_Ctrl[11].bit[0] = 0; |
1295 | state->CH_Ctrl[11].val[0] = 1; |
1296 | state->CH_Ctrl[11].addr[1] = 110; |
1297 | state->CH_Ctrl[11].bit[1] = 1; |
1298 | state->CH_Ctrl[11].val[1] = 0; |
1299 | |
1300 | state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; |
1301 | state->CH_Ctrl[12].size = 3 ; |
1302 | state->CH_Ctrl[12].addr[0] = 69; |
1303 | state->CH_Ctrl[12].bit[0] = 2; |
1304 | state->CH_Ctrl[12].val[0] = 0; |
1305 | state->CH_Ctrl[12].addr[1] = 69; |
1306 | state->CH_Ctrl[12].bit[1] = 3; |
1307 | state->CH_Ctrl[12].val[1] = 0; |
1308 | state->CH_Ctrl[12].addr[2] = 69; |
1309 | state->CH_Ctrl[12].bit[2] = 4; |
1310 | state->CH_Ctrl[12].val[2] = 0; |
1311 | |
1312 | state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; |
1313 | state->CH_Ctrl[13].size = 6 ; |
1314 | state->CH_Ctrl[13].addr[0] = 110; |
1315 | state->CH_Ctrl[13].bit[0] = 2; |
1316 | state->CH_Ctrl[13].val[0] = 0; |
1317 | state->CH_Ctrl[13].addr[1] = 110; |
1318 | state->CH_Ctrl[13].bit[1] = 3; |
1319 | state->CH_Ctrl[13].val[1] = 0; |
1320 | state->CH_Ctrl[13].addr[2] = 110; |
1321 | state->CH_Ctrl[13].bit[2] = 4; |
1322 | state->CH_Ctrl[13].val[2] = 0; |
1323 | state->CH_Ctrl[13].addr[3] = 110; |
1324 | state->CH_Ctrl[13].bit[3] = 5; |
1325 | state->CH_Ctrl[13].val[3] = 0; |
1326 | state->CH_Ctrl[13].addr[4] = 110; |
1327 | state->CH_Ctrl[13].bit[4] = 6; |
1328 | state->CH_Ctrl[13].val[4] = 0; |
1329 | state->CH_Ctrl[13].addr[5] = 110; |
1330 | state->CH_Ctrl[13].bit[5] = 7; |
1331 | state->CH_Ctrl[13].val[5] = 1; |
1332 | |
1333 | state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; |
1334 | state->CH_Ctrl[14].size = 7 ; |
1335 | state->CH_Ctrl[14].addr[0] = 14; |
1336 | state->CH_Ctrl[14].bit[0] = 0; |
1337 | state->CH_Ctrl[14].val[0] = 0; |
1338 | state->CH_Ctrl[14].addr[1] = 14; |
1339 | state->CH_Ctrl[14].bit[1] = 1; |
1340 | state->CH_Ctrl[14].val[1] = 0; |
1341 | state->CH_Ctrl[14].addr[2] = 14; |
1342 | state->CH_Ctrl[14].bit[2] = 2; |
1343 | state->CH_Ctrl[14].val[2] = 0; |
1344 | state->CH_Ctrl[14].addr[3] = 14; |
1345 | state->CH_Ctrl[14].bit[3] = 3; |
1346 | state->CH_Ctrl[14].val[3] = 0; |
1347 | state->CH_Ctrl[14].addr[4] = 14; |
1348 | state->CH_Ctrl[14].bit[4] = 4; |
1349 | state->CH_Ctrl[14].val[4] = 0; |
1350 | state->CH_Ctrl[14].addr[5] = 14; |
1351 | state->CH_Ctrl[14].bit[5] = 5; |
1352 | state->CH_Ctrl[14].val[5] = 0; |
1353 | state->CH_Ctrl[14].addr[6] = 14; |
1354 | state->CH_Ctrl[14].bit[6] = 6; |
1355 | state->CH_Ctrl[14].val[6] = 0; |
1356 | |
1357 | state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; |
1358 | state->CH_Ctrl[15].size = 18 ; |
1359 | state->CH_Ctrl[15].addr[0] = 17; |
1360 | state->CH_Ctrl[15].bit[0] = 6; |
1361 | state->CH_Ctrl[15].val[0] = 0; |
1362 | state->CH_Ctrl[15].addr[1] = 17; |
1363 | state->CH_Ctrl[15].bit[1] = 7; |
1364 | state->CH_Ctrl[15].val[1] = 0; |
1365 | state->CH_Ctrl[15].addr[2] = 16; |
1366 | state->CH_Ctrl[15].bit[2] = 0; |
1367 | state->CH_Ctrl[15].val[2] = 0; |
1368 | state->CH_Ctrl[15].addr[3] = 16; |
1369 | state->CH_Ctrl[15].bit[3] = 1; |
1370 | state->CH_Ctrl[15].val[3] = 0; |
1371 | state->CH_Ctrl[15].addr[4] = 16; |
1372 | state->CH_Ctrl[15].bit[4] = 2; |
1373 | state->CH_Ctrl[15].val[4] = 0; |
1374 | state->CH_Ctrl[15].addr[5] = 16; |
1375 | state->CH_Ctrl[15].bit[5] = 3; |
1376 | state->CH_Ctrl[15].val[5] = 0; |
1377 | state->CH_Ctrl[15].addr[6] = 16; |
1378 | state->CH_Ctrl[15].bit[6] = 4; |
1379 | state->CH_Ctrl[15].val[6] = 0; |
1380 | state->CH_Ctrl[15].addr[7] = 16; |
1381 | state->CH_Ctrl[15].bit[7] = 5; |
1382 | state->CH_Ctrl[15].val[7] = 0; |
1383 | state->CH_Ctrl[15].addr[8] = 16; |
1384 | state->CH_Ctrl[15].bit[8] = 6; |
1385 | state->CH_Ctrl[15].val[8] = 0; |
1386 | state->CH_Ctrl[15].addr[9] = 16; |
1387 | state->CH_Ctrl[15].bit[9] = 7; |
1388 | state->CH_Ctrl[15].val[9] = 0; |
1389 | state->CH_Ctrl[15].addr[10] = 15; |
1390 | state->CH_Ctrl[15].bit[10] = 0; |
1391 | state->CH_Ctrl[15].val[10] = 0; |
1392 | state->CH_Ctrl[15].addr[11] = 15; |
1393 | state->CH_Ctrl[15].bit[11] = 1; |
1394 | state->CH_Ctrl[15].val[11] = 0; |
1395 | state->CH_Ctrl[15].addr[12] = 15; |
1396 | state->CH_Ctrl[15].bit[12] = 2; |
1397 | state->CH_Ctrl[15].val[12] = 0; |
1398 | state->CH_Ctrl[15].addr[13] = 15; |
1399 | state->CH_Ctrl[15].bit[13] = 3; |
1400 | state->CH_Ctrl[15].val[13] = 0; |
1401 | state->CH_Ctrl[15].addr[14] = 15; |
1402 | state->CH_Ctrl[15].bit[14] = 4; |
1403 | state->CH_Ctrl[15].val[14] = 0; |
1404 | state->CH_Ctrl[15].addr[15] = 15; |
1405 | state->CH_Ctrl[15].bit[15] = 5; |
1406 | state->CH_Ctrl[15].val[15] = 0; |
1407 | state->CH_Ctrl[15].addr[16] = 15; |
1408 | state->CH_Ctrl[15].bit[16] = 6; |
1409 | state->CH_Ctrl[15].val[16] = 1; |
1410 | state->CH_Ctrl[15].addr[17] = 15; |
1411 | state->CH_Ctrl[15].bit[17] = 7; |
1412 | state->CH_Ctrl[15].val[17] = 1; |
1413 | |
1414 | state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; |
1415 | state->CH_Ctrl[16].size = 5 ; |
1416 | state->CH_Ctrl[16].addr[0] = 112; |
1417 | state->CH_Ctrl[16].bit[0] = 0; |
1418 | state->CH_Ctrl[16].val[0] = 0; |
1419 | state->CH_Ctrl[16].addr[1] = 112; |
1420 | state->CH_Ctrl[16].bit[1] = 1; |
1421 | state->CH_Ctrl[16].val[1] = 0; |
1422 | state->CH_Ctrl[16].addr[2] = 112; |
1423 | state->CH_Ctrl[16].bit[2] = 2; |
1424 | state->CH_Ctrl[16].val[2] = 0; |
1425 | state->CH_Ctrl[16].addr[3] = 112; |
1426 | state->CH_Ctrl[16].bit[3] = 3; |
1427 | state->CH_Ctrl[16].val[3] = 0; |
1428 | state->CH_Ctrl[16].addr[4] = 112; |
1429 | state->CH_Ctrl[16].bit[4] = 4; |
1430 | state->CH_Ctrl[16].val[4] = 1; |
1431 | |
1432 | state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; |
1433 | state->CH_Ctrl[17].size = 1 ; |
1434 | state->CH_Ctrl[17].addr[0] = 14; |
1435 | state->CH_Ctrl[17].bit[0] = 7; |
1436 | state->CH_Ctrl[17].val[0] = 0; |
1437 | |
1438 | state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; |
1439 | state->CH_Ctrl[18].size = 4 ; |
1440 | state->CH_Ctrl[18].addr[0] = 107; |
1441 | state->CH_Ctrl[18].bit[0] = 3; |
1442 | state->CH_Ctrl[18].val[0] = 0; |
1443 | state->CH_Ctrl[18].addr[1] = 107; |
1444 | state->CH_Ctrl[18].bit[1] = 4; |
1445 | state->CH_Ctrl[18].val[1] = 0; |
1446 | state->CH_Ctrl[18].addr[2] = 107; |
1447 | state->CH_Ctrl[18].bit[2] = 5; |
1448 | state->CH_Ctrl[18].val[2] = 0; |
1449 | state->CH_Ctrl[18].addr[3] = 107; |
1450 | state->CH_Ctrl[18].bit[3] = 6; |
1451 | state->CH_Ctrl[18].val[3] = 0; |
1452 | |
1453 | state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; |
1454 | state->CH_Ctrl[19].size = 3 ; |
1455 | state->CH_Ctrl[19].addr[0] = 107; |
1456 | state->CH_Ctrl[19].bit[0] = 7; |
1457 | state->CH_Ctrl[19].val[0] = 1; |
1458 | state->CH_Ctrl[19].addr[1] = 106; |
1459 | state->CH_Ctrl[19].bit[1] = 0; |
1460 | state->CH_Ctrl[19].val[1] = 1; |
1461 | state->CH_Ctrl[19].addr[2] = 106; |
1462 | state->CH_Ctrl[19].bit[2] = 1; |
1463 | state->CH_Ctrl[19].val[2] = 1; |
1464 | |
1465 | state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; |
1466 | state->CH_Ctrl[20].size = 11 ; |
1467 | state->CH_Ctrl[20].addr[0] = 109; |
1468 | state->CH_Ctrl[20].bit[0] = 2; |
1469 | state->CH_Ctrl[20].val[0] = 0; |
1470 | state->CH_Ctrl[20].addr[1] = 109; |
1471 | state->CH_Ctrl[20].bit[1] = 3; |
1472 | state->CH_Ctrl[20].val[1] = 0; |
1473 | state->CH_Ctrl[20].addr[2] = 109; |
1474 | state->CH_Ctrl[20].bit[2] = 4; |
1475 | state->CH_Ctrl[20].val[2] = 0; |
1476 | state->CH_Ctrl[20].addr[3] = 109; |
1477 | state->CH_Ctrl[20].bit[3] = 5; |
1478 | state->CH_Ctrl[20].val[3] = 0; |
1479 | state->CH_Ctrl[20].addr[4] = 109; |
1480 | state->CH_Ctrl[20].bit[4] = 6; |
1481 | state->CH_Ctrl[20].val[4] = 0; |
1482 | state->CH_Ctrl[20].addr[5] = 109; |
1483 | state->CH_Ctrl[20].bit[5] = 7; |
1484 | state->CH_Ctrl[20].val[5] = 0; |
1485 | state->CH_Ctrl[20].addr[6] = 108; |
1486 | state->CH_Ctrl[20].bit[6] = 0; |
1487 | state->CH_Ctrl[20].val[6] = 0; |
1488 | state->CH_Ctrl[20].addr[7] = 108; |
1489 | state->CH_Ctrl[20].bit[7] = 1; |
1490 | state->CH_Ctrl[20].val[7] = 0; |
1491 | state->CH_Ctrl[20].addr[8] = 108; |
1492 | state->CH_Ctrl[20].bit[8] = 2; |
1493 | state->CH_Ctrl[20].val[8] = 1; |
1494 | state->CH_Ctrl[20].addr[9] = 108; |
1495 | state->CH_Ctrl[20].bit[9] = 3; |
1496 | state->CH_Ctrl[20].val[9] = 1; |
1497 | state->CH_Ctrl[20].addr[10] = 108; |
1498 | state->CH_Ctrl[20].bit[10] = 4; |
1499 | state->CH_Ctrl[20].val[10] = 1; |
1500 | |
1501 | state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; |
1502 | state->CH_Ctrl[21].size = 6 ; |
1503 | state->CH_Ctrl[21].addr[0] = 106; |
1504 | state->CH_Ctrl[21].bit[0] = 2; |
1505 | state->CH_Ctrl[21].val[0] = 0; |
1506 | state->CH_Ctrl[21].addr[1] = 106; |
1507 | state->CH_Ctrl[21].bit[1] = 3; |
1508 | state->CH_Ctrl[21].val[1] = 0; |
1509 | state->CH_Ctrl[21].addr[2] = 106; |
1510 | state->CH_Ctrl[21].bit[2] = 4; |
1511 | state->CH_Ctrl[21].val[2] = 0; |
1512 | state->CH_Ctrl[21].addr[3] = 106; |
1513 | state->CH_Ctrl[21].bit[3] = 5; |
1514 | state->CH_Ctrl[21].val[3] = 0; |
1515 | state->CH_Ctrl[21].addr[4] = 106; |
1516 | state->CH_Ctrl[21].bit[4] = 6; |
1517 | state->CH_Ctrl[21].val[4] = 0; |
1518 | state->CH_Ctrl[21].addr[5] = 106; |
1519 | state->CH_Ctrl[21].bit[5] = 7; |
1520 | state->CH_Ctrl[21].val[5] = 1; |
1521 | |
1522 | state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; |
1523 | state->CH_Ctrl[22].size = 1 ; |
1524 | state->CH_Ctrl[22].addr[0] = 138; |
1525 | state->CH_Ctrl[22].bit[0] = 4; |
1526 | state->CH_Ctrl[22].val[0] = 1; |
1527 | |
1528 | state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; |
1529 | state->CH_Ctrl[23].size = 1 ; |
1530 | state->CH_Ctrl[23].addr[0] = 17; |
1531 | state->CH_Ctrl[23].bit[0] = 5; |
1532 | state->CH_Ctrl[23].val[0] = 0; |
1533 | |
1534 | state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; |
1535 | state->CH_Ctrl[24].size = 1 ; |
1536 | state->CH_Ctrl[24].addr[0] = 111; |
1537 | state->CH_Ctrl[24].bit[0] = 3; |
1538 | state->CH_Ctrl[24].val[0] = 0; |
1539 | |
1540 | state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; |
1541 | state->CH_Ctrl[25].size = 1 ; |
1542 | state->CH_Ctrl[25].addr[0] = 112; |
1543 | state->CH_Ctrl[25].bit[0] = 7; |
1544 | state->CH_Ctrl[25].val[0] = 0; |
1545 | |
1546 | state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; |
1547 | state->CH_Ctrl[26].size = 1 ; |
1548 | state->CH_Ctrl[26].addr[0] = 136; |
1549 | state->CH_Ctrl[26].bit[0] = 7; |
1550 | state->CH_Ctrl[26].val[0] = 0; |
1551 | |
1552 | state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; |
1553 | state->CH_Ctrl[27].size = 1 ; |
1554 | state->CH_Ctrl[27].addr[0] = 149; |
1555 | state->CH_Ctrl[27].bit[0] = 7; |
1556 | state->CH_Ctrl[27].val[0] = 0; |
1557 | |
1558 | state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; |
1559 | state->CH_Ctrl[28].size = 1 ; |
1560 | state->CH_Ctrl[28].addr[0] = 149; |
1561 | state->CH_Ctrl[28].bit[0] = 6; |
1562 | state->CH_Ctrl[28].val[0] = 0; |
1563 | |
1564 | state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; |
1565 | state->CH_Ctrl[29].size = 1 ; |
1566 | state->CH_Ctrl[29].addr[0] = 149; |
1567 | state->CH_Ctrl[29].bit[0] = 5; |
1568 | state->CH_Ctrl[29].val[0] = 1; |
1569 | |
1570 | state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; |
1571 | state->CH_Ctrl[30].size = 1 ; |
1572 | state->CH_Ctrl[30].addr[0] = 149; |
1573 | state->CH_Ctrl[30].bit[0] = 4; |
1574 | state->CH_Ctrl[30].val[0] = 1; |
1575 | |
1576 | state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; |
1577 | state->CH_Ctrl[31].size = 1 ; |
1578 | state->CH_Ctrl[31].addr[0] = 149; |
1579 | state->CH_Ctrl[31].bit[0] = 3; |
1580 | state->CH_Ctrl[31].val[0] = 0; |
1581 | |
1582 | state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; |
1583 | state->CH_Ctrl[32].size = 1 ; |
1584 | state->CH_Ctrl[32].addr[0] = 93; |
1585 | state->CH_Ctrl[32].bit[0] = 1; |
1586 | state->CH_Ctrl[32].val[0] = 0; |
1587 | |
1588 | state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; |
1589 | state->CH_Ctrl[33].size = 1 ; |
1590 | state->CH_Ctrl[33].addr[0] = 93; |
1591 | state->CH_Ctrl[33].bit[0] = 0; |
1592 | state->CH_Ctrl[33].val[0] = 0; |
1593 | |
1594 | state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; |
1595 | state->CH_Ctrl[34].size = 6 ; |
1596 | state->CH_Ctrl[34].addr[0] = 92; |
1597 | state->CH_Ctrl[34].bit[0] = 2; |
1598 | state->CH_Ctrl[34].val[0] = 0; |
1599 | state->CH_Ctrl[34].addr[1] = 92; |
1600 | state->CH_Ctrl[34].bit[1] = 3; |
1601 | state->CH_Ctrl[34].val[1] = 0; |
1602 | state->CH_Ctrl[34].addr[2] = 92; |
1603 | state->CH_Ctrl[34].bit[2] = 4; |
1604 | state->CH_Ctrl[34].val[2] = 0; |
1605 | state->CH_Ctrl[34].addr[3] = 92; |
1606 | state->CH_Ctrl[34].bit[3] = 5; |
1607 | state->CH_Ctrl[34].val[3] = 0; |
1608 | state->CH_Ctrl[34].addr[4] = 92; |
1609 | state->CH_Ctrl[34].bit[4] = 6; |
1610 | state->CH_Ctrl[34].val[4] = 0; |
1611 | state->CH_Ctrl[34].addr[5] = 92; |
1612 | state->CH_Ctrl[34].bit[5] = 7; |
1613 | state->CH_Ctrl[34].val[5] = 0; |
1614 | |
1615 | state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; |
1616 | state->CH_Ctrl[35].size = 6 ; |
1617 | state->CH_Ctrl[35].addr[0] = 93; |
1618 | state->CH_Ctrl[35].bit[0] = 2; |
1619 | state->CH_Ctrl[35].val[0] = 0; |
1620 | state->CH_Ctrl[35].addr[1] = 93; |
1621 | state->CH_Ctrl[35].bit[1] = 3; |
1622 | state->CH_Ctrl[35].val[1] = 0; |
1623 | state->CH_Ctrl[35].addr[2] = 93; |
1624 | state->CH_Ctrl[35].bit[2] = 4; |
1625 | state->CH_Ctrl[35].val[2] = 0; |
1626 | state->CH_Ctrl[35].addr[3] = 93; |
1627 | state->CH_Ctrl[35].bit[3] = 5; |
1628 | state->CH_Ctrl[35].val[3] = 0; |
1629 | state->CH_Ctrl[35].addr[4] = 93; |
1630 | state->CH_Ctrl[35].bit[4] = 6; |
1631 | state->CH_Ctrl[35].val[4] = 0; |
1632 | state->CH_Ctrl[35].addr[5] = 93; |
1633 | state->CH_Ctrl[35].bit[5] = 7; |
1634 | state->CH_Ctrl[35].val[5] = 0; |
1635 | |
1636 | #ifdef _MXL_PRODUCTION |
1637 | state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; |
1638 | state->CH_Ctrl[36].size = 1 ; |
1639 | state->CH_Ctrl[36].addr[0] = 109; |
1640 | state->CH_Ctrl[36].bit[0] = 1; |
1641 | state->CH_Ctrl[36].val[0] = 1; |
1642 | |
1643 | state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; |
1644 | state->CH_Ctrl[37].size = 2 ; |
1645 | state->CH_Ctrl[37].addr[0] = 112; |
1646 | state->CH_Ctrl[37].bit[0] = 5; |
1647 | state->CH_Ctrl[37].val[0] = 0; |
1648 | state->CH_Ctrl[37].addr[1] = 112; |
1649 | state->CH_Ctrl[37].bit[1] = 6; |
1650 | state->CH_Ctrl[37].val[1] = 0; |
1651 | |
1652 | state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; |
1653 | state->CH_Ctrl[38].size = 1 ; |
1654 | state->CH_Ctrl[38].addr[0] = 65; |
1655 | state->CH_Ctrl[38].bit[0] = 1; |
1656 | state->CH_Ctrl[38].val[0] = 0; |
1657 | #endif |
1658 | |
1659 | return 0 ; |
1660 | } |
1661 | |
1662 | static void InitTunerControls(struct dvb_frontend *fe) |
1663 | { |
1664 | MXL5005_RegisterInit(fe); |
1665 | MXL5005_ControlInit(fe); |
1666 | #ifdef _MXL_INTERNAL |
1667 | MXL5005_MXLControlInit(fe); |
1668 | #endif |
1669 | } |
1670 | |
1671 | static u16 MXL5005_TunerConfig(struct dvb_frontend *fe, |
1672 | u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ |
1673 | u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ |
1674 | u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ |
1675 | u32 IF_out, /* Desired IF Out Frequency */ |
1676 | u32 Fxtal, /* XTAL Frequency */ |
1677 | u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ |
1678 | u16 TOP, /* 0: Dual AGC; Value: take over point */ |
1679 | u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ |
1680 | u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */ |
1681 | u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ |
1682 | u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ |
1683 | u8 , /* 0: disable RSSI; 1: enable RSSI */ |
1684 | |
1685 | /* Modulation Type; */ |
1686 | /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ |
1687 | u8 Mod_Type, |
1688 | |
1689 | /* Tracking Filter */ |
1690 | /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ |
1691 | u8 TF_Type |
1692 | ) |
1693 | { |
1694 | struct mxl5005s_state *state = fe->tuner_priv; |
1695 | |
1696 | state->Mode = Mode; |
1697 | state->IF_Mode = IF_mode; |
1698 | state->Chan_Bandwidth = Bandwidth; |
1699 | state->IF_OUT = IF_out; |
1700 | state->Fxtal = Fxtal; |
1701 | state->AGC_Mode = AGC_Mode; |
1702 | state->TOP = TOP; |
1703 | state->IF_OUT_LOAD = IF_OUT_LOAD; |
1704 | state->CLOCK_OUT = CLOCK_OUT; |
1705 | state->DIV_OUT = DIV_OUT; |
1706 | state->CAPSELECT = CAPSELECT; |
1707 | state->EN_RSSI = EN_RSSI; |
1708 | state->Mod_Type = Mod_Type; |
1709 | state->TF_Type = TF_Type; |
1710 | |
1711 | /* Initialize all the controls and registers */ |
1712 | InitTunerControls(fe); |
1713 | |
1714 | /* Synthesizer LO frequency calculation */ |
1715 | MXL_SynthIFLO_Calc(fe); |
1716 | |
1717 | return 0; |
1718 | } |
1719 | |
1720 | static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) |
1721 | { |
1722 | struct mxl5005s_state *state = fe->tuner_priv; |
1723 | if (state->Mode == 1) /* Digital Mode */ |
1724 | state->IF_LO = state->IF_OUT; |
1725 | else /* Analog Mode */ { |
1726 | if (state->IF_Mode == 0) /* Analog Zero IF mode */ |
1727 | state->IF_LO = state->IF_OUT + 400000; |
1728 | else /* Analog Low IF mode */ |
1729 | state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; |
1730 | } |
1731 | } |
1732 | |
1733 | static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) |
1734 | { |
1735 | struct mxl5005s_state *state = fe->tuner_priv; |
1736 | |
1737 | if (state->Mode == 1) /* Digital Mode */ { |
1738 | /* remove 20.48MHz setting for 2.6.10 */ |
1739 | state->RF_LO = state->RF_IN; |
1740 | /* change for 2.6.6 */ |
1741 | state->TG_LO = state->RF_IN - 750000; |
1742 | } else /* Analog Mode */ { |
1743 | if (state->IF_Mode == 0) /* Analog Zero IF mode */ { |
1744 | state->RF_LO = state->RF_IN - 400000; |
1745 | state->TG_LO = state->RF_IN - 1750000; |
1746 | } else /* Analog Low IF mode */ { |
1747 | state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; |
1748 | state->TG_LO = state->RF_IN - |
1749 | state->Chan_Bandwidth + 500000; |
1750 | } |
1751 | } |
1752 | } |
1753 | |
1754 | static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) |
1755 | { |
1756 | u16 status = 0; |
1757 | |
1758 | status += MXL_ControlWrite(fe, ControlNum: OVERRIDE_1, value: 1); |
1759 | status += MXL_ControlWrite(fe, ControlNum: OVERRIDE_2, value: 1); |
1760 | status += MXL_ControlWrite(fe, ControlNum: OVERRIDE_3, value: 1); |
1761 | status += MXL_ControlWrite(fe, ControlNum: OVERRIDE_4, value: 1); |
1762 | |
1763 | return status; |
1764 | } |
1765 | |
1766 | static u16 MXL_BlockInit(struct dvb_frontend *fe) |
1767 | { |
1768 | struct mxl5005s_state *state = fe->tuner_priv; |
1769 | u16 status = 0; |
1770 | |
1771 | status += MXL_OverwriteICDefault(fe); |
1772 | |
1773 | /* Downconverter Control Dig Ana */ |
1774 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTN_AMP_CUT, value: state->Mode ? 1 : 0); |
1775 | |
1776 | /* Filter Control Dig Ana */ |
1777 | status += MXL_ControlWrite(fe, ControlNum: BB_MODE, value: state->Mode ? 0 : 1); |
1778 | status += MXL_ControlWrite(fe, ControlNum: BB_BUF, value: state->Mode ? 3 : 2); |
1779 | status += MXL_ControlWrite(fe, ControlNum: BB_BUF_OA, value: state->Mode ? 1 : 0); |
1780 | status += MXL_ControlWrite(fe, ControlNum: BB_IQSWAP, value: state->Mode ? 0 : 1); |
1781 | status += MXL_ControlWrite(fe, ControlNum: BB_INITSTATE_DLPF_TUNE, value: 0); |
1782 | |
1783 | /* Initialize Low-Pass Filter */ |
1784 | if (state->Mode) { /* Digital Mode */ |
1785 | switch (state->Chan_Bandwidth) { |
1786 | case 8000000: |
1787 | status += MXL_ControlWrite(fe, ControlNum: BB_DLPF_BANDSEL, value: 0); |
1788 | break; |
1789 | case 7000000: |
1790 | status += MXL_ControlWrite(fe, ControlNum: BB_DLPF_BANDSEL, value: 2); |
1791 | break; |
1792 | case 6000000: |
1793 | status += MXL_ControlWrite(fe, |
1794 | ControlNum: BB_DLPF_BANDSEL, value: 3); |
1795 | break; |
1796 | } |
1797 | } else { /* Analog Mode */ |
1798 | switch (state->Chan_Bandwidth) { |
1799 | case 8000000: /* Low Zero */ |
1800 | status += MXL_ControlWrite(fe, ControlNum: BB_ALPF_BANDSELECT, |
1801 | value: (state->IF_Mode ? 0 : 3)); |
1802 | break; |
1803 | case 7000000: |
1804 | status += MXL_ControlWrite(fe, ControlNum: BB_ALPF_BANDSELECT, |
1805 | value: (state->IF_Mode ? 1 : 4)); |
1806 | break; |
1807 | case 6000000: |
1808 | status += MXL_ControlWrite(fe, ControlNum: BB_ALPF_BANDSELECT, |
1809 | value: (state->IF_Mode ? 2 : 5)); |
1810 | break; |
1811 | } |
1812 | } |
1813 | |
1814 | /* Charge Pump Control Dig Ana */ |
1815 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, value: state->Mode ? 5 : 8); |
1816 | status += MXL_ControlWrite(fe, |
1817 | ControlNum: RFSYN_EN_CHP_HIGAIN, value: state->Mode ? 1 : 1); |
1818 | status += MXL_ControlWrite(fe, ControlNum: EN_CHP_LIN_B, value: state->Mode ? 0 : 0); |
1819 | |
1820 | /* AGC TOP Control */ |
1821 | if (state->AGC_Mode == 0) /* Dual AGC */ { |
1822 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 15); |
1823 | status += MXL_ControlWrite(fe, ControlNum: AGC_RF, value: 15); |
1824 | } else /* Single AGC Mode Dig Ana */ |
1825 | status += MXL_ControlWrite(fe, ControlNum: AGC_RF, value: state->Mode ? 15 : 12); |
1826 | |
1827 | if (state->TOP == 55) /* TOP == 5.5 */ |
1828 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0x0); |
1829 | |
1830 | if (state->TOP == 72) /* TOP == 7.2 */ |
1831 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0x1); |
1832 | |
1833 | if (state->TOP == 92) /* TOP == 9.2 */ |
1834 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0x2); |
1835 | |
1836 | if (state->TOP == 110) /* TOP == 11.0 */ |
1837 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0x3); |
1838 | |
1839 | if (state->TOP == 129) /* TOP == 12.9 */ |
1840 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0x4); |
1841 | |
1842 | if (state->TOP == 147) /* TOP == 14.7 */ |
1843 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0x5); |
1844 | |
1845 | if (state->TOP == 168) /* TOP == 16.8 */ |
1846 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0x6); |
1847 | |
1848 | if (state->TOP == 194) /* TOP == 19.4 */ |
1849 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0x7); |
1850 | |
1851 | if (state->TOP == 212) /* TOP == 21.2 */ |
1852 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0x9); |
1853 | |
1854 | if (state->TOP == 232) /* TOP == 23.2 */ |
1855 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0xA); |
1856 | |
1857 | if (state->TOP == 252) /* TOP == 25.2 */ |
1858 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0xB); |
1859 | |
1860 | if (state->TOP == 271) /* TOP == 27.1 */ |
1861 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0xC); |
1862 | |
1863 | if (state->TOP == 292) /* TOP == 29.2 */ |
1864 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0xD); |
1865 | |
1866 | if (state->TOP == 317) /* TOP == 31.7 */ |
1867 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0xE); |
1868 | |
1869 | if (state->TOP == 349) /* TOP == 34.9 */ |
1870 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 0xF); |
1871 | |
1872 | /* IF Synthesizer Control */ |
1873 | status += MXL_IFSynthInit(fe); |
1874 | |
1875 | /* IF UpConverter Control */ |
1876 | if (state->IF_OUT_LOAD == 200) { |
1877 | status += MXL_ControlWrite(fe, ControlNum: DRV_RES_SEL, value: 6); |
1878 | status += MXL_ControlWrite(fe, ControlNum: I_DRIVER, value: 2); |
1879 | } |
1880 | if (state->IF_OUT_LOAD == 300) { |
1881 | status += MXL_ControlWrite(fe, ControlNum: DRV_RES_SEL, value: 4); |
1882 | status += MXL_ControlWrite(fe, ControlNum: I_DRIVER, value: 1); |
1883 | } |
1884 | |
1885 | /* Anti-Alias Filtering Control |
1886 | * initialise Anti-Aliasing Filter |
1887 | */ |
1888 | if (state->Mode) { /* Digital Mode */ |
1889 | if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) { |
1890 | status += MXL_ControlWrite(fe, ControlNum: EN_AAF, value: 1); |
1891 | status += MXL_ControlWrite(fe, ControlNum: EN_3P, value: 1); |
1892 | status += MXL_ControlWrite(fe, ControlNum: EN_AUX_3P, value: 1); |
1893 | status += MXL_ControlWrite(fe, ControlNum: SEL_AAF_BAND, value: 0); |
1894 | } |
1895 | if ((state->IF_OUT == 36125000UL) || |
1896 | (state->IF_OUT == 36150000UL)) { |
1897 | status += MXL_ControlWrite(fe, ControlNum: EN_AAF, value: 1); |
1898 | status += MXL_ControlWrite(fe, ControlNum: EN_3P, value: 1); |
1899 | status += MXL_ControlWrite(fe, ControlNum: EN_AUX_3P, value: 1); |
1900 | status += MXL_ControlWrite(fe, ControlNum: SEL_AAF_BAND, value: 1); |
1901 | } |
1902 | if (state->IF_OUT > 36150000UL) { |
1903 | status += MXL_ControlWrite(fe, ControlNum: EN_AAF, value: 0); |
1904 | status += MXL_ControlWrite(fe, ControlNum: EN_3P, value: 1); |
1905 | status += MXL_ControlWrite(fe, ControlNum: EN_AUX_3P, value: 1); |
1906 | status += MXL_ControlWrite(fe, ControlNum: SEL_AAF_BAND, value: 1); |
1907 | } |
1908 | } else { /* Analog Mode */ |
1909 | if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) { |
1910 | status += MXL_ControlWrite(fe, ControlNum: EN_AAF, value: 1); |
1911 | status += MXL_ControlWrite(fe, ControlNum: EN_3P, value: 1); |
1912 | status += MXL_ControlWrite(fe, ControlNum: EN_AUX_3P, value: 1); |
1913 | status += MXL_ControlWrite(fe, ControlNum: SEL_AAF_BAND, value: 0); |
1914 | } |
1915 | if (state->IF_OUT > 5000000UL) { |
1916 | status += MXL_ControlWrite(fe, ControlNum: EN_AAF, value: 0); |
1917 | status += MXL_ControlWrite(fe, ControlNum: EN_3P, value: 0); |
1918 | status += MXL_ControlWrite(fe, ControlNum: EN_AUX_3P, value: 0); |
1919 | status += MXL_ControlWrite(fe, ControlNum: SEL_AAF_BAND, value: 0); |
1920 | } |
1921 | } |
1922 | |
1923 | /* Demod Clock Out */ |
1924 | if (state->CLOCK_OUT) |
1925 | status += MXL_ControlWrite(fe, ControlNum: SEQ_ENCLK16_CLK_OUT, value: 1); |
1926 | else |
1927 | status += MXL_ControlWrite(fe, ControlNum: SEQ_ENCLK16_CLK_OUT, value: 0); |
1928 | |
1929 | if (state->DIV_OUT == 1) |
1930 | status += MXL_ControlWrite(fe, ControlNum: SEQ_SEL4_16B, value: 1); |
1931 | if (state->DIV_OUT == 0) |
1932 | status += MXL_ControlWrite(fe, ControlNum: SEQ_SEL4_16B, value: 0); |
1933 | |
1934 | /* Crystal Control */ |
1935 | if (state->CAPSELECT) |
1936 | status += MXL_ControlWrite(fe, ControlNum: XTAL_CAPSELECT, value: 1); |
1937 | else |
1938 | status += MXL_ControlWrite(fe, ControlNum: XTAL_CAPSELECT, value: 0); |
1939 | |
1940 | if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) |
1941 | status += MXL_ControlWrite(fe, ControlNum: IF_SEL_DBL, value: 1); |
1942 | if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) |
1943 | status += MXL_ControlWrite(fe, ControlNum: IF_SEL_DBL, value: 0); |
1944 | |
1945 | if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) |
1946 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_R_DIV, value: 3); |
1947 | if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL) |
1948 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_R_DIV, value: 0); |
1949 | |
1950 | /* Misc Controls */ |
1951 | if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */ |
1952 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTIQFSMPULSE, value: 0); |
1953 | else |
1954 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTIQFSMPULSE, value: 1); |
1955 | |
1956 | /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ |
1957 | |
1958 | /* Set TG_R_DIV */ |
1959 | status += MXL_ControlWrite(fe, ControlNum: TG_R_DIV, |
1960 | value: MXL_Ceiling(value: state->Fxtal, resolution: 1000000)); |
1961 | |
1962 | /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ |
1963 | |
1964 | /* RSSI Control */ |
1965 | if (state->EN_RSSI) { |
1966 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTSYNTHCALIF, value: 1); |
1967 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTDCCAL, value: 1); |
1968 | status += MXL_ControlWrite(fe, ControlNum: AGC_EN_RSSI, value: 1); |
1969 | status += MXL_ControlWrite(fe, ControlNum: RFA_ENCLKRFAGC, value: 1); |
1970 | |
1971 | /* RSSI reference point */ |
1972 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REF, value: 2); |
1973 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFH, value: 3); |
1974 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFL, value: 1); |
1975 | |
1976 | /* TOP point */ |
1977 | status += MXL_ControlWrite(fe, ControlNum: RFA_FLR, value: 0); |
1978 | status += MXL_ControlWrite(fe, ControlNum: RFA_CEIL, value: 12); |
1979 | } |
1980 | |
1981 | /* Modulation type bit settings |
1982 | * Override the control values preset |
1983 | */ |
1984 | if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { |
1985 | state->AGC_Mode = 1; /* Single AGC Mode */ |
1986 | |
1987 | /* Enable RSSI */ |
1988 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTSYNTHCALIF, value: 1); |
1989 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTDCCAL, value: 1); |
1990 | status += MXL_ControlWrite(fe, ControlNum: AGC_EN_RSSI, value: 1); |
1991 | status += MXL_ControlWrite(fe, ControlNum: RFA_ENCLKRFAGC, value: 1); |
1992 | |
1993 | /* RSSI reference point */ |
1994 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REF, value: 3); |
1995 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFH, value: 5); |
1996 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFL, value: 1); |
1997 | |
1998 | /* TOP point */ |
1999 | status += MXL_ControlWrite(fe, ControlNum: RFA_FLR, value: 2); |
2000 | status += MXL_ControlWrite(fe, ControlNum: RFA_CEIL, value: 13); |
2001 | if (state->IF_OUT <= 6280000UL) /* Low IF */ |
2002 | status += MXL_ControlWrite(fe, ControlNum: BB_IQSWAP, value: 0); |
2003 | else /* High IF */ |
2004 | status += MXL_ControlWrite(fe, ControlNum: BB_IQSWAP, value: 1); |
2005 | |
2006 | } |
2007 | if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { |
2008 | state->AGC_Mode = 1; /* Single AGC Mode */ |
2009 | |
2010 | /* Enable RSSI */ |
2011 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTSYNTHCALIF, value: 1); |
2012 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTDCCAL, value: 1); |
2013 | status += MXL_ControlWrite(fe, ControlNum: AGC_EN_RSSI, value: 1); |
2014 | status += MXL_ControlWrite(fe, ControlNum: RFA_ENCLKRFAGC, value: 1); |
2015 | |
2016 | /* RSSI reference point */ |
2017 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REF, value: 2); |
2018 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFH, value: 4); |
2019 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFL, value: 1); |
2020 | |
2021 | /* TOP point */ |
2022 | status += MXL_ControlWrite(fe, ControlNum: RFA_FLR, value: 2); |
2023 | status += MXL_ControlWrite(fe, ControlNum: RFA_CEIL, value: 13); |
2024 | status += MXL_ControlWrite(fe, ControlNum: BB_INITSTATE_DLPF_TUNE, value: 1); |
2025 | /* Low Zero */ |
2026 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, value: 5); |
2027 | |
2028 | if (state->IF_OUT <= 6280000UL) /* Low IF */ |
2029 | status += MXL_ControlWrite(fe, ControlNum: BB_IQSWAP, value: 0); |
2030 | else /* High IF */ |
2031 | status += MXL_ControlWrite(fe, ControlNum: BB_IQSWAP, value: 1); |
2032 | } |
2033 | if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { |
2034 | state->Mode = MXL_DIGITAL_MODE; |
2035 | |
2036 | /* state->AGC_Mode = 1; */ /* Single AGC Mode */ |
2037 | |
2038 | /* Disable RSSI */ /* change here for v2.6.5 */ |
2039 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTSYNTHCALIF, value: 1); |
2040 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTDCCAL, value: 1); |
2041 | status += MXL_ControlWrite(fe, ControlNum: AGC_EN_RSSI, value: 0); |
2042 | status += MXL_ControlWrite(fe, ControlNum: RFA_ENCLKRFAGC, value: 1); |
2043 | |
2044 | /* RSSI reference point */ |
2045 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFH, value: 5); |
2046 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REF, value: 3); |
2047 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFL, value: 2); |
2048 | /* change here for v2.6.5 */ |
2049 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, value: 3); |
2050 | |
2051 | if (state->IF_OUT <= 6280000UL) /* Low IF */ |
2052 | status += MXL_ControlWrite(fe, ControlNum: BB_IQSWAP, value: 0); |
2053 | else /* High IF */ |
2054 | status += MXL_ControlWrite(fe, ControlNum: BB_IQSWAP, value: 1); |
2055 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, value: 2); |
2056 | |
2057 | } |
2058 | if (state->Mod_Type == MXL_ANALOG_CABLE) { |
2059 | /* Analog Cable Mode */ |
2060 | /* state->Mode = MXL_DIGITAL_MODE; */ |
2061 | |
2062 | state->AGC_Mode = 1; /* Single AGC Mode */ |
2063 | |
2064 | /* Disable RSSI */ |
2065 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTSYNTHCALIF, value: 1); |
2066 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTDCCAL, value: 1); |
2067 | status += MXL_ControlWrite(fe, ControlNum: AGC_EN_RSSI, value: 0); |
2068 | status += MXL_ControlWrite(fe, ControlNum: RFA_ENCLKRFAGC, value: 1); |
2069 | /* change for 2.6.3 */ |
2070 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 1); |
2071 | status += MXL_ControlWrite(fe, ControlNum: AGC_RF, value: 15); |
2072 | status += MXL_ControlWrite(fe, ControlNum: BB_IQSWAP, value: 1); |
2073 | } |
2074 | |
2075 | if (state->Mod_Type == MXL_ANALOG_OTA) { |
2076 | /* Analog OTA Terrestrial mode add for 2.6.7 */ |
2077 | /* state->Mode = MXL_ANALOG_MODE; */ |
2078 | |
2079 | /* Enable RSSI */ |
2080 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTSYNTHCALIF, value: 1); |
2081 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTDCCAL, value: 1); |
2082 | status += MXL_ControlWrite(fe, ControlNum: AGC_EN_RSSI, value: 1); |
2083 | status += MXL_ControlWrite(fe, ControlNum: RFA_ENCLKRFAGC, value: 1); |
2084 | |
2085 | /* RSSI reference point */ |
2086 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFH, value: 5); |
2087 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REF, value: 3); |
2088 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFL, value: 2); |
2089 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, value: 3); |
2090 | status += MXL_ControlWrite(fe, ControlNum: BB_IQSWAP, value: 1); |
2091 | } |
2092 | |
2093 | /* RSSI disable */ |
2094 | if (state->EN_RSSI == 0) { |
2095 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTSYNTHCALIF, value: 1); |
2096 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTDCCAL, value: 1); |
2097 | status += MXL_ControlWrite(fe, ControlNum: AGC_EN_RSSI, value: 0); |
2098 | status += MXL_ControlWrite(fe, ControlNum: RFA_ENCLKRFAGC, value: 1); |
2099 | } |
2100 | |
2101 | return status; |
2102 | } |
2103 | |
2104 | static u16 MXL_IFSynthInit(struct dvb_frontend *fe) |
2105 | { |
2106 | struct mxl5005s_state *state = fe->tuner_priv; |
2107 | u16 status = 0 ; |
2108 | u32 Fref = 0 ; |
2109 | u32 Kdbl, intModVal ; |
2110 | u32 fracModVal ; |
2111 | Kdbl = 2 ; |
2112 | |
2113 | if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) |
2114 | Kdbl = 2 ; |
2115 | if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) |
2116 | Kdbl = 1 ; |
2117 | |
2118 | /* IF Synthesizer Control */ |
2119 | if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ { |
2120 | if (state->IF_LO == 41000000UL) { |
2121 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2122 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x0C); |
2123 | Fref = 328000000UL ; |
2124 | } |
2125 | if (state->IF_LO == 47000000UL) { |
2126 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2127 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2128 | Fref = 376000000UL ; |
2129 | } |
2130 | if (state->IF_LO == 54000000UL) { |
2131 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x10); |
2132 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x0C); |
2133 | Fref = 324000000UL ; |
2134 | } |
2135 | if (state->IF_LO == 60000000UL) { |
2136 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x10); |
2137 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2138 | Fref = 360000000UL ; |
2139 | } |
2140 | if (state->IF_LO == 39250000UL) { |
2141 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2142 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x0C); |
2143 | Fref = 314000000UL ; |
2144 | } |
2145 | if (state->IF_LO == 39650000UL) { |
2146 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2147 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x0C); |
2148 | Fref = 317200000UL ; |
2149 | } |
2150 | if (state->IF_LO == 40150000UL) { |
2151 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2152 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x0C); |
2153 | Fref = 321200000UL ; |
2154 | } |
2155 | if (state->IF_LO == 40650000UL) { |
2156 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2157 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x0C); |
2158 | Fref = 325200000UL ; |
2159 | } |
2160 | } |
2161 | |
2162 | if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { |
2163 | if (state->IF_LO == 57000000UL) { |
2164 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x10); |
2165 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2166 | Fref = 342000000UL ; |
2167 | } |
2168 | if (state->IF_LO == 44000000UL) { |
2169 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2170 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2171 | Fref = 352000000UL ; |
2172 | } |
2173 | if (state->IF_LO == 43750000UL) { |
2174 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2175 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2176 | Fref = 350000000UL ; |
2177 | } |
2178 | if (state->IF_LO == 36650000UL) { |
2179 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x04); |
2180 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2181 | Fref = 366500000UL ; |
2182 | } |
2183 | if (state->IF_LO == 36150000UL) { |
2184 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x04); |
2185 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2186 | Fref = 361500000UL ; |
2187 | } |
2188 | if (state->IF_LO == 36000000UL) { |
2189 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x04); |
2190 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2191 | Fref = 360000000UL ; |
2192 | } |
2193 | if (state->IF_LO == 35250000UL) { |
2194 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x04); |
2195 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2196 | Fref = 352500000UL ; |
2197 | } |
2198 | if (state->IF_LO == 34750000UL) { |
2199 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x04); |
2200 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2201 | Fref = 347500000UL ; |
2202 | } |
2203 | if (state->IF_LO == 6280000UL) { |
2204 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x07); |
2205 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2206 | Fref = 376800000UL ; |
2207 | } |
2208 | if (state->IF_LO == 5000000UL) { |
2209 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x09); |
2210 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2211 | Fref = 360000000UL ; |
2212 | } |
2213 | if (state->IF_LO == 4500000UL) { |
2214 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x06); |
2215 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2216 | Fref = 360000000UL ; |
2217 | } |
2218 | if (state->IF_LO == 4570000UL) { |
2219 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x06); |
2220 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2221 | Fref = 365600000UL ; |
2222 | } |
2223 | if (state->IF_LO == 4000000UL) { |
2224 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x05); |
2225 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2226 | Fref = 360000000UL ; |
2227 | } |
2228 | if (state->IF_LO == 57400000UL) { |
2229 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x10); |
2230 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2231 | Fref = 344400000UL ; |
2232 | } |
2233 | if (state->IF_LO == 44400000UL) { |
2234 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2235 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2236 | Fref = 355200000UL ; |
2237 | } |
2238 | if (state->IF_LO == 44150000UL) { |
2239 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x08); |
2240 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2241 | Fref = 353200000UL ; |
2242 | } |
2243 | if (state->IF_LO == 37050000UL) { |
2244 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x04); |
2245 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2246 | Fref = 370500000UL ; |
2247 | } |
2248 | if (state->IF_LO == 36550000UL) { |
2249 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x04); |
2250 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2251 | Fref = 365500000UL ; |
2252 | } |
2253 | if (state->IF_LO == 36125000UL) { |
2254 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x04); |
2255 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2256 | Fref = 361250000UL ; |
2257 | } |
2258 | if (state->IF_LO == 6000000UL) { |
2259 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x07); |
2260 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2261 | Fref = 360000000UL ; |
2262 | } |
2263 | if (state->IF_LO == 5400000UL) { |
2264 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x07); |
2265 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x0C); |
2266 | Fref = 324000000UL ; |
2267 | } |
2268 | if (state->IF_LO == 5380000UL) { |
2269 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x07); |
2270 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x0C); |
2271 | Fref = 322800000UL ; |
2272 | } |
2273 | if (state->IF_LO == 5200000UL) { |
2274 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x09); |
2275 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2276 | Fref = 374400000UL ; |
2277 | } |
2278 | if (state->IF_LO == 4900000UL) { |
2279 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x09); |
2280 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2281 | Fref = 352800000UL ; |
2282 | } |
2283 | if (state->IF_LO == 4400000UL) { |
2284 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x06); |
2285 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2286 | Fref = 352000000UL ; |
2287 | } |
2288 | if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ { |
2289 | status += MXL_ControlWrite(fe, ControlNum: IF_DIVVAL, value: 0x05); |
2290 | status += MXL_ControlWrite(fe, ControlNum: IF_VCO_BIAS, value: 0x08); |
2291 | Fref = 365670000UL ; |
2292 | } |
2293 | } |
2294 | /* CHCAL_INT_MOD_IF */ |
2295 | /* CHCAL_FRAC_MOD_IF */ |
2296 | intModVal = Fref / (state->Fxtal * Kdbl/2); |
2297 | status += MXL_ControlWrite(fe, ControlNum: CHCAL_INT_MOD_IF, value: intModVal); |
2298 | |
2299 | fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * |
2300 | intModVal); |
2301 | |
2302 | fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000); |
2303 | status += MXL_ControlWrite(fe, ControlNum: CHCAL_FRAC_MOD_IF, value: fracModVal); |
2304 | |
2305 | return status ; |
2306 | } |
2307 | |
2308 | static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) |
2309 | { |
2310 | struct mxl5005s_state *state = fe->tuner_priv; |
2311 | u16 status = 0; |
2312 | u32 divider_val, E3, E4, E5, E5A; |
2313 | u32 Fmax, Fmin, FmaxBin, FminBin; |
2314 | u32 Kdbl_RF = 2; |
2315 | u32 tg_divval; |
2316 | u32 tg_lo; |
2317 | |
2318 | u32 Fref_TG; |
2319 | u32 Fvco; |
2320 | |
2321 | state->RF_IN = RF_Freq; |
2322 | |
2323 | MXL_SynthRFTGLO_Calc(fe); |
2324 | |
2325 | if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) |
2326 | Kdbl_RF = 2; |
2327 | if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) |
2328 | Kdbl_RF = 1; |
2329 | |
2330 | /* Downconverter Controls |
2331 | * Look-Up Table Implementation for: |
2332 | * DN_POLY |
2333 | * DN_RFGAIN |
2334 | * DN_CAP_RFLPF |
2335 | * DN_EN_VHFUHFBAR |
2336 | * DN_GAIN_ADJUST |
2337 | * Change the boundary reference from RF_IN to RF_LO |
2338 | */ |
2339 | if (state->RF_LO < 40000000UL) |
2340 | return -1; |
2341 | |
2342 | if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { |
2343 | status += MXL_ControlWrite(fe, ControlNum: DN_POLY, value: 2); |
2344 | status += MXL_ControlWrite(fe, ControlNum: DN_RFGAIN, value: 3); |
2345 | status += MXL_ControlWrite(fe, ControlNum: DN_CAP_RFLPF, value: 423); |
2346 | status += MXL_ControlWrite(fe, ControlNum: DN_EN_VHFUHFBAR, value: 1); |
2347 | status += MXL_ControlWrite(fe, ControlNum: DN_GAIN_ADJUST, value: 1); |
2348 | } |
2349 | if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { |
2350 | status += MXL_ControlWrite(fe, ControlNum: DN_POLY, value: 3); |
2351 | status += MXL_ControlWrite(fe, ControlNum: DN_RFGAIN, value: 3); |
2352 | status += MXL_ControlWrite(fe, ControlNum: DN_CAP_RFLPF, value: 222); |
2353 | status += MXL_ControlWrite(fe, ControlNum: DN_EN_VHFUHFBAR, value: 1); |
2354 | status += MXL_ControlWrite(fe, ControlNum: DN_GAIN_ADJUST, value: 1); |
2355 | } |
2356 | if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { |
2357 | status += MXL_ControlWrite(fe, ControlNum: DN_POLY, value: 3); |
2358 | status += MXL_ControlWrite(fe, ControlNum: DN_RFGAIN, value: 3); |
2359 | status += MXL_ControlWrite(fe, ControlNum: DN_CAP_RFLPF, value: 147); |
2360 | status += MXL_ControlWrite(fe, ControlNum: DN_EN_VHFUHFBAR, value: 1); |
2361 | status += MXL_ControlWrite(fe, ControlNum: DN_GAIN_ADJUST, value: 2); |
2362 | } |
2363 | if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { |
2364 | status += MXL_ControlWrite(fe, ControlNum: DN_POLY, value: 3); |
2365 | status += MXL_ControlWrite(fe, ControlNum: DN_RFGAIN, value: 3); |
2366 | status += MXL_ControlWrite(fe, ControlNum: DN_CAP_RFLPF, value: 9); |
2367 | status += MXL_ControlWrite(fe, ControlNum: DN_EN_VHFUHFBAR, value: 1); |
2368 | status += MXL_ControlWrite(fe, ControlNum: DN_GAIN_ADJUST, value: 2); |
2369 | } |
2370 | if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { |
2371 | status += MXL_ControlWrite(fe, ControlNum: DN_POLY, value: 3); |
2372 | status += MXL_ControlWrite(fe, ControlNum: DN_RFGAIN, value: 3); |
2373 | status += MXL_ControlWrite(fe, ControlNum: DN_CAP_RFLPF, value: 0); |
2374 | status += MXL_ControlWrite(fe, ControlNum: DN_EN_VHFUHFBAR, value: 1); |
2375 | status += MXL_ControlWrite(fe, ControlNum: DN_GAIN_ADJUST, value: 3); |
2376 | } |
2377 | if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { |
2378 | status += MXL_ControlWrite(fe, ControlNum: DN_POLY, value: 3); |
2379 | status += MXL_ControlWrite(fe, ControlNum: DN_RFGAIN, value: 1); |
2380 | status += MXL_ControlWrite(fe, ControlNum: DN_CAP_RFLPF, value: 0); |
2381 | status += MXL_ControlWrite(fe, ControlNum: DN_EN_VHFUHFBAR, value: 0); |
2382 | status += MXL_ControlWrite(fe, ControlNum: DN_GAIN_ADJUST, value: 3); |
2383 | } |
2384 | if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { |
2385 | status += MXL_ControlWrite(fe, ControlNum: DN_POLY, value: 3); |
2386 | status += MXL_ControlWrite(fe, ControlNum: DN_RFGAIN, value: 2); |
2387 | status += MXL_ControlWrite(fe, ControlNum: DN_CAP_RFLPF, value: 0); |
2388 | status += MXL_ControlWrite(fe, ControlNum: DN_EN_VHFUHFBAR, value: 0); |
2389 | status += MXL_ControlWrite(fe, ControlNum: DN_GAIN_ADJUST, value: 3); |
2390 | } |
2391 | if (state->RF_LO > 900000000UL) |
2392 | return -1; |
2393 | |
2394 | /* DN_IQTNBUF_AMP */ |
2395 | /* DN_IQTNGNBFBIAS_BST */ |
2396 | if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { |
2397 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2398 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2399 | } |
2400 | if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { |
2401 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2402 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2403 | } |
2404 | if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { |
2405 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2406 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2407 | } |
2408 | if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { |
2409 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2410 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2411 | } |
2412 | if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { |
2413 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2414 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2415 | } |
2416 | if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) { |
2417 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2418 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2419 | } |
2420 | if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) { |
2421 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2422 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2423 | } |
2424 | if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) { |
2425 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2426 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2427 | } |
2428 | if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) { |
2429 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2430 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2431 | } |
2432 | if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) { |
2433 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2434 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2435 | } |
2436 | if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) { |
2437 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2438 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2439 | } |
2440 | if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) { |
2441 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2442 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2443 | } |
2444 | if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) { |
2445 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2446 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2447 | } |
2448 | if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) { |
2449 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 1); |
2450 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 0); |
2451 | } |
2452 | if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) { |
2453 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 10); |
2454 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 1); |
2455 | } |
2456 | if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) { |
2457 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNBUF_AMP, value: 10); |
2458 | status += MXL_ControlWrite(fe, ControlNum: DN_IQTNGNBFBIAS_BST, value: 1); |
2459 | } |
2460 | |
2461 | /* |
2462 | * Set RF Synth and LO Path Control |
2463 | * |
2464 | * Look-Up table implementation for: |
2465 | * RFSYN_EN_OUTMUX |
2466 | * RFSYN_SEL_VCO_OUT |
2467 | * RFSYN_SEL_VCO_HI |
2468 | * RFSYN_SEL_DIVM |
2469 | * RFSYN_RF_DIV_BIAS |
2470 | * DN_SEL_FREQ |
2471 | * |
2472 | * Set divider_val, Fmax, Fmix to use in Equations |
2473 | */ |
2474 | FminBin = 28000000UL ; |
2475 | FmaxBin = 42500000UL ; |
2476 | if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { |
2477 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 1); |
2478 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 0); |
2479 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 0); |
2480 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 0); |
2481 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2482 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 1); |
2483 | divider_val = 64 ; |
2484 | Fmax = FmaxBin ; |
2485 | Fmin = FminBin ; |
2486 | } |
2487 | FminBin = 42500000UL ; |
2488 | FmaxBin = 56000000UL ; |
2489 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2490 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 1); |
2491 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 0); |
2492 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 1); |
2493 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 0); |
2494 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2495 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 1); |
2496 | divider_val = 64 ; |
2497 | Fmax = FmaxBin ; |
2498 | Fmin = FminBin ; |
2499 | } |
2500 | FminBin = 56000000UL ; |
2501 | FmaxBin = 85000000UL ; |
2502 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2503 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 0); |
2504 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 1); |
2505 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 0); |
2506 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 0); |
2507 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2508 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 1); |
2509 | divider_val = 32 ; |
2510 | Fmax = FmaxBin ; |
2511 | Fmin = FminBin ; |
2512 | } |
2513 | FminBin = 85000000UL ; |
2514 | FmaxBin = 112000000UL ; |
2515 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2516 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 0); |
2517 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 1); |
2518 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 1); |
2519 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 0); |
2520 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2521 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 1); |
2522 | divider_val = 32 ; |
2523 | Fmax = FmaxBin ; |
2524 | Fmin = FminBin ; |
2525 | } |
2526 | FminBin = 112000000UL ; |
2527 | FmaxBin = 170000000UL ; |
2528 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2529 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 0); |
2530 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 1); |
2531 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 0); |
2532 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 0); |
2533 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2534 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 2); |
2535 | divider_val = 16 ; |
2536 | Fmax = FmaxBin ; |
2537 | Fmin = FminBin ; |
2538 | } |
2539 | FminBin = 170000000UL ; |
2540 | FmaxBin = 225000000UL ; |
2541 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2542 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 0); |
2543 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 1); |
2544 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 1); |
2545 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 0); |
2546 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2547 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 2); |
2548 | divider_val = 16 ; |
2549 | Fmax = FmaxBin ; |
2550 | Fmin = FminBin ; |
2551 | } |
2552 | FminBin = 225000000UL ; |
2553 | FmaxBin = 300000000UL ; |
2554 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2555 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 0); |
2556 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 1); |
2557 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 0); |
2558 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 0); |
2559 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2560 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 4); |
2561 | divider_val = 8 ; |
2562 | Fmax = 340000000UL ; |
2563 | Fmin = FminBin ; |
2564 | } |
2565 | FminBin = 300000000UL ; |
2566 | FmaxBin = 340000000UL ; |
2567 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2568 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 1); |
2569 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 0); |
2570 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 0); |
2571 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 0); |
2572 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2573 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 0); |
2574 | divider_val = 8 ; |
2575 | Fmax = FmaxBin ; |
2576 | Fmin = 225000000UL ; |
2577 | } |
2578 | FminBin = 340000000UL ; |
2579 | FmaxBin = 450000000UL ; |
2580 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2581 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 1); |
2582 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 0); |
2583 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 1); |
2584 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 0); |
2585 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 2); |
2586 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 0); |
2587 | divider_val = 8 ; |
2588 | Fmax = FmaxBin ; |
2589 | Fmin = FminBin ; |
2590 | } |
2591 | FminBin = 450000000UL ; |
2592 | FmaxBin = 680000000UL ; |
2593 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2594 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 0); |
2595 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 1); |
2596 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 0); |
2597 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 1); |
2598 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2599 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 0); |
2600 | divider_val = 4 ; |
2601 | Fmax = FmaxBin ; |
2602 | Fmin = FminBin ; |
2603 | } |
2604 | FminBin = 680000000UL ; |
2605 | FmaxBin = 900000000UL ; |
2606 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2607 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_EN_OUTMUX, value: 0); |
2608 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_OUT, value: 1); |
2609 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_VCO_HI, value: 1); |
2610 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_SEL_DIVM, value: 1); |
2611 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_RF_DIV_BIAS, value: 1); |
2612 | status += MXL_ControlWrite(fe, ControlNum: DN_SEL_FREQ, value: 0); |
2613 | divider_val = 4 ; |
2614 | Fmax = FmaxBin ; |
2615 | Fmin = FminBin ; |
2616 | } |
2617 | |
2618 | /* CHCAL_INT_MOD_RF |
2619 | * CHCAL_FRAC_MOD_RF |
2620 | * RFSYN_LPF_R |
2621 | * CHCAL_EN_INT_RF |
2622 | */ |
2623 | /* Equation E3 RFSYN_VCO_BIAS */ |
2624 | E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; |
2625 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_VCO_BIAS, value: E3); |
2626 | |
2627 | /* Equation E4 CHCAL_INT_MOD_RF */ |
2628 | E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000); |
2629 | MXL_ControlWrite(fe, ControlNum: CHCAL_INT_MOD_RF, value: E4); |
2630 | |
2631 | /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */ |
2632 | E5 = ((2<<17)*(state->RF_LO/10000*divider_val - |
2633 | (E4*(2*state->Fxtal*Kdbl_RF)/10000))) / |
2634 | (2*state->Fxtal*Kdbl_RF/10000); |
2635 | |
2636 | status += MXL_ControlWrite(fe, ControlNum: CHCAL_FRAC_MOD_RF, value: E5); |
2637 | |
2638 | /* Equation E5A RFSYN_LPF_R */ |
2639 | E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; |
2640 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_LPF_R, value: E5A); |
2641 | |
2642 | /* Euqation E5B CHCAL_EN_INIT_RF */ |
2643 | status += MXL_ControlWrite(fe, ControlNum: CHCAL_EN_INT_RF, value: ((E5 == 0) ? 1 : 0)); |
2644 | /*if (E5 == 0) |
2645 | * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); |
2646 | *else |
2647 | * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5); |
2648 | */ |
2649 | |
2650 | /* |
2651 | * Set TG Synth |
2652 | * |
2653 | * Look-Up table implementation for: |
2654 | * TG_LO_DIVVAL |
2655 | * TG_LO_SELVAL |
2656 | * |
2657 | * Set divider_val, Fmax, Fmix to use in Equations |
2658 | */ |
2659 | if (state->TG_LO < 33000000UL) |
2660 | return -1; |
2661 | |
2662 | FminBin = 33000000UL ; |
2663 | FmaxBin = 50000000UL ; |
2664 | if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { |
2665 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_DIVVAL, value: 0x6); |
2666 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_SELVAL, value: 0x0); |
2667 | divider_val = 36 ; |
2668 | Fmax = FmaxBin ; |
2669 | Fmin = FminBin ; |
2670 | } |
2671 | FminBin = 50000000UL ; |
2672 | FmaxBin = 67000000UL ; |
2673 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
2674 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_DIVVAL, value: 0x1); |
2675 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_SELVAL, value: 0x0); |
2676 | divider_val = 24 ; |
2677 | Fmax = FmaxBin ; |
2678 | Fmin = FminBin ; |
2679 | } |
2680 | FminBin = 67000000UL ; |
2681 | FmaxBin = 100000000UL ; |
2682 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
2683 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_DIVVAL, value: 0xC); |
2684 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_SELVAL, value: 0x2); |
2685 | divider_val = 18 ; |
2686 | Fmax = FmaxBin ; |
2687 | Fmin = FminBin ; |
2688 | } |
2689 | FminBin = 100000000UL ; |
2690 | FmaxBin = 150000000UL ; |
2691 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
2692 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_DIVVAL, value: 0x8); |
2693 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_SELVAL, value: 0x2); |
2694 | divider_val = 12 ; |
2695 | Fmax = FmaxBin ; |
2696 | Fmin = FminBin ; |
2697 | } |
2698 | FminBin = 150000000UL ; |
2699 | FmaxBin = 200000000UL ; |
2700 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
2701 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_DIVVAL, value: 0x0); |
2702 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_SELVAL, value: 0x2); |
2703 | divider_val = 8 ; |
2704 | Fmax = FmaxBin ; |
2705 | Fmin = FminBin ; |
2706 | } |
2707 | FminBin = 200000000UL ; |
2708 | FmaxBin = 300000000UL ; |
2709 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
2710 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_DIVVAL, value: 0x8); |
2711 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_SELVAL, value: 0x3); |
2712 | divider_val = 6 ; |
2713 | Fmax = FmaxBin ; |
2714 | Fmin = FminBin ; |
2715 | } |
2716 | FminBin = 300000000UL ; |
2717 | FmaxBin = 400000000UL ; |
2718 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
2719 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_DIVVAL, value: 0x0); |
2720 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_SELVAL, value: 0x3); |
2721 | divider_val = 4 ; |
2722 | Fmax = FmaxBin ; |
2723 | Fmin = FminBin ; |
2724 | } |
2725 | FminBin = 400000000UL ; |
2726 | FmaxBin = 600000000UL ; |
2727 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
2728 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_DIVVAL, value: 0x8); |
2729 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_SELVAL, value: 0x7); |
2730 | divider_val = 3 ; |
2731 | Fmax = FmaxBin ; |
2732 | Fmin = FminBin ; |
2733 | } |
2734 | FminBin = 600000000UL ; |
2735 | FmaxBin = 900000000UL ; |
2736 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
2737 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_DIVVAL, value: 0x0); |
2738 | status += MXL_ControlWrite(fe, ControlNum: TG_LO_SELVAL, value: 0x7); |
2739 | divider_val = 2 ; |
2740 | } |
2741 | |
2742 | /* TG_DIV_VAL */ |
2743 | tg_divval = (state->TG_LO*divider_val/100000) * |
2744 | (MXL_Ceiling(value: state->Fxtal, resolution: 1000000) * 100) / |
2745 | (state->Fxtal/1000); |
2746 | |
2747 | status += MXL_ControlWrite(fe, ControlNum: TG_DIV_VAL, value: tg_divval); |
2748 | |
2749 | if (state->TG_LO > 600000000UL) |
2750 | status += MXL_ControlWrite(fe, ControlNum: TG_DIV_VAL, value: tg_divval + 1); |
2751 | |
2752 | Fmax = 1800000000UL ; |
2753 | Fmin = 1200000000UL ; |
2754 | |
2755 | /* prevent overflow of 32 bit unsigned integer, use |
2756 | * following equation. Edit for v2.6.4 |
2757 | */ |
2758 | /* Fref_TF = Fref_TG * 1000 */ |
2759 | Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(value: state->Fxtal, resolution: 1000000); |
2760 | |
2761 | /* Fvco = Fvco/10 */ |
2762 | Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; |
2763 | |
2764 | tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; |
2765 | |
2766 | /* below equation is same as above but much harder to debug. |
2767 | * |
2768 | * static u32 MXL_GetXtalInt(u32 Xtal_Freq) |
2769 | * { |
2770 | * if ((Xtal_Freq % 1000000) == 0) |
2771 | * return (Xtal_Freq / 10000); |
2772 | * else |
2773 | * return (((Xtal_Freq / 1000000) + 1)*100); |
2774 | * } |
2775 | * |
2776 | * u32 Xtal_Int = MXL_GetXtalInt(state->Fxtal); |
2777 | * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - |
2778 | * ((state->TG_LO/10000)*divider_val * |
2779 | * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * |
2780 | * Xtal_Int/100) + 8; |
2781 | */ |
2782 | |
2783 | status += MXL_ControlWrite(fe, ControlNum: TG_VCO_BIAS , value: tg_lo); |
2784 | |
2785 | /* add for 2.6.5 Special setting for QAM */ |
2786 | if (state->Mod_Type == MXL_QAM) { |
2787 | if (state->config->qam_gain != 0) |
2788 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, |
2789 | value: state->config->qam_gain); |
2790 | else if (state->RF_IN < 680000000) |
2791 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, value: 3); |
2792 | else |
2793 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, value: 2); |
2794 | } |
2795 | |
2796 | /* Off Chip Tracking Filter Control */ |
2797 | if (state->TF_Type == MXL_TF_OFF) { |
2798 | /* Tracking Filter Off State; turn off all the banks */ |
2799 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2800 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
2801 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); /* Bank1 Off */ |
2802 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); /* Bank2 Off */ |
2803 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); /* Bank3 Off */ |
2804 | } |
2805 | |
2806 | if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ { |
2807 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
2808 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_A, value: 0); |
2809 | |
2810 | if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { |
2811 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2812 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
2813 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
2814 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2815 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2816 | } |
2817 | if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { |
2818 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2819 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
2820 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2821 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
2822 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2823 | } |
2824 | if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { |
2825 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2826 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
2827 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2828 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
2829 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
2830 | } |
2831 | if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { |
2832 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2833 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
2834 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2835 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2836 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
2837 | } |
2838 | if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { |
2839 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2840 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 29); |
2841 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2842 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2843 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
2844 | } |
2845 | if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { |
2846 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2847 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
2848 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2849 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2850 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
2851 | } |
2852 | if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { |
2853 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2854 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 16); |
2855 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2856 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2857 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2858 | } |
2859 | if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { |
2860 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2861 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 7); |
2862 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2863 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2864 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2865 | } |
2866 | if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { |
2867 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2868 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
2869 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2870 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2871 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2872 | } |
2873 | } |
2874 | |
2875 | if (state->TF_Type == MXL_TF_C_H) { |
2876 | |
2877 | /* Tracking Filter type C-H for Hauppauge only */ |
2878 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_A, value: 0); |
2879 | |
2880 | if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { |
2881 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2882 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
2883 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2884 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2885 | } |
2886 | if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { |
2887 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2888 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2889 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
2890 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2891 | } |
2892 | if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { |
2893 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2894 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2895 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
2896 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
2897 | } |
2898 | if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { |
2899 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2900 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2901 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2902 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
2903 | } |
2904 | if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { |
2905 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2906 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2907 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2908 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
2909 | } |
2910 | if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { |
2911 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2912 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2913 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2914 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
2915 | } |
2916 | if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { |
2917 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2918 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2919 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2920 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2921 | } |
2922 | if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { |
2923 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2924 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2925 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2926 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2927 | } |
2928 | if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { |
2929 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
2930 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2931 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2932 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2933 | } |
2934 | } |
2935 | |
2936 | if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */ |
2937 | |
2938 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
2939 | |
2940 | if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { |
2941 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
2942 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
2943 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2944 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2945 | } |
2946 | if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { |
2947 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
2948 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
2949 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
2950 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2951 | } |
2952 | if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { |
2953 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
2954 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2955 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
2956 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2957 | } |
2958 | if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { |
2959 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
2960 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2961 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
2962 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
2963 | } |
2964 | if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { |
2965 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
2966 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2967 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2968 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
2969 | } |
2970 | if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { |
2971 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
2972 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2973 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2974 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
2975 | } |
2976 | if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { |
2977 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
2978 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2979 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2980 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2981 | } |
2982 | } |
2983 | |
2984 | if (state->TF_Type == MXL_TF_D_L) { |
2985 | |
2986 | /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */ |
2987 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_A, value: 0); |
2988 | |
2989 | /* if UHF and terrestrial => Turn off Tracking Filter */ |
2990 | if (state->RF_IN >= 471000000 && |
2991 | (state->RF_IN - 471000000)%6000000 != 0) { |
2992 | /* Turn off all the banks */ |
2993 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
2994 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
2995 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
2996 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
2997 | status += MXL_ControlWrite(fe, ControlNum: AGC_IF, value: 10); |
2998 | } else { |
2999 | /* if VHF or cable => Turn on Tracking Filter */ |
3000 | if (state->RF_IN >= 43000000 && |
3001 | state->RF_IN < 140000000) { |
3002 | |
3003 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
3004 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3005 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3006 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3007 | } |
3008 | if (state->RF_IN >= 140000000 && |
3009 | state->RF_IN < 240000000) { |
3010 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
3011 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3012 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3013 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3014 | } |
3015 | if (state->RF_IN >= 240000000 && |
3016 | state->RF_IN < 340000000) { |
3017 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
3018 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3019 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3020 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3021 | } |
3022 | if (state->RF_IN >= 340000000 && |
3023 | state->RF_IN < 430000000) { |
3024 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
3025 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3026 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3027 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3028 | } |
3029 | if (state->RF_IN >= 430000000 && |
3030 | state->RF_IN < 470000000) { |
3031 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
3032 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3033 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3034 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3035 | } |
3036 | if (state->RF_IN >= 470000000 && |
3037 | state->RF_IN < 570000000) { |
3038 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
3039 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3040 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3041 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3042 | } |
3043 | if (state->RF_IN >= 570000000 && |
3044 | state->RF_IN < 620000000) { |
3045 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 0); |
3046 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3047 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3048 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3049 | } |
3050 | if (state->RF_IN >= 620000000 && |
3051 | state->RF_IN < 760000000) { |
3052 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
3053 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3054 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3055 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3056 | } |
3057 | if (state->RF_IN >= 760000000 && |
3058 | state->RF_IN <= 900000000) { |
3059 | status += MXL_ControlWrite(fe, ControlNum: DAC_A_ENABLE, value: 1); |
3060 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3061 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3062 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3063 | } |
3064 | } |
3065 | } |
3066 | |
3067 | if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ { |
3068 | |
3069 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
3070 | |
3071 | if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { |
3072 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3073 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3074 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3075 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3076 | } |
3077 | if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { |
3078 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3079 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3080 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3081 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3082 | } |
3083 | if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { |
3084 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3085 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3086 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3087 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3088 | } |
3089 | if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { |
3090 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3091 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3092 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3093 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3094 | } |
3095 | if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { |
3096 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3097 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3098 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3099 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3100 | } |
3101 | if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { |
3102 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3103 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3104 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3105 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3106 | } |
3107 | if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { |
3108 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3109 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3110 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3111 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3112 | } |
3113 | } |
3114 | |
3115 | if (state->TF_Type == MXL_TF_F) { |
3116 | |
3117 | /* Tracking Filter type F */ |
3118 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
3119 | |
3120 | if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) { |
3121 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3122 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3123 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3124 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3125 | } |
3126 | if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) { |
3127 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3128 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3129 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3130 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3131 | } |
3132 | if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) { |
3133 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3134 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3135 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3136 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3137 | } |
3138 | if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) { |
3139 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3140 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3141 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3142 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3143 | } |
3144 | if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) { |
3145 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3146 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3147 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3148 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3149 | } |
3150 | if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) { |
3151 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3152 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3153 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3154 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3155 | } |
3156 | if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) { |
3157 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3158 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3159 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3160 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3161 | } |
3162 | } |
3163 | |
3164 | if (state->TF_Type == MXL_TF_E_2) { |
3165 | |
3166 | /* Tracking Filter type E_2 */ |
3167 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
3168 | |
3169 | if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { |
3170 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3171 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3172 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3173 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3174 | } |
3175 | if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { |
3176 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3177 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3178 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3179 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3180 | } |
3181 | if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { |
3182 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3183 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3184 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3185 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3186 | } |
3187 | if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { |
3188 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3189 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3190 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3191 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3192 | } |
3193 | if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { |
3194 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3195 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3196 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3197 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3198 | } |
3199 | if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { |
3200 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3201 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3202 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3203 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3204 | } |
3205 | if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { |
3206 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3207 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3208 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3209 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3210 | } |
3211 | } |
3212 | |
3213 | if (state->TF_Type == MXL_TF_G) { |
3214 | |
3215 | /* Tracking Filter type G add for v2.6.8 */ |
3216 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
3217 | |
3218 | if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) { |
3219 | |
3220 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3221 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3222 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3223 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3224 | } |
3225 | if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) { |
3226 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3227 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3228 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3229 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3230 | } |
3231 | if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) { |
3232 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3233 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3234 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3235 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3236 | } |
3237 | if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { |
3238 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3239 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3240 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3241 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3242 | } |
3243 | if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) { |
3244 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3245 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3246 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3247 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3248 | } |
3249 | if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { |
3250 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3251 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3252 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3253 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3254 | } |
3255 | if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) { |
3256 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3257 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3258 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3259 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3260 | } |
3261 | if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) { |
3262 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3263 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3264 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3265 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3266 | } |
3267 | } |
3268 | |
3269 | if (state->TF_Type == MXL_TF_E_NA) { |
3270 | |
3271 | /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */ |
3272 | status += MXL_ControlWrite(fe, ControlNum: DAC_DIN_B, value: 0); |
3273 | |
3274 | /* if UHF and terrestrial=> Turn off Tracking Filter */ |
3275 | if (state->RF_IN >= 471000000 && |
3276 | (state->RF_IN - 471000000)%6000000 != 0) { |
3277 | |
3278 | /* Turn off all the banks */ |
3279 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3280 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3281 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3282 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3283 | |
3284 | /* 2.6.12 Turn on RSSI */ |
3285 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTSYNTHCALIF, value: 1); |
3286 | status += MXL_ControlWrite(fe, ControlNum: SEQ_EXTDCCAL, value: 1); |
3287 | status += MXL_ControlWrite(fe, ControlNum: AGC_EN_RSSI, value: 1); |
3288 | status += MXL_ControlWrite(fe, ControlNum: RFA_ENCLKRFAGC, value: 1); |
3289 | |
3290 | /* RSSI reference point */ |
3291 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFH, value: 5); |
3292 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REF, value: 3); |
3293 | status += MXL_ControlWrite(fe, ControlNum: RFA_RSSI_REFL, value: 2); |
3294 | |
3295 | /* following parameter is from analog OTA mode, |
3296 | * can be change to seek better performance */ |
3297 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, value: 3); |
3298 | } else { |
3299 | /* if VHF or Cable => Turn on Tracking Filter */ |
3300 | |
3301 | /* 2.6.12 Turn off RSSI */ |
3302 | status += MXL_ControlWrite(fe, ControlNum: AGC_EN_RSSI, value: 0); |
3303 | |
3304 | /* change back from above condition */ |
3305 | status += MXL_ControlWrite(fe, ControlNum: RFSYN_CHP_GAIN, value: 5); |
3306 | |
3307 | |
3308 | if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { |
3309 | |
3310 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3311 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3312 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3313 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3314 | } |
3315 | if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { |
3316 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3317 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 0); |
3318 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3319 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3320 | } |
3321 | if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { |
3322 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3323 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3324 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3325 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3326 | } |
3327 | if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { |
3328 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3329 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3330 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 0); |
3331 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3332 | } |
3333 | if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { |
3334 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 0); |
3335 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3336 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3337 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3338 | } |
3339 | if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { |
3340 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3341 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3342 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3343 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 0); |
3344 | } |
3345 | if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { |
3346 | status += MXL_ControlWrite(fe, ControlNum: DAC_B_ENABLE, value: 1); |
3347 | status += MXL_SetGPIO(fe, GPIO_Num: 4, GPIO_Val: 1); |
3348 | status += MXL_SetGPIO(fe, GPIO_Num: 1, GPIO_Val: 1); |
3349 | status += MXL_SetGPIO(fe, GPIO_Num: 3, GPIO_Val: 1); |
3350 | } |
3351 | } |
3352 | } |
3353 | return status ; |
3354 | } |
3355 | |
3356 | static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) |
3357 | { |
3358 | u16 status = 0; |
3359 | |
3360 | if (GPIO_Num == 1) |
3361 | status += MXL_ControlWrite(fe, ControlNum: GPIO_1B, value: GPIO_Val ? 0 : 1); |
3362 | |
3363 | /* GPIO2 is not available */ |
3364 | |
3365 | if (GPIO_Num == 3) { |
3366 | if (GPIO_Val == 1) { |
3367 | status += MXL_ControlWrite(fe, ControlNum: GPIO_3, value: 0); |
3368 | status += MXL_ControlWrite(fe, ControlNum: GPIO_3B, value: 0); |
3369 | } |
3370 | if (GPIO_Val == 0) { |
3371 | status += MXL_ControlWrite(fe, ControlNum: GPIO_3, value: 1); |
3372 | status += MXL_ControlWrite(fe, ControlNum: GPIO_3B, value: 1); |
3373 | } |
3374 | if (GPIO_Val == 3) { /* tri-state */ |
3375 | status += MXL_ControlWrite(fe, ControlNum: GPIO_3, value: 0); |
3376 | status += MXL_ControlWrite(fe, ControlNum: GPIO_3B, value: 1); |
3377 | } |
3378 | } |
3379 | if (GPIO_Num == 4) { |
3380 | if (GPIO_Val == 1) { |
3381 | status += MXL_ControlWrite(fe, ControlNum: GPIO_4, value: 0); |
3382 | status += MXL_ControlWrite(fe, ControlNum: GPIO_4B, value: 0); |
3383 | } |
3384 | if (GPIO_Val == 0) { |
3385 | status += MXL_ControlWrite(fe, ControlNum: GPIO_4, value: 1); |
3386 | status += MXL_ControlWrite(fe, ControlNum: GPIO_4B, value: 1); |
3387 | } |
3388 | if (GPIO_Val == 3) { /* tri-state */ |
3389 | status += MXL_ControlWrite(fe, ControlNum: GPIO_4, value: 0); |
3390 | status += MXL_ControlWrite(fe, ControlNum: GPIO_4B, value: 1); |
3391 | } |
3392 | } |
3393 | |
3394 | return status; |
3395 | } |
3396 | |
3397 | static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) |
3398 | { |
3399 | u16 status = 0; |
3400 | |
3401 | /* Will write ALL Matching Control Name */ |
3402 | /* Write Matching INIT Control */ |
3403 | status += MXL_ControlWrite_Group(fe, controlNum: ControlNum, value, controlGroup: 1); |
3404 | /* Write Matching CH Control */ |
3405 | status += MXL_ControlWrite_Group(fe, controlNum: ControlNum, value, controlGroup: 2); |
3406 | #ifdef _MXL_INTERNAL |
3407 | /* Write Matching MXL Control */ |
3408 | status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); |
3409 | #endif |
3410 | return status; |
3411 | } |
3412 | |
3413 | static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, |
3414 | u32 value, u16 controlGroup) |
3415 | { |
3416 | struct mxl5005s_state *state = fe->tuner_priv; |
3417 | u16 i, j; |
3418 | u32 highLimit; |
3419 | |
3420 | if (controlGroup == 1) /* Initial Control */ { |
3421 | |
3422 | for (i = 0; i < state->Init_Ctrl_Num; i++) { |
3423 | |
3424 | if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { |
3425 | |
3426 | u16 size = min_t(u16, state->Init_Ctrl[i].size, |
3427 | ARRAY_SIZE(state->Init_Ctrl[i].val)); |
3428 | highLimit = 1 << size; |
3429 | if (value < highLimit) { |
3430 | for (j = 0; j < size; j++) { |
3431 | state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); |
3432 | MXL_RegWriteBit(fe, address: (u8)(state->Init_Ctrl[i].addr[j]), |
3433 | bit: (u8)(state->Init_Ctrl[i].bit[j]), |
3434 | bitVal: (u8)((value>>j) & 0x01)); |
3435 | } |
3436 | } else |
3437 | return -1; |
3438 | } |
3439 | } |
3440 | } |
3441 | if (controlGroup == 2) /* Chan change Control */ { |
3442 | |
3443 | for (i = 0; i < state->CH_Ctrl_Num; i++) { |
3444 | |
3445 | if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { |
3446 | |
3447 | u16 size = min_t(u16, state->CH_Ctrl[i].size, |
3448 | ARRAY_SIZE(state->CH_Ctrl[i].val)); |
3449 | highLimit = 1 << size; |
3450 | if (value < highLimit) { |
3451 | for (j = 0; j < size; j++) { |
3452 | state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); |
3453 | MXL_RegWriteBit(fe, address: (u8)(state->CH_Ctrl[i].addr[j]), |
3454 | bit: (u8)(state->CH_Ctrl[i].bit[j]), |
3455 | bitVal: (u8)((value>>j) & 0x01)); |
3456 | } |
3457 | } else |
3458 | return -1; |
3459 | } |
3460 | } |
3461 | } |
3462 | #ifdef _MXL_INTERNAL |
3463 | if (controlGroup == 3) /* Maxlinear Control */ { |
3464 | |
3465 | for (i = 0; i < state->MXL_Ctrl_Num; i++) { |
3466 | |
3467 | if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { |
3468 | |
3469 | highLimit = (1 << state->MXL_Ctrl[i].size); |
3470 | if (value < highLimit) { |
3471 | for (j = 0; j < state->MXL_Ctrl[i].size; j++) { |
3472 | state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); |
3473 | MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), |
3474 | (u8)(state->MXL_Ctrl[i].bit[j]), |
3475 | (u8)((value>>j) & 0x01)); |
3476 | } |
3477 | } else |
3478 | return -1; |
3479 | } |
3480 | } |
3481 | } |
3482 | #endif |
3483 | return 0 ; /* successful return */ |
3484 | } |
3485 | |
3486 | static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) |
3487 | { |
3488 | struct mxl5005s_state *state = fe->tuner_priv; |
3489 | int i ; |
3490 | |
3491 | for (i = 0; i < 104; i++) { |
3492 | if (RegNum == state->TunerRegs[i].Reg_Num) { |
3493 | *RegVal = (u8)(state->TunerRegs[i].Reg_Val); |
3494 | return 0; |
3495 | } |
3496 | } |
3497 | |
3498 | return 1; |
3499 | } |
3500 | |
3501 | static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) |
3502 | { |
3503 | struct mxl5005s_state *state = fe->tuner_priv; |
3504 | u32 ctrlVal ; |
3505 | u16 i, k ; |
3506 | |
3507 | for (i = 0; i < state->Init_Ctrl_Num ; i++) { |
3508 | |
3509 | if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { |
3510 | |
3511 | ctrlVal = 0; |
3512 | for (k = 0; k < state->Init_Ctrl[i].size; k++) |
3513 | ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k); |
3514 | *value = ctrlVal; |
3515 | return 0; |
3516 | } |
3517 | } |
3518 | |
3519 | for (i = 0; i < state->CH_Ctrl_Num ; i++) { |
3520 | |
3521 | if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { |
3522 | |
3523 | ctrlVal = 0; |
3524 | for (k = 0; k < state->CH_Ctrl[i].size; k++) |
3525 | ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); |
3526 | *value = ctrlVal; |
3527 | return 0; |
3528 | |
3529 | } |
3530 | } |
3531 | |
3532 | #ifdef _MXL_INTERNAL |
3533 | for (i = 0; i < state->MXL_Ctrl_Num ; i++) { |
3534 | |
3535 | if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { |
3536 | |
3537 | ctrlVal = 0; |
3538 | for (k = 0; k < state->MXL_Ctrl[i].size; k++) |
3539 | ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k); |
3540 | *value = ctrlVal; |
3541 | return 0; |
3542 | |
3543 | } |
3544 | } |
3545 | #endif |
3546 | return 1; |
3547 | } |
3548 | |
3549 | static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, |
3550 | u8 bitVal) |
3551 | { |
3552 | struct mxl5005s_state *state = fe->tuner_priv; |
3553 | int i ; |
3554 | |
3555 | const u8 AND_MAP[8] = { |
3556 | 0xFE, 0xFD, 0xFB, 0xF7, |
3557 | 0xEF, 0xDF, 0xBF, 0x7F } ; |
3558 | |
3559 | const u8 OR_MAP[8] = { |
3560 | 0x01, 0x02, 0x04, 0x08, |
3561 | 0x10, 0x20, 0x40, 0x80 } ; |
3562 | |
3563 | for (i = 0; i < state->TunerRegs_Num; i++) { |
3564 | if (state->TunerRegs[i].Reg_Num == address) { |
3565 | if (bitVal) |
3566 | state->TunerRegs[i].Reg_Val |= OR_MAP[bit]; |
3567 | else |
3568 | state->TunerRegs[i].Reg_Val &= AND_MAP[bit]; |
3569 | break ; |
3570 | } |
3571 | } |
3572 | } |
3573 | |
3574 | static u32 MXL_Ceiling(u32 value, u32 resolution) |
3575 | { |
3576 | return value / resolution + (value % resolution > 0 ? 1 : 0); |
3577 | } |
3578 | |
3579 | /* Retrieve the Initialization Registers */ |
3580 | static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, |
3581 | u8 *RegVal, int *count) |
3582 | { |
3583 | u16 status = 0; |
3584 | int i ; |
3585 | |
3586 | static const u8 RegAddr[] = { |
3587 | 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, |
3588 | 76, 77, 91, 134, 135, 137, 147, |
3589 | 156, 166, 167, 168, 25 |
3590 | }; |
3591 | |
3592 | *count = ARRAY_SIZE(RegAddr); |
3593 | |
3594 | status += MXL_BlockInit(fe); |
3595 | |
3596 | for (i = 0 ; i < *count; i++) { |
3597 | RegNum[i] = RegAddr[i]; |
3598 | status += MXL_RegRead(fe, RegNum: RegNum[i], RegVal: &RegVal[i]); |
3599 | } |
3600 | |
3601 | return status; |
3602 | } |
3603 | |
3604 | static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, |
3605 | int *count) |
3606 | { |
3607 | u16 status = 0; |
3608 | int i ; |
3609 | |
3610 | /* add 77, 166, 167, 168 register for 2.6.12 */ |
3611 | #ifdef _MXL_PRODUCTION |
3612 | static const u8 RegAddr[] = { |
3613 | 14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, |
3614 | 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 |
3615 | }; |
3616 | #else |
3617 | static const u8 RegAddr[] = { |
3618 | 14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, |
3619 | 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 |
3620 | }; |
3621 | /* |
3622 | u8 RegAddr[171]; |
3623 | for (i = 0; i <= 170; i++) |
3624 | RegAddr[i] = i; |
3625 | */ |
3626 | #endif |
3627 | |
3628 | *count = ARRAY_SIZE(RegAddr); |
3629 | |
3630 | for (i = 0 ; i < *count; i++) { |
3631 | RegNum[i] = RegAddr[i]; |
3632 | status += MXL_RegRead(fe, RegNum: RegNum[i], RegVal: &RegVal[i]); |
3633 | } |
3634 | |
3635 | return status; |
3636 | } |
3637 | |
3638 | static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, |
3639 | u8 *RegVal, int *count) |
3640 | { |
3641 | u16 status = 0; |
3642 | int i; |
3643 | |
3644 | static const u8 RegAddr[] = {43, 136}; |
3645 | |
3646 | *count = ARRAY_SIZE(RegAddr); |
3647 | |
3648 | for (i = 0; i < *count; i++) { |
3649 | RegNum[i] = RegAddr[i]; |
3650 | status += MXL_RegRead(fe, RegNum: RegNum[i], RegVal: &RegVal[i]); |
3651 | } |
3652 | |
3653 | return status; |
3654 | } |
3655 | |
3656 | static u16 MXL_GetMasterControl(u8 *MasterReg, int state) |
3657 | { |
3658 | if (state == 1) /* Load_Start */ |
3659 | *MasterReg = 0xF3; |
3660 | if (state == 2) /* Power_Down */ |
3661 | *MasterReg = 0x41; |
3662 | if (state == 3) /* Synth_Reset */ |
3663 | *MasterReg = 0xB1; |
3664 | if (state == 4) /* Seq_Off */ |
3665 | *MasterReg = 0xF1; |
3666 | |
3667 | return 0; |
3668 | } |
3669 | |
3670 | #ifdef _MXL_PRODUCTION |
3671 | static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) |
3672 | { |
3673 | struct mxl5005s_state *state = fe->tuner_priv; |
3674 | u16 status = 0 ; |
3675 | |
3676 | if (VCO_Range == 1) { |
3677 | status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); |
3678 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); |
3679 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
3680 | status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); |
3681 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); |
3682 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
3683 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); |
3684 | if (state->Mode == 0 && state->IF_Mode == 1) { |
3685 | /* Analog Low IF Mode */ |
3686 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
3687 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
3688 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); |
3689 | status += MXL_ControlWrite(fe, |
3690 | CHCAL_FRAC_MOD_RF, 180224); |
3691 | } |
3692 | if (state->Mode == 0 && state->IF_Mode == 0) { |
3693 | /* Analog Zero IF Mode */ |
3694 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
3695 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
3696 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); |
3697 | status += MXL_ControlWrite(fe, |
3698 | CHCAL_FRAC_MOD_RF, 222822); |
3699 | } |
3700 | if (state->Mode == 1) /* Digital Mode */ { |
3701 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
3702 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
3703 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); |
3704 | status += MXL_ControlWrite(fe, |
3705 | CHCAL_FRAC_MOD_RF, 229376); |
3706 | } |
3707 | } |
3708 | |
3709 | if (VCO_Range == 2) { |
3710 | status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); |
3711 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); |
3712 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
3713 | status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); |
3714 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); |
3715 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
3716 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); |
3717 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
3718 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
3719 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); |
3720 | if (state->Mode == 0 && state->IF_Mode == 1) { |
3721 | /* Analog Low IF Mode */ |
3722 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
3723 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
3724 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); |
3725 | status += MXL_ControlWrite(fe, |
3726 | CHCAL_FRAC_MOD_RF, 206438); |
3727 | } |
3728 | if (state->Mode == 0 && state->IF_Mode == 0) { |
3729 | /* Analog Zero IF Mode */ |
3730 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
3731 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
3732 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); |
3733 | status += MXL_ControlWrite(fe, |
3734 | CHCAL_FRAC_MOD_RF, 206438); |
3735 | } |
3736 | if (state->Mode == 1) /* Digital Mode */ { |
3737 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
3738 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
3739 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); |
3740 | status += MXL_ControlWrite(fe, |
3741 | CHCAL_FRAC_MOD_RF, 16384); |
3742 | } |
3743 | } |
3744 | |
3745 | if (VCO_Range == 3) { |
3746 | status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); |
3747 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); |
3748 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
3749 | status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); |
3750 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); |
3751 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
3752 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); |
3753 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
3754 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
3755 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); |
3756 | if (state->Mode == 0 && state->IF_Mode == 1) { |
3757 | /* Analog Low IF Mode */ |
3758 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
3759 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
3760 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); |
3761 | status += MXL_ControlWrite(fe, |
3762 | CHCAL_FRAC_MOD_RF, 173670); |
3763 | } |
3764 | if (state->Mode == 0 && state->IF_Mode == 0) { |
3765 | /* Analog Zero IF Mode */ |
3766 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
3767 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
3768 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); |
3769 | status += MXL_ControlWrite(fe, |
3770 | CHCAL_FRAC_MOD_RF, 173670); |
3771 | } |
3772 | if (state->Mode == 1) /* Digital Mode */ { |
3773 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
3774 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
3775 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); |
3776 | status += MXL_ControlWrite(fe, |
3777 | CHCAL_FRAC_MOD_RF, 245760); |
3778 | } |
3779 | } |
3780 | |
3781 | if (VCO_Range == 4) { |
3782 | status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); |
3783 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); |
3784 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
3785 | status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); |
3786 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); |
3787 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
3788 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); |
3789 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
3790 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
3791 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); |
3792 | if (state->Mode == 0 && state->IF_Mode == 1) { |
3793 | /* Analog Low IF Mode */ |
3794 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
3795 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
3796 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); |
3797 | status += MXL_ControlWrite(fe, |
3798 | CHCAL_FRAC_MOD_RF, 206438); |
3799 | } |
3800 | if (state->Mode == 0 && state->IF_Mode == 0) { |
3801 | /* Analog Zero IF Mode */ |
3802 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
3803 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
3804 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); |
3805 | status += MXL_ControlWrite(fe, |
3806 | CHCAL_FRAC_MOD_RF, 206438); |
3807 | } |
3808 | if (state->Mode == 1) /* Digital Mode */ { |
3809 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
3810 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
3811 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); |
3812 | status += MXL_ControlWrite(fe, |
3813 | CHCAL_FRAC_MOD_RF, 212992); |
3814 | } |
3815 | } |
3816 | |
3817 | return status; |
3818 | } |
3819 | |
3820 | static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) |
3821 | { |
3822 | struct mxl5005s_state *state = fe->tuner_priv; |
3823 | u16 status = 0; |
3824 | |
3825 | if (Hystersis == 1) |
3826 | status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1); |
3827 | |
3828 | return status; |
3829 | } |
3830 | #endif |
3831 | /* End: Reference driver code found in the Realtek driver that |
3832 | * is copyright MaxLinear */ |
3833 | |
3834 | /* ---------------------------------------------------------------- |
3835 | * Begin: Everything after here is new code to adapt the |
3836 | * proprietary Realtek driver into a Linux API tuner. |
3837 | * Copyright (C) 2008 Steven Toth <stoth@linuxtv.org> |
3838 | */ |
3839 | static int mxl5005s_reset(struct dvb_frontend *fe) |
3840 | { |
3841 | struct mxl5005s_state *state = fe->tuner_priv; |
3842 | int ret = 0; |
3843 | |
3844 | u8 buf[2] = { 0xff, 0x00 }; |
3845 | struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, |
3846 | .buf = buf, .len = 2 }; |
3847 | |
3848 | dprintk(2, "%s()\n" , __func__); |
3849 | |
3850 | if (fe->ops.i2c_gate_ctrl) |
3851 | fe->ops.i2c_gate_ctrl(fe, 1); |
3852 | |
3853 | if (i2c_transfer(adap: state->i2c, msgs: &msg, num: 1) != 1) { |
3854 | printk(KERN_WARNING "mxl5005s I2C reset failed\n" ); |
3855 | ret = -EREMOTEIO; |
3856 | } |
3857 | |
3858 | if (fe->ops.i2c_gate_ctrl) |
3859 | fe->ops.i2c_gate_ctrl(fe, 0); |
3860 | |
3861 | return ret; |
3862 | } |
3863 | |
3864 | /* Write a single byte to a single reg, latch the value if required by |
3865 | * following the transaction with the latch byte. |
3866 | */ |
3867 | static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) |
3868 | { |
3869 | struct mxl5005s_state *state = fe->tuner_priv; |
3870 | u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; |
3871 | struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, |
3872 | .buf = buf, .len = 3 }; |
3873 | |
3874 | if (latch == 0) |
3875 | msg.len = 2; |
3876 | |
3877 | dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n" , __func__, reg, val, msg.addr); |
3878 | |
3879 | if (i2c_transfer(adap: state->i2c, msgs: &msg, num: 1) != 1) { |
3880 | printk(KERN_WARNING "mxl5005s I2C write failed\n" ); |
3881 | return -EREMOTEIO; |
3882 | } |
3883 | return 0; |
3884 | } |
3885 | |
3886 | static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, |
3887 | u8 *datatable, u8 len) |
3888 | { |
3889 | int ret = 0, i; |
3890 | |
3891 | if (fe->ops.i2c_gate_ctrl) |
3892 | fe->ops.i2c_gate_ctrl(fe, 1); |
3893 | |
3894 | for (i = 0 ; i < len-1; i++) { |
3895 | ret = mxl5005s_writereg(fe, reg: addrtable[i], val: datatable[i], latch: 0); |
3896 | if (ret < 0) |
3897 | break; |
3898 | } |
3899 | |
3900 | ret = mxl5005s_writereg(fe, reg: addrtable[i], val: datatable[i], latch: 1); |
3901 | |
3902 | if (fe->ops.i2c_gate_ctrl) |
3903 | fe->ops.i2c_gate_ctrl(fe, 0); |
3904 | |
3905 | return ret; |
3906 | } |
3907 | |
3908 | static int mxl5005s_init(struct dvb_frontend *fe) |
3909 | { |
3910 | struct mxl5005s_state *state = fe->tuner_priv; |
3911 | |
3912 | dprintk(1, "%s()\n" , __func__); |
3913 | state->current_mode = MXL_QAM; |
3914 | return mxl5005s_reconfigure(fe, mod_type: MXL_QAM, bandwidth: MXL5005S_BANDWIDTH_6MHZ); |
3915 | } |
3916 | |
3917 | static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, |
3918 | u32 bandwidth) |
3919 | { |
3920 | struct mxl5005s_state *state = fe->tuner_priv; |
3921 | u8 *AddrTable; |
3922 | u8 *ByteTable; |
3923 | int TableLen; |
3924 | |
3925 | dprintk(1, "%s(type=%d, bw=%d)\n" , __func__, mod_type, bandwidth); |
3926 | |
3927 | mxl5005s_reset(fe); |
3928 | |
3929 | AddrTable = kcalloc(MXL5005S_REG_WRITING_TABLE_LEN_MAX, size: sizeof(u8), |
3930 | GFP_KERNEL); |
3931 | if (!AddrTable) |
3932 | return -ENOMEM; |
3933 | |
3934 | ByteTable = kcalloc(MXL5005S_REG_WRITING_TABLE_LEN_MAX, size: sizeof(u8), |
3935 | GFP_KERNEL); |
3936 | if (!ByteTable) { |
3937 | kfree(objp: AddrTable); |
3938 | return -ENOMEM; |
3939 | } |
3940 | |
3941 | /* Tuner initialization stage 0 */ |
3942 | MXL_GetMasterControl(MasterReg: ByteTable, state: MC_SYNTH_RESET); |
3943 | AddrTable[0] = MASTER_CONTROL_ADDR; |
3944 | ByteTable[0] |= state->config->AgcMasterByte; |
3945 | |
3946 | mxl5005s_writeregs(fe, addrtable: AddrTable, datatable: ByteTable, len: 1); |
3947 | |
3948 | mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); |
3949 | |
3950 | /* Tuner initialization stage 1 */ |
3951 | MXL_GetInitRegister(fe, RegNum: AddrTable, RegVal: ByteTable, count: &TableLen); |
3952 | |
3953 | mxl5005s_writeregs(fe, addrtable: AddrTable, datatable: ByteTable, len: TableLen); |
3954 | |
3955 | kfree(objp: AddrTable); |
3956 | kfree(objp: ByteTable); |
3957 | |
3958 | return 0; |
3959 | } |
3960 | |
3961 | static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, |
3962 | u32 bandwidth) |
3963 | { |
3964 | struct mxl5005s_state *state = fe->tuner_priv; |
3965 | struct mxl5005s_config *c = state->config; |
3966 | |
3967 | InitTunerControls(fe); |
3968 | |
3969 | /* Set MxL5005S parameters. */ |
3970 | MXL5005_TunerConfig( |
3971 | fe, |
3972 | Mode: c->mod_mode, |
3973 | IF_mode: c->if_mode, |
3974 | Bandwidth: bandwidth, |
3975 | IF_out: c->if_freq, |
3976 | Fxtal: c->xtal_freq, |
3977 | AGC_Mode: c->agc_mode, |
3978 | TOP: c->top, |
3979 | IF_OUT_LOAD: c->output_load, |
3980 | CLOCK_OUT: c->clock_out, |
3981 | DIV_OUT: c->div_out, |
3982 | CAPSELECT: c->cap_select, |
3983 | EN_RSSI: c->rssi_enable, |
3984 | Mod_Type: mod_type, |
3985 | TF_Type: c->tracking_filter); |
3986 | |
3987 | return 0; |
3988 | } |
3989 | |
3990 | static int mxl5005s_set_params(struct dvb_frontend *fe) |
3991 | { |
3992 | struct mxl5005s_state *state = fe->tuner_priv; |
3993 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
3994 | u32 delsys = c->delivery_system; |
3995 | u32 bw = c->bandwidth_hz; |
3996 | u32 req_mode, req_bw = 0; |
3997 | int ret; |
3998 | |
3999 | dprintk(1, "%s()\n" , __func__); |
4000 | |
4001 | switch (delsys) { |
4002 | case SYS_ATSC: |
4003 | req_mode = MXL_ATSC; |
4004 | req_bw = MXL5005S_BANDWIDTH_6MHZ; |
4005 | break; |
4006 | case SYS_DVBC_ANNEX_B: |
4007 | req_mode = MXL_QAM; |
4008 | req_bw = MXL5005S_BANDWIDTH_6MHZ; |
4009 | break; |
4010 | default: /* Assume DVB-T */ |
4011 | req_mode = MXL_DVBT; |
4012 | switch (bw) { |
4013 | case 6000000: |
4014 | req_bw = MXL5005S_BANDWIDTH_6MHZ; |
4015 | break; |
4016 | case 7000000: |
4017 | req_bw = MXL5005S_BANDWIDTH_7MHZ; |
4018 | break; |
4019 | case 8000000: |
4020 | case 0: |
4021 | req_bw = MXL5005S_BANDWIDTH_8MHZ; |
4022 | break; |
4023 | default: |
4024 | return -EINVAL; |
4025 | } |
4026 | } |
4027 | |
4028 | /* Change tuner for new modulation type if reqd */ |
4029 | if (req_mode != state->current_mode || |
4030 | req_bw != state->Chan_Bandwidth) { |
4031 | state->current_mode = req_mode; |
4032 | ret = mxl5005s_reconfigure(fe, mod_type: req_mode, bandwidth: req_bw); |
4033 | |
4034 | } else |
4035 | ret = 0; |
4036 | |
4037 | if (ret == 0) { |
4038 | dprintk(1, "%s() freq=%d\n" , __func__, c->frequency); |
4039 | ret = mxl5005s_SetRfFreqHz(fe, RfFreqHz: c->frequency); |
4040 | } |
4041 | |
4042 | return ret; |
4043 | } |
4044 | |
4045 | static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) |
4046 | { |
4047 | struct mxl5005s_state *state = fe->tuner_priv; |
4048 | dprintk(1, "%s()\n" , __func__); |
4049 | |
4050 | *frequency = state->RF_IN; |
4051 | |
4052 | return 0; |
4053 | } |
4054 | |
4055 | static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) |
4056 | { |
4057 | struct mxl5005s_state *state = fe->tuner_priv; |
4058 | dprintk(1, "%s()\n" , __func__); |
4059 | |
4060 | *bandwidth = state->Chan_Bandwidth; |
4061 | |
4062 | return 0; |
4063 | } |
4064 | |
4065 | static int mxl5005s_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) |
4066 | { |
4067 | struct mxl5005s_state *state = fe->tuner_priv; |
4068 | dprintk(1, "%s()\n" , __func__); |
4069 | |
4070 | *frequency = state->IF_OUT; |
4071 | |
4072 | return 0; |
4073 | } |
4074 | |
4075 | static void mxl5005s_release(struct dvb_frontend *fe) |
4076 | { |
4077 | dprintk(1, "%s()\n" , __func__); |
4078 | kfree(objp: fe->tuner_priv); |
4079 | fe->tuner_priv = NULL; |
4080 | } |
4081 | |
4082 | static const struct dvb_tuner_ops mxl5005s_tuner_ops = { |
4083 | .info = { |
4084 | .name = "MaxLinear MXL5005S" , |
4085 | .frequency_min_hz = 48 * MHz, |
4086 | .frequency_max_hz = 860 * MHz, |
4087 | .frequency_step_hz = 50 * kHz, |
4088 | }, |
4089 | |
4090 | .release = mxl5005s_release, |
4091 | .init = mxl5005s_init, |
4092 | |
4093 | .set_params = mxl5005s_set_params, |
4094 | .get_frequency = mxl5005s_get_frequency, |
4095 | .get_bandwidth = mxl5005s_get_bandwidth, |
4096 | .get_if_frequency = mxl5005s_get_if_frequency, |
4097 | }; |
4098 | |
4099 | struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, |
4100 | struct i2c_adapter *i2c, |
4101 | struct mxl5005s_config *config) |
4102 | { |
4103 | struct mxl5005s_state *state = NULL; |
4104 | dprintk(1, "%s()\n" , __func__); |
4105 | |
4106 | state = kzalloc(size: sizeof(struct mxl5005s_state), GFP_KERNEL); |
4107 | if (state == NULL) |
4108 | return NULL; |
4109 | |
4110 | state->frontend = fe; |
4111 | state->config = config; |
4112 | state->i2c = i2c; |
4113 | |
4114 | printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n" , |
4115 | config->i2c_address); |
4116 | |
4117 | memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, |
4118 | sizeof(struct dvb_tuner_ops)); |
4119 | |
4120 | fe->tuner_priv = state; |
4121 | return fe; |
4122 | } |
4123 | EXPORT_SYMBOL_GPL(mxl5005s_attach); |
4124 | |
4125 | MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver" ); |
4126 | MODULE_AUTHOR("Steven Toth" ); |
4127 | MODULE_LICENSE("GPL" ); |
4128 | |