| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | |
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| 3 | /* |
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| 4 | * em28xx-reg.h - Register definitions for em28xx driver |
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| 5 | */ |
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| 6 | |
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| 7 | #define EM_GPIO_0 ((unsigned char)BIT(0)) |
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| 8 | #define EM_GPIO_1 ((unsigned char)BIT(1)) |
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| 9 | #define EM_GPIO_2 ((unsigned char)BIT(2)) |
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| 10 | #define EM_GPIO_3 ((unsigned char)BIT(3)) |
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| 11 | #define EM_GPIO_4 ((unsigned char)BIT(4)) |
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| 12 | #define EM_GPIO_5 ((unsigned char)BIT(5)) |
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| 13 | #define EM_GPIO_6 ((unsigned char)BIT(6)) |
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| 14 | #define EM_GPIO_7 ((unsigned char)BIT(7)) |
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| 15 | |
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| 16 | #define EM_GPO_0 ((unsigned char)BIT(0)) |
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| 17 | #define EM_GPO_1 ((unsigned char)BIT(1)) |
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| 18 | #define EM_GPO_2 ((unsigned char)BIT(2)) |
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| 19 | #define EM_GPO_3 ((unsigned char)BIT(3)) |
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| 20 | |
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| 21 | /* em28xx endpoints */ |
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| 22 | /* 0x82: (always ?) analog */ |
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| 23 | #define EM28XX_EP_AUDIO 0x83 |
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| 24 | /* 0x84: digital or analog */ |
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| 25 | |
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| 26 | /* em2800 registers */ |
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| 27 | #define EM2800_R08_AUDIOSRC 0x08 |
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| 28 | |
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| 29 | /* em28xx registers */ |
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| 30 | |
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| 31 | #define EM28XX_R00_CHIPCFG 0x00 |
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| 32 | |
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| 33 | /* em28xx Chip Configuration 0x00 */ |
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| 34 | #define EM2860_CHIPCFG_VENDOR_AUDIO 0x80 |
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| 35 | #define EM2860_CHIPCFG_I2S_VOLUME_CAPABLE 0x40 |
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| 36 | #define EM2820_CHIPCFG_I2S_3_SAMPRATES 0x30 |
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| 37 | #define EM2860_CHIPCFG_I2S_5_SAMPRATES 0x30 |
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| 38 | #define EM2820_CHIPCFG_I2S_1_SAMPRATE 0x20 |
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| 39 | #define EM2860_CHIPCFG_I2S_3_SAMPRATES 0x20 |
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| 40 | #define EM28XX_CHIPCFG_AC97 0x10 |
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| 41 | #define EM28XX_CHIPCFG_AUDIOMASK 0x30 |
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| 42 | |
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| 43 | #define EM28XX_R01_CHIPCFG2 0x01 |
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| 44 | |
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| 45 | /* em28xx Chip Configuration 2 0x01 */ |
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| 46 | #define EM28XX_CHIPCFG2_TS_PRESENT 0x10 |
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| 47 | #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK 0x0c /* bits 3-2 */ |
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| 48 | #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF 0x00 |
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| 49 | #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF 0x04 |
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| 50 | #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF 0x08 |
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| 51 | #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF 0x0c |
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| 52 | #define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK 0x03 /* bits 0-1 */ |
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| 53 | #define EM28XX_CHIPCFG2_TS_PACKETSIZE_188 0x00 |
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| 54 | #define EM28XX_CHIPCFG2_TS_PACKETSIZE_376 0x01 |
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| 55 | #define EM28XX_CHIPCFG2_TS_PACKETSIZE_564 0x02 |
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| 56 | #define EM28XX_CHIPCFG2_TS_PACKETSIZE_752 0x03 |
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| 57 | |
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| 58 | /* GPIO/GPO registers */ |
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| 59 | #define EM2880_R04_GPO 0x04 /* em2880-em2883 only */ |
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| 60 | #define EM2820_R08_GPIO_CTRL 0x08 /* em2820-em2873/83 only */ |
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| 61 | #define EM2820_R09_GPIO_STATE 0x09 /* em2820-em2873/83 only */ |
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| 62 | |
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| 63 | #define EM28XX_R06_I2C_CLK 0x06 |
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| 64 | |
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| 65 | /* em28xx I2C Clock Register (0x06) */ |
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| 66 | #define EM28XX_I2C_CLK_ACK_LAST_READ 0x80 |
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| 67 | #define EM28XX_I2C_CLK_WAIT_ENABLE 0x40 |
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| 68 | #define EM28XX_I2C_EEPROM_ON_BOARD 0x08 |
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| 69 | #define EM28XX_I2C_EEPROM_KEY_VALID 0x04 |
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| 70 | #define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c buses */ |
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| 71 | #define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */ |
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| 72 | #define EM28XX_I2C_FREQ_25_KHZ 0x02 |
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| 73 | #define EM28XX_I2C_FREQ_400_KHZ 0x01 |
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| 74 | #define EM28XX_I2C_FREQ_100_KHZ 0x00 |
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| 75 | |
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| 76 | #define EM28XX_R0A_CHIPID 0x0a |
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| 77 | #define EM28XX_R0C_USBSUSP 0x0c |
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| 78 | #define EM28XX_R0C_USBSUSP_SNAPSHOT 0x20 /* 1=button pressed, needs reset */ |
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| 79 | |
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| 80 | #define EM28XX_R0E_AUDIOSRC 0x0e |
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| 81 | #define EM28XX_R0F_XCLK 0x0f |
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| 82 | |
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| 83 | /* em28xx XCLK Register (0x0f) */ |
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| 84 | #define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */ |
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| 85 | #define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */ |
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| 86 | #define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */ |
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| 87 | #define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x10 |
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| 88 | #define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */ |
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| 89 | #define EM28XX_XCLK_FREQUENCY_15MHZ 0x01 |
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| 90 | #define EM28XX_XCLK_FREQUENCY_10MHZ 0x02 |
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| 91 | #define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x03 |
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| 92 | #define EM28XX_XCLK_FREQUENCY_6MHZ 0x04 |
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| 93 | #define EM28XX_XCLK_FREQUENCY_5MHZ 0x05 |
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| 94 | #define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x06 |
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| 95 | #define EM28XX_XCLK_FREQUENCY_12MHZ 0x07 |
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| 96 | #define EM28XX_XCLK_FREQUENCY_20MHZ 0x08 |
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| 97 | #define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x09 |
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| 98 | #define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a |
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| 99 | #define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b |
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| 100 | |
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| 101 | #define EM28XX_R10_VINMODE 0x10 |
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| 102 | /* used by all non-camera devices: */ |
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| 103 | #define EM28XX_VINMODE_YUV422_CbYCrY 0x10 |
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| 104 | /* used by camera devices: */ |
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| 105 | #define EM28XX_VINMODE_YUV422_YUYV 0x08 |
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| 106 | #define EM28XX_VINMODE_YUV422_YVYU 0x09 |
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| 107 | #define EM28XX_VINMODE_YUV422_UYVY 0x0a |
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| 108 | #define EM28XX_VINMODE_YUV422_VYUY 0x0b |
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| 109 | #define EM28XX_VINMODE_RGB8_BGGR 0x0c |
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| 110 | #define EM28XX_VINMODE_RGB8_GRBG 0x0d |
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| 111 | #define EM28XX_VINMODE_RGB8_GBRG 0x0e |
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| 112 | #define EM28XX_VINMODE_RGB8_RGGB 0x0f |
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| 113 | /* |
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| 114 | * apparently: |
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| 115 | * bit 0: swap component 1+2 with 3+4 |
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| 116 | * => e.g.: YUYV => YVYU, BGGR => GRBG |
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| 117 | * bit 1: swap component 1 with 2 and 3 with 4 |
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| 118 | * => e.g.: YUYV => UYVY, BGGR => GBRG |
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| 119 | */ |
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| 120 | |
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| 121 | #define EM28XX_R11_VINCTRL 0x11 |
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| 122 | |
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| 123 | /* em28xx Video Input Control Register 0x11 */ |
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| 124 | #define EM28XX_VINCTRL_VBI_SLICED 0x80 |
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| 125 | #define EM28XX_VINCTRL_VBI_RAW 0x40 |
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| 126 | #define EM28XX_VINCTRL_VOUT_MODE_IN 0x20 /* HREF,VREF,VACT in output */ |
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| 127 | #define EM28XX_VINCTRL_CCIR656_ENABLE 0x10 |
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| 128 | #define EM28XX_VINCTRL_VBI_16BIT_RAW 0x08 /* otherwise 8-bit raw */ |
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| 129 | #define EM28XX_VINCTRL_FID_ON_HREF 0x04 |
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| 130 | #define EM28XX_VINCTRL_DUAL_EDGE_STROBE 0x02 |
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| 131 | #define EM28XX_VINCTRL_INTERLACED 0x01 |
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| 132 | |
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| 133 | #define EM28XX_R12_VINENABLE 0x12 /* */ |
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| 134 | |
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| 135 | #define EM28XX_R14_GAMMA 0x14 |
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| 136 | #define EM28XX_R15_RGAIN 0x15 |
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| 137 | #define EM28XX_R16_GGAIN 0x16 |
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| 138 | #define EM28XX_R17_BGAIN 0x17 |
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| 139 | #define EM28XX_R18_ROFFSET 0x18 |
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| 140 | #define EM28XX_R19_GOFFSET 0x19 |
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| 141 | #define EM28XX_R1A_BOFFSET 0x1a |
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| 142 | |
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| 143 | #define EM28XX_R1B_OFLOW 0x1b |
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| 144 | #define EM28XX_R1C_HSTART 0x1c |
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| 145 | #define EM28XX_R1D_VSTART 0x1d |
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| 146 | #define EM28XX_R1E_CWIDTH 0x1e |
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| 147 | #define EM28XX_R1F_CHEIGHT 0x1f |
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| 148 | |
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| 149 | #define EM28XX_R20_YGAIN 0x20 /* contrast [0:4] */ |
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| 150 | #define CONTRAST_DEFAULT 0x10 |
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| 151 | |
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| 152 | #define EM28XX_R21_YOFFSET 0x21 /* brightness */ /* signed */ |
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| 153 | #define BRIGHTNESS_DEFAULT 0x00 |
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| 154 | |
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| 155 | #define EM28XX_R22_UVGAIN 0x22 /* saturation [0:4] */ |
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| 156 | #define SATURATION_DEFAULT 0x10 |
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| 157 | |
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| 158 | #define EM28XX_R23_UOFFSET 0x23 /* blue balance */ /* signed */ |
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| 159 | #define BLUE_BALANCE_DEFAULT 0x00 |
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| 160 | |
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| 161 | #define EM28XX_R24_VOFFSET 0x24 /* red balance */ /* signed */ |
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| 162 | #define RED_BALANCE_DEFAULT 0x00 |
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| 163 | |
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| 164 | #define EM28XX_R25_SHARPNESS 0x25 /* sharpness [0:4] */ |
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| 165 | #define SHARPNESS_DEFAULT 0x00 |
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| 166 | |
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| 167 | #define EM28XX_R26_COMPR 0x26 |
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| 168 | #define EM28XX_R27_OUTFMT 0x27 |
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| 169 | |
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| 170 | /* em28xx Output Format Register (0x27) */ |
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| 171 | #define EM28XX_OUTFMT_RGB_8_RGRG 0x00 |
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| 172 | #define EM28XX_OUTFMT_RGB_8_GRGR 0x01 |
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| 173 | #define EM28XX_OUTFMT_RGB_8_GBGB 0x02 |
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| 174 | #define EM28XX_OUTFMT_RGB_8_BGBG 0x03 |
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| 175 | #define EM28XX_OUTFMT_RGB_16_656 0x04 |
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| 176 | #define EM28XX_OUTFMT_RGB_8_BAYER 0x08 /* Pattern in Reg 0x10[1-0] */ |
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| 177 | #define EM28XX_OUTFMT_YUV211 0x10 |
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| 178 | #define EM28XX_OUTFMT_YUV422_Y0UY1V 0x14 |
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| 179 | #define EM28XX_OUTFMT_YUV422_Y1UY0V 0x15 |
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| 180 | #define EM28XX_OUTFMT_YUV411 0x18 |
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| 181 | |
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| 182 | #define EM28XX_R28_XMIN 0x28 |
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| 183 | #define EM28XX_R29_XMAX 0x29 |
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| 184 | #define EM28XX_R2A_YMIN 0x2a |
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| 185 | #define EM28XX_R2B_YMAX 0x2b |
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| 186 | |
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| 187 | #define EM28XX_R30_HSCALELOW 0x30 |
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| 188 | #define EM28XX_R31_HSCALEHIGH 0x31 |
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| 189 | #define EM28XX_R32_VSCALELOW 0x32 |
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| 190 | #define EM28XX_R33_VSCALEHIGH 0x33 |
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| 191 | #define EM28XX_HVSCALE_MAX 0x3fff /* => 20% */ |
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| 192 | |
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| 193 | #define EM28XX_R34_VBI_START_H 0x34 |
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| 194 | #define EM28XX_R35_VBI_START_V 0x35 |
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| 195 | /* |
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| 196 | * NOTE: the EM276x (and EM25xx, EM277x/8x ?) (camera bridges) use these |
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| 197 | * registers for a different unknown purpose. |
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| 198 | * => register 0x34 is set to capture width / 16 |
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| 199 | * => register 0x35 is set to capture height / 16 |
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| 200 | */ |
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| 201 | |
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| 202 | #define EM28XX_R36_VBI_WIDTH 0x36 |
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| 203 | #define EM28XX_R37_VBI_HEIGHT 0x37 |
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| 204 | |
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| 205 | #define EM28XX_R40_AC97LSB 0x40 |
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| 206 | #define EM28XX_R41_AC97MSB 0x41 |
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| 207 | #define EM28XX_R42_AC97ADDR 0x42 |
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| 208 | #define EM28XX_R43_AC97BUSY 0x43 |
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| 209 | |
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| 210 | #define EM28XX_R45_IR 0x45 |
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| 211 | /* |
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| 212 | * 0x45 bit 7 - parity bit |
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| 213 | * bits 6-0 - count |
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| 214 | * 0x46 IR brand |
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| 215 | * 0x47 IR data |
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| 216 | */ |
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| 217 | |
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| 218 | /* em2874 registers */ |
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| 219 | #define EM2874_R50_IR_CONFIG 0x50 |
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| 220 | #define EM2874_R51_IR 0x51 |
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| 221 | #define EM2874_R5D_TS1_PKT_SIZE 0x5d |
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| 222 | #define EM2874_R5E_TS2_PKT_SIZE 0x5e |
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| 223 | /* |
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| 224 | * For both TS1 and TS2, In isochronous mode: |
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| 225 | * 0x01 188 bytes |
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| 226 | * 0x02 376 bytes |
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| 227 | * 0x03 564 bytes |
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| 228 | * 0x04 752 bytes |
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| 229 | * 0x05 940 bytes |
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| 230 | * In bulk mode: |
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| 231 | * 0x01..0xff total packet count in 188-byte |
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| 232 | */ |
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| 233 | |
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| 234 | #define EM2874_R5F_TS_ENABLE 0x5f |
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| 235 | |
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| 236 | /* em2874/174/84, em25xx, em276x/7x/8x GPIO registers */ |
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| 237 | /* |
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| 238 | * NOTE: not all ports are bonded out; |
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| 239 | * Some ports are multiplexed with special function I/O |
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| 240 | */ |
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| 241 | #define EM2874_R80_GPIO_P0_CTRL 0x80 |
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| 242 | #define EM2874_R81_GPIO_P1_CTRL 0x81 |
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| 243 | #define EM2874_R82_GPIO_P2_CTRL 0x82 |
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| 244 | #define EM2874_R83_GPIO_P3_CTRL 0x83 |
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| 245 | #define EM2874_R84_GPIO_P0_STATE 0x84 |
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| 246 | #define EM2874_R85_GPIO_P1_STATE 0x85 |
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| 247 | #define EM2874_R86_GPIO_P2_STATE 0x86 |
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| 248 | #define EM2874_R87_GPIO_P3_STATE 0x87 |
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| 249 | |
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| 250 | /* em2874 IR config register (0x50) */ |
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| 251 | #define EM2874_IR_NEC 0x00 |
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| 252 | #define EM2874_IR_NEC_NO_PARITY 0x01 |
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| 253 | #define EM2874_IR_RC5 0x04 |
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| 254 | #define EM2874_IR_RC6_MODE_0 0x08 |
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| 255 | #define EM2874_IR_RC6_MODE_6A 0x0b |
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| 256 | |
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| 257 | /* em2874 Transport Stream Enable Register (0x5f) */ |
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| 258 | #define EM2874_TS1_CAPTURE_ENABLE ((unsigned char)BIT(0)) |
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| 259 | #define EM2874_TS1_FILTER_ENABLE ((unsigned char)BIT(1)) |
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| 260 | #define EM2874_TS1_NULL_DISCARD ((unsigned char)BIT(2)) |
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| 261 | #define EM2874_TS2_CAPTURE_ENABLE ((unsigned char)BIT(4)) |
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| 262 | #define EM2874_TS2_FILTER_ENABLE ((unsigned char)BIT(5)) |
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| 263 | #define EM2874_TS2_NULL_DISCARD ((unsigned char)BIT(6)) |
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| 264 | |
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| 265 | /* register settings */ |
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| 266 | #define EM2800_AUDIO_SRC_TUNER 0x0d |
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| 267 | #define EM2800_AUDIO_SRC_LINE 0x0c |
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| 268 | #define EM28XX_AUDIO_SRC_TUNER 0xc0 |
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| 269 | #define EM28XX_AUDIO_SRC_LINE 0x80 |
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| 270 | |
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| 271 | /* FIXME: Need to be populated with the other chip ID's */ |
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| 272 | enum em28xx_chip_id { |
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| 273 | CHIP_ID_EM2800 = 7, |
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| 274 | CHIP_ID_EM2710 = 17, |
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| 275 | CHIP_ID_EM2820 = 18, /* Also used by some em2710 */ |
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| 276 | CHIP_ID_EM2840 = 20, |
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| 277 | CHIP_ID_EM2750 = 33, |
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| 278 | CHIP_ID_EM2860 = 34, |
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| 279 | CHIP_ID_EM2870 = 35, |
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| 280 | CHIP_ID_EM2883 = 36, |
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| 281 | CHIP_ID_EM2765 = 54, |
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| 282 | CHIP_ID_EM2874 = 65, |
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| 283 | CHIP_ID_EM2884 = 68, |
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| 284 | CHIP_ID_EM28174 = 113, |
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| 285 | CHIP_ID_EM28178 = 114, |
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| 286 | }; |
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| 287 | |
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| 288 | /* |
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| 289 | * Registers used by em202 |
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| 290 | */ |
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| 291 | |
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| 292 | /* EMP202 vendor registers */ |
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| 293 | #define EM202_EXT_MODEM_CTRL 0x3e |
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| 294 | #define EM202_GPIO_CONF 0x4c |
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| 295 | #define EM202_GPIO_POLARITY 0x4e |
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| 296 | #define EM202_GPIO_STICKY 0x50 |
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| 297 | #define EM202_GPIO_MASK 0x52 |
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| 298 | #define EM202_GPIO_STATUS 0x54 |
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| 299 | #define EM202_SPDIF_OUT_SEL 0x6a |
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| 300 | #define EM202_ANTIPOP 0x72 |
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| 301 | #define EM202_EAPD_GPIO_ACCESS 0x74 |
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| 302 | |
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