| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * GSPCA Endpoints (formerly known as AOX) se401 USB Camera sub Driver |
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| 4 | * |
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| 5 | * Copyright (C) 2011 Hans de Goede <hdegoede@redhat.com> |
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| 6 | * |
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| 7 | * Based on the v4l1 se401 driver which is: |
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| 8 | * |
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| 9 | * Copyright (c) 2000 Jeroen B. Vreeken (pe1rxq@amsat.org) |
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| 10 | */ |
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| 11 | |
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| 12 | #define SE401_REQ_GET_CAMERA_DESCRIPTOR 0x06 |
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| 13 | #define SE401_REQ_START_CONTINUOUS_CAPTURE 0x41 |
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| 14 | #define SE401_REQ_STOP_CONTINUOUS_CAPTURE 0x42 |
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| 15 | #define SE401_REQ_CAPTURE_FRAME 0x43 |
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| 16 | #define SE401_REQ_GET_BRT 0x44 |
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| 17 | #define SE401_REQ_SET_BRT 0x45 |
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| 18 | #define SE401_REQ_GET_WIDTH 0x4c |
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| 19 | #define SE401_REQ_SET_WIDTH 0x4d |
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| 20 | #define SE401_REQ_GET_HEIGHT 0x4e |
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| 21 | #define SE401_REQ_SET_HEIGHT 0x4f |
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| 22 | #define SE401_REQ_GET_OUTPUT_MODE 0x50 |
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| 23 | #define SE401_REQ_SET_OUTPUT_MODE 0x51 |
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| 24 | #define SE401_REQ_GET_EXT_FEATURE 0x52 |
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| 25 | #define SE401_REQ_SET_EXT_FEATURE 0x53 |
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| 26 | #define SE401_REQ_CAMERA_POWER 0x56 |
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| 27 | #define SE401_REQ_LED_CONTROL 0x57 |
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| 28 | #define SE401_REQ_BIOS 0xff |
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| 29 | |
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| 30 | #define SE401_BIOS_READ 0x07 |
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| 31 | |
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| 32 | #define SE401_FORMAT_BAYER 0x40 |
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| 33 | |
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| 34 | /* Hyundai hv7131b registers |
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| 35 | 7121 and 7141 should be the same (haven't really checked...) */ |
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| 36 | /* Mode registers: */ |
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| 37 | #define HV7131_REG_MODE_A 0x00 |
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| 38 | #define HV7131_REG_MODE_B 0x01 |
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| 39 | #define HV7131_REG_MODE_C 0x02 |
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| 40 | /* Frame registers: */ |
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| 41 | #define HV7131_REG_FRSU 0x10 |
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| 42 | #define HV7131_REG_FRSL 0x11 |
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| 43 | #define HV7131_REG_FCSU 0x12 |
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| 44 | #define HV7131_REG_FCSL 0x13 |
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| 45 | #define HV7131_REG_FWHU 0x14 |
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| 46 | #define HV7131_REG_FWHL 0x15 |
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| 47 | #define HV7131_REG_FWWU 0x16 |
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| 48 | #define HV7131_REG_FWWL 0x17 |
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| 49 | /* Timing registers: */ |
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| 50 | #define HV7131_REG_THBU 0x20 |
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| 51 | #define HV7131_REG_THBL 0x21 |
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| 52 | #define HV7131_REG_TVBU 0x22 |
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| 53 | #define HV7131_REG_TVBL 0x23 |
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| 54 | #define HV7131_REG_TITU 0x25 |
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| 55 | #define HV7131_REG_TITM 0x26 |
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| 56 | #define HV7131_REG_TITL 0x27 |
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| 57 | #define HV7131_REG_TMCD 0x28 |
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| 58 | /* Adjust Registers: */ |
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| 59 | #define HV7131_REG_ARLV 0x30 |
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| 60 | #define HV7131_REG_ARCG 0x31 |
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| 61 | #define HV7131_REG_AGCG 0x32 |
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| 62 | #define HV7131_REG_ABCG 0x33 |
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| 63 | #define HV7131_REG_APBV 0x34 |
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| 64 | #define HV7131_REG_ASLP 0x54 |
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| 65 | /* Offset Registers: */ |
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| 66 | #define HV7131_REG_OFSR 0x50 |
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| 67 | #define HV7131_REG_OFSG 0x51 |
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| 68 | #define HV7131_REG_OFSB 0x52 |
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| 69 | /* REset level statistics registers: */ |
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| 70 | #define HV7131_REG_LOREFNOH 0x57 |
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| 71 | #define HV7131_REG_LOREFNOL 0x58 |
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| 72 | #define HV7131_REG_HIREFNOH 0x59 |
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| 73 | #define HV7131_REG_HIREFNOL 0x5a |
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| 74 | |
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| 75 | /* se401 registers */ |
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| 76 | #define SE401_OPERATINGMODE 0x2000 |
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| 77 | |
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