| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * STK1160 driver |
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| 4 | * |
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| 5 | * Copyright (C) 2012 Ezequiel Garcia |
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| 6 | * <elezegarcia--a.t--gmail.com> |
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| 7 | * |
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| 8 | * Based on Easycap driver by R.M. Thomas |
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| 9 | * Copyright (C) 2010 R.M. Thomas |
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| 10 | * <rmthomas--a.t--sciolus.org> |
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| 11 | */ |
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| 12 | |
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| 13 | /* GPIO Control */ |
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| 14 | #define STK1160_GCTRL 0x000 |
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| 15 | |
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| 16 | /* Remote Wakeup Control */ |
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| 17 | #define STK1160_RMCTL 0x00c |
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| 18 | |
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| 19 | /* Power-on Strapping Data */ |
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| 20 | #define STK1160_POSVA 0x010 |
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| 21 | #define STK1160_POSV_L 0x010 |
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| 22 | #define STK1160_POSV_M 0x011 |
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| 23 | #define STK1160_POSV_H 0x012 |
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| 24 | #define STK1160_POSV_L_ACDOUT BIT(3) |
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| 25 | #define STK1160_POSV_L_ACSYNC BIT(2) |
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| 26 | |
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| 27 | /* |
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| 28 | * Decoder Control Register: |
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| 29 | * This byte controls capture start/stop |
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| 30 | * with bit #7 (0x?? OR 0x80 to activate). |
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| 31 | */ |
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| 32 | #define STK1160_DCTRL 0x100 |
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| 33 | |
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| 34 | /* |
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| 35 | * Decimation Control Register: |
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| 36 | * Byte 104: Horizontal Decimation Line Unit Count |
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| 37 | * Byte 105: Vertical Decimation Line Unit Count |
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| 38 | * Byte 106: Decimation Control |
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| 39 | * Bit 0 - Horizontal Decimation Control |
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| 40 | * 0 Horizontal decimation is disabled. |
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| 41 | * 1 Horizontal decimation is enabled. |
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| 42 | * Bit 1 - Decimates Half or More Column |
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| 43 | * 0 Decimates less than half from original column, |
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| 44 | * send count unit (0x105) before each unit skipped. |
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| 45 | * 1 Decimates half or more from original column, |
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| 46 | * skip count unit (0x105) before each unit sent. |
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| 47 | * Bit 2 - Vertical Decimation Control |
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| 48 | * 0 Vertical decimation is disabled. |
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| 49 | * 1 Vertical decimation is enabled. |
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| 50 | * Bit 3 - Vertical Greater or Equal to Half |
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| 51 | * 0 Decimates less than half from original row, |
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| 52 | * send count unit (0x105) before each unit skipped. |
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| 53 | * 1 Decimates half or more from original row, |
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| 54 | * skip count unit (0x105) before each unit sent. |
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| 55 | * Bit 4 - Decimation Unit |
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| 56 | * 0 Decimation will work with 2 rows or columns per unit. |
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| 57 | * 1 Decimation will work with 4 rows or columns per unit. |
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| 58 | */ |
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| 59 | #define STK1160_DMCTRL_H_UNITS 0x104 |
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| 60 | #define STK1160_DMCTRL_V_UNITS 0x105 |
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| 61 | #define STK1160_DMCTRL 0x106 |
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| 62 | #define STK1160_H_DEC_EN BIT(0) |
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| 63 | #define STK1160_H_DEC_MODE BIT(1) |
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| 64 | #define STK1160_V_DEC_EN BIT(2) |
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| 65 | #define STK1160_V_DEC_MODE BIT(3) |
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| 66 | #define STK1160_DEC_UNIT_SIZE BIT(4) |
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| 67 | |
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| 68 | /* Capture Frame Start Position */ |
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| 69 | #define STK116_CFSPO 0x110 |
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| 70 | #define STK116_CFSPO_STX_L 0x110 |
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| 71 | #define STK116_CFSPO_STX_H 0x111 |
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| 72 | #define STK116_CFSPO_STY_L 0x112 |
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| 73 | #define STK116_CFSPO_STY_H 0x113 |
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| 74 | |
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| 75 | /* Capture Frame End Position */ |
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| 76 | #define STK116_CFEPO 0x114 |
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| 77 | #define STK116_CFEPO_ENX_L 0x114 |
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| 78 | #define STK116_CFEPO_ENX_H 0x115 |
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| 79 | #define STK116_CFEPO_ENY_L 0x116 |
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| 80 | #define STK116_CFEPO_ENY_H 0x117 |
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| 81 | |
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| 82 | /* Serial Interface Control */ |
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| 83 | #define STK1160_SICTL 0x200 |
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| 84 | #define STK1160_SICTL_CD 0x202 |
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| 85 | #define STK1160_SICTL_SDA 0x203 |
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| 86 | |
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| 87 | /* Serial Bus Write */ |
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| 88 | #define STK1160_SBUSW 0x204 |
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| 89 | #define STK1160_SBUSW_WA 0x204 |
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| 90 | #define STK1160_SBUSW_WD 0x205 |
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| 91 | |
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| 92 | /* Serial Bus Read */ |
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| 93 | #define STK1160_SBUSR 0x208 |
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| 94 | #define STK1160_SBUSR_RA 0x208 |
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| 95 | #define STK1160_SBUSR_RD 0x209 |
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| 96 | |
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| 97 | /* Alternate Serial Interface Control */ |
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| 98 | #define STK1160_ASIC 0x2fc |
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| 99 | |
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| 100 | /* PLL Select Options */ |
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| 101 | #define STK1160_PLLSO 0x018 |
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| 102 | |
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| 103 | /* PLL Frequency Divider */ |
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| 104 | #define STK1160_PLLFD 0x01c |
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| 105 | |
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| 106 | /* Timing Generator */ |
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| 107 | #define STK1160_TIGEN 0x300 |
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| 108 | |
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| 109 | /* Timing Control Parameter */ |
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| 110 | #define STK1160_TICTL 0x350 |
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| 111 | |
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| 112 | /* AC97 Audio Control */ |
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| 113 | #define STK1160_AC97CTL_0 0x500 |
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| 114 | #define STK1160_AC97CTL_1 0x504 |
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| 115 | #define STK1160_AC97CTL_0_CR BIT(1) |
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| 116 | #define STK1160_AC97CTL_0_CW BIT(2) |
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| 117 | |
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| 118 | /* Use [0:6] bits of register 0x504 to set codec command address */ |
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| 119 | #define STK1160_AC97_ADDR 0x504 |
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| 120 | /* Use [16:31] bits of register 0x500 to set codec command data */ |
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| 121 | #define STK1160_AC97_CMD 0x502 |
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| 122 | |
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| 123 | /* Audio I2S Interface */ |
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| 124 | #define STK1160_I2SCTL 0x50c |
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| 125 | |
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| 126 | /* EEPROM Interface */ |
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| 127 | #define STK1160_EEPROM_SZ 0x5f0 |
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| 128 | |
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