| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* Driver for Realtek PCI-Express card reader |
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| 3 | * |
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| 4 | * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. |
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| 5 | * |
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| 6 | * Author: |
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| 7 | * Ricky WU <ricky_wu@realtek.com> |
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| 8 | * Rui FENG <rui_feng@realsil.com.cn> |
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| 9 | * Wei WANG <wei_wang@realsil.com.cn> |
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| 10 | */ |
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| 11 | #ifndef RTS5228_H |
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| 12 | #define RTS5228_H |
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| 13 | |
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| 14 | |
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| 15 | #define RTS5228_AUTOLOAD_CFG0 0xFF7B |
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| 16 | #define RTS5228_AUTOLOAD_CFG1 0xFF7C |
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| 17 | #define RTS5228_AUTOLOAD_CFG2 0xFF7D |
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| 18 | #define RTS5228_AUTOLOAD_CFG3 0xFF7E |
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| 19 | #define RTS5228_AUTOLOAD_CFG4 0xFF7F |
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| 20 | |
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| 21 | #define RTS5228_REG_VREF 0xFE97 |
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| 22 | #define RTS5228_PWD_SUSPND_EN (1 << 4) |
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| 23 | |
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| 24 | #define RTS5228_PAD_H3L1 0xFF79 |
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| 25 | #define PAD_GPIO_H3L1 (1 << 3) |
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| 26 | |
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| 27 | /* SSC_CTL2 0xFC12 */ |
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| 28 | #define RTS5228_SSC_DEPTH_MASK 0x07 |
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| 29 | #define RTS5228_SSC_DEPTH_DISALBE 0x00 |
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| 30 | #define RTS5228_SSC_DEPTH_8M 0x01 |
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| 31 | #define RTS5228_SSC_DEPTH_4M 0x02 |
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| 32 | #define RTS5228_SSC_DEPTH_2M 0x03 |
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| 33 | #define RTS5228_SSC_DEPTH_1M 0x04 |
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| 34 | #define RTS5228_SSC_DEPTH_512K 0x05 |
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| 35 | #define RTS5228_SSC_DEPTH_256K 0x06 |
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| 36 | #define RTS5228_SSC_DEPTH_128K 0x07 |
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| 37 | |
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| 38 | /* DMACTL 0xFE2C */ |
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| 39 | #define RTS5228_DMA_PACK_SIZE_MASK 0xF0 |
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| 40 | |
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| 41 | #define RTS5228_REG_LDO12_CFG 0xFF6E |
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| 42 | #define RTS5228_LDO12_VO_TUNE_MASK (0x07<<1) |
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| 43 | #define RTS5228_LDO12_100 (0x00<<1) |
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| 44 | #define RTS5228_LDO12_105 (0x01<<1) |
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| 45 | #define RTS5228_LDO12_110 (0x02<<1) |
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| 46 | #define RTS5228_LDO12_115 (0x03<<1) |
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| 47 | #define RTS5228_LDO12_120 (0x04<<1) |
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| 48 | #define RTS5228_LDO12_125 (0x05<<1) |
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| 49 | #define RTS5228_LDO12_130 (0x06<<1) |
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| 50 | #define RTS5228_LDO12_135 (0x07<<1) |
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| 51 | #define RTS5228_REG_PWD_LDO12 (0x01<<0) |
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| 52 | |
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| 53 | #define RTS5228_REG_LDO12_L12 0xFF6F |
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| 54 | #define RTS5228_LDO12_L12_MASK (0x07<<4) |
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| 55 | #define RTS5228_LDO12_L12_120 (0x04<<4) |
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| 56 | |
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| 57 | /* LDO control register */ |
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| 58 | #define RTS5228_CARD_PWR_CTL 0xFD50 |
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| 59 | #define RTS5228_PUPDC (0x01<<5) |
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| 60 | |
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| 61 | #define RTS5228_LDO1233318_POW_CTL 0xFF70 |
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| 62 | #define RTS5228_LDO3318_POWERON (0x01<<3) |
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| 63 | #define RTS5228_LDO1_POWEROFF (0x00<<0) |
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| 64 | #define RTS5228_LDO1_SOFTSTART (0x01<<0) |
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| 65 | #define RTS5228_LDO1_FULLON (0x03<<0) |
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| 66 | #define RTS5228_LDO1_POWERON_MASK (0x03<<0) |
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| 67 | #define RTS5228_LDO_POWERON_MASK (0x0F<<0) |
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| 68 | |
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| 69 | #define RTS5228_DV3318_CFG 0xFF71 |
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| 70 | #define RTS5228_DV3318_TUNE_MASK (0x07<<4) |
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| 71 | #define RTS5228_DV3318_17 (0x00<<4) |
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| 72 | #define RTS5228_DV3318_1V75 (0x01<<4) |
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| 73 | #define RTS5228_DV3318_18 (0x02<<4) |
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| 74 | #define RTS5228_DV3318_1V85 (0x03<<4) |
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| 75 | #define RTS5228_DV3318_19 (0x04<<4) |
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| 76 | #define RTS5228_DV3318_33 (0x07<<4) |
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| 77 | #define RTS5228_DV3318_SR_MASK (0x03<<2) |
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| 78 | #define RTS5228_DV3318_SR_0 (0x00<<2) |
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| 79 | #define RTS5228_DV3318_SR_250 (0x01<<2) |
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| 80 | #define RTS5228_DV3318_SR_500 (0x02<<2) |
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| 81 | #define RTS5228_DV3318_SR_1000 (0x03<<2) |
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| 82 | |
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| 83 | #define RTS5228_LDO1_CFG0 0xFF72 |
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| 84 | #define RTS5228_LDO1_OCP_THD_MASK (0x07<<5) |
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| 85 | #define RTS5228_LDO1_OCP_EN (0x01<<4) |
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| 86 | #define RTS5228_LDO1_OCP_LMT_THD_MASK (0x03<<2) |
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| 87 | #define RTS5228_LDO1_OCP_LMT_EN (0x01<<1) |
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| 88 | |
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| 89 | #define RTS5228_LDO1_OCP_THD_730 (0x00<<5) |
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| 90 | #define RTS5228_LDO1_OCP_THD_780 (0x01<<5) |
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| 91 | #define RTS5228_LDO1_OCP_THD_860 (0x02<<5) |
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| 92 | #define RTS5228_LDO1_OCP_THD_930 (0x03<<5) |
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| 93 | #define RTS5228_LDO1_OCP_THD_1000 (0x04<<5) |
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| 94 | #define RTS5228_LDO1_OCP_THD_1070 (0x05<<5) |
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| 95 | #define RTS5228_LDO1_OCP_THD_1140 (0x06<<5) |
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| 96 | #define RTS5228_LDO1_OCP_THD_1220 (0x07<<5) |
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| 97 | |
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| 98 | #define RTS5228_LDO1_LMT_THD_450 (0x00<<2) |
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| 99 | #define RTS5228_LDO1_LMT_THD_1000 (0x01<<2) |
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| 100 | #define RTS5228_LDO1_LMT_THD_1500 (0x02<<2) |
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| 101 | #define RTS5228_LDO1_LMT_THD_2000 (0x03<<2) |
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| 102 | |
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| 103 | #define RTS5228_LDO1_CFG1 0xFF73 |
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| 104 | #define RTS5228_LDO1_SR_TIME_MASK (0x03<<6) |
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| 105 | #define RTS5228_LDO1_SR_0_0 (0x00<<6) |
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| 106 | #define RTS5228_LDO1_SR_0_25 (0x01<<6) |
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| 107 | #define RTS5228_LDO1_SR_0_5 (0x02<<6) |
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| 108 | #define RTS5228_LDO1_SR_1_0 (0x03<<6) |
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| 109 | #define RTS5228_LDO1_TUNE_MASK (0x07<<1) |
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| 110 | #define RTS5228_LDO1_18 (0x05<<1) |
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| 111 | #define RTS5228_LDO1_33 (0x07<<1) |
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| 112 | #define RTS5228_LDO1_PWD_MASK (0x01<<0) |
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| 113 | |
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| 114 | #define RTS5228_AUXCLK_GAT_CTL 0xFF74 |
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| 115 | |
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| 116 | #define RTS5228_REG_RREF_CTL_0 0xFF75 |
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| 117 | #define RTS5228_FORCE_RREF_EXTL (0x01<<7) |
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| 118 | #define RTS5228_REG_BG33_MASK (0x07<<0) |
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| 119 | #define RTS5228_RREF_12_1V (0x04<<0) |
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| 120 | #define RTS5228_RREF_12_3V (0x05<<0) |
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| 121 | |
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| 122 | #define RTS5228_REG_RREF_CTL_1 0xFF76 |
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| 123 | |
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| 124 | #define RTS5228_REG_RREF_CTL_2 0xFF77 |
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| 125 | #define RTS5228_TEST_INTL_RREF (0x01<<7) |
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| 126 | #define RTS5228_DGLCH_TIME_MASK (0x03<<5) |
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| 127 | #define RTS5228_DGLCH_TIME_50 (0x00<<5) |
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| 128 | #define RTS5228_DGLCH_TIME_75 (0x01<<5) |
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| 129 | #define RTS5228_DGLCH_TIME_100 (0x02<<5) |
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| 130 | #define RTS5228_DGLCH_TIME_125 (0x03<<5) |
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| 131 | #define RTS5228_REG_REXT_TUNE_MASK (0x1F<<0) |
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| 132 | |
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| 133 | #define RTS5228_REG_PME_FORCE_CTL 0xFF78 |
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| 134 | #define FORCE_PM_CONTROL 0x20 |
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| 135 | #define FORCE_PM_VALUE 0x10 |
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| 136 | |
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| 137 | |
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| 138 | /* Single LUN, support SD */ |
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| 139 | #define DEFAULT_SINGLE 0 |
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| 140 | #define SD_LUN 1 |
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| 141 | |
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| 142 | |
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| 143 | /* For Change_FPGA_SSCClock Function */ |
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| 144 | #define MULTIPLY_BY_1 0x00 |
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| 145 | #define MULTIPLY_BY_2 0x01 |
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| 146 | #define MULTIPLY_BY_3 0x02 |
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| 147 | #define MULTIPLY_BY_4 0x03 |
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| 148 | #define MULTIPLY_BY_5 0x04 |
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| 149 | #define MULTIPLY_BY_6 0x05 |
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| 150 | #define MULTIPLY_BY_7 0x06 |
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| 151 | #define MULTIPLY_BY_8 0x07 |
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| 152 | #define MULTIPLY_BY_9 0x08 |
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| 153 | #define MULTIPLY_BY_10 0x09 |
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| 154 | |
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| 155 | #define DIVIDE_BY_2 0x01 |
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| 156 | #define DIVIDE_BY_3 0x02 |
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| 157 | #define DIVIDE_BY_4 0x03 |
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| 158 | #define DIVIDE_BY_5 0x04 |
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| 159 | #define DIVIDE_BY_6 0x05 |
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| 160 | #define DIVIDE_BY_7 0x06 |
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| 161 | #define DIVIDE_BY_8 0x07 |
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| 162 | #define DIVIDE_BY_9 0x08 |
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| 163 | #define DIVIDE_BY_10 0x09 |
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| 164 | |
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| 165 | int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, |
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| 166 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); |
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| 167 | |
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| 168 | #endif /* RTS5228_H */ |
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| 169 | |
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