1 | /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ |
2 | /* |
3 | * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. |
4 | */ |
5 | #ifndef _ENA_ADMIN_H_ |
6 | #define _ENA_ADMIN_H_ |
7 | |
8 | #define 10 |
9 | |
10 | enum ena_admin_aq_opcode { |
11 | ENA_ADMIN_CREATE_SQ = 1, |
12 | ENA_ADMIN_DESTROY_SQ = 2, |
13 | ENA_ADMIN_CREATE_CQ = 3, |
14 | ENA_ADMIN_DESTROY_CQ = 4, |
15 | ENA_ADMIN_GET_FEATURE = 8, |
16 | ENA_ADMIN_SET_FEATURE = 9, |
17 | ENA_ADMIN_GET_STATS = 11, |
18 | }; |
19 | |
20 | enum ena_admin_aq_completion_status { |
21 | ENA_ADMIN_SUCCESS = 0, |
22 | ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, |
23 | ENA_ADMIN_BAD_OPCODE = 2, |
24 | ENA_ADMIN_UNSUPPORTED_OPCODE = 3, |
25 | ENA_ADMIN_MALFORMED_REQUEST = 4, |
26 | /* Additional status is provided in ACQ entry extended_status */ |
27 | ENA_ADMIN_ILLEGAL_PARAMETER = 5, |
28 | ENA_ADMIN_UNKNOWN_ERROR = 6, |
29 | ENA_ADMIN_RESOURCE_BUSY = 7, |
30 | }; |
31 | |
32 | /* subcommands for the set/get feature admin commands */ |
33 | enum ena_admin_aq_feature_id { |
34 | ENA_ADMIN_DEVICE_ATTRIBUTES = 1, |
35 | ENA_ADMIN_MAX_QUEUES_NUM = 2, |
36 | ENA_ADMIN_HW_HINTS = 3, |
37 | ENA_ADMIN_LLQ = 4, |
38 | ENA_ADMIN_MAX_QUEUES_EXT = 7, |
39 | = 10, |
40 | ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, |
41 | = 12, |
42 | ENA_ADMIN_MTU = 14, |
43 | = 18, |
44 | ENA_ADMIN_INTERRUPT_MODERATION = 20, |
45 | ENA_ADMIN_AENQ_CONFIG = 26, |
46 | ENA_ADMIN_LINK_CONFIG = 27, |
47 | ENA_ADMIN_HOST_ATTR_CONFIG = 28, |
48 | ENA_ADMIN_FEATURES_OPCODE_NUM = 32, |
49 | }; |
50 | |
51 | /* device capabilities */ |
52 | enum ena_admin_aq_caps_id { |
53 | ENA_ADMIN_ENI_STATS = 0, |
54 | }; |
55 | |
56 | enum ena_admin_placement_policy_type { |
57 | /* descriptors and headers are in host memory */ |
58 | ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, |
59 | /* descriptors and headers are in device memory (a.k.a Low Latency |
60 | * Queue) |
61 | */ |
62 | ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, |
63 | }; |
64 | |
65 | enum ena_admin_link_types { |
66 | ENA_ADMIN_LINK_SPEED_1G = 0x1, |
67 | ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, |
68 | ENA_ADMIN_LINK_SPEED_5G = 0x4, |
69 | ENA_ADMIN_LINK_SPEED_10G = 0x8, |
70 | ENA_ADMIN_LINK_SPEED_25G = 0x10, |
71 | ENA_ADMIN_LINK_SPEED_40G = 0x20, |
72 | ENA_ADMIN_LINK_SPEED_50G = 0x40, |
73 | ENA_ADMIN_LINK_SPEED_100G = 0x80, |
74 | ENA_ADMIN_LINK_SPEED_200G = 0x100, |
75 | ENA_ADMIN_LINK_SPEED_400G = 0x200, |
76 | }; |
77 | |
78 | enum ena_admin_completion_policy_type { |
79 | /* completion queue entry for each sq descriptor */ |
80 | ENA_ADMIN_COMPLETION_POLICY_DESC = 0, |
81 | /* completion queue entry upon request in sq descriptor */ |
82 | ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, |
83 | /* current queue head pointer is updated in OS memory upon sq |
84 | * descriptor request |
85 | */ |
86 | ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, |
87 | /* current queue head pointer is updated in OS memory for each sq |
88 | * descriptor |
89 | */ |
90 | ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, |
91 | }; |
92 | |
93 | /* basic stats return ena_admin_basic_stats while extanded stats return a |
94 | * buffer (string format) with additional statistics per queue and per |
95 | * device id |
96 | */ |
97 | enum ena_admin_get_stats_type { |
98 | ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, |
99 | ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, |
100 | /* extra HW stats for specific network interface */ |
101 | ENA_ADMIN_GET_STATS_TYPE_ENI = 2, |
102 | }; |
103 | |
104 | enum ena_admin_get_stats_scope { |
105 | ENA_ADMIN_SPECIFIC_QUEUE = 0, |
106 | ENA_ADMIN_ETH_TRAFFIC = 1, |
107 | }; |
108 | |
109 | struct ena_admin_aq_common_desc { |
110 | /* 11:0 : command_id |
111 | * 15:12 : reserved12 |
112 | */ |
113 | u16 command_id; |
114 | |
115 | /* as appears in ena_admin_aq_opcode */ |
116 | u8 opcode; |
117 | |
118 | /* 0 : phase |
119 | * 1 : ctrl_data - control buffer address valid |
120 | * 2 : ctrl_data_indirect - control buffer address |
121 | * points to list of pages with addresses of control |
122 | * buffers |
123 | * 7:3 : reserved3 |
124 | */ |
125 | u8 flags; |
126 | }; |
127 | |
128 | /* used in ena_admin_aq_entry. Can point directly to control data, or to a |
129 | * page list chunk. Used also at the end of indirect mode page list chunks, |
130 | * for chaining. |
131 | */ |
132 | struct ena_admin_ctrl_buff_info { |
133 | u32 length; |
134 | |
135 | struct ena_common_mem_addr address; |
136 | }; |
137 | |
138 | struct ena_admin_sq { |
139 | u16 sq_idx; |
140 | |
141 | /* 4:0 : reserved |
142 | * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx |
143 | */ |
144 | u8 sq_identity; |
145 | |
146 | u8 reserved1; |
147 | }; |
148 | |
149 | struct ena_admin_aq_entry { |
150 | struct ena_admin_aq_common_desc aq_common_descriptor; |
151 | |
152 | union { |
153 | u32 inline_data_w1[3]; |
154 | |
155 | struct ena_admin_ctrl_buff_info control_buffer; |
156 | } u; |
157 | |
158 | u32 inline_data_w4[12]; |
159 | }; |
160 | |
161 | struct ena_admin_acq_common_desc { |
162 | /* command identifier to associate it with the aq descriptor |
163 | * 11:0 : command_id |
164 | * 15:12 : reserved12 |
165 | */ |
166 | u16 command; |
167 | |
168 | u8 status; |
169 | |
170 | /* 0 : phase |
171 | * 7:1 : reserved1 |
172 | */ |
173 | u8 flags; |
174 | |
175 | u16 extended_status; |
176 | |
177 | /* indicates to the driver which AQ entry has been consumed by the |
178 | * device and could be reused |
179 | */ |
180 | u16 sq_head_indx; |
181 | }; |
182 | |
183 | struct ena_admin_acq_entry { |
184 | struct ena_admin_acq_common_desc acq_common_descriptor; |
185 | |
186 | u32 response_specific_data[14]; |
187 | }; |
188 | |
189 | struct ena_admin_aq_create_sq_cmd { |
190 | struct ena_admin_aq_common_desc aq_common_descriptor; |
191 | |
192 | /* 4:0 : reserved0_w1 |
193 | * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx |
194 | */ |
195 | u8 sq_identity; |
196 | |
197 | u8 reserved8_w1; |
198 | |
199 | /* 3:0 : placement_policy - Describing where the SQ |
200 | * descriptor ring and the SQ packet headers reside: |
201 | * 0x1 - descriptors and headers are in OS memory, |
202 | * 0x3 - descriptors and headers in device memory |
203 | * (a.k.a Low Latency Queue) |
204 | * 6:4 : completion_policy - Describing what policy |
205 | * to use for generation completion entry (cqe) in |
206 | * the CQ associated with this SQ: 0x0 - cqe for each |
207 | * sq descriptor, 0x1 - cqe upon request in sq |
208 | * descriptor, 0x2 - current queue head pointer is |
209 | * updated in OS memory upon sq descriptor request |
210 | * 0x3 - current queue head pointer is updated in OS |
211 | * memory for each sq descriptor |
212 | * 7 : reserved15_w1 |
213 | */ |
214 | u8 sq_caps_2; |
215 | |
216 | /* 0 : is_physically_contiguous - Described if the |
217 | * queue ring memory is allocated in physical |
218 | * contiguous pages or split. |
219 | * 7:1 : reserved17_w1 |
220 | */ |
221 | u8 sq_caps_3; |
222 | |
223 | /* associated completion queue id. This CQ must be created prior to SQ |
224 | * creation |
225 | */ |
226 | u16 cq_idx; |
227 | |
228 | /* submission queue depth in entries */ |
229 | u16 sq_depth; |
230 | |
231 | /* SQ physical base address in OS memory. This field should not be |
232 | * used for Low Latency queues. Has to be page aligned. |
233 | */ |
234 | struct ena_common_mem_addr sq_ba; |
235 | |
236 | /* specifies queue head writeback location in OS memory. Valid if |
237 | * completion_policy is set to completion_policy_head_on_demand or |
238 | * completion_policy_head. Has to be cache aligned |
239 | */ |
240 | struct ena_common_mem_addr sq_head_writeback; |
241 | |
242 | u32 reserved0_w7; |
243 | |
244 | u32 reserved0_w8; |
245 | }; |
246 | |
247 | enum ena_admin_sq_direction { |
248 | ENA_ADMIN_SQ_DIRECTION_TX = 1, |
249 | ENA_ADMIN_SQ_DIRECTION_RX = 2, |
250 | }; |
251 | |
252 | struct ena_admin_acq_create_sq_resp_desc { |
253 | struct ena_admin_acq_common_desc acq_common_desc; |
254 | |
255 | u16 sq_idx; |
256 | |
257 | u16 reserved; |
258 | |
259 | /* queue doorbell address as an offset to PCIe MMIO REG BAR */ |
260 | u32 sq_doorbell_offset; |
261 | |
262 | /* low latency queue ring base address as an offset to PCIe MMIO |
263 | * LLQ_MEM BAR |
264 | */ |
265 | u32 llq_descriptors_offset; |
266 | |
267 | /* low latency queue headers' memory as an offset to PCIe MMIO |
268 | * LLQ_MEM BAR |
269 | */ |
270 | u32 ; |
271 | }; |
272 | |
273 | struct ena_admin_aq_destroy_sq_cmd { |
274 | struct ena_admin_aq_common_desc aq_common_descriptor; |
275 | |
276 | struct ena_admin_sq sq; |
277 | }; |
278 | |
279 | struct ena_admin_acq_destroy_sq_resp_desc { |
280 | struct ena_admin_acq_common_desc acq_common_desc; |
281 | }; |
282 | |
283 | struct ena_admin_aq_create_cq_cmd { |
284 | struct ena_admin_aq_common_desc aq_common_descriptor; |
285 | |
286 | /* 4:0 : reserved5 |
287 | * 5 : interrupt_mode_enabled - if set, cq operates |
288 | * in interrupt mode, otherwise - polling |
289 | * 7:6 : reserved6 |
290 | */ |
291 | u8 cq_caps_1; |
292 | |
293 | /* 4:0 : cq_entry_size_words - size of CQ entry in |
294 | * 32-bit words, valid values: 4, 8. |
295 | * 7:5 : reserved7 |
296 | */ |
297 | u8 cq_caps_2; |
298 | |
299 | /* completion queue depth in # of entries. must be power of 2 */ |
300 | u16 cq_depth; |
301 | |
302 | /* msix vector assigned to this cq */ |
303 | u32 msix_vector; |
304 | |
305 | /* cq physical base address in OS memory. CQ must be physically |
306 | * contiguous |
307 | */ |
308 | struct ena_common_mem_addr cq_ba; |
309 | }; |
310 | |
311 | struct ena_admin_acq_create_cq_resp_desc { |
312 | struct ena_admin_acq_common_desc acq_common_desc; |
313 | |
314 | u16 cq_idx; |
315 | |
316 | /* actual cq depth in number of entries */ |
317 | u16 cq_actual_depth; |
318 | |
319 | u32 numa_node_register_offset; |
320 | |
321 | u32 cq_head_db_register_offset; |
322 | |
323 | u32 cq_interrupt_unmask_register_offset; |
324 | }; |
325 | |
326 | struct ena_admin_aq_destroy_cq_cmd { |
327 | struct ena_admin_aq_common_desc aq_common_descriptor; |
328 | |
329 | u16 cq_idx; |
330 | |
331 | u16 reserved1; |
332 | }; |
333 | |
334 | struct ena_admin_acq_destroy_cq_resp_desc { |
335 | struct ena_admin_acq_common_desc acq_common_desc; |
336 | }; |
337 | |
338 | /* ENA AQ Get Statistics command. Extended statistics are placed in control |
339 | * buffer pointed by AQ entry |
340 | */ |
341 | struct ena_admin_aq_get_stats_cmd { |
342 | struct ena_admin_aq_common_desc aq_common_descriptor; |
343 | |
344 | union { |
345 | /* command specific inline data */ |
346 | u32 inline_data_w1[3]; |
347 | |
348 | struct ena_admin_ctrl_buff_info control_buffer; |
349 | } u; |
350 | |
351 | /* stats type as defined in enum ena_admin_get_stats_type */ |
352 | u8 type; |
353 | |
354 | /* stats scope defined in enum ena_admin_get_stats_scope */ |
355 | u8 scope; |
356 | |
357 | u16 reserved3; |
358 | |
359 | /* queue id. used when scope is specific_queue */ |
360 | u16 queue_idx; |
361 | |
362 | /* device id, value 0xFFFF means mine. only privileged device can get |
363 | * stats of other device |
364 | */ |
365 | u16 device_id; |
366 | }; |
367 | |
368 | /* Basic Statistics Command. */ |
369 | struct ena_admin_basic_stats { |
370 | u32 tx_bytes_low; |
371 | |
372 | u32 tx_bytes_high; |
373 | |
374 | u32 tx_pkts_low; |
375 | |
376 | u32 tx_pkts_high; |
377 | |
378 | u32 rx_bytes_low; |
379 | |
380 | u32 rx_bytes_high; |
381 | |
382 | u32 rx_pkts_low; |
383 | |
384 | u32 rx_pkts_high; |
385 | |
386 | u32 rx_drops_low; |
387 | |
388 | u32 rx_drops_high; |
389 | |
390 | u32 tx_drops_low; |
391 | |
392 | u32 tx_drops_high; |
393 | }; |
394 | |
395 | /* ENI Statistics Command. */ |
396 | struct ena_admin_eni_stats { |
397 | /* The number of packets shaped due to inbound aggregate BW |
398 | * allowance being exceeded |
399 | */ |
400 | u64 bw_in_allowance_exceeded; |
401 | |
402 | /* The number of packets shaped due to outbound aggregate BW |
403 | * allowance being exceeded |
404 | */ |
405 | u64 bw_out_allowance_exceeded; |
406 | |
407 | /* The number of packets shaped due to PPS allowance being exceeded */ |
408 | u64 pps_allowance_exceeded; |
409 | |
410 | /* The number of packets shaped due to connection tracking |
411 | * allowance being exceeded and leading to failure in establishment |
412 | * of new connections |
413 | */ |
414 | u64 conntrack_allowance_exceeded; |
415 | |
416 | /* The number of packets shaped due to linklocal packet rate |
417 | * allowance being exceeded |
418 | */ |
419 | u64 linklocal_allowance_exceeded; |
420 | }; |
421 | |
422 | struct ena_admin_acq_get_stats_resp { |
423 | struct ena_admin_acq_common_desc acq_common_desc; |
424 | |
425 | union { |
426 | u64 raw[7]; |
427 | |
428 | struct ena_admin_basic_stats basic_stats; |
429 | |
430 | struct ena_admin_eni_stats eni_stats; |
431 | } u; |
432 | }; |
433 | |
434 | struct ena_admin_get_set_feature_common_desc { |
435 | /* 1:0 : select - 0x1 - current value; 0x3 - default |
436 | * value |
437 | * 7:3 : reserved3 |
438 | */ |
439 | u8 flags; |
440 | |
441 | /* as appears in ena_admin_aq_feature_id */ |
442 | u8 feature_id; |
443 | |
444 | /* The driver specifies the max feature version it supports and the |
445 | * device responds with the currently supported feature version. The |
446 | * field is zero based |
447 | */ |
448 | u8 feature_version; |
449 | |
450 | u8 reserved8; |
451 | }; |
452 | |
453 | struct ena_admin_device_attr_feature_desc { |
454 | u32 impl_id; |
455 | |
456 | u32 device_version; |
457 | |
458 | /* bitmap of ena_admin_aq_feature_id, which represents supported |
459 | * subcommands for the set/get feature admin commands. |
460 | */ |
461 | u32 supported_features; |
462 | |
463 | /* bitmap of ena_admin_aq_caps_id, which represents device |
464 | * capabilities. |
465 | */ |
466 | u32 capabilities; |
467 | |
468 | /* Indicates how many bits are used physical address access. */ |
469 | u32 phys_addr_width; |
470 | |
471 | /* Indicates how many bits are used virtual address access. */ |
472 | u32 virt_addr_width; |
473 | |
474 | /* unicast MAC address (in Network byte order) */ |
475 | u8 mac_addr[6]; |
476 | |
477 | u8 reserved7[2]; |
478 | |
479 | u32 max_mtu; |
480 | }; |
481 | |
482 | enum { |
483 | /* header is in descriptor list */ |
484 | = 1, |
485 | /* header in a separate ring, implies 16B descriptor list entry */ |
486 | = 2, |
487 | }; |
488 | |
489 | enum ena_admin_llq_ring_entry_size { |
490 | ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, |
491 | ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, |
492 | ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, |
493 | }; |
494 | |
495 | enum { |
496 | = 0, |
497 | = 1, |
498 | = 2, |
499 | = 4, |
500 | = 8, |
501 | }; |
502 | |
503 | /* packet descriptor list entry always starts with one or more descriptors, |
504 | * followed by a header. The rest of the descriptors are located in the |
505 | * beginning of the subsequent entry. Stride refers to how the rest of the |
506 | * descriptors are placed. This field is relevant only for inline header |
507 | * mode |
508 | */ |
509 | enum ena_admin_llq_stride_ctrl { |
510 | ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, |
511 | ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, |
512 | }; |
513 | |
514 | enum ena_admin_accel_mode_feat { |
515 | ENA_ADMIN_DISABLE_META_CACHING = 0, |
516 | ENA_ADMIN_LIMIT_TX_BURST = 1, |
517 | }; |
518 | |
519 | struct ena_admin_accel_mode_get { |
520 | /* bit field of enum ena_admin_accel_mode_feat */ |
521 | u16 supported_flags; |
522 | |
523 | /* maximum burst size between two doorbells. The size is in bytes */ |
524 | u16 max_tx_burst_size; |
525 | }; |
526 | |
527 | struct ena_admin_accel_mode_set { |
528 | /* bit field of enum ena_admin_accel_mode_feat */ |
529 | u16 enabled_flags; |
530 | |
531 | u16 reserved; |
532 | }; |
533 | |
534 | struct ena_admin_accel_mode_req { |
535 | union { |
536 | u32 raw[2]; |
537 | |
538 | struct ena_admin_accel_mode_get get; |
539 | |
540 | struct ena_admin_accel_mode_set set; |
541 | } u; |
542 | }; |
543 | |
544 | struct ena_admin_feature_llq_desc { |
545 | u32 max_llq_num; |
546 | |
547 | u32 max_llq_depth; |
548 | |
549 | /* specify the header locations the device supports. bitfield of enum |
550 | * ena_admin_llq_header_location. |
551 | */ |
552 | u16 ; |
553 | |
554 | /* the header location the driver selected to use. */ |
555 | u16 ; |
556 | |
557 | /* if inline header is specified - this is the size of descriptor list |
558 | * entry. If header in a separate ring is specified - this is the size |
559 | * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size. |
560 | * specify the entry sizes the device supports |
561 | */ |
562 | u16 entry_size_ctrl_supported; |
563 | |
564 | /* the entry size the driver selected to use. */ |
565 | u16 entry_size_ctrl_enabled; |
566 | |
567 | /* valid only if inline header is specified. First entry associated with |
568 | * the packet includes descriptors and header. Rest of the entries |
569 | * occupied by descriptors. This parameter defines the max number of |
570 | * descriptors precedding the header in the first entry. The field is |
571 | * bitfield of enum ena_admin_llq_num_descs_before_header and specify |
572 | * the values the device supports |
573 | */ |
574 | u16 ; |
575 | |
576 | /* the desire field the driver selected to use */ |
577 | u16 ; |
578 | |
579 | /* valid only if inline was chosen. bitfield of enum |
580 | * ena_admin_llq_stride_ctrl |
581 | */ |
582 | u16 descriptors_stride_ctrl_supported; |
583 | |
584 | /* the stride control the driver selected to use */ |
585 | u16 descriptors_stride_ctrl_enabled; |
586 | |
587 | /* reserved */ |
588 | u32 reserved1; |
589 | |
590 | /* accelerated low latency queues requirement. driver needs to |
591 | * support those requirements in order to use accelerated llq |
592 | */ |
593 | struct ena_admin_accel_mode_req accel_mode; |
594 | }; |
595 | |
596 | struct ena_admin_queue_ext_feature_fields { |
597 | u32 max_tx_sq_num; |
598 | |
599 | u32 max_tx_cq_num; |
600 | |
601 | u32 max_rx_sq_num; |
602 | |
603 | u32 max_rx_cq_num; |
604 | |
605 | u32 max_tx_sq_depth; |
606 | |
607 | u32 max_tx_cq_depth; |
608 | |
609 | u32 max_rx_sq_depth; |
610 | |
611 | u32 max_rx_cq_depth; |
612 | |
613 | u32 ; |
614 | |
615 | /* Maximum Descriptors number, including meta descriptor, allowed for a |
616 | * single Tx packet |
617 | */ |
618 | u16 max_per_packet_tx_descs; |
619 | |
620 | /* Maximum Descriptors number allowed for a single Rx packet */ |
621 | u16 max_per_packet_rx_descs; |
622 | }; |
623 | |
624 | struct ena_admin_queue_feature_desc { |
625 | u32 max_sq_num; |
626 | |
627 | u32 max_sq_depth; |
628 | |
629 | u32 max_cq_num; |
630 | |
631 | u32 max_cq_depth; |
632 | |
633 | u32 max_legacy_llq_num; |
634 | |
635 | u32 max_legacy_llq_depth; |
636 | |
637 | u32 ; |
638 | |
639 | /* Maximum Descriptors number, including meta descriptor, allowed for a |
640 | * single Tx packet |
641 | */ |
642 | u16 max_packet_tx_descs; |
643 | |
644 | /* Maximum Descriptors number allowed for a single Rx packet */ |
645 | u16 max_packet_rx_descs; |
646 | }; |
647 | |
648 | struct ena_admin_set_feature_mtu_desc { |
649 | /* exclude L2 */ |
650 | u32 mtu; |
651 | }; |
652 | |
653 | struct ena_admin_set_feature_host_attr_desc { |
654 | /* host OS info base address in OS memory. host info is 4KB of |
655 | * physically contiguous |
656 | */ |
657 | struct ena_common_mem_addr os_info_ba; |
658 | |
659 | /* host debug area base address in OS memory. debug area must be |
660 | * physically contiguous |
661 | */ |
662 | struct ena_common_mem_addr debug_ba; |
663 | |
664 | /* debug area size */ |
665 | u32 debug_area_size; |
666 | }; |
667 | |
668 | struct ena_admin_feature_intr_moder_desc { |
669 | /* interrupt delay granularity in usec */ |
670 | u16 intr_delay_resolution; |
671 | |
672 | u16 reserved; |
673 | }; |
674 | |
675 | struct ena_admin_get_feature_link_desc { |
676 | /* Link speed in Mb */ |
677 | u32 speed; |
678 | |
679 | /* bit field of enum ena_admin_link types */ |
680 | u32 supported; |
681 | |
682 | /* 0 : autoneg |
683 | * 1 : duplex - Full Duplex |
684 | * 31:2 : reserved2 |
685 | */ |
686 | u32 flags; |
687 | }; |
688 | |
689 | struct ena_admin_feature_aenq_desc { |
690 | /* bitmask for AENQ groups the device can report */ |
691 | u32 supported_groups; |
692 | |
693 | /* bitmask for AENQ groups to report */ |
694 | u32 enabled_groups; |
695 | }; |
696 | |
697 | struct ena_admin_feature_offload_desc { |
698 | /* 0 : TX_L3_csum_ipv4 |
699 | * 1 : TX_L4_ipv4_csum_part - The checksum field |
700 | * should be initialized with pseudo header checksum |
701 | * 2 : TX_L4_ipv4_csum_full |
702 | * 3 : TX_L4_ipv6_csum_part - The checksum field |
703 | * should be initialized with pseudo header checksum |
704 | * 4 : TX_L4_ipv6_csum_full |
705 | * 5 : tso_ipv4 |
706 | * 6 : tso_ipv6 |
707 | * 7 : tso_ecn |
708 | */ |
709 | u32 tx; |
710 | |
711 | /* Receive side supported stateless offload |
712 | * 0 : RX_L3_csum_ipv4 - IPv4 checksum |
713 | * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum |
714 | * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum |
715 | * 3 : RX_hash - Hash calculation |
716 | */ |
717 | u32 rx_supported; |
718 | |
719 | u32 rx_enabled; |
720 | }; |
721 | |
722 | enum ena_admin_hash_functions { |
723 | ENA_ADMIN_TOEPLITZ = 1, |
724 | ENA_ADMIN_CRC32 = 2, |
725 | }; |
726 | |
727 | struct { |
728 | u32 ; |
729 | |
730 | u32 ; |
731 | |
732 | u32 [ENA_ADMIN_RSS_KEY_PARTS]; |
733 | }; |
734 | |
735 | struct { |
736 | /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ |
737 | u32 ; |
738 | |
739 | /* 7:0 : selected_func - bitmask of |
740 | * ena_admin_hash_functions |
741 | */ |
742 | u32 ; |
743 | |
744 | /* initial value */ |
745 | u32 ; |
746 | }; |
747 | |
748 | /* RSS flow hash protocols */ |
749 | enum ena_admin_flow_hash_proto { |
750 | = 0, |
751 | = 1, |
752 | = 2, |
753 | = 3, |
754 | = 4, |
755 | = 5, |
756 | = 6, |
757 | = 7, |
758 | /* TCPv6 with extension header */ |
759 | = 8, |
760 | /* IPv6 with extension header */ |
761 | = 9, |
762 | = 16, |
763 | }; |
764 | |
765 | /* RSS flow hash fields */ |
766 | enum ena_admin_flow_hash_fields { |
767 | /* Ethernet Dest Addr */ |
768 | = BIT(0), |
769 | /* Ethernet Src Addr */ |
770 | = BIT(1), |
771 | /* ipv4/6 Dest Addr */ |
772 | = BIT(2), |
773 | /* ipv4/6 Src Addr */ |
774 | = BIT(3), |
775 | /* tcp/udp Dest Port */ |
776 | = BIT(4), |
777 | /* tcp/udp Src Port */ |
778 | = BIT(5), |
779 | }; |
780 | |
781 | struct ena_admin_proto_input { |
782 | /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ |
783 | u16 fields; |
784 | |
785 | u16 reserved2; |
786 | }; |
787 | |
788 | struct { |
789 | struct ena_admin_proto_input [ENA_ADMIN_RSS_PROTO_NUM]; |
790 | |
791 | struct ena_admin_proto_input [ENA_ADMIN_RSS_PROTO_NUM]; |
792 | |
793 | struct ena_admin_proto_input [ENA_ADMIN_RSS_PROTO_NUM]; |
794 | |
795 | struct ena_admin_proto_input [ENA_ADMIN_RSS_PROTO_NUM]; |
796 | }; |
797 | |
798 | struct { |
799 | /* supported hash input sorting |
800 | * 1 : L3_sort - support swap L3 addresses if DA is |
801 | * smaller than SA |
802 | * 2 : L4_sort - support swap L4 ports if DP smaller |
803 | * SP |
804 | */ |
805 | u16 ; |
806 | |
807 | /* enabled hash input sorting |
808 | * 1 : enable_L3_sort - enable swap L3 addresses if |
809 | * DA smaller than SA |
810 | * 2 : enable_L4_sort - enable swap L4 ports if DP |
811 | * smaller than SP |
812 | */ |
813 | u16 ; |
814 | }; |
815 | |
816 | enum ena_admin_os_type { |
817 | ENA_ADMIN_OS_LINUX = 1, |
818 | ENA_ADMIN_OS_WIN = 2, |
819 | ENA_ADMIN_OS_DPDK = 3, |
820 | ENA_ADMIN_OS_FREEBSD = 4, |
821 | ENA_ADMIN_OS_IPXE = 5, |
822 | ENA_ADMIN_OS_ESXI = 6, |
823 | ENA_ADMIN_OS_GROUPS_NUM = 6, |
824 | }; |
825 | |
826 | struct ena_admin_host_info { |
827 | /* defined in enum ena_admin_os_type */ |
828 | u32 os_type; |
829 | |
830 | /* os distribution string format */ |
831 | u8 os_dist_str[128]; |
832 | |
833 | /* OS distribution numeric format */ |
834 | u32 os_dist; |
835 | |
836 | /* kernel version string format */ |
837 | u8 kernel_ver_str[32]; |
838 | |
839 | /* Kernel version numeric format */ |
840 | u32 kernel_ver; |
841 | |
842 | /* 7:0 : major |
843 | * 15:8 : minor |
844 | * 23:16 : sub_minor |
845 | * 31:24 : module_type |
846 | */ |
847 | u32 driver_version; |
848 | |
849 | /* features bitmap */ |
850 | u32 supported_network_features[2]; |
851 | |
852 | /* ENA spec version of driver */ |
853 | u16 ena_spec_version; |
854 | |
855 | /* ENA device's Bus, Device and Function |
856 | * 2:0 : function |
857 | * 7:3 : device |
858 | * 15:8 : bus |
859 | */ |
860 | u16 bdf; |
861 | |
862 | /* Number of CPUs */ |
863 | u16 num_cpus; |
864 | |
865 | u16 reserved; |
866 | |
867 | /* 0 : reserved |
868 | * 1 : rx_offset |
869 | * 2 : interrupt_moderation |
870 | * 3 : rx_buf_mirroring |
871 | * 4 : rss_configurable_function_key |
872 | * 5 : reserved |
873 | * 6 : rx_page_reuse |
874 | * 31:7 : reserved |
875 | */ |
876 | u32 driver_supported_features; |
877 | }; |
878 | |
879 | struct { |
880 | u16 ; |
881 | |
882 | u16 ; |
883 | }; |
884 | |
885 | struct { |
886 | /* min supported table size (2^min_size) */ |
887 | u16 ; |
888 | |
889 | /* max supported table size (2^max_size) */ |
890 | u16 ; |
891 | |
892 | /* table size (2^size) */ |
893 | u16 ; |
894 | |
895 | u16 ; |
896 | |
897 | /* index of the inline entry. 0xFFFFFFFF means invalid */ |
898 | u32 ; |
899 | |
900 | /* used for updating single entry, ignored when setting the entire |
901 | * table through the control buffer. |
902 | */ |
903 | struct ena_admin_rss_ind_table_entry ; |
904 | }; |
905 | |
906 | /* When hint value is 0, driver should use it's own predefined value */ |
907 | struct ena_admin_ena_hw_hints { |
908 | /* value in ms */ |
909 | u16 mmio_read_timeout; |
910 | |
911 | /* value in ms */ |
912 | u16 driver_watchdog_timeout; |
913 | |
914 | /* Per packet tx completion timeout. value in ms */ |
915 | u16 missing_tx_completion_timeout; |
916 | |
917 | u16 missed_tx_completion_count_threshold_to_reset; |
918 | |
919 | /* value in ms */ |
920 | u16 admin_completion_tx_timeout; |
921 | |
922 | u16 netdev_wd_timeout; |
923 | |
924 | u16 max_tx_sgl_size; |
925 | |
926 | u16 max_rx_sgl_size; |
927 | |
928 | u16 reserved[8]; |
929 | }; |
930 | |
931 | struct ena_admin_get_feat_cmd { |
932 | struct ena_admin_aq_common_desc aq_common_descriptor; |
933 | |
934 | struct ena_admin_ctrl_buff_info control_buffer; |
935 | |
936 | struct ena_admin_get_set_feature_common_desc feat_common; |
937 | |
938 | u32 raw[11]; |
939 | }; |
940 | |
941 | struct ena_admin_queue_ext_feature_desc { |
942 | /* version */ |
943 | u8 version; |
944 | |
945 | u8 reserved1[3]; |
946 | |
947 | union { |
948 | struct ena_admin_queue_ext_feature_fields max_queue_ext; |
949 | |
950 | u32 raw[10]; |
951 | }; |
952 | }; |
953 | |
954 | struct ena_admin_get_feat_resp { |
955 | struct ena_admin_acq_common_desc acq_common_desc; |
956 | |
957 | union { |
958 | u32 raw[14]; |
959 | |
960 | struct ena_admin_device_attr_feature_desc dev_attr; |
961 | |
962 | struct ena_admin_feature_llq_desc llq; |
963 | |
964 | struct ena_admin_queue_feature_desc max_queue; |
965 | |
966 | struct ena_admin_queue_ext_feature_desc max_queue_ext; |
967 | |
968 | struct ena_admin_feature_aenq_desc aenq; |
969 | |
970 | struct ena_admin_get_feature_link_desc link; |
971 | |
972 | struct ena_admin_feature_offload_desc offload; |
973 | |
974 | struct ena_admin_feature_rss_flow_hash_function flow_hash_func; |
975 | |
976 | struct ena_admin_feature_rss_flow_hash_input flow_hash_input; |
977 | |
978 | struct ena_admin_feature_rss_ind_table ind_table; |
979 | |
980 | struct ena_admin_feature_intr_moder_desc intr_moderation; |
981 | |
982 | struct ena_admin_ena_hw_hints hw_hints; |
983 | } u; |
984 | }; |
985 | |
986 | struct ena_admin_set_feat_cmd { |
987 | struct ena_admin_aq_common_desc aq_common_descriptor; |
988 | |
989 | struct ena_admin_ctrl_buff_info control_buffer; |
990 | |
991 | struct ena_admin_get_set_feature_common_desc feat_common; |
992 | |
993 | union { |
994 | u32 raw[11]; |
995 | |
996 | /* mtu size */ |
997 | struct ena_admin_set_feature_mtu_desc mtu; |
998 | |
999 | /* host attributes */ |
1000 | struct ena_admin_set_feature_host_attr_desc host_attr; |
1001 | |
1002 | /* AENQ configuration */ |
1003 | struct ena_admin_feature_aenq_desc aenq; |
1004 | |
1005 | /* rss flow hash function */ |
1006 | struct ena_admin_feature_rss_flow_hash_function flow_hash_func; |
1007 | |
1008 | /* rss flow hash input */ |
1009 | struct ena_admin_feature_rss_flow_hash_input flow_hash_input; |
1010 | |
1011 | /* rss indirection table */ |
1012 | struct ena_admin_feature_rss_ind_table ind_table; |
1013 | |
1014 | /* LLQ configuration */ |
1015 | struct ena_admin_feature_llq_desc llq; |
1016 | } u; |
1017 | }; |
1018 | |
1019 | struct ena_admin_set_feat_resp { |
1020 | struct ena_admin_acq_common_desc acq_common_desc; |
1021 | |
1022 | union { |
1023 | u32 raw[14]; |
1024 | } u; |
1025 | }; |
1026 | |
1027 | struct ena_admin_aenq_common_desc { |
1028 | u16 group; |
1029 | |
1030 | u16 syndrome; |
1031 | |
1032 | /* 0 : phase |
1033 | * 7:1 : reserved - MBZ |
1034 | */ |
1035 | u8 flags; |
1036 | |
1037 | u8 reserved1[3]; |
1038 | |
1039 | u32 timestamp_low; |
1040 | |
1041 | u32 timestamp_high; |
1042 | }; |
1043 | |
1044 | /* asynchronous event notification groups */ |
1045 | enum ena_admin_aenq_group { |
1046 | ENA_ADMIN_LINK_CHANGE = 0, |
1047 | ENA_ADMIN_FATAL_ERROR = 1, |
1048 | ENA_ADMIN_WARNING = 2, |
1049 | ENA_ADMIN_NOTIFICATION = 3, |
1050 | ENA_ADMIN_KEEP_ALIVE = 4, |
1051 | ENA_ADMIN_AENQ_GROUPS_NUM = 5, |
1052 | }; |
1053 | |
1054 | enum ena_admin_aenq_notification_syndrome { |
1055 | ENA_ADMIN_UPDATE_HINTS = 2, |
1056 | }; |
1057 | |
1058 | struct ena_admin_aenq_entry { |
1059 | struct ena_admin_aenq_common_desc aenq_common_desc; |
1060 | |
1061 | /* command specific inline data */ |
1062 | u32 inline_data_w4[12]; |
1063 | }; |
1064 | |
1065 | struct ena_admin_aenq_link_change_desc { |
1066 | struct ena_admin_aenq_common_desc aenq_common_desc; |
1067 | |
1068 | /* 0 : link_status */ |
1069 | u32 flags; |
1070 | }; |
1071 | |
1072 | struct ena_admin_aenq_keep_alive_desc { |
1073 | struct ena_admin_aenq_common_desc aenq_common_desc; |
1074 | |
1075 | u32 rx_drops_low; |
1076 | |
1077 | u32 rx_drops_high; |
1078 | |
1079 | u32 tx_drops_low; |
1080 | |
1081 | u32 tx_drops_high; |
1082 | }; |
1083 | |
1084 | struct ena_admin_ena_mmio_req_read_less_resp { |
1085 | u16 req_id; |
1086 | |
1087 | u16 reg_off; |
1088 | |
1089 | /* value is valid when poll is cleared */ |
1090 | u32 reg_val; |
1091 | }; |
1092 | |
1093 | /* aq_common_desc */ |
1094 | #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) |
1095 | #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) |
1096 | #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 |
1097 | #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) |
1098 | #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 |
1099 | #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) |
1100 | |
1101 | /* sq */ |
1102 | #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 |
1103 | #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) |
1104 | |
1105 | /* acq_common_desc */ |
1106 | #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) |
1107 | #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) |
1108 | |
1109 | /* aq_create_sq_cmd */ |
1110 | #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 |
1111 | #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) |
1112 | #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) |
1113 | #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 |
1114 | #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) |
1115 | #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) |
1116 | |
1117 | /* aq_create_cq_cmd */ |
1118 | #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 |
1119 | #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) |
1120 | #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) |
1121 | |
1122 | /* get_set_feature_common_desc */ |
1123 | #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) |
1124 | |
1125 | /* get_feature_link_desc */ |
1126 | #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) |
1127 | #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 |
1128 | #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) |
1129 | |
1130 | /* feature_offload_desc */ |
1131 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) |
1132 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 |
1133 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) |
1134 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 |
1135 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) |
1136 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 |
1137 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) |
1138 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 |
1139 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) |
1140 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 |
1141 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) |
1142 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 |
1143 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) |
1144 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 |
1145 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) |
1146 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) |
1147 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 |
1148 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) |
1149 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 |
1150 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) |
1151 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 |
1152 | #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) |
1153 | |
1154 | /* feature_rss_flow_hash_function */ |
1155 | #define GENMASK(7, 0) |
1156 | #define GENMASK(7, 0) |
1157 | |
1158 | /* feature_rss_flow_hash_input */ |
1159 | #define 1 |
1160 | #define BIT(1) |
1161 | #define 2 |
1162 | #define BIT(2) |
1163 | #define 1 |
1164 | #define BIT(1) |
1165 | #define 2 |
1166 | #define BIT(2) |
1167 | |
1168 | /* host_info */ |
1169 | #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) |
1170 | #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 |
1171 | #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) |
1172 | #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 |
1173 | #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) |
1174 | #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 |
1175 | #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) |
1176 | #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) |
1177 | #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 |
1178 | #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) |
1179 | #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 |
1180 | #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) |
1181 | #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 |
1182 | #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) |
1183 | #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 |
1184 | #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) |
1185 | #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 |
1186 | #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) |
1187 | #define 4 |
1188 | #define BIT(4) |
1189 | #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 6 |
1190 | #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6) |
1191 | |
1192 | /* aenq_common_desc */ |
1193 | #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) |
1194 | |
1195 | /* aenq_link_change_desc */ |
1196 | #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) |
1197 | |
1198 | #endif /* _ENA_ADMIN_H_ */ |
1199 | |