1 | /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ |
2 | /* |
3 | * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. |
4 | */ |
5 | #ifndef _ENA_ETH_IO_H_ |
6 | #define _ENA_ETH_IO_H_ |
7 | |
8 | enum ena_eth_io_l3_proto_index { |
9 | ENA_ETH_IO_L3_PROTO_UNKNOWN = 0, |
10 | ENA_ETH_IO_L3_PROTO_IPV4 = 8, |
11 | ENA_ETH_IO_L3_PROTO_IPV6 = 11, |
12 | ENA_ETH_IO_L3_PROTO_FCOE = 21, |
13 | ENA_ETH_IO_L3_PROTO_ROCE = 22, |
14 | }; |
15 | |
16 | enum ena_eth_io_l4_proto_index { |
17 | ENA_ETH_IO_L4_PROTO_UNKNOWN = 0, |
18 | ENA_ETH_IO_L4_PROTO_TCP = 12, |
19 | ENA_ETH_IO_L4_PROTO_UDP = 13, |
20 | ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23, |
21 | }; |
22 | |
23 | struct ena_eth_io_tx_desc { |
24 | /* 15:0 : length - Buffer length in bytes, must |
25 | * include any packet trailers that the ENA supposed |
26 | * to update like End-to-End CRC, Authentication GMAC |
27 | * etc. This length must not include the |
28 | * 'Push_Buffer' length. This length must not include |
29 | * the 4-byte added in the end for 802.3 Ethernet FCS |
30 | * 21:16 : req_id_hi - Request ID[15:10] |
31 | * 22 : reserved22 - MBZ |
32 | * 23 : meta_desc - MBZ |
33 | * 24 : phase |
34 | * 25 : reserved1 - MBZ |
35 | * 26 : first - Indicates first descriptor in |
36 | * transaction |
37 | * 27 : last - Indicates last descriptor in |
38 | * transaction |
39 | * 28 : comp_req - Indicates whether completion |
40 | * should be posted, after packet is transmitted. |
41 | * Valid only for first descriptor |
42 | * 30:29 : reserved29 - MBZ |
43 | * 31 : reserved31 - MBZ |
44 | */ |
45 | u32 len_ctrl; |
46 | |
47 | /* 3:0 : l3_proto_idx - L3 protocol. This field |
48 | * required when l3_csum_en,l3_csum or tso_en are set. |
49 | * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and |
50 | * DF flags of the IPv4 header is 0. Otherwise must |
51 | * be set to 1 |
52 | * 6:5 : reserved5 |
53 | * 7 : tso_en - Enable TSO, For TCP only. |
54 | * 12:8 : l4_proto_idx - L4 protocol. This field need |
55 | * to be set when l4_csum_en or tso_en are set. |
56 | * 13 : l3_csum_en - enable IPv4 header checksum. |
57 | * 14 : l4_csum_en - enable TCP/UDP checksum. |
58 | * 15 : ethernet_fcs_dis - when set, the controller |
59 | * will not append the 802.3 Ethernet Frame Check |
60 | * Sequence to the packet |
61 | * 16 : reserved16 |
62 | * 17 : l4_csum_partial - L4 partial checksum. when |
63 | * set to 0, the ENA calculates the L4 checksum, |
64 | * where the Destination Address required for the |
65 | * TCP/UDP pseudo-header is taken from the actual |
66 | * packet L3 header. when set to 1, the ENA doesn't |
67 | * calculate the sum of the pseudo-header, instead, |
68 | * the checksum field of the L4 is used instead. When |
69 | * TSO enabled, the checksum of the pseudo-header |
70 | * must not include the tcp length field. L4 partial |
71 | * checksum should be used for IPv6 packet that |
72 | * contains Routing Headers. |
73 | * 20:18 : reserved18 - MBZ |
74 | * 21 : reserved21 - MBZ |
75 | * 31:22 : req_id_lo - Request ID[9:0] |
76 | */ |
77 | u32 meta_ctrl; |
78 | |
79 | u32 buff_addr_lo; |
80 | |
81 | /* address high and header size |
82 | * 15:0 : addr_hi - Buffer Pointer[47:32] |
83 | * 23:16 : reserved16_w2 |
84 | * 31:24 : header_length - Header length. For Low |
85 | * Latency Queues, this fields indicates the number |
86 | * of bytes written to the headers' memory. For |
87 | * normal queues, if packet is TCP or UDP, and longer |
88 | * than max_header_size, then this field should be |
89 | * set to the sum of L4 header offset and L4 header |
90 | * size(without options), otherwise, this field |
91 | * should be set to 0. For both modes, this field |
92 | * must not exceed the max_header_size. |
93 | * max_header_size value is reported by the Max |
94 | * Queues Feature descriptor |
95 | */ |
96 | u32 buff_addr_hi_hdr_sz; |
97 | }; |
98 | |
99 | struct ena_eth_io_tx_meta_desc { |
100 | /* 9:0 : req_id_lo - Request ID[9:0] |
101 | * 11:10 : reserved10 - MBZ |
102 | * 12 : reserved12 - MBZ |
103 | * 13 : reserved13 - MBZ |
104 | * 14 : ext_valid - if set, offset fields in Word2 |
105 | * are valid Also MSS High in Word 0 and bits [31:24] |
106 | * in Word 3 |
107 | * 15 : reserved15 |
108 | * 19:16 : mss_hi |
109 | * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1: |
110 | * Extended Metadata Descriptor |
111 | * 21 : meta_store - Store extended metadata in queue |
112 | * cache |
113 | * 22 : reserved22 - MBZ |
114 | * 23 : meta_desc - MBO |
115 | * 24 : phase |
116 | * 25 : reserved25 - MBZ |
117 | * 26 : first - Indicates first descriptor in |
118 | * transaction |
119 | * 27 : last - Indicates last descriptor in |
120 | * transaction |
121 | * 28 : comp_req - Indicates whether completion |
122 | * should be posted, after packet is transmitted. |
123 | * Valid only for first descriptor |
124 | * 30:29 : reserved29 - MBZ |
125 | * 31 : reserved31 - MBZ |
126 | */ |
127 | u32 len_ctrl; |
128 | |
129 | /* 5:0 : req_id_hi |
130 | * 31:6 : reserved6 - MBZ |
131 | */ |
132 | u32 word1; |
133 | |
134 | /* 7:0 : l3_hdr_len |
135 | * 15:8 : l3_hdr_off |
136 | * 21:16 : l4_hdr_len_in_words - counts the L4 header |
137 | * length in words. there is an explicit assumption |
138 | * that L4 header appears right after L3 header and |
139 | * L4 offset is based on l3_hdr_off+l3_hdr_len |
140 | * 31:22 : mss_lo |
141 | */ |
142 | u32 word2; |
143 | |
144 | u32 reserved; |
145 | }; |
146 | |
147 | struct ena_eth_io_tx_cdesc { |
148 | /* Request ID[15:0] */ |
149 | u16 req_id; |
150 | |
151 | u8 status; |
152 | |
153 | /* flags |
154 | * 0 : phase |
155 | * 7:1 : reserved1 |
156 | */ |
157 | u8 flags; |
158 | |
159 | u16 sub_qid; |
160 | |
161 | u16 sq_head_idx; |
162 | }; |
163 | |
164 | struct ena_eth_io_rx_desc { |
165 | /* In bytes. 0 means 64KB */ |
166 | u16 length; |
167 | |
168 | /* MBZ */ |
169 | u8 reserved2; |
170 | |
171 | /* 0 : phase |
172 | * 1 : reserved1 - MBZ |
173 | * 2 : first - Indicates first descriptor in |
174 | * transaction |
175 | * 3 : last - Indicates last descriptor in transaction |
176 | * 4 : comp_req |
177 | * 5 : reserved5 - MBO |
178 | * 7:6 : reserved6 - MBZ |
179 | */ |
180 | u8 ctrl; |
181 | |
182 | u16 req_id; |
183 | |
184 | /* MBZ */ |
185 | u16 reserved6; |
186 | |
187 | u32 buff_addr_lo; |
188 | |
189 | u16 buff_addr_hi; |
190 | |
191 | /* MBZ */ |
192 | u16 reserved16_w3; |
193 | }; |
194 | |
195 | /* 4-word format Note: all ethernet parsing information are valid only when |
196 | * last=1 |
197 | */ |
198 | struct ena_eth_io_rx_cdesc_base { |
199 | /* 4:0 : l3_proto_idx |
200 | * 6:5 : src_vlan_cnt |
201 | * 7 : reserved7 - MBZ |
202 | * 12:8 : l4_proto_idx |
203 | * 13 : l3_csum_err - when set, either the L3 |
204 | * checksum error detected, or, the controller didn't |
205 | * validate the checksum. This bit is valid only when |
206 | * l3_proto_idx indicates IPv4 packet |
207 | * 14 : l4_csum_err - when set, either the L4 |
208 | * checksum error detected, or, the controller didn't |
209 | * validate the checksum. This bit is valid only when |
210 | * l4_proto_idx indicates TCP/UDP packet, and, |
211 | * ipv4_frag is not set. This bit is valid only when |
212 | * l4_csum_checked below is set. |
213 | * 15 : ipv4_frag - Indicates IPv4 fragmented packet |
214 | * 16 : l4_csum_checked - L4 checksum was verified |
215 | * (could be OK or error), when cleared the status of |
216 | * checksum is unknown |
217 | * 23:17 : reserved17 - MBZ |
218 | * 24 : phase |
219 | * 25 : l3_csum2 - second checksum engine result |
220 | * 26 : first - Indicates first descriptor in |
221 | * transaction |
222 | * 27 : last - Indicates last descriptor in |
223 | * transaction |
224 | * 29:28 : reserved28 |
225 | * 30 : buffer - 0: Metadata descriptor. 1: Buffer |
226 | * Descriptor was used |
227 | * 31 : reserved31 |
228 | */ |
229 | u32 status; |
230 | |
231 | u16 length; |
232 | |
233 | u16 req_id; |
234 | |
235 | /* 32-bit hash result */ |
236 | u32 hash; |
237 | |
238 | u16 sub_qid; |
239 | |
240 | u8 offset; |
241 | |
242 | u8 reserved; |
243 | }; |
244 | |
245 | /* 8-word format */ |
246 | struct ena_eth_io_rx_cdesc_ext { |
247 | struct ena_eth_io_rx_cdesc_base base; |
248 | |
249 | u32 buff_addr_lo; |
250 | |
251 | u16 buff_addr_hi; |
252 | |
253 | u16 reserved16; |
254 | |
255 | u32 reserved_w6; |
256 | |
257 | u32 reserved_w7; |
258 | }; |
259 | |
260 | struct ena_eth_io_intr_reg { |
261 | /* 14:0 : rx_intr_delay |
262 | * 29:15 : tx_intr_delay |
263 | * 30 : intr_unmask |
264 | * 31 : reserved |
265 | */ |
266 | u32 intr_control; |
267 | }; |
268 | |
269 | struct ena_eth_io_numa_node_cfg_reg { |
270 | /* 7:0 : numa |
271 | * 30:8 : reserved |
272 | * 31 : enabled |
273 | */ |
274 | u32 numa_cfg; |
275 | }; |
276 | |
277 | /* tx_desc */ |
278 | #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0) |
279 | #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16 |
280 | #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) |
281 | #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23 |
282 | #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) |
283 | #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24 |
284 | #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) |
285 | #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26 |
286 | #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) |
287 | #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27 |
288 | #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) |
289 | #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28 |
290 | #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) |
291 | #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) |
292 | #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4 |
293 | #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) |
294 | #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7 |
295 | #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) |
296 | #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8 |
297 | #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) |
298 | #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13 |
299 | #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) |
300 | #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14 |
301 | #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) |
302 | #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 |
303 | #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) |
304 | #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 |
305 | #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) |
306 | #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22 |
307 | #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) |
308 | #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) |
309 | #define 24 |
310 | #define GENMASK(31, 24) |
311 | |
312 | /* tx_meta_desc */ |
313 | #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) |
314 | #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14 |
315 | #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) |
316 | #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16 |
317 | #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) |
318 | #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20 |
319 | #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) |
320 | #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21 |
321 | #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) |
322 | #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23 |
323 | #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) |
324 | #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24 |
325 | #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) |
326 | #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26 |
327 | #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) |
328 | #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27 |
329 | #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) |
330 | #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28 |
331 | #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) |
332 | #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) |
333 | #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) |
334 | #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8 |
335 | #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) |
336 | #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16 |
337 | #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16) |
338 | #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22 |
339 | #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) |
340 | |
341 | /* tx_cdesc */ |
342 | #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) |
343 | |
344 | /* rx_desc */ |
345 | #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) |
346 | #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2 |
347 | #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) |
348 | #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3 |
349 | #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) |
350 | #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4 |
351 | #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) |
352 | |
353 | /* rx_cdesc_base */ |
354 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) |
355 | #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 |
356 | #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) |
357 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 |
358 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) |
359 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 |
360 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) |
361 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14 |
362 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) |
363 | #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15 |
364 | #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) |
365 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16 |
366 | #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16) |
367 | #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 |
368 | #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) |
369 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 |
370 | #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) |
371 | #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26 |
372 | #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) |
373 | #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27 |
374 | #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) |
375 | #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30 |
376 | #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) |
377 | |
378 | /* intr_reg */ |
379 | #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0) |
380 | #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15 |
381 | #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15) |
382 | #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30 |
383 | #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) |
384 | |
385 | /* numa_node_cfg_reg */ |
386 | #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0) |
387 | #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31 |
388 | #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) |
389 | |
390 | #endif /* _ENA_ETH_IO_H_ */ |
391 | |