1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. |
4 | * |
5 | * Derived from Intel e1000 driver |
6 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
7 | */ |
8 | |
9 | #ifndef _ATL1C_HW_H_ |
10 | #define _ATL1C_HW_H_ |
11 | |
12 | #include <linux/types.h> |
13 | #include <linux/mii.h> |
14 | |
15 | #define FIELD_GETX(_x, _name) ((_x) >> (_name##_SHIFT) & (_name##_MASK)) |
16 | #define FIELD_SETX(_x, _name, _v) \ |
17 | (((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\ |
18 | (((_v) & (_name##_MASK)) << (_name##_SHIFT))) |
19 | #define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT)) |
20 | |
21 | struct atl1c_adapter; |
22 | struct atl1c_hw; |
23 | |
24 | /* function prototype */ |
25 | void atl1c_phy_disable(struct atl1c_hw *hw); |
26 | void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr); |
27 | int atl1c_phy_reset(struct atl1c_hw *hw); |
28 | int atl1c_read_mac_addr(struct atl1c_hw *hw); |
29 | bool atl1c_get_link_status(struct atl1c_hw *hw); |
30 | int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex); |
31 | u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr); |
32 | void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value); |
33 | int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); |
34 | int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data); |
35 | bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value); |
36 | int atl1c_phy_init(struct atl1c_hw *hw); |
37 | int atl1c_check_eeprom_exist(struct atl1c_hw *hw); |
38 | int atl1c_restart_autoneg(struct atl1c_hw *hw); |
39 | int atl1c_phy_to_ps_link(struct atl1c_hw *hw); |
40 | int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc); |
41 | bool atl1c_wait_mdio_idle(struct atl1c_hw *hw); |
42 | void atl1c_stop_phy_polling(struct atl1c_hw *hw); |
43 | void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel); |
44 | int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, |
45 | u16 reg, u16 *phy_data); |
46 | int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, |
47 | u16 reg, u16 phy_data); |
48 | int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr, |
49 | u16 reg_addr, u16 *phy_data); |
50 | int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr, |
51 | u16 reg_addr, u16 phy_data); |
52 | int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); |
53 | int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data); |
54 | void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); |
55 | |
56 | /* hw-ids */ |
57 | #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062 |
58 | #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063 |
59 | #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */ |
60 | #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */ |
61 | #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */ |
62 | #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */ |
63 | #define L2CB_V10 0xc0 |
64 | #define L2CB_V11 0xc1 |
65 | #define L2CB_V20 0xc0 |
66 | #define L2CB_V21 0xc1 |
67 | |
68 | /* register definition */ |
69 | #define REG_DEVICE_CAP 0x5C |
70 | #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7 |
71 | #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0 |
72 | |
73 | #define DEVICE_CTRL_MAXRRS_MIN 2 |
74 | |
75 | #define REG_LINK_CTRL 0x68 |
76 | #define LINK_CTRL_L0S_EN 0x01 |
77 | #define LINK_CTRL_L1_EN 0x02 |
78 | #define LINK_CTRL_EXT_SYNC 0x80 |
79 | |
80 | #define REG_PCIE_IND_ACC_ADDR 0x80 |
81 | #define REG_PCIE_IND_ACC_DATA 0x84 |
82 | |
83 | #define REG_DEV_SERIALNUM_CTRL 0x200 |
84 | #define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */ |
85 | #define REG_DEV_MAC_SEL_SHIFT 0 |
86 | #define REG_DEV_SERIAL_NUM_EN_MASK 0x1 |
87 | #define REG_DEV_SERIAL_NUM_EN_SHIFT 1 |
88 | |
89 | #define REG_TWSI_CTRL 0x218 |
90 | #define TWSI_CTLR_FREQ_MASK 0x3UL |
91 | #define TWSI_CTRL_FREQ_SHIFT 24 |
92 | #define TWSI_CTRL_FREQ_100K 0 |
93 | #define TWSI_CTRL_FREQ_200K 1 |
94 | #define TWSI_CTRL_FREQ_300K 2 |
95 | #define TWSI_CTRL_FREQ_400K 3 |
96 | #define TWSI_CTRL_LD_EXIST BIT(23) |
97 | #define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */ |
98 | #define TWSI_CTRL_SW_LDSTART BIT(11) |
99 | #define TWSI_CTRL_LD_OFFSET_MASK 0xFF |
100 | #define TWSI_CTRL_LD_OFFSET_SHIFT 0 |
101 | |
102 | #define REG_PCIE_DEV_MISC_CTRL 0x21C |
103 | #define PCIE_DEV_MISC_EXT_PIPE 0x2 |
104 | #define PCIE_DEV_MISC_RETRY_BUFDIS 0x1 |
105 | #define PCIE_DEV_MISC_SPIROM_EXIST 0x4 |
106 | #define PCIE_DEV_MISC_SERDES_ENDIAN 0x8 |
107 | #define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10 |
108 | |
109 | #define REG_PCIE_PHYMISC 0x1000 |
110 | #define PCIE_PHYMISC_FORCE_RCV_DET BIT(2) |
111 | #define PCIE_PHYMISC_NFTS_MASK 0xFFUL |
112 | #define PCIE_PHYMISC_NFTS_SHIFT 16 |
113 | |
114 | #define REG_PCIE_PHYMISC2 0x1004 |
115 | #define PCIE_PHYMISC2_L0S_TH_MASK 0x3UL |
116 | #define PCIE_PHYMISC2_L0S_TH_SHIFT 18 |
117 | #define L2CB1_PCIE_PHYMISC2_L0S_TH 3 |
118 | #define PCIE_PHYMISC2_CDR_BW_MASK 0x3UL |
119 | #define PCIE_PHYMISC2_CDR_BW_SHIFT 16 |
120 | #define L2CB1_PCIE_PHYMISC2_CDR_BW 3 |
121 | |
122 | #define REG_TWSI_DEBUG 0x1108 |
123 | #define TWSI_DEBUG_DEV_EXIST BIT(29) |
124 | |
125 | #define REG_DMA_DBG 0x1114 |
126 | #define DMA_DBG_VENDOR_MSG BIT(0) |
127 | |
128 | #define REG_EEPROM_CTRL 0x12C0 |
129 | #define EEPROM_CTRL_DATA_HI_MASK 0xFFFF |
130 | #define EEPROM_CTRL_DATA_HI_SHIFT 0 |
131 | #define EEPROM_CTRL_ADDR_MASK 0x3FF |
132 | #define EEPROM_CTRL_ADDR_SHIFT 16 |
133 | #define EEPROM_CTRL_ACK 0x40000000 |
134 | #define EEPROM_CTRL_RW 0x80000000 |
135 | |
136 | #define REG_EEPROM_DATA_LO 0x12C4 |
137 | |
138 | #define REG_OTP_CTRL 0x12F0 |
139 | #define OTP_CTRL_CLK_EN BIT(1) |
140 | |
141 | #define REG_PM_CTRL 0x12F8 |
142 | #define PM_CTRL_HOTRST BIT(31) |
143 | #define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on |
144 | * thrghput(setting in 15A0) */ |
145 | #define PM_CTRL_SA_DLY_EN BIT(29) |
146 | #define PM_CTRL_L0S_BUFSRX_EN BIT(28) |
147 | #define PM_CTRL_LCKDET_TIMER_MASK 0xFUL |
148 | #define PM_CTRL_LCKDET_TIMER_SHIFT 24 |
149 | #define PM_CTRL_LCKDET_TIMER_DEF 0xC |
150 | #define PM_CTRL_PM_REQ_TIMER_MASK 0xFUL |
151 | #define PM_CTRL_PM_REQ_TIMER_SHIFT 20 /* pm_request_l1 time > @ |
152 | * ->L0s not L1 */ |
153 | #define PM_CTRL_PM_REQ_TO_DEF 0xF |
154 | #define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */ |
155 | #define L1D_PMCTRL_L1_ENTRY_TM_MASK 7UL /* l1dv2.0+, 3bits */ |
156 | #define L1D_PMCTRL_L1_ENTRY_TM_SHIFT 16 |
157 | #define L1D_PMCTRL_L1_ENTRY_TM_DIS 0 |
158 | #define L1D_PMCTRL_L1_ENTRY_TM_2US 1 |
159 | #define L1D_PMCTRL_L1_ENTRY_TM_4US 2 |
160 | #define L1D_PMCTRL_L1_ENTRY_TM_8US 3 |
161 | #define L1D_PMCTRL_L1_ENTRY_TM_16US 4 |
162 | #define L1D_PMCTRL_L1_ENTRY_TM_24US 5 |
163 | #define L1D_PMCTRL_L1_ENTRY_TM_32US 6 |
164 | #define L1D_PMCTRL_L1_ENTRY_TM_63US 7 |
165 | #define PM_CTRL_L1_ENTRY_TIMER_MASK 0xFUL /* l1C 4bits */ |
166 | #define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16 |
167 | #define L2CB1_PM_CTRL_L1_ENTRY_TM 7 |
168 | #define L1C_PM_CTRL_L1_ENTRY_TM 0xF |
169 | #define PM_CTRL_RCVR_WT_TIMER BIT(15) /* 1:1us, 0:2ms */ |
170 | #define PM_CTRL_CLK_PWM_VER1_1 BIT(14) /* 0:1.0a,1:1.1 */ |
171 | #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */ |
172 | #define PM_CTRL_ASPM_L0S_EN BIT(12) |
173 | #define PM_CTRL_RXL1_AFTER_L0S BIT(11) /* l1dv2.0+ */ |
174 | #define L1D_PMCTRL_L0S_TIMER_MASK 7UL /* l1d2.0+, 3bits*/ |
175 | #define L1D_PMCTRL_L0S_TIMER_SHIFT 8 |
176 | #define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xFUL /* l1c, 4bits */ |
177 | #define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8 |
178 | #define PM_CTRL_SERDES_BUFS_RX_L1_EN BIT(7) |
179 | #define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */ |
180 | #define PM_CTRL_SERDES_PLL_L1_EN BIT(5) |
181 | #define PM_CTRL_SERDES_L1_EN BIT(4) |
182 | #define PM_CTRL_ASPM_L1_EN BIT(3) |
183 | #define PM_CTRL_CLK_REQ_EN BIT(2) |
184 | #define PM_CTRL_RBER_EN BIT(1) |
185 | #define PM_CTRL_SPRSDWER_EN BIT(0) |
186 | |
187 | #define REG_LTSSM_ID_CTRL 0x12FC |
188 | #define LTSSM_ID_EN_WRO 0x1000 |
189 | |
190 | |
191 | /* Selene Master Control Register */ |
192 | #define REG_MASTER_CTRL 0x1400 |
193 | #define MASTER_CTRL_OTP_SEL BIT(31) |
194 | #define MASTER_DEV_NUM_MASK 0x7FUL |
195 | #define MASTER_DEV_NUM_SHIFT 24 |
196 | #define MASTER_REV_NUM_MASK 0xFFUL |
197 | #define MASTER_REV_NUM_SHIFT 16 |
198 | #define MASTER_CTRL_INT_RDCLR BIT(14) |
199 | #define MASTER_CTRL_CLK_SEL_DIS BIT(12) /* 1:alwys sel pclk from |
200 | * serdes, not sw to 25M */ |
201 | #define MASTER_CTRL_RX_ITIMER_EN BIT(11) /* IRQ MODURATION FOR RX */ |
202 | #define MASTER_CTRL_TX_ITIMER_EN BIT(10) /* MODURATION FOR TX/RX */ |
203 | #define MASTER_CTRL_MANU_INT BIT(9) /* SOFT MANUAL INT */ |
204 | #define MASTER_CTRL_MANUTIMER_EN BIT(8) |
205 | #define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */ |
206 | #define MASTER_CTRL_OOB_DIS BIT(6) /* OUT OF BOX DIS */ |
207 | #define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */ |
208 | #define MASTER_CTRL_BERT_START BIT(4) |
209 | #define MASTER_PCIE_TSTMOD_MASK 3UL |
210 | #define MASTER_PCIE_TSTMOD_SHIFT 2 |
211 | #define MASTER_PCIE_RST BIT(1) |
212 | #define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */ |
213 | #define DMA_MAC_RST_TO 50 |
214 | |
215 | /* Timer Initial Value Register */ |
216 | #define REG_MANUAL_TIMER_INIT 0x1404 |
217 | |
218 | /* IRQ ModeratorTimer Initial Value Register */ |
219 | #define REG_IRQ_MODRT_TIMER_INIT 0x1408 |
220 | #define IRQ_MODRT_TIMER_MASK 0xffff |
221 | #define IRQ_MODRT_TX_TIMER_SHIFT 0 |
222 | #define IRQ_MODRT_RX_TIMER_SHIFT 16 |
223 | |
224 | #define REG_GPHY_CTRL 0x140C |
225 | #define GPHY_CTRL_ADDR_MASK 0x1FUL |
226 | #define GPHY_CTRL_ADDR_SHIFT 19 |
227 | #define GPHY_CTRL_BP_VLTGSW BIT(18) |
228 | #define GPHY_CTRL_100AB_EN BIT(17) |
229 | #define GPHY_CTRL_10AB_EN BIT(16) |
230 | #define GPHY_CTRL_PHY_PLL_BYPASS BIT(15) |
231 | #define GPHY_CTRL_PWDOWN_HW BIT(14) /* affect MAC&PHY, to low pw */ |
232 | #define GPHY_CTRL_PHY_PLL_ON BIT(13) /* 1:pll always on, 0:can sw */ |
233 | #define GPHY_CTRL_SEL_ANA_RST BIT(12) |
234 | #define GPHY_CTRL_HIB_PULSE BIT(11) |
235 | #define GPHY_CTRL_HIB_EN BIT(10) |
236 | #define GPHY_CTRL_GIGA_DIS BIT(9) |
237 | #define GPHY_CTRL_PHY_IDDQ_DIS BIT(8) /* pw on RST */ |
238 | #define GPHY_CTRL_PHY_IDDQ BIT(7) /* bit8 affect bit7 while rb */ |
239 | #define GPHY_CTRL_LPW_EXIT BIT(6) |
240 | #define GPHY_CTRL_GATE_25M_EN BIT(5) |
241 | #define GPHY_CTRL_REV_ANEG BIT(4) |
242 | #define GPHY_CTRL_ANEG_NOW BIT(3) |
243 | #define GPHY_CTRL_LED_MODE BIT(2) |
244 | #define GPHY_CTRL_RTL_MODE BIT(1) |
245 | #define GPHY_CTRL_EXT_RESET BIT(0) /* 1:out of DSP RST status */ |
246 | #define GPHY_CTRL_EXT_RST_TO 80 /* 800us atmost */ |
247 | #define GPHY_CTRL_CLS (\ |
248 | GPHY_CTRL_LED_MODE |\ |
249 | GPHY_CTRL_100AB_EN |\ |
250 | GPHY_CTRL_PHY_PLL_ON) |
251 | |
252 | /* Block IDLE Status Register */ |
253 | #define REG_IDLE_STATUS 0x1410 |
254 | #define IDLE_STATUS_SFORCE_MASK 0xFUL |
255 | #define IDLE_STATUS_SFORCE_SHIFT 14 |
256 | #define IDLE_STATUS_CALIB_DONE BIT(13) |
257 | #define IDLE_STATUS_CALIB_RES_MASK 0x1FUL |
258 | #define IDLE_STATUS_CALIB_RES_SHIFT 8 |
259 | #define IDLE_STATUS_CALIBERR_MASK 0xFUL |
260 | #define IDLE_STATUS_CALIBERR_SHIFT 4 |
261 | #define IDLE_STATUS_TXQ_BUSY BIT(3) |
262 | #define IDLE_STATUS_RXQ_BUSY BIT(2) |
263 | #define IDLE_STATUS_TXMAC_BUSY BIT(1) |
264 | #define IDLE_STATUS_RXMAC_BUSY BIT(0) |
265 | #define IDLE_STATUS_MASK (\ |
266 | IDLE_STATUS_TXQ_BUSY |\ |
267 | IDLE_STATUS_RXQ_BUSY |\ |
268 | IDLE_STATUS_TXMAC_BUSY |\ |
269 | IDLE_STATUS_RXMAC_BUSY) |
270 | |
271 | /* MDIO Control Register */ |
272 | #define REG_MDIO_CTRL 0x1414 |
273 | #define MDIO_CTRL_MODE_EXT BIT(30) |
274 | #define MDIO_CTRL_POST_READ BIT(29) |
275 | #define MDIO_CTRL_AP_EN BIT(28) |
276 | #define MDIO_CTRL_BUSY BIT(27) |
277 | #define MDIO_CTRL_CLK_SEL_MASK 0x7UL |
278 | #define MDIO_CTRL_CLK_SEL_SHIFT 24 |
279 | #define MDIO_CTRL_CLK_25_4 0 /* 25MHz divide 4 */ |
280 | #define MDIO_CTRL_CLK_25_6 2 |
281 | #define MDIO_CTRL_CLK_25_8 3 |
282 | #define MDIO_CTRL_CLK_25_10 4 |
283 | #define MDIO_CTRL_CLK_25_32 5 |
284 | #define MDIO_CTRL_CLK_25_64 6 |
285 | #define MDIO_CTRL_CLK_25_128 7 |
286 | #define MDIO_CTRL_START BIT(23) |
287 | #define MDIO_CTRL_SPRES_PRMBL BIT(22) |
288 | #define MDIO_CTRL_OP_READ BIT(21) /* 1:read, 0:write */ |
289 | #define MDIO_CTRL_REG_MASK 0x1FUL |
290 | #define MDIO_CTRL_REG_SHIFT 16 |
291 | #define MDIO_CTRL_DATA_MASK 0xFFFFUL |
292 | #define MDIO_CTRL_DATA_SHIFT 0 |
293 | #define MDIO_MAX_AC_TO 120 /* 1.2ms timeout for slow clk */ |
294 | |
295 | /* for extension reg access */ |
296 | #define REG_MDIO_EXTN 0x1448 |
297 | #define MDIO_EXTN_PORTAD_MASK 0x1FUL |
298 | #define MDIO_EXTN_PORTAD_SHIFT 21 |
299 | #define MDIO_EXTN_DEVAD_MASK 0x1FUL |
300 | #define MDIO_EXTN_DEVAD_SHIFT 16 |
301 | #define MDIO_EXTN_REG_MASK 0xFFFFUL |
302 | #define MDIO_EXTN_REG_SHIFT 0 |
303 | |
304 | /* BIST Control and Status Register0 (for the Packet Memory) */ |
305 | #define REG_BIST0_CTRL 0x141c |
306 | #define BIST0_NOW 0x1 |
307 | #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is |
308 | * un-repairable because |
309 | * it has address decoder |
310 | * failure or more than 1 cell |
311 | * stuck-to-x failure */ |
312 | #define BIST0_FUSE_FLAG 0x4 |
313 | |
314 | /* BIST Control and Status Register1(for the retry buffer of PCI Express) */ |
315 | #define REG_BIST1_CTRL 0x1420 |
316 | #define BIST1_NOW 0x1 |
317 | #define BIST1_SRAM_FAIL 0x2 |
318 | #define BIST1_FUSE_FLAG 0x4 |
319 | |
320 | /* SerDes Lock Detect Control and Status Register */ |
321 | #define REG_SERDES 0x1424 |
322 | #define SERDES_PHY_CLK_SLOWDOWN BIT(18) |
323 | #define SERDES_MAC_CLK_SLOWDOWN BIT(17) |
324 | #define SERDES_SELFB_PLL_MASK 0x3UL |
325 | #define SERDES_SELFB_PLL_SHIFT 14 |
326 | #define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */ |
327 | #define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */ |
328 | #define SERDES_BUFS_RX_EN BIT(11) |
329 | #define SERDES_PD_RX BIT(10) |
330 | #define SERDES_PLL_EN BIT(9) |
331 | #define SERDES_EN BIT(8) |
332 | #define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */ |
333 | #define SERDES_SELFB_PLL_CSR_MASK 0x3UL |
334 | #define SERDES_SELFB_PLL_CSR_SHIFT 4 |
335 | #define SERDES_SELFB_PLL_CSR_4 3 /* 4-12% OV-CLK */ |
336 | #define SERDES_SELFB_PLL_CSR_0 2 /* 0-4% OV-CLK */ |
337 | #define SERDES_SELFB_PLL_CSR_12 1 /* 12-18% OV-CLK */ |
338 | #define SERDES_SELFB_PLL_CSR_18 0 /* 18-25% OV-CLK */ |
339 | #define SERDES_VCO_SLOW BIT(3) |
340 | #define SERDES_VCO_FAST BIT(2) |
341 | #define SERDES_LOCK_DETECT_EN BIT(1) |
342 | #define SERDES_LOCK_DETECT BIT(0) |
343 | |
344 | #define REG_LPI_DECISN_TIMER 0x143C |
345 | #define L2CB_LPI_DESISN_TIMER 0x7D00 |
346 | |
347 | #define REG_LPI_CTRL 0x1440 |
348 | #define LPI_CTRL_CHK_DA BIT(31) |
349 | #define LPI_CTRL_ENH_TO_MASK 0x1FFFUL |
350 | #define LPI_CTRL_ENH_TO_SHIFT 12 |
351 | #define LPI_CTRL_ENH_TH_MASK 0x1FUL |
352 | #define LPI_CTRL_ENH_TH_SHIFT 6 |
353 | #define LPI_CTRL_ENH_EN BIT(5) |
354 | #define LPI_CTRL_CHK_RX BIT(4) |
355 | #define LPI_CTRL_CHK_STATE BIT(3) |
356 | #define LPI_CTRL_GMII BIT(2) |
357 | #define LPI_CTRL_TO_PHY BIT(1) |
358 | #define LPI_CTRL_EN BIT(0) |
359 | |
360 | #define REG_LPI_WAIT 0x1444 |
361 | #define LPI_WAIT_TIMER_MASK 0xFFFFUL |
362 | #define LPI_WAIT_TIMER_SHIFT 0 |
363 | |
364 | /* MAC Control Register */ |
365 | #define REG_MAC_CTRL 0x1480 |
366 | #define MAC_CTRL_SPEED_MODE_SW BIT(30) /* 0:phy,1:sw */ |
367 | #define MAC_CTRL_HASH_ALG_CRC32 BIT(29) /* 1:legacy,0:lw_5b */ |
368 | #define MAC_CTRL_SINGLE_PAUSE_EN BIT(28) |
369 | #define MAC_CTRL_DBG BIT(27) |
370 | #define MAC_CTRL_BC_EN BIT(26) |
371 | #define MAC_CTRL_MC_ALL_EN BIT(25) |
372 | #define MAC_CTRL_RX_CHKSUM_EN BIT(24) |
373 | #define MAC_CTRL_TX_HUGE BIT(23) |
374 | #define MAC_CTRL_DBG_TX_BKPRESURE BIT(22) |
375 | #define MAC_CTRL_SPEED_MASK 3UL |
376 | #define MAC_CTRL_SPEED_SHIFT 20 |
377 | #define MAC_CTRL_SPEED_10_100 1 |
378 | #define MAC_CTRL_SPEED_1000 2 |
379 | #define MAC_CTRL_TX_SIMURST BIT(19) |
380 | #define MAC_CTRL_SCNT BIT(17) |
381 | #define MAC_CTRL_TX_PAUSE BIT(16) |
382 | #define MAC_CTRL_PROMIS_EN BIT(15) |
383 | #define MAC_CTRL_RMV_VLAN BIT(14) |
384 | #define MAC_CTRL_PRMLEN_MASK 0xFUL |
385 | #define MAC_CTRL_PRMLEN_SHIFT 10 |
386 | #define MAC_CTRL_HUGE_EN BIT(9) |
387 | #define MAC_CTRL_LENCHK BIT(8) |
388 | #define MAC_CTRL_PAD BIT(7) |
389 | #define MAC_CTRL_ADD_CRC BIT(6) |
390 | #define MAC_CTRL_DUPLX BIT(5) |
391 | #define MAC_CTRL_LOOPBACK BIT(4) |
392 | #define MAC_CTRL_RX_FLOW BIT(3) |
393 | #define MAC_CTRL_TX_FLOW BIT(2) |
394 | #define MAC_CTRL_RX_EN BIT(1) |
395 | #define MAC_CTRL_TX_EN BIT(0) |
396 | |
397 | /* MAC IPG/IFG Control Register */ |
398 | #define REG_MAC_IPG_IFG 0x1484 |
399 | #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back |
400 | * inter-packet gap. The |
401 | * default is 96-bit time */ |
402 | #define MAC_IPG_IFG_IPGT_MASK 0x7f |
403 | #define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to |
404 | * enforce in between RX frames */ |
405 | #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */ |
406 | #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */ |
407 | #define MAC_IPG_IFG_IPGR1_MASK 0x7f |
408 | #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */ |
409 | #define MAC_IPG_IFG_IPGR2_MASK 0x7f |
410 | |
411 | /* MAC STATION ADDRESS */ |
412 | #define REG_MAC_STA_ADDR 0x1488 |
413 | |
414 | /* Hash table for multicast address */ |
415 | #define REG_RX_HASH_TABLE 0x1490 |
416 | |
417 | /* MAC Half-Duplex Control Register */ |
418 | #define REG_MAC_HALF_DUPLX_CTRL 0x1498 |
419 | #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */ |
420 | #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff |
421 | #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 |
422 | #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf |
423 | #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 |
424 | #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 |
425 | #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure, |
426 | * immediately start the |
427 | * transmission after back pressure */ |
428 | #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */ |
429 | #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */ |
430 | #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf |
431 | #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */ |
432 | #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */ |
433 | |
434 | /* Maximum Frame Length Control Register */ |
435 | #define REG_MTU 0x149c |
436 | |
437 | /* Wake-On-Lan control register */ |
438 | #define REG_WOL_CTRL 0x14a0 |
439 | #define WOL_PT7_MATCH BIT(31) |
440 | #define WOL_PT6_MATCH BIT(30) |
441 | #define WOL_PT5_MATCH BIT(29) |
442 | #define WOL_PT4_MATCH BIT(28) |
443 | #define WOL_PT3_MATCH BIT(27) |
444 | #define WOL_PT2_MATCH BIT(26) |
445 | #define WOL_PT1_MATCH BIT(25) |
446 | #define WOL_PT0_MATCH BIT(24) |
447 | #define WOL_PT7_EN BIT(23) |
448 | #define WOL_PT6_EN BIT(22) |
449 | #define WOL_PT5_EN BIT(21) |
450 | #define WOL_PT4_EN BIT(20) |
451 | #define WOL_PT3_EN BIT(19) |
452 | #define WOL_PT2_EN BIT(18) |
453 | #define WOL_PT1_EN BIT(17) |
454 | #define WOL_PT0_EN BIT(16) |
455 | #define WOL_LNKCHG_ST BIT(10) |
456 | #define WOL_MAGIC_ST BIT(9) |
457 | #define WOL_PATTERN_ST BIT(8) |
458 | #define WOL_OOB_EN BIT(6) |
459 | #define WOL_LINK_CHG_PME_EN BIT(5) |
460 | #define WOL_LINK_CHG_EN BIT(4) |
461 | #define WOL_MAGIC_PME_EN BIT(3) |
462 | #define WOL_MAGIC_EN BIT(2) |
463 | #define WOL_PATTERN_PME_EN BIT(1) |
464 | #define WOL_PATTERN_EN BIT(0) |
465 | |
466 | /* WOL Length ( 2 DWORD ) */ |
467 | #define REG_WOL_PTLEN1 0x14A4 |
468 | #define WOL_PTLEN1_3_MASK 0xFFUL |
469 | #define WOL_PTLEN1_3_SHIFT 24 |
470 | #define WOL_PTLEN1_2_MASK 0xFFUL |
471 | #define WOL_PTLEN1_2_SHIFT 16 |
472 | #define WOL_PTLEN1_1_MASK 0xFFUL |
473 | #define WOL_PTLEN1_1_SHIFT 8 |
474 | #define WOL_PTLEN1_0_MASK 0xFFUL |
475 | #define WOL_PTLEN1_0_SHIFT 0 |
476 | |
477 | #define REG_WOL_PTLEN2 0x14A8 |
478 | #define WOL_PTLEN2_7_MASK 0xFFUL |
479 | #define WOL_PTLEN2_7_SHIFT 24 |
480 | #define WOL_PTLEN2_6_MASK 0xFFUL |
481 | #define WOL_PTLEN2_6_SHIFT 16 |
482 | #define WOL_PTLEN2_5_MASK 0xFFUL |
483 | #define WOL_PTLEN2_5_SHIFT 8 |
484 | #define WOL_PTLEN2_4_MASK 0xFFUL |
485 | #define WOL_PTLEN2_4_SHIFT 0 |
486 | |
487 | /* Internal SRAM Partition Register */ |
488 | #define RFDX_HEAD_ADDR_MASK 0x03FF |
489 | #define RFDX_HARD_ADDR_SHIFT 0 |
490 | #define RFDX_TAIL_ADDR_MASK 0x03FF |
491 | #define RFDX_TAIL_ADDR_SHIFT 16 |
492 | |
493 | #define REG_SRAM_RFD0_INFO 0x1500 |
494 | #define REG_SRAM_RFD1_INFO 0x1504 |
495 | #define REG_SRAM_RFD2_INFO 0x1508 |
496 | #define REG_SRAM_RFD3_INFO 0x150C |
497 | |
498 | #define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */ |
499 | #define RFD_NIC_LEN_MASK 0x03FF |
500 | |
501 | #define REG_SRAM_TRD_ADDR 0x1518 |
502 | #define TPD_HEAD_ADDR_MASK 0x03FF |
503 | #define TPD_HEAD_ADDR_SHIFT 0 |
504 | #define TPD_TAIL_ADDR_MASK 0x03FF |
505 | #define TPD_TAIL_ADDR_SHIFT 16 |
506 | |
507 | #define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */ |
508 | #define TPD_NIC_LEN_MASK 0x03FF |
509 | |
510 | #define REG_SRAM_RXF_ADDR 0x1520 |
511 | #define REG_SRAM_RXF_LEN 0x1524 |
512 | #define REG_SRAM_TXF_ADDR 0x1528 |
513 | #define REG_SRAM_TXF_LEN 0x152C |
514 | #define REG_SRAM_TCPH_ADDR 0x1530 |
515 | #define REG_SRAM_PKTH_ADDR 0x1532 |
516 | |
517 | /* |
518 | * Load Ptr Register |
519 | * Software sets this bit after the initialization of the head and tail */ |
520 | #define REG_LOAD_PTR 0x1534 |
521 | |
522 | /* |
523 | * addresses of all descriptors, as well as the following descriptor |
524 | * control register, which triggers each function block to load the head |
525 | * pointer to prepare for the operation. This bit is then self-cleared |
526 | * after one cycle. |
527 | */ |
528 | #define REG_RX_BASE_ADDR_HI 0x1540 |
529 | #define REG_TX_BASE_ADDR_HI 0x1544 |
530 | #define REG_RFD0_HEAD_ADDR_LO 0x1550 |
531 | #define REG_RFD1_HEAD_ADDR_LO 0x1554 |
532 | #define REG_RFD2_HEAD_ADDR_LO 0x1558 |
533 | #define REG_RFD3_HEAD_ADDR_LO 0x155C |
534 | #define REG_RFD_RING_SIZE 0x1560 |
535 | #define RFD_RING_SIZE_MASK 0x0FFF |
536 | #define REG_RX_BUF_SIZE 0x1564 |
537 | #define RX_BUF_SIZE_MASK 0xFFFF |
538 | #define REG_RRD0_HEAD_ADDR_LO 0x1568 |
539 | #define REG_RRD1_HEAD_ADDR_LO 0x156C |
540 | #define REG_RRD2_HEAD_ADDR_LO 0x1570 |
541 | #define REG_RRD3_HEAD_ADDR_LO 0x1574 |
542 | #define REG_RRD_RING_SIZE 0x1578 |
543 | #define RRD_RING_SIZE_MASK 0x0FFF |
544 | #define REG_TPD_PRI1_ADDR_LO 0x157C |
545 | #define REG_TPD_PRI0_ADDR_LO 0x1580 |
546 | #define REG_TPD_PRI2_ADDR_LO 0x1F10 |
547 | #define REG_TPD_PRI3_ADDR_LO 0x1F14 |
548 | |
549 | #define REG_TPD_RING_SIZE 0x1584 |
550 | #define TPD_RING_SIZE_MASK 0xFFFF |
551 | |
552 | /* TXQ Control Register */ |
553 | #define REG_TXQ_CTRL 0x1590 |
554 | #define TXQ_TXF_BURST_NUM_MASK 0xFFFFUL |
555 | #define TXQ_TXF_BURST_NUM_SHIFT 16 |
556 | #define L1C_TXQ_TXF_BURST_PREF 0x200 |
557 | #define L2CB_TXQ_TXF_BURST_PREF 0x40 |
558 | #define TXQ_CTRL_PEDING_CLR BIT(8) |
559 | #define TXQ_CTRL_LS_8023_EN BIT(7) |
560 | #define TXQ_CTRL_ENH_MODE BIT(6) |
561 | #define TXQ_CTRL_EN BIT(5) |
562 | #define TXQ_CTRL_IP_OPTION_EN BIT(4) |
563 | #define TXQ_NUM_TPD_BURST_MASK 0xFUL |
564 | #define TXQ_NUM_TPD_BURST_SHIFT 0 |
565 | #define TXQ_NUM_TPD_BURST_DEF 5 |
566 | #define TXQ_CFGV (\ |
567 | FIELDX(TXQ_NUM_TPD_BURST, TXQ_NUM_TPD_BURST_DEF) |\ |
568 | TXQ_CTRL_ENH_MODE |\ |
569 | TXQ_CTRL_LS_8023_EN |\ |
570 | TXQ_CTRL_IP_OPTION_EN) |
571 | #define L1C_TXQ_CFGV (\ |
572 | TXQ_CFGV |\ |
573 | FIELDX(TXQ_TXF_BURST_NUM, L1C_TXQ_TXF_BURST_PREF)) |
574 | #define L2CB_TXQ_CFGV (\ |
575 | TXQ_CFGV |\ |
576 | FIELDX(TXQ_TXF_BURST_NUM, L2CB_TXQ_TXF_BURST_PREF)) |
577 | |
578 | |
579 | /* Jumbo packet Threshold for task offload */ |
580 | #define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */ |
581 | #define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF |
582 | #define MAX_TSO_FRAME_SIZE (7*1024) |
583 | |
584 | #define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */ |
585 | #define TXF_WATER_MARK_MASK 0x0FFF |
586 | #define TXF_LOW_WATER_MARK_SHIFT 0 |
587 | #define TXF_HIGH_WATER_MARK_SHIFT 16 |
588 | #define TXQ_CTRL_BURST_MODE_EN 0x80000000 |
589 | |
590 | #define REG_THRUPUT_MON_CTRL 0x159C |
591 | #define THRUPUT_MON_RATE_MASK 0x3 |
592 | #define THRUPUT_MON_RATE_SHIFT 0 |
593 | #define THRUPUT_MON_EN 0x80 |
594 | |
595 | /* RXQ Control Register */ |
596 | #define REG_RXQ_CTRL 0x15A0 |
597 | #define ASPM_THRUPUT_LIMIT_MASK 0x3 |
598 | #define ASPM_THRUPUT_LIMIT_SHIFT 0 |
599 | #define ASPM_THRUPUT_LIMIT_NO 0x00 |
600 | #define ASPM_THRUPUT_LIMIT_1M 0x01 |
601 | #define ASPM_THRUPUT_LIMIT_10M 0x02 |
602 | #define ASPM_THRUPUT_LIMIT_100M 0x03 |
603 | #define IPV6_CHKSUM_CTRL_EN BIT(7) |
604 | #define RXQ_RFD_BURST_NUM_MASK 0x003F |
605 | #define RXQ_RFD_BURST_NUM_SHIFT 20 |
606 | #define RXQ_NUM_RFD_PREF_DEF 8 |
607 | #define 3UL |
608 | #define 26 |
609 | #define 0 |
610 | #define 1 |
611 | #define 2 |
612 | #define 3 |
613 | #define BIT(28) /* 0:q0, 1:table */ |
614 | #define RRS_HASH_CTRL_EN BIT(29) |
615 | #define RX_CUT_THRU_EN BIT(30) |
616 | #define RXQ_CTRL_EN BIT(31) |
617 | |
618 | #define REG_RFD_FREE_THRESH 0x15A4 |
619 | #define RFD_FREE_THRESH_MASK 0x003F |
620 | #define RFD_FREE_HI_THRESH_SHIFT 0 |
621 | #define RFD_FREE_LO_THRESH_SHIFT 6 |
622 | |
623 | /* RXF flow control register */ |
624 | #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 |
625 | #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0 |
626 | #define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF |
627 | #define RXQ_RXF_PAUSE_TH_LO_SHIFT 16 |
628 | #define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF |
629 | |
630 | #define REG_RXD_DMA_CTRL 0x15AC |
631 | #define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */ |
632 | #define RXD_DMA_THRESH_SHIFT 0 |
633 | #define RXD_DMA_DOWN_TIMER_MASK 0xFFFF |
634 | #define RXD_DMA_DOWN_TIMER_SHIFT 16 |
635 | |
636 | /* DMA Engine Control Register */ |
637 | #define REG_DMA_CTRL 0x15C0 |
638 | #define DMA_CTRL_SMB_NOW BIT(31) |
639 | #define DMA_CTRL_WPEND_CLR BIT(30) |
640 | #define DMA_CTRL_RPEND_CLR BIT(29) |
641 | #define DMA_CTRL_WDLY_CNT_MASK 0xFUL |
642 | #define DMA_CTRL_WDLY_CNT_SHIFT 16 |
643 | #define DMA_CTRL_WDLY_CNT_DEF 4 |
644 | #define DMA_CTRL_RDLY_CNT_MASK 0x1FUL |
645 | #define DMA_CTRL_RDLY_CNT_SHIFT 11 |
646 | #define DMA_CTRL_RDLY_CNT_DEF 15 |
647 | #define DMA_CTRL_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */ |
648 | #define DMA_CTRL_WREQ_BLEN_MASK 7UL |
649 | #define DMA_CTRL_WREQ_BLEN_SHIFT 7 |
650 | #define DMA_CTRL_RREQ_BLEN_MASK 7UL |
651 | #define DMA_CTRL_RREQ_BLEN_SHIFT 4 |
652 | #define L1C_CTRL_DMA_RCB_LEN128 BIT(3) /* 0:64bytes,1:128bytes */ |
653 | #define DMA_CTRL_RORDER_MODE_MASK 7UL |
654 | #define DMA_CTRL_RORDER_MODE_SHIFT 0 |
655 | #define DMA_CTRL_RORDER_MODE_OUT 4 |
656 | #define DMA_CTRL_RORDER_MODE_ENHANCE 2 |
657 | #define DMA_CTRL_RORDER_MODE_IN 1 |
658 | |
659 | /* INT-triggle/SMB Control Register */ |
660 | #define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */ |
661 | #define SMB_STAT_TIMER_MASK 0xFFFFFF |
662 | #define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig intrrupt */ |
663 | |
664 | /* Mail box */ |
665 | #define MB_RFDX_PROD_IDX_MASK 0xFFFF |
666 | #define REG_MB_RFD0_PROD_IDX 0x15E0 |
667 | #define REG_MB_RFD1_PROD_IDX 0x15E4 |
668 | #define REG_MB_RFD2_PROD_IDX 0x15E8 |
669 | #define REG_MB_RFD3_PROD_IDX 0x15EC |
670 | |
671 | #define REG_TPD_PRI1_PIDX 0x15F0 /* 16bit,hi-tpd producer idx */ |
672 | #define REG_TPD_PRI0_PIDX 0x15F2 /* 16bit,lo-tpd producer idx */ |
673 | #define REG_TPD_PRI1_CIDX 0x15F4 /* 16bit,hi-tpd consumer idx */ |
674 | #define REG_TPD_PRI0_CIDX 0x15F6 /* 16bit,lo-tpd consumer idx */ |
675 | #define REG_TPD_PRI3_PIDX 0x1F18 |
676 | #define REG_TPD_PRI2_PIDX 0x1F1A |
677 | #define REG_TPD_PRI3_CIDX 0x1F1C |
678 | #define REG_TPD_PRI2_CIDX 0x1F1E |
679 | |
680 | |
681 | #define REG_MB_RFD01_CONS_IDX 0x15F8 |
682 | #define MB_RFD0_CONS_IDX_MASK 0x0000FFFF |
683 | #define MB_RFD1_CONS_IDX_MASK 0xFFFF0000 |
684 | #define REG_MB_RFD23_CONS_IDX 0x15FC |
685 | #define MB_RFD2_CONS_IDX_MASK 0x0000FFFF |
686 | #define MB_RFD3_CONS_IDX_MASK 0xFFFF0000 |
687 | |
688 | /* Interrupt Status Register */ |
689 | #define REG_ISR 0x1600 |
690 | #define ISR_SMB 0x00000001 |
691 | #define ISR_TIMER 0x00000002 |
692 | /* |
693 | * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set |
694 | * in Table 51 Selene Master Control Register (Offset 0x1400). |
695 | */ |
696 | #define ISR_MANUAL 0x00000004 |
697 | #define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */ |
698 | #define ISR_RFD0_UR 0x00000010 /* RFD0 under run */ |
699 | #define ISR_RFD1_UR 0x00000020 |
700 | #define ISR_RFD2_UR 0x00000040 |
701 | #define ISR_RFD3_UR 0x00000080 |
702 | #define ISR_TXF_UR 0x00000100 |
703 | #define ISR_DMAR_TO_RST 0x00000200 |
704 | #define ISR_DMAW_TO_RST 0x00000400 |
705 | #define ISR_TX_CREDIT 0x00000800 |
706 | #define ISR_GPHY 0x00001000 |
707 | /* GPHY low power state interrupt */ |
708 | #define ISR_GPHY_LPW 0x00002000 |
709 | #define ISR_TXQ_TO_RST 0x00004000 |
710 | #define ISR_TX_PKT_0 0x00008000 |
711 | #define ISR_RX_PKT_0 0x00010000 |
712 | #define ISR_RX_PKT_1 0x00020000 |
713 | #define ISR_RX_PKT_2 0x00040000 |
714 | #define ISR_RX_PKT_3 0x00080000 |
715 | #define ISR_MAC_RX 0x00100000 |
716 | #define ISR_MAC_TX 0x00200000 |
717 | #define ISR_UR_DETECTED 0x00400000 |
718 | #define ISR_FERR_DETECTED 0x00800000 |
719 | #define ISR_NFERR_DETECTED 0x01000000 |
720 | #define ISR_CERR_DETECTED 0x02000000 |
721 | #define ISR_PHY_LINKDOWN 0x04000000 |
722 | #define ISR_TX_PKT_1 0x10000000 |
723 | #define ISR_TX_PKT_2 0x20000000 |
724 | #define ISR_TX_PKT_3 0x40000000 |
725 | #define ISR_DIS_INT 0x80000000 |
726 | |
727 | /* Interrupt Mask Register */ |
728 | #define REG_IMR 0x1604 |
729 | |
730 | #define IMR_NORMAL_MASK (\ |
731 | ISR_MANUAL |\ |
732 | ISR_HW_RXF_OV |\ |
733 | ISR_RFD0_UR |\ |
734 | ISR_TXF_UR |\ |
735 | ISR_DMAR_TO_RST |\ |
736 | ISR_TXQ_TO_RST |\ |
737 | ISR_DMAW_TO_RST |\ |
738 | ISR_GPHY |\ |
739 | ISR_GPHY_LPW |\ |
740 | ISR_PHY_LINKDOWN) |
741 | |
742 | #define ISR_TX_PKT ( \ |
743 | ISR_TX_PKT_0 | \ |
744 | ISR_TX_PKT_1 | \ |
745 | ISR_TX_PKT_2 | \ |
746 | ISR_TX_PKT_3) |
747 | |
748 | #define ISR_RX_PKT (\ |
749 | ISR_RX_PKT_0 |\ |
750 | ISR_RX_PKT_1 |\ |
751 | ISR_RX_PKT_2 |\ |
752 | ISR_RX_PKT_3) |
753 | |
754 | #define ISR_OVER (\ |
755 | ISR_RFD0_UR |\ |
756 | ISR_RFD1_UR |\ |
757 | ISR_RFD2_UR |\ |
758 | ISR_RFD3_UR |\ |
759 | ISR_HW_RXF_OV |\ |
760 | ISR_TXF_UR) |
761 | |
762 | #define ISR_ERROR (\ |
763 | ISR_DMAR_TO_RST |\ |
764 | ISR_TXQ_TO_RST |\ |
765 | ISR_DMAW_TO_RST |\ |
766 | ISR_PHY_LINKDOWN) |
767 | |
768 | #define REG_INT_RETRIG_TIMER 0x1608 |
769 | #define INT_RETRIG_TIMER_MASK 0xFFFF |
770 | |
771 | #define REG_MAC_RX_STATUS_BIN 0x1700 |
772 | #define REG_MAC_RX_STATUS_END 0x175c |
773 | #define REG_MAC_TX_STATUS_BIN 0x1760 |
774 | #define REG_MAC_TX_STATUS_END 0x17c0 |
775 | |
776 | #define REG_CLK_GATING_CTRL 0x1814 |
777 | #define CLK_GATING_DMAW_EN 0x0001 |
778 | #define CLK_GATING_DMAR_EN 0x0002 |
779 | #define CLK_GATING_TXQ_EN 0x0004 |
780 | #define CLK_GATING_RXQ_EN 0x0008 |
781 | #define CLK_GATING_TXMAC_EN 0x0010 |
782 | #define CLK_GATING_RXMAC_EN 0x0020 |
783 | |
784 | #define CLK_GATING_EN_ALL (CLK_GATING_DMAW_EN |\ |
785 | CLK_GATING_DMAR_EN |\ |
786 | CLK_GATING_TXQ_EN |\ |
787 | CLK_GATING_RXQ_EN |\ |
788 | CLK_GATING_TXMAC_EN|\ |
789 | CLK_GATING_RXMAC_EN) |
790 | |
791 | /* DEBUG ADDR */ |
792 | #define REG_DEBUG_DATA0 0x1900 |
793 | #define REG_DEBUG_DATA1 0x1904 |
794 | |
795 | #define REG_MT_MAGIC 0x1F00 |
796 | #define REG_MT_MODE 0x1F04 |
797 | #define REG_MT_SPEED 0x1F08 |
798 | #define REG_MT_VERSION 0x1F0C |
799 | |
800 | #define MT_MAGIC 0xaabb1234 |
801 | #define MT_MODE_4Q BIT(0) |
802 | |
803 | #define L1D_MPW_PHYID1 0xD01C /* V7 */ |
804 | #define L1D_MPW_PHYID2 0xD01D /* V1-V6 */ |
805 | #define L1D_MPW_PHYID3 0xD01E /* V8 */ |
806 | |
807 | |
808 | /* Autoneg Advertisement Register */ |
809 | #define ADVERTISE_DEFAULT_CAP \ |
810 | (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM) |
811 | |
812 | /* 1000BASE-T Control Register */ |
813 | #define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */ |
814 | |
815 | #define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ |
816 | #define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ |
817 | #define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ |
818 | #define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ |
819 | #define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ |
820 | #define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ |
821 | #define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ |
822 | #define GIGA_CR_1000T_SPEED_MASK 0x0300 |
823 | #define GIGA_CR_1000T_DEFAULT_CAP 0x0300 |
824 | |
825 | /* PHY Specific Status Register */ |
826 | #define MII_GIGA_PSSR 0x11 |
827 | #define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ |
828 | #define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ |
829 | #define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ |
830 | #define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */ |
831 | #define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */ |
832 | #define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ |
833 | |
834 | /* PHY Interrupt Enable Register */ |
835 | #define MII_IER 0x12 |
836 | #define IER_LINK_UP 0x0400 |
837 | #define IER_LINK_DOWN 0x0800 |
838 | |
839 | /* PHY Interrupt Status Register */ |
840 | #define MII_ISR 0x13 |
841 | #define ISR_LINK_UP 0x0400 |
842 | #define ISR_LINK_DOWN 0x0800 |
843 | |
844 | /* Cable-Detect-Test Control Register */ |
845 | #define MII_CDTC 0x16 |
846 | #define CDTC_EN_OFF 0 /* sc */ |
847 | #define CDTC_EN_BITS 1 |
848 | #define CDTC_PAIR_OFF 8 |
849 | #define CDTC_PAIR_BIT 2 |
850 | |
851 | /* Cable-Detect-Test Status Register */ |
852 | #define MII_CDTS 0x1C |
853 | #define CDTS_STATUS_OFF 8 |
854 | #define CDTS_STATUS_BITS 2 |
855 | #define CDTS_STATUS_NORMAL 0 |
856 | #define CDTS_STATUS_SHORT 1 |
857 | #define CDTS_STATUS_OPEN 2 |
858 | #define CDTS_STATUS_INVALID 3 |
859 | |
860 | #define MII_DBG_ADDR 0x1D |
861 | #define MII_DBG_DATA 0x1E |
862 | |
863 | /***************************** debug port *************************************/ |
864 | |
865 | #define MIIDBG_ANACTRL 0x00 |
866 | #define ANACTRL_CLK125M_DELAY_EN 0x8000 |
867 | #define ANACTRL_VCO_FAST 0x4000 |
868 | #define ANACTRL_VCO_SLOW 0x2000 |
869 | #define ANACTRL_AFE_MODE_EN 0x1000 |
870 | #define ANACTRL_LCKDET_PHY 0x800 |
871 | #define ANACTRL_LCKDET_EN 0x400 |
872 | #define ANACTRL_OEN_125M 0x200 |
873 | #define ANACTRL_HBIAS_EN 0x100 |
874 | #define ANACTRL_HB_EN 0x80 |
875 | #define ANACTRL_SEL_HSP 0x40 |
876 | #define ANACTRL_CLASSA_EN 0x20 |
877 | #define ANACTRL_MANUSWON_SWR_MASK 3U |
878 | #define ANACTRL_MANUSWON_SWR_SHIFT 2 |
879 | #define ANACTRL_MANUSWON_SWR_2V 0 |
880 | #define ANACTRL_MANUSWON_SWR_1P9V 1 |
881 | #define ANACTRL_MANUSWON_SWR_1P8V 2 |
882 | #define ANACTRL_MANUSWON_SWR_1P7V 3 |
883 | #define ANACTRL_MANUSWON_BW3_4M 0x2 |
884 | #define ANACTRL_RESTART_CAL 0x1 |
885 | #define ANACTRL_DEF 0x02EF |
886 | |
887 | #define MIIDBG_SYSMODCTRL 0x04 |
888 | #define SYSMODCTRL_IECHOADJ_PFMH_PHY 0x8000 |
889 | #define SYSMODCTRL_IECHOADJ_BIASGEN 0x4000 |
890 | #define SYSMODCTRL_IECHOADJ_PFML_PHY 0x2000 |
891 | #define SYSMODCTRL_IECHOADJ_PS_MASK 3U |
892 | #define SYSMODCTRL_IECHOADJ_PS_SHIFT 10 |
893 | #define SYSMODCTRL_IECHOADJ_PS_40 3 |
894 | #define SYSMODCTRL_IECHOADJ_PS_20 2 |
895 | #define SYSMODCTRL_IECHOADJ_PS_0 1 |
896 | #define SYSMODCTRL_IECHOADJ_10BT_100MV 0x40 /* 1:100mv, 0:200mv */ |
897 | #define SYSMODCTRL_IECHOADJ_HLFAP_MASK 3U |
898 | #define SYSMODCTRL_IECHOADJ_HLFAP_SHIFT 4 |
899 | #define SYSMODCTRL_IECHOADJ_VDFULBW 0x8 |
900 | #define SYSMODCTRL_IECHOADJ_VDBIASHLF 0x4 |
901 | #define SYSMODCTRL_IECHOADJ_VDAMPHLF 0x2 |
902 | #define SYSMODCTRL_IECHOADJ_VDLANSW 0x1 |
903 | #define SYSMODCTRL_IECHOADJ_DEF 0x88BB /* ???? */ |
904 | |
905 | /* for l1d & l2cb */ |
906 | #define SYSMODCTRL_IECHOADJ_CUR_ADD 0x8000 |
907 | #define SYSMODCTRL_IECHOADJ_CUR_MASK 7U |
908 | #define SYSMODCTRL_IECHOADJ_CUR_SHIFT 12 |
909 | #define SYSMODCTRL_IECHOADJ_VOL_MASK 0xFU |
910 | #define SYSMODCTRL_IECHOADJ_VOL_SHIFT 8 |
911 | #define SYSMODCTRL_IECHOADJ_VOL_17ALL 3 |
912 | #define SYSMODCTRL_IECHOADJ_VOL_100M15 1 |
913 | #define SYSMODCTRL_IECHOADJ_VOL_10M17 0 |
914 | #define SYSMODCTRL_IECHOADJ_BIAS1_MASK 0xFU |
915 | #define SYSMODCTRL_IECHOADJ_BIAS1_SHIFT 4 |
916 | #define SYSMODCTRL_IECHOADJ_BIAS2_MASK 0xFU |
917 | #define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT 0 |
918 | #define L1D_SYSMODCTRL_IECHOADJ_DEF 0x4FBB |
919 | |
920 | #define MIIDBG_SRDSYSMOD 0x05 |
921 | #define SRDSYSMOD_LCKDET_EN 0x2000 |
922 | #define SRDSYSMOD_PLL_EN 0x800 |
923 | #define SRDSYSMOD_SEL_HSP 0x400 |
924 | #define SRDSYSMOD_HLFTXDR 0x200 |
925 | #define SRDSYSMOD_TXCLK_DELAY_EN 0x100 |
926 | #define SRDSYSMOD_TXELECIDLE 0x80 |
927 | #define SRDSYSMOD_DEEMP_EN 0x40 |
928 | #define SRDSYSMOD_MS_PAD 0x4 |
929 | #define SRDSYSMOD_CDR_ADC_VLTG 0x2 |
930 | #define SRDSYSMOD_CDR_DAC_1MA 0x1 |
931 | #define SRDSYSMOD_DEF 0x2C46 |
932 | |
933 | #define MIIDBG_CFGLPSPD 0x0A |
934 | #define CFGLPSPD_RSTCNT_MASK 3U |
935 | #define CFGLPSPD_RSTCNT_SHIFT 14 |
936 | #define CFGLPSPD_RSTCNT_CLK125SW 0x2000 |
937 | |
938 | #define MIIDBG_HIBNEG 0x0B |
939 | #define HIBNEG_PSHIB_EN 0x8000 |
940 | #define HIBNEG_WAKE_BOTH 0x4000 |
941 | #define HIBNEG_ONOFF_ANACHG_SUDEN 0x2000 |
942 | #define HIBNEG_HIB_PULSE 0x1000 |
943 | #define HIBNEG_GATE_25M_EN 0x800 |
944 | #define HIBNEG_RST_80U 0x400 |
945 | #define HIBNEG_RST_TIMER_MASK 3U |
946 | #define HIBNEG_RST_TIMER_SHIFT 8 |
947 | #define HIBNEG_GTX_CLK_DELAY_MASK 3U |
948 | #define HIBNEG_GTX_CLK_DELAY_SHIFT 5 |
949 | #define HIBNEG_BYPSS_BRKTIMER 0x10 |
950 | #define HIBNEG_DEF 0xBC40 |
951 | |
952 | #define MIIDBG_TST10BTCFG 0x12 |
953 | #define TST10BTCFG_INTV_TIMER_MASK 3U |
954 | #define TST10BTCFG_INTV_TIMER_SHIFT 14 |
955 | #define TST10BTCFG_TRIGER_TIMER_MASK 3U |
956 | #define TST10BTCFG_TRIGER_TIMER_SHIFT 12 |
957 | #define TST10BTCFG_DIV_MAN_MLT3_EN 0x800 |
958 | #define TST10BTCFG_OFF_DAC_IDLE 0x400 |
959 | #define TST10BTCFG_LPBK_DEEP 0x4 /* 1:deep,0:shallow */ |
960 | #define TST10BTCFG_DEF 0x4C04 |
961 | |
962 | #define MIIDBG_AZ_ANADECT 0x15 |
963 | #define AZ_ANADECT_10BTRX_TH 0x8000 |
964 | #define AZ_ANADECT_BOTH_01CHNL 0x4000 |
965 | #define AZ_ANADECT_INTV_MASK 0x3FU |
966 | #define AZ_ANADECT_INTV_SHIFT 8 |
967 | #define AZ_ANADECT_THRESH_MASK 0xFU |
968 | #define AZ_ANADECT_THRESH_SHIFT 4 |
969 | #define AZ_ANADECT_CHNL_MASK 0xFU |
970 | #define AZ_ANADECT_CHNL_SHIFT 0 |
971 | #define AZ_ANADECT_DEF 0x3220 |
972 | #define AZ_ANADECT_LONG 0xb210 |
973 | |
974 | #define MIIDBG_MSE16DB 0x18 /* l1d */ |
975 | #define L1D_MSE16DB_UP 0x05EA |
976 | #define L1D_MSE16DB_DOWN 0x02EA |
977 | |
978 | #define MIIDBG_LEGCYPS 0x29 |
979 | #define LEGCYPS_EN 0x8000 |
980 | #define LEGCYPS_DAC_AMP1000_MASK 7U |
981 | #define LEGCYPS_DAC_AMP1000_SHIFT 12 |
982 | #define LEGCYPS_DAC_AMP100_MASK 7U |
983 | #define LEGCYPS_DAC_AMP100_SHIFT 9 |
984 | #define LEGCYPS_DAC_AMP10_MASK 7U |
985 | #define LEGCYPS_DAC_AMP10_SHIFT 6 |
986 | #define LEGCYPS_UNPLUG_TIMER_MASK 7U |
987 | #define LEGCYPS_UNPLUG_TIMER_SHIFT 3 |
988 | #define LEGCYPS_UNPLUG_DECT_EN 0x4 |
989 | #define LEGCYPS_ECNC_PS_EN 0x1 |
990 | #define L1D_LEGCYPS_DEF 0x129D |
991 | #define L1C_LEGCYPS_DEF 0x36DD |
992 | |
993 | #define MIIDBG_TST100BTCFG 0x36 |
994 | #define TST100BTCFG_NORMAL_BW_EN 0x8000 |
995 | #define TST100BTCFG_BADLNK_BYPASS 0x4000 |
996 | #define TST100BTCFG_SHORTCABL_TH_MASK 0x3FU |
997 | #define TST100BTCFG_SHORTCABL_TH_SHIFT 8 |
998 | #define TST100BTCFG_LITCH_EN 0x80 |
999 | #define TST100BTCFG_VLT_SW 0x40 |
1000 | #define TST100BTCFG_LONGCABL_TH_MASK 0x3FU |
1001 | #define TST100BTCFG_LONGCABL_TH_SHIFT 0 |
1002 | #define TST100BTCFG_DEF 0xE12C |
1003 | |
1004 | #define MIIDBG_VOLT_CTRL 0x3B /* only for l2cb 1 & 2 */ |
1005 | #define VOLT_CTRL_CABLE1TH_MASK 0x1FFU |
1006 | #define VOLT_CTRL_CABLE1TH_SHIFT 7 |
1007 | #define VOLT_CTRL_AMPCTRL_MASK 3U |
1008 | #define VOLT_CTRL_AMPCTRL_SHIFT 5 |
1009 | #define VOLT_CTRL_SW_BYPASS 0x10 |
1010 | #define VOLT_CTRL_SWLOWEST 0x8 |
1011 | #define VOLT_CTRL_DACAMP10_MASK 7U |
1012 | #define VOLT_CTRL_DACAMP10_SHIFT 0 |
1013 | |
1014 | #define MIIDBG_CABLE1TH_DET 0x3E |
1015 | #define CABLE1TH_DET_EN 0x8000 |
1016 | |
1017 | |
1018 | /******* dev 3 *********/ |
1019 | #define MIIEXT_PCS 3 |
1020 | |
1021 | #define MIIEXT_CLDCTRL3 0x8003 |
1022 | #define CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000 |
1023 | #define CLDCTRL3_AZ_DISAMP 0x1000 |
1024 | #define L2CB_CLDCTRL3 0x4D19 |
1025 | #define L1D_CLDCTRL3 0xDD19 |
1026 | |
1027 | #define MIIEXT_CLDCTRL6 0x8006 |
1028 | #define CLDCTRL6_CAB_LEN_MASK 0x1FFU |
1029 | #define CLDCTRL6_CAB_LEN_SHIFT 0 |
1030 | #define CLDCTRL6_CAB_LEN_SHORT 0x50 |
1031 | |
1032 | /********* dev 7 **********/ |
1033 | #define MIIEXT_ANEG 7 |
1034 | |
1035 | #define MIIEXT_LOCAL_EEEADV 0x3C |
1036 | #define LOCAL_EEEADV_1000BT 0x4 |
1037 | #define LOCAL_EEEADV_100BT 0x2 |
1038 | |
1039 | #define MIIEXT_REMOTE_EEEADV 0x3D |
1040 | #define REMOTE_EEEADV_1000BT 0x4 |
1041 | #define REMOTE_EEEADV_100BT 0x2 |
1042 | |
1043 | #define MIIEXT_EEE_ANEG 0x8000 |
1044 | #define EEE_ANEG_1000M 0x4 |
1045 | #define EEE_ANEG_100M 0x2 |
1046 | |
1047 | #endif /*_ATL1C_HW_H_*/ |
1048 | |