| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | #ifndef __BCM4908_ENET_H |
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| 3 | #define __BCM4908_ENET_H |
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| 4 | |
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| 5 | #define ENET_CONTROL 0x000 |
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| 6 | #define ENET_MIB_CTRL 0x004 |
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| 7 | #define ENET_MIB_CTRL_CLR_MIB 0x00000001 |
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| 8 | #define ENET_RX_ERR_MASK 0x008 |
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| 9 | #define ENET_MIB_MAX_PKT_SIZE 0x00C |
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| 10 | #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff |
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| 11 | #define ENET_DIAG_OUT 0x01c |
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| 12 | #define ENET_ENABLE_DROP_PKT 0x020 |
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| 13 | #define ENET_IRQ_ENABLE 0x024 |
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| 14 | #define ENET_IRQ_ENABLE_OVFL 0x00000001 |
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| 15 | #define ENET_GMAC_STATUS 0x028 |
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| 16 | #define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003 |
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| 17 | #define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000 |
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| 18 | #define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001 |
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| 19 | #define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002 |
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| 20 | #define ENET_GMAC_STATUS_HD 0x00000004 |
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| 21 | #define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008 |
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| 22 | #define ENET_GMAC_STATUS_LINK_UP 0x00000010 |
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| 23 | #define ENET_IRQ_STATUS 0x02c |
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| 24 | #define ENET_IRQ_STATUS_OVFL 0x00000001 |
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| 25 | #define ENET_OVERFLOW_COUNTER 0x030 |
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| 26 | #define ENET_FLUSH 0x034 |
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| 27 | #define ENET_FLUSH_RXFIFO_FLUSH 0x00000001 |
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| 28 | #define ENET_FLUSH_TXFIFO_FLUSH 0x00000002 |
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| 29 | #define ENET_RSV_SELECT 0x038 |
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| 30 | #define ENET_BP_FORCE 0x03c |
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| 31 | #define ENET_BP_FORCE_FORCE 0x00000001 |
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| 32 | #define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040 |
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| 33 | #define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f |
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| 34 | #define ENET_TX_CRC_CTRL 0x044 |
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| 35 | #define ENET_MIB 0x200 |
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| 36 | #define ENET_UNIMAC 0x400 |
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| 37 | #define ENET_DMA 0x800 |
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| 38 | #define ENET_DMA_CONTROLLER_CFG 0x800 |
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| 39 | #define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001 |
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| 40 | #define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002 |
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| 41 | #define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004 |
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| 42 | #define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804 |
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| 43 | #define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808 |
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| 44 | #define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c |
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| 45 | #define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000 |
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| 46 | #define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810 |
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| 47 | #define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814 |
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| 48 | #define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818 |
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| 49 | #define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C |
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| 50 | #define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820 |
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| 51 | #define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824 |
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| 52 | #define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828 |
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| 53 | #define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C |
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| 54 | #define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830 |
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| 55 | #define ENET_DMA_CTRL_CHANNEL_RESET 0x834 |
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| 56 | #define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838 |
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| 57 | #define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840 |
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| 58 | #define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844 |
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| 59 | #define ENET_DMA_CH0_CFG 0xa00 /* RX */ |
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| 60 | #define ENET_DMA_CH1_CFG 0xa10 /* TX */ |
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| 61 | #define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */ |
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| 62 | #define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */ |
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| 63 | |
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| 64 | #define ENET_DMA_CH_CFG 0x00 /* assorted configuration */ |
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| 65 | #define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */ |
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| 66 | #define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ |
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| 67 | #define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */ |
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| 68 | #define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */ |
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| 69 | #define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */ |
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| 70 | #define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */ |
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| 71 | #define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */ |
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| 72 | #define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */ |
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| 73 | #define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */ |
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| 74 | #define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */ |
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| 75 | #define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ |
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| 76 | #define ENET_DMA_CH_CFG_SIZE 0x10 |
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| 77 | |
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| 78 | #define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */ |
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| 79 | #define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */ |
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| 80 | #define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */ |
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| 81 | #define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */ |
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| 82 | #define ENET_DMA_CH_STATE_RAM_SIZE 0x10 |
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| 83 | |
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| 84 | #define DMA_CTL_STATUS_APPEND_CRC 0x00000100 |
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| 85 | #define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200 |
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| 86 | #define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */ |
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| 87 | #define DMA_CTL_STATUS_WRAP 0x00001000 /* */ |
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| 88 | #define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */ |
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| 89 | #define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */ |
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| 90 | #define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */ |
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| 91 | #define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000 |
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| 92 | #define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16 |
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| 93 | #define DMA_CTL_LEN_DESC_MULTICAST 0x40000000 |
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| 94 | #define DMA_CTL_LEN_DESC_USEFPM 0x80000000 |
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| 95 | |
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| 96 | #endif |
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| 97 | |
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