1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2025 Broadcom */
3
4#ifndef _BNGE_RMEM_H_
5#define _BNGE_RMEM_H_
6
7struct bnge_ctx_mem_type;
8struct bnge_dev;
9struct bnge_net;
10
11#define PTU_PTE_VALID 0x1UL
12#define PTU_PTE_LAST 0x2UL
13#define PTU_PTE_NEXT_TO_LAST 0x4UL
14
15struct bnge_ring_mem_info {
16 /* Number of pages to next level */
17 int nr_pages;
18 int page_size;
19 u16 flags;
20#define BNGE_RMEM_VALID_PTE_FLAG 1
21#define BNGE_RMEM_RING_PTE_FLAG 2
22#define BNGE_RMEM_USE_FULL_PAGE_FLAG 4
23
24 u16 depth;
25
26 void **pg_arr;
27 dma_addr_t *dma_arr;
28
29 __le64 *pg_tbl;
30 dma_addr_t dma_pg_tbl;
31
32 int vmem_size;
33 void **vmem;
34
35 struct bnge_ctx_mem_type *ctx_mem;
36};
37
38/* The hardware supports certain page sizes.
39 * Use the supported page sizes to allocate the rings.
40 */
41#if (PAGE_SHIFT < 12)
42#define BNGE_PAGE_SHIFT 12
43#elif (PAGE_SHIFT <= 13)
44#define BNGE_PAGE_SHIFT PAGE_SHIFT
45#elif (PAGE_SHIFT < 16)
46#define BNGE_PAGE_SHIFT 13
47#else
48#define BNGE_PAGE_SHIFT 16
49#endif
50#define BNGE_PAGE_SIZE (1 << BNGE_PAGE_SHIFT)
51/* The RXBD length is 16-bit so we can only support page sizes < 64K */
52#if (PAGE_SHIFT > 15)
53#define BNGE_RX_PAGE_SHIFT 15
54#else
55#define BNGE_RX_PAGE_SHIFT PAGE_SHIFT
56#endif
57#define MAX_CTX_PAGES (BNGE_PAGE_SIZE / 8)
58#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
59
60struct bnge_ctx_pg_info {
61 u32 entries;
62 u32 nr_pages;
63 void *ctx_pg_arr[MAX_CTX_PAGES];
64 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
65 struct bnge_ring_mem_info ring_mem;
66 struct bnge_ctx_pg_info **ctx_pg_tbl;
67};
68
69#define BNGE_MAX_TQM_SP_RINGS 1
70#define BNGE_MAX_TQM_FP_RINGS 8
71#define BNGE_MAX_TQM_RINGS \
72 (BNGE_MAX_TQM_SP_RINGS + BNGE_MAX_TQM_FP_RINGS)
73#define BNGE_BACKING_STORE_CFG_LEGACY_LEN 256
74#define BNGE_SET_CTX_PAGE_ATTR(attr) \
75do { \
76 if (BNGE_PAGE_SIZE == 0x2000) \
77 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
78 else if (BNGE_PAGE_SIZE == 0x10000) \
79 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
80 else \
81 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
82} while (0)
83
84#define BNGE_CTX_MRAV_AV_SPLIT_ENTRY 0
85
86#define BNGE_CTX_QP \
87 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP
88#define BNGE_CTX_SRQ \
89 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ
90#define BNGE_CTX_CQ \
91 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ
92#define BNGE_CTX_VNIC \
93 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC
94#define BNGE_CTX_STAT \
95 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT
96#define BNGE_CTX_STQM \
97 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING
98#define BNGE_CTX_FTQM \
99 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING
100#define BNGE_CTX_MRAV \
101 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV
102#define BNGE_CTX_TIM \
103 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM
104#define BNGE_CTX_TCK \
105 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK
106#define BNGE_CTX_RCK \
107 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK
108#define BNGE_CTX_MTQM \
109 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING
110#define BNGE_CTX_SQDBS \
111 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW
112#define BNGE_CTX_RQDBS \
113 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW
114#define BNGE_CTX_SRQDBS \
115 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW
116#define BNGE_CTX_CQDBS \
117 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW
118#define BNGE_CTX_SRT_TRACE \
119 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE
120#define BNGE_CTX_SRT2_TRACE \
121 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE
122#define BNGE_CTX_CRT_TRACE \
123 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE
124#define BNGE_CTX_CRT2_TRACE \
125 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE
126#define BNGE_CTX_RIGP0_TRACE \
127 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE
128#define BNGE_CTX_L2_HWRM_TRACE \
129 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE
130#define BNGE_CTX_ROCE_HWRM_TRACE \
131 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE
132
133#define BNGE_CTX_MAX (BNGE_CTX_TIM + 1)
134#define BNGE_CTX_L2_MAX (BNGE_CTX_FTQM + 1)
135#define BNGE_CTX_INV ((u16)-1)
136
137#define BNGE_CTX_V2_MAX \
138 (FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE + 1)
139
140#define BNGE_BS_CFG_ALL_DONE \
141 FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE
142
143struct bnge_ctx_mem_type {
144 u16 type;
145 u16 entry_size;
146 u32 flags;
147#define BNGE_CTX_MEM_TYPE_VALID \
148 FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID
149 u32 instance_bmap;
150 u8 init_value;
151 u8 entry_multiple;
152 u16 init_offset;
153#define BNGE_CTX_INIT_INVALID_OFFSET 0xffff
154 u32 max_entries;
155 u32 min_entries;
156 u8 last:1;
157 u8 split_entry_cnt;
158#define BNGE_MAX_SPLIT_ENTRY 4
159 union {
160 struct {
161 u32 qp_l2_entries;
162 u32 qp_qp1_entries;
163 u32 qp_fast_qpmd_entries;
164 };
165 u32 srq_l2_entries;
166 u32 cq_l2_entries;
167 u32 vnic_entries;
168 struct {
169 u32 mrav_av_entries;
170 u32 mrav_num_entries_units;
171 };
172 u32 split[BNGE_MAX_SPLIT_ENTRY];
173 };
174 struct bnge_ctx_pg_info *pg_info;
175};
176
177struct bnge_ctx_mem_info {
178 u8 tqm_fp_rings_count;
179 u32 flags;
180#define BNGE_CTX_FLAG_INITED 0x01
181 struct bnge_ctx_mem_type ctx_arr[BNGE_CTX_V2_MAX];
182};
183
184struct bnge_ring_struct {
185 struct bnge_ring_mem_info ring_mem;
186
187 u16 fw_ring_id;
188 union {
189 u16 grp_idx;
190 u16 map_idx; /* Used by NQs */
191 };
192 u32 handle;
193 u8 queue_id;
194};
195
196int bnge_alloc_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem);
197void bnge_free_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem);
198int bnge_alloc_ctx_mem(struct bnge_dev *bd);
199void bnge_free_ctx_mem(struct bnge_dev *bd);
200void bnge_init_ring_struct(struct bnge_net *bn);
201
202#endif /* _BNGE_RMEM_H_ */
203

source code of linux/drivers/net/ethernet/broadcom/bnge/bnge_rmem.h