1 | /* Copyright 2008-2013 Broadcom Corporation |
2 | * Copyright (c) 2014 QLogic Corporation |
3 | * All rights reserved |
4 | * |
5 | * Unless you and QLogic execute a separate written software license |
6 | * agreement governing use of this software, this software is licensed to you |
7 | * under the terms of the GNU General Public License version 2, available |
8 | * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL"). |
9 | * |
10 | * Notwithstanding the above, under no circumstances may you combine this |
11 | * software in any way with any other Qlogic software provided under a |
12 | * license other than the GPL, without Qlogic's express prior written |
13 | * consent. |
14 | * |
15 | * Written by Yaniv Rosner |
16 | * |
17 | */ |
18 | |
19 | #ifndef BNX2X_LINK_H |
20 | #define BNX2X_LINK_H |
21 | |
22 | |
23 | |
24 | /***********************************************************/ |
25 | /* Defines */ |
26 | /***********************************************************/ |
27 | #define DEFAULT_PHY_DEV_ADDR 3 |
28 | #define E2_DEFAULT_PHY_DEV_ADDR 5 |
29 | |
30 | |
31 | |
32 | #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO |
33 | #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX |
34 | #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX |
35 | #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH |
36 | #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE |
37 | |
38 | #define NET_SERDES_IF_XFI 1 |
39 | #define NET_SERDES_IF_SFI 2 |
40 | #define NET_SERDES_IF_KR 3 |
41 | #define NET_SERDES_IF_DXGXS 4 |
42 | |
43 | #define SPEED_AUTO_NEG 0 |
44 | #define SPEED_20000 20000 |
45 | |
46 | #define I2C_DEV_ADDR_A0 0xa0 |
47 | #define I2C_DEV_ADDR_A2 0xa2 |
48 | |
49 | #define SFP_EEPROM_PAGE_SIZE 16 |
50 | #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14 |
51 | #define SFP_EEPROM_VENDOR_NAME_SIZE 16 |
52 | #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25 |
53 | #define SFP_EEPROM_VENDOR_OUI_SIZE 3 |
54 | #define SFP_EEPROM_PART_NO_ADDR 0x28 |
55 | #define SFP_EEPROM_PART_NO_SIZE 16 |
56 | #define SFP_EEPROM_REVISION_ADDR 0x38 |
57 | #define SFP_EEPROM_REVISION_SIZE 4 |
58 | #define SFP_EEPROM_SERIAL_ADDR 0x44 |
59 | #define SFP_EEPROM_SERIAL_SIZE 16 |
60 | #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ |
61 | #define SFP_EEPROM_DATE_SIZE 6 |
62 | #define SFP_EEPROM_DIAG_TYPE_ADDR 0x5c |
63 | #define SFP_EEPROM_DIAG_TYPE_SIZE 1 |
64 | #define SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2) |
65 | #define SFP_EEPROM_DDM_IMPLEMENTED (1<<6) |
66 | #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e |
67 | #define SFP_EEPROM_SFF_8472_COMP_SIZE 1 |
68 | |
69 | #define SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e |
70 | #define SFP_EEPROM_A2_CC_DMI_ADDR 0x5f |
71 | |
72 | #define PWR_FLT_ERR_MSG_LEN 250 |
73 | |
74 | #define XGXS_EXT_PHY_TYPE(ext_phy_config) \ |
75 | ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) |
76 | #define XGXS_EXT_PHY_ADDR(ext_phy_config) \ |
77 | (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ |
78 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) |
79 | #define SERDES_EXT_PHY_TYPE(ext_phy_config) \ |
80 | ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) |
81 | |
82 | /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ |
83 | #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) |
84 | /* Single Media board contains single external phy */ |
85 | #define SINGLE_MEDIA(params) (params->num_phys == 2) |
86 | /* Dual Media board contains two external phy with different media */ |
87 | #define DUAL_MEDIA(params) (params->num_phys == 3) |
88 | |
89 | #define FW_PARAM_PHY_ADDR_MASK 0x000000FF |
90 | #define FW_PARAM_PHY_TYPE_MASK 0x0000FF00 |
91 | #define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000 |
92 | #define FW_PARAM_MDIO_CTRL_OFFSET 16 |
93 | #define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ |
94 | FW_PARAM_PHY_ADDR_MASK) |
95 | #define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ |
96 | FW_PARAM_PHY_TYPE_MASK) |
97 | #define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ |
98 | FW_PARAM_MDIO_CTRL_MASK) >> \ |
99 | FW_PARAM_MDIO_CTRL_OFFSET) |
100 | #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ |
101 | (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET) |
102 | |
103 | |
104 | #define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170 |
105 | #define PFC_BRB_FULL_LB_XON_THRESHOLD 250 |
106 | |
107 | #define MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) |
108 | |
109 | #define BMAC_CONTROL_RX_ENABLE 2 |
110 | /***********************************************************/ |
111 | /* Structs */ |
112 | /***********************************************************/ |
113 | #define INT_PHY 0 |
114 | #define EXT_PHY1 1 |
115 | #define EXT_PHY2 2 |
116 | #define MAX_PHYS 3 |
117 | |
118 | /* Same configuration is shared between the XGXS and the first external phy */ |
119 | #define LINK_CONFIG_SIZE (MAX_PHYS - 1) |
120 | #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \ |
121 | 0 : (_phy_idx - 1)) |
122 | /***********************************************************/ |
123 | /* bnx2x_phy struct */ |
124 | /* Defines the required arguments and function per phy */ |
125 | /***********************************************************/ |
126 | struct link_vars; |
127 | struct link_params; |
128 | struct bnx2x_phy; |
129 | |
130 | typedef void (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params, |
131 | struct link_vars *vars); |
132 | typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params, |
133 | struct link_vars *vars); |
134 | typedef void (*link_reset_t)(struct bnx2x_phy *phy, |
135 | struct link_params *params); |
136 | typedef void (*config_loopback_t)(struct bnx2x_phy *phy, |
137 | struct link_params *params); |
138 | typedef int (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len); |
139 | typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params); |
140 | typedef void (*set_link_led_t)(struct bnx2x_phy *phy, |
141 | struct link_params *params, u8 mode); |
142 | typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy, |
143 | struct link_params *params, u32 action); |
144 | struct bnx2x_reg_set { |
145 | u8 devad; |
146 | u16 reg; |
147 | u16 val; |
148 | }; |
149 | |
150 | struct bnx2x_phy { |
151 | u32 type; |
152 | |
153 | /* Loaded during init */ |
154 | u8 addr; |
155 | u8 def_md_devad; |
156 | u16 flags; |
157 | /* No Over-Current detection */ |
158 | #define FLAGS_NOC (1<<1) |
159 | /* Fan failure detection required */ |
160 | #define FLAGS_FAN_FAILURE_DET_REQ (1<<2) |
161 | /* Initialize first the XGXS and only then the phy itself */ |
162 | #define FLAGS_INIT_XGXS_FIRST (1<<3) |
163 | #define FLAGS_WC_DUAL_MODE (1<<4) |
164 | #define FLAGS_4_PORT_MODE (1<<5) |
165 | #define FLAGS_REARM_LATCH_SIGNAL (1<<6) |
166 | #define FLAGS_SFP_NOT_APPROVED (1<<7) |
167 | #define FLAGS_MDC_MDIO_WA (1<<8) |
168 | #define FLAGS_DUMMY_READ (1<<9) |
169 | #define FLAGS_MDC_MDIO_WA_B0 (1<<10) |
170 | #define FLAGS_TX_ERROR_CHECK (1<<12) |
171 | #define FLAGS_EEE (1<<13) |
172 | #define FLAGS_MDC_MDIO_WA_G (1<<15) |
173 | |
174 | /* preemphasis values for the rx side */ |
175 | u16 rx_preemphasis[4]; |
176 | |
177 | /* preemphasis values for the tx side */ |
178 | u16 tx_preemphasis[4]; |
179 | |
180 | /* EMAC address for access MDIO */ |
181 | u32 mdio_ctrl; |
182 | |
183 | u32 supported; |
184 | |
185 | u32 media_type; |
186 | #define ETH_PHY_UNSPECIFIED 0x0 |
187 | #define ETH_PHY_SFPP_10G_FIBER 0x1 |
188 | #define ETH_PHY_XFP_FIBER 0x2 |
189 | #define ETH_PHY_DA_TWINAX 0x3 |
190 | #define ETH_PHY_BASE_T 0x4 |
191 | #define ETH_PHY_SFP_1G_FIBER 0x5 |
192 | #define ETH_PHY_KR 0xf0 |
193 | #define ETH_PHY_CX4 0xf1 |
194 | #define ETH_PHY_NOT_PRESENT 0xff |
195 | |
196 | /* The address in which version is located*/ |
197 | u32 ver_addr; |
198 | |
199 | u16 req_flow_ctrl; |
200 | |
201 | u16 req_line_speed; |
202 | |
203 | u32 speed_cap_mask; |
204 | |
205 | u16 req_duplex; |
206 | u16 rsrv; |
207 | /* Called per phy/port init, and it configures LASI, speed, autoneg, |
208 | duplex, flow control negotiation, etc. */ |
209 | config_init_t config_init; |
210 | |
211 | /* Called due to interrupt. It determines the link, speed */ |
212 | read_status_t read_status; |
213 | |
214 | /* Called when driver is unloading. Should reset the phy */ |
215 | link_reset_t link_reset; |
216 | |
217 | /* Set the loopback configuration for the phy */ |
218 | config_loopback_t config_loopback; |
219 | |
220 | /* Format the given raw number into str up to len */ |
221 | format_fw_ver_t format_fw_ver; |
222 | |
223 | /* Reset the phy (both ports) */ |
224 | hw_reset_t hw_reset; |
225 | |
226 | /* Set link led mode (on/off/oper)*/ |
227 | set_link_led_t set_link_led; |
228 | |
229 | /* PHY Specific tasks */ |
230 | phy_specific_func_t phy_specific_func; |
231 | #define DISABLE_TX 1 |
232 | #define ENABLE_TX 2 |
233 | #define PHY_INIT 3 |
234 | }; |
235 | |
236 | /* Inputs parameters to the CLC */ |
237 | struct link_params { |
238 | |
239 | u8 port; |
240 | |
241 | /* Default / User Configuration */ |
242 | u8 loopback_mode; |
243 | #define LOOPBACK_NONE 0 |
244 | #define LOOPBACK_EMAC 1 |
245 | #define LOOPBACK_BMAC 2 |
246 | #define LOOPBACK_XGXS 3 |
247 | #define LOOPBACK_EXT_PHY 4 |
248 | #define LOOPBACK_EXT 5 |
249 | #define LOOPBACK_UMAC 6 |
250 | #define LOOPBACK_XMAC 7 |
251 | |
252 | /* Device parameters */ |
253 | u8 mac_addr[6]; |
254 | |
255 | u16 req_duplex[LINK_CONFIG_SIZE]; |
256 | u16 req_flow_ctrl[LINK_CONFIG_SIZE]; |
257 | |
258 | u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ |
259 | |
260 | /* shmem parameters */ |
261 | u32 shmem_base; |
262 | u32 shmem2_base; |
263 | u32 speed_cap_mask[LINK_CONFIG_SIZE]; |
264 | u32 switch_cfg; |
265 | #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH |
266 | #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH |
267 | #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT |
268 | |
269 | u32 lane_config; |
270 | |
271 | /* Phy register parameter */ |
272 | u32 chip_id; |
273 | |
274 | /* features */ |
275 | u32 feature_config_flags; |
276 | #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) |
277 | #define FEATURE_CONFIG_PFC_ENABLED (1<<1) |
278 | #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) |
279 | #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) |
280 | #define FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8) |
281 | #define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9) |
282 | #define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10) |
283 | #define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11) |
284 | #define FEATURE_CONFIG_MT_SUPPORT (1<<13) |
285 | #define FEATURE_CONFIG_BOOT_FROM_SAN (1<<14) |
286 | |
287 | /* Will be populated during common init */ |
288 | struct bnx2x_phy phy[MAX_PHYS]; |
289 | |
290 | /* Will be populated during common init */ |
291 | u8 num_phys; |
292 | |
293 | u8 rsrv; |
294 | |
295 | /* Used to configure the EEE Tx LPI timer, has several modes of |
296 | * operation, according to bits 29:28 - |
297 | * 2'b00: Timer will be configured by nvram, output will be the value |
298 | * from nvram. |
299 | * 2'b01: Timer will be configured by nvram, output will be in |
300 | * microseconds. |
301 | * 2'b10: bits 1:0 contain an nvram value which will be used instead |
302 | * of the one located in the nvram. Output will be that value. |
303 | * 2'b11: bits 19:0 contain the idle timer in microseconds; output |
304 | * will be in microseconds. |
305 | * Bits 31:30 should be 2'b11 in order for EEE to be enabled. |
306 | */ |
307 | u32 eee_mode; |
308 | #define EEE_MODE_NVRAM_BALANCED_TIME (0xa00) |
309 | #define EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100) |
310 | #define EEE_MODE_NVRAM_LATENCY_TIME (0x6000) |
311 | #define EEE_MODE_NVRAM_MASK (0x3) |
312 | #define EEE_MODE_TIMER_MASK (0xfffff) |
313 | #define EEE_MODE_OUTPUT_TIME (1<<28) |
314 | #define EEE_MODE_OVERRIDE_NVRAM (1<<29) |
315 | #define EEE_MODE_ENABLE_LPI (1<<30) |
316 | #define EEE_MODE_ADV_LPI (1<<31) |
317 | |
318 | u16 hw_led_mode; /* part of the hw_config read from the shmem */ |
319 | u32 multi_phy_config; |
320 | |
321 | /* Device pointer passed to all callback functions */ |
322 | struct bnx2x *bp; |
323 | u16 req_fc_auto_adv; /* Should be set to TX / BOTH when |
324 | req_flow_ctrl is set to AUTO */ |
325 | u16 link_flags; |
326 | #define LINK_FLAGS_INT_DISABLED (1<<0) |
327 | #define PHY_INITIALIZED (1<<1) |
328 | u32 lfa_base; |
329 | |
330 | /* The same definitions as the shmem2 parameter */ |
331 | u32 link_attr_sync; |
332 | }; |
333 | |
334 | /* Output parameters */ |
335 | struct link_vars { |
336 | u8 phy_flags; |
337 | #define PHY_XGXS_FLAG (1<<0) |
338 | #define PHY_SGMII_FLAG (1<<1) |
339 | #define PHY_PHYSICAL_LINK_FLAG (1<<2) |
340 | #define PHY_HALF_OPEN_CONN_FLAG (1<<3) |
341 | #define PHY_OVER_CURRENT_FLAG (1<<4) |
342 | #define PHY_SFP_TX_FAULT_FLAG (1<<5) |
343 | |
344 | u8 mac_type; |
345 | #define MAC_TYPE_NONE 0 |
346 | #define MAC_TYPE_EMAC 1 |
347 | #define MAC_TYPE_BMAC 2 |
348 | #define MAC_TYPE_UMAC 3 |
349 | #define MAC_TYPE_XMAC 4 |
350 | |
351 | u8 phy_link_up; /* internal phy link indication */ |
352 | u8 link_up; |
353 | |
354 | u16 line_speed; |
355 | u16 duplex; |
356 | |
357 | u16 flow_ctrl; |
358 | u16 ieee_fc; |
359 | |
360 | /* The same definitions as the shmem parameter */ |
361 | u32 link_status; |
362 | u32 eee_status; |
363 | u8 fault_detected; |
364 | u8 check_kr2_recovery_cnt; |
365 | #define CHECK_KR2_RECOVERY_CNT 5 |
366 | u16 periodic_flags; |
367 | #define PERIODIC_FLAGS_LINK_EVENT 0x0001 |
368 | |
369 | u32 aeu_int_mask; |
370 | u8 rx_tx_asic_rst; |
371 | u8 turn_to_run_wc_rt; |
372 | u16 rsrv2; |
373 | }; |
374 | |
375 | /***********************************************************/ |
376 | /* Functions */ |
377 | /***********************************************************/ |
378 | int bnx2x_phy_init(struct link_params *params, struct link_vars *vars); |
379 | |
380 | /* Reset the link. Should be called when driver or interface goes down |
381 | Before calling phy firmware upgrade, the reset_ext_phy should be set |
382 | to 0 */ |
383 | int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, |
384 | u8 reset_ext_phy); |
385 | int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars); |
386 | /* bnx2x_link_update should be called upon link interrupt */ |
387 | int bnx2x_link_update(struct link_params *params, struct link_vars *vars); |
388 | |
389 | /* use the following phy functions to read/write from external_phy |
390 | In order to use it to read/write internal phy registers, use |
391 | DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as |
392 | the register */ |
393 | int bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
394 | u8 devad, u16 reg, u16 *ret_val); |
395 | |
396 | int bnx2x_phy_write(struct link_params *params, u8 phy_addr, |
397 | u8 devad, u16 reg, u16 val); |
398 | |
399 | /* Reads the link_status from the shmem, |
400 | and update the link vars accordingly */ |
401 | void bnx2x_link_status_update(struct link_params *input, |
402 | struct link_vars *output); |
403 | /* returns string representing the fw_version of the external phy */ |
404 | int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, |
405 | u16 len); |
406 | |
407 | /* Set/Unset the led |
408 | Basically, the CLC takes care of the led for the link, but in case one needs |
409 | to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to |
410 | blink the led, and LED_MODE_OFF to set the led off.*/ |
411 | int bnx2x_set_led(struct link_params *params, |
412 | struct link_vars *vars, u8 mode, u32 speed); |
413 | #define LED_MODE_OFF 0 |
414 | #define LED_MODE_ON 1 |
415 | #define LED_MODE_OPER 2 |
416 | #define LED_MODE_FRONT_PANEL_OFF 3 |
417 | |
418 | /* bnx2x_handle_module_detect_int should be called upon module detection |
419 | interrupt */ |
420 | void bnx2x_handle_module_detect_int(struct link_params *params); |
421 | |
422 | /* Get the actual link status. In case it returns 0, link is up, |
423 | otherwise link is down*/ |
424 | int bnx2x_test_link(struct link_params *params, struct link_vars *vars, |
425 | u8 is_serdes); |
426 | |
427 | /* One-time initialization for external phy after power up */ |
428 | int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
429 | u32 shmem2_base_path[], u32 chip_id); |
430 | |
431 | /* Reset the external PHY using GPIO */ |
432 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port); |
433 | |
434 | /* Reset the external of SFX7101 */ |
435 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy); |
436 | |
437 | /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ |
438 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
439 | struct link_params *params, u8 dev_addr, |
440 | u16 addr, u16 byte_cnt, u8 *o_buf); |
441 | |
442 | void bnx2x_hw_reset_phy(struct link_params *params); |
443 | |
444 | /* Check swap bit and adjust PHY order */ |
445 | u32 bnx2x_phy_selection(struct link_params *params); |
446 | |
447 | /* Probe the phys on board, and populate them in "params" */ |
448 | int bnx2x_phy_probe(struct link_params *params); |
449 | |
450 | /* Checks if fan failure detection is required on one of the phys on board */ |
451 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base, |
452 | u32 shmem2_base, u8 port); |
453 | |
454 | /* Open / close the gate between the NIG and the BRB */ |
455 | void bnx2x_set_rx_filter(struct link_params *params, u8 en); |
456 | |
457 | /* DCBX structs */ |
458 | |
459 | /* Number of maximum COS per chip */ |
460 | #define DCBX_E2E3_MAX_NUM_COS (2) |
461 | #define DCBX_E3B0_MAX_NUM_COS_PORT0 (6) |
462 | #define DCBX_E3B0_MAX_NUM_COS_PORT1 (3) |
463 | #define DCBX_E3B0_MAX_NUM_COS ( \ |
464 | MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \ |
465 | DCBX_E3B0_MAX_NUM_COS_PORT1)) |
466 | |
467 | #define DCBX_MAX_NUM_COS ( \ |
468 | MAXVAL(DCBX_E3B0_MAX_NUM_COS, \ |
469 | DCBX_E2E3_MAX_NUM_COS)) |
470 | |
471 | /* PFC port configuration params */ |
472 | struct bnx2x_nig_brb_pfc_port_params { |
473 | /* NIG */ |
474 | u32 pause_enable; |
475 | u32 llfc_out_en; |
476 | u32 llfc_enable; |
477 | u32 pkt_priority_to_cos; |
478 | u8 num_of_rx_cos_priority_mask; |
479 | u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS]; |
480 | u32 llfc_high_priority_classes; |
481 | u32 llfc_low_priority_classes; |
482 | }; |
483 | |
484 | |
485 | /* ETS port configuration params */ |
486 | struct bnx2x_ets_bw_params { |
487 | u8 bw; |
488 | }; |
489 | |
490 | struct bnx2x_ets_sp_params { |
491 | /** |
492 | * valid values are 0 - 5. 0 is highest strict priority. |
493 | * There can't be two COS's with the same pri. |
494 | */ |
495 | u8 pri; |
496 | }; |
497 | |
498 | enum bnx2x_cos_state { |
499 | bnx2x_cos_state_strict = 0, |
500 | bnx2x_cos_state_bw = 1, |
501 | }; |
502 | |
503 | struct bnx2x_ets_cos_params { |
504 | enum bnx2x_cos_state state ; |
505 | union { |
506 | struct bnx2x_ets_bw_params bw_params; |
507 | struct bnx2x_ets_sp_params sp_params; |
508 | } params; |
509 | }; |
510 | |
511 | struct bnx2x_ets_params { |
512 | u8 num_of_cos; /* Number of valid COS entries*/ |
513 | struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS]; |
514 | }; |
515 | |
516 | /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB |
517 | * when link is already up |
518 | */ |
519 | int bnx2x_update_pfc(struct link_params *params, |
520 | struct link_vars *vars, |
521 | struct bnx2x_nig_brb_pfc_port_params *pfc_params); |
522 | |
523 | |
524 | /* Used to configure the ETS to disable */ |
525 | int bnx2x_ets_disabled(struct link_params *params, |
526 | struct link_vars *vars); |
527 | |
528 | /* Used to configure the ETS to BW limited */ |
529 | void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, |
530 | const u32 cos1_bw); |
531 | |
532 | /* Used to configure the ETS to strict */ |
533 | int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos); |
534 | |
535 | |
536 | /* Configure the COS to ETS according to BW and SP settings.*/ |
537 | int bnx2x_ets_e3b0_config(const struct link_params *params, |
538 | const struct link_vars *vars, |
539 | struct bnx2x_ets_params *ets_params); |
540 | |
541 | void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, |
542 | u32 chip_id, u32 shmem_base, u32 shmem2_base, |
543 | u8 port); |
544 | |
545 | void bnx2x_period_func(struct link_params *params, struct link_vars *vars); |
546 | |
547 | #endif /* BNX2X_LINK_H */ |
548 | |