| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */ |
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| 3 | |
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| 4 | /* |
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| 5 | * FPGA specific definitions |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __CHELSIO_FPGA_DEFS_H__ |
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| 9 | #define __CHELSIO_FPGA_DEFS_H__ |
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| 10 | |
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| 11 | #define FPGA_PCIX_ADDR_VERSION 0xA08 |
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| 12 | #define FPGA_PCIX_ADDR_STAT 0xA0C |
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| 13 | |
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| 14 | /* FPGA master interrupt Cause/Enable bits */ |
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| 15 | #define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1 |
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| 16 | #define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2 |
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| 17 | #define FPGA_PCIX_INTERRUPT_TP 0x4 |
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| 18 | #define FPGA_PCIX_INTERRUPT_MC3 0x8 |
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| 19 | #define FPGA_PCIX_INTERRUPT_GMAC 0x10 |
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| 20 | #define FPGA_PCIX_INTERRUPT_PCIX 0x20 |
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| 21 | |
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| 22 | /* TP interrupt register addresses */ |
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| 23 | #define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10 |
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| 24 | #define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14 |
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| 25 | #define FPGA_TP_ADDR_VERSION 0xA18 |
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| 26 | |
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| 27 | /* TP interrupt Cause/Enable bits */ |
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| 28 | #define FPGA_TP_INTERRUPT_MC4 0x1 |
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| 29 | #define FPGA_TP_INTERRUPT_MC5 0x2 |
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| 30 | |
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| 31 | /* |
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| 32 | * PM interrupt register addresses |
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| 33 | */ |
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| 34 | #define FPGA_MC3_REG_INTRENABLE 0xA20 |
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| 35 | #define FPGA_MC3_REG_INTRCAUSE 0xA24 |
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| 36 | #define FPGA_MC3_REG_VERSION 0xA28 |
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| 37 | |
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| 38 | /* |
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| 39 | * GMAC interrupt register addresses |
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| 40 | */ |
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| 41 | #define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30 |
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| 42 | #define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34 |
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| 43 | #define FPGA_GMAC_ADDR_VERSION 0xA38 |
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| 44 | |
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| 45 | /* GMAC Cause/Enable bits */ |
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| 46 | #define FPGA_GMAC_INTERRUPT_PORT0 0x1 |
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| 47 | #define FPGA_GMAC_INTERRUPT_PORT1 0x2 |
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| 48 | #define FPGA_GMAC_INTERRUPT_PORT2 0x4 |
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| 49 | #define FPGA_GMAC_INTERRUPT_PORT3 0x8 |
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| 50 | |
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| 51 | /* MI0 registers */ |
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| 52 | #define A_MI0_CLK 0xb00 |
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| 53 | |
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| 54 | #define S_MI0_CLK_DIV 0 |
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| 55 | #define M_MI0_CLK_DIV 0xff |
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| 56 | #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV) |
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| 57 | #define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV) |
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| 58 | |
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| 59 | #define S_MI0_CLK_CNT 8 |
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| 60 | #define M_MI0_CLK_CNT 0xff |
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| 61 | #define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT) |
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| 62 | #define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT) |
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| 63 | |
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| 64 | #define A_MI0_CSR 0xb04 |
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| 65 | |
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| 66 | #define S_MI0_CSR_POLL 0 |
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| 67 | #define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL) |
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| 68 | #define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U) |
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| 69 | |
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| 70 | #define S_MI0_PREAMBLE 1 |
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| 71 | #define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE) |
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| 72 | #define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U) |
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| 73 | |
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| 74 | #define S_MI0_INTR_ENABLE 2 |
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| 75 | #define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE) |
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| 76 | #define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U) |
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| 77 | |
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| 78 | #define S_MI0_BUSY 3 |
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| 79 | #define V_MI0_BUSY(x) ((x) << S_MI0_BUSY) |
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| 80 | #define F_MI0_BUSY V_MI0_BUSY(1U) |
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| 81 | |
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| 82 | #define S_MI0_MDIO 4 |
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| 83 | #define V_MI0_MDIO(x) ((x) << S_MI0_MDIO) |
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| 84 | #define F_MI0_MDIO V_MI0_MDIO(1U) |
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| 85 | |
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| 86 | #define A_MI0_ADDR 0xb08 |
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| 87 | |
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| 88 | #define S_MI0_PHY_REG_ADDR 0 |
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| 89 | #define M_MI0_PHY_REG_ADDR 0x1f |
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| 90 | #define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR) |
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| 91 | #define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR) |
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| 92 | |
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| 93 | #define S_MI0_PHY_ADDR 5 |
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| 94 | #define M_MI0_PHY_ADDR 0x1f |
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| 95 | #define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR) |
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| 96 | #define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR) |
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| 97 | |
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| 98 | #define A_MI0_DATA_EXT 0xb0c |
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| 99 | #define A_MI0_DATA_INT 0xb10 |
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| 100 | |
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| 101 | /* GMAC registers */ |
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| 102 | #define A_GMAC_MACID_LO 0x28 |
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| 103 | #define A_GMAC_MACID_HI 0x2c |
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| 104 | #define A_GMAC_CSR 0x30 |
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| 105 | |
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| 106 | #define S_INTERFACE 0 |
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| 107 | #define M_INTERFACE 0x3 |
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| 108 | #define V_INTERFACE(x) ((x) << S_INTERFACE) |
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| 109 | #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE) |
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| 110 | |
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| 111 | #define S_MAC_TX_ENABLE 2 |
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| 112 | #define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE) |
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| 113 | #define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U) |
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| 114 | |
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| 115 | #define S_MAC_RX_ENABLE 3 |
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| 116 | #define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE) |
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| 117 | #define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U) |
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| 118 | |
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| 119 | #define S_MAC_LB_ENABLE 4 |
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| 120 | #define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE) |
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| 121 | #define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U) |
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| 122 | |
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| 123 | #define S_MAC_SPEED 5 |
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| 124 | #define M_MAC_SPEED 0x3 |
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| 125 | #define V_MAC_SPEED(x) ((x) << S_MAC_SPEED) |
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| 126 | #define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED) |
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| 127 | |
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| 128 | #define S_MAC_HD_FC_ENABLE 7 |
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| 129 | #define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE) |
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| 130 | #define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U) |
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| 131 | |
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| 132 | #define S_MAC_HALF_DUPLEX 8 |
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| 133 | #define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX) |
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| 134 | #define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U) |
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| 135 | |
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| 136 | #define S_MAC_PROMISC 9 |
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| 137 | #define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC) |
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| 138 | #define F_MAC_PROMISC V_MAC_PROMISC(1U) |
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| 139 | |
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| 140 | #define S_MAC_MC_ENABLE 10 |
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| 141 | #define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE) |
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| 142 | #define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U) |
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| 143 | |
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| 144 | #define S_MAC_RESET 11 |
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| 145 | #define V_MAC_RESET(x) ((x) << S_MAC_RESET) |
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| 146 | #define F_MAC_RESET V_MAC_RESET(1U) |
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| 147 | |
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| 148 | #define S_MAC_RX_PAUSE_ENABLE 12 |
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| 149 | #define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE) |
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| 150 | #define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U) |
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| 151 | |
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| 152 | #define S_MAC_TX_PAUSE_ENABLE 13 |
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| 153 | #define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE) |
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| 154 | #define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U) |
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| 155 | |
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| 156 | #define S_MAC_LWM_ENABLE 14 |
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| 157 | #define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE) |
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| 158 | #define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U) |
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| 159 | |
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| 160 | #define S_MAC_MAGIC_PKT_ENABLE 15 |
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| 161 | #define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE) |
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| 162 | #define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U) |
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| 163 | |
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| 164 | #define S_MAC_ISL_ENABLE 16 |
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| 165 | #define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE) |
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| 166 | #define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U) |
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| 167 | |
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| 168 | #define S_MAC_JUMBO_ENABLE 17 |
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| 169 | #define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE) |
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| 170 | #define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U) |
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| 171 | |
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| 172 | #define S_MAC_RX_PAD_ENABLE 18 |
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| 173 | #define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE) |
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| 174 | #define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U) |
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| 175 | |
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| 176 | #define S_MAC_RX_CRC_ENABLE 19 |
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| 177 | #define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE) |
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| 178 | #define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U) |
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| 179 | |
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| 180 | #define A_GMAC_IFS 0x34 |
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| 181 | |
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| 182 | #define S_MAC_IFS2 0 |
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| 183 | #define M_MAC_IFS2 0x3f |
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| 184 | #define V_MAC_IFS2(x) ((x) << S_MAC_IFS2) |
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| 185 | #define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2) |
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| 186 | |
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| 187 | #define S_MAC_IFS1 8 |
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| 188 | #define M_MAC_IFS1 0x7f |
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| 189 | #define V_MAC_IFS1(x) ((x) << S_MAC_IFS1) |
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| 190 | #define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1) |
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| 191 | |
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| 192 | #define A_GMAC_JUMBO_FRAME_LEN 0x38 |
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| 193 | #define A_GMAC_LNK_DLY 0x3c |
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| 194 | #define A_GMAC_PAUSETIME 0x40 |
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| 195 | #define A_GMAC_MCAST_LO 0x44 |
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| 196 | #define A_GMAC_MCAST_HI 0x48 |
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| 197 | #define A_GMAC_MCAST_MASK_LO 0x4c |
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| 198 | #define A_GMAC_MCAST_MASK_HI 0x50 |
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| 199 | #define A_GMAC_RMT_CNT 0x54 |
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| 200 | #define A_GMAC_RMT_DATA 0x58 |
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| 201 | #define A_GMAC_BACKOFF_SEED 0x5c |
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| 202 | #define A_GMAC_TXF_THRES 0x60 |
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| 203 | |
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| 204 | #define S_TXF_READ_THRESHOLD 0 |
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| 205 | #define M_TXF_READ_THRESHOLD 0xff |
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| 206 | #define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD) |
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| 207 | #define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD) |
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| 208 | |
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| 209 | #define S_TXF_WRITE_THRESHOLD 16 |
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| 210 | #define M_TXF_WRITE_THRESHOLD 0xff |
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| 211 | #define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD) |
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| 212 | #define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD) |
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| 213 | |
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| 214 | #define MAC_REG_BASE 0x600 |
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| 215 | #define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg)) |
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| 216 | |
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| 217 | #define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO) |
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| 218 | #define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI) |
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| 219 | #define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR) |
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| 220 | #define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS) |
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| 221 | #define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN) |
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| 222 | #define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY) |
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| 223 | #define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME) |
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| 224 | #define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO) |
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| 225 | #define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI) |
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| 226 | #define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO) |
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| 227 | #define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI) |
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| 228 | #define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT) |
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| 229 | #define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA) |
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| 230 | #define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED) |
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| 231 | #define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES) |
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| 232 | |
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| 233 | #endif |
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| 234 | |
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