1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright(c) 2013 - 2021 Intel Corporation. */ |
3 | |
4 | #ifndef _I40E_ADMINQ_CMD_H_ |
5 | #define _I40E_ADMINQ_CMD_H_ |
6 | |
7 | #include <linux/bits.h> |
8 | |
9 | /* This header file defines the i40e Admin Queue commands and is shared between |
10 | * i40e Firmware and Software. |
11 | * |
12 | * This file needs to comply with the Linux Kernel coding style. |
13 | */ |
14 | |
15 | #define I40E_FW_API_VERSION_MAJOR 0x0001 |
16 | #define I40E_FW_API_VERSION_MINOR_X722 0x000C |
17 | #define I40E_FW_API_VERSION_MINOR_X710 0x000F |
18 | |
19 | #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ |
20 | I40E_FW_API_VERSION_MINOR_X710 : \ |
21 | I40E_FW_API_VERSION_MINOR_X722) |
22 | |
23 | /* API version 1.7 implements additional link and PHY-specific APIs */ |
24 | #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 |
25 | /* API version 1.9 for X722 implements additional link and PHY-specific APIs */ |
26 | #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009 |
27 | /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ |
28 | #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 |
29 | /* API version 1.10 for X722 devices adds ability to request FEC encoding */ |
30 | #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A |
31 | |
32 | struct i40e_aq_desc { |
33 | __le16 flags; |
34 | __le16 opcode; |
35 | __le16 datalen; |
36 | __le16 retval; |
37 | __le32 cookie_high; |
38 | __le32 cookie_low; |
39 | union { |
40 | struct { |
41 | __le32 param0; |
42 | __le32 param1; |
43 | __le32 param2; |
44 | __le32 param3; |
45 | } internal; |
46 | struct { |
47 | __le32 param0; |
48 | __le32 param1; |
49 | __le32 addr_high; |
50 | __le32 addr_low; |
51 | } external; |
52 | u8 raw[16]; |
53 | } params; |
54 | }; |
55 | |
56 | /* Flags sub-structure |
57 | * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | |
58 | * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | |
59 | */ |
60 | |
61 | /* command flags and offsets*/ |
62 | #define I40E_AQ_FLAG_ERR_SHIFT 2 |
63 | #define I40E_AQ_FLAG_LB_SHIFT 9 |
64 | #define I40E_AQ_FLAG_RD_SHIFT 10 |
65 | #define I40E_AQ_FLAG_BUF_SHIFT 12 |
66 | #define I40E_AQ_FLAG_SI_SHIFT 13 |
67 | |
68 | #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ |
69 | #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ |
70 | #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ |
71 | #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ |
72 | #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ |
73 | |
74 | /* error codes */ |
75 | enum i40e_admin_queue_err { |
76 | I40E_AQ_RC_OK = 0, /* success */ |
77 | I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ |
78 | I40E_AQ_RC_ENOENT = 2, /* No such element */ |
79 | I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ |
80 | I40E_AQ_RC_EINTR = 4, /* operation interrupted */ |
81 | I40E_AQ_RC_EIO = 5, /* I/O error */ |
82 | I40E_AQ_RC_ENXIO = 6, /* No such resource */ |
83 | I40E_AQ_RC_E2BIG = 7, /* Arg too long */ |
84 | I40E_AQ_RC_EAGAIN = 8, /* Try again */ |
85 | I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ |
86 | I40E_AQ_RC_EACCES = 10, /* Permission denied */ |
87 | I40E_AQ_RC_EFAULT = 11, /* Bad address */ |
88 | I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ |
89 | I40E_AQ_RC_EEXIST = 13, /* object already exists */ |
90 | I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ |
91 | I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ |
92 | I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ |
93 | I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ |
94 | I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ |
95 | I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ |
96 | I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ |
97 | I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ |
98 | I40E_AQ_RC_EFBIG = 22, /* File too large */ |
99 | }; |
100 | |
101 | /* Admin Queue command opcodes */ |
102 | enum i40e_admin_queue_opc { |
103 | /* aq commands */ |
104 | i40e_aqc_opc_get_version = 0x0001, |
105 | i40e_aqc_opc_driver_version = 0x0002, |
106 | i40e_aqc_opc_queue_shutdown = 0x0003, |
107 | i40e_aqc_opc_set_pf_context = 0x0004, |
108 | |
109 | /* resource ownership */ |
110 | i40e_aqc_opc_request_resource = 0x0008, |
111 | i40e_aqc_opc_release_resource = 0x0009, |
112 | |
113 | i40e_aqc_opc_list_func_capabilities = 0x000A, |
114 | i40e_aqc_opc_list_dev_capabilities = 0x000B, |
115 | |
116 | /* Proxy commands */ |
117 | i40e_aqc_opc_set_proxy_config = 0x0104, |
118 | i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, |
119 | |
120 | /* LAA */ |
121 | i40e_aqc_opc_mac_address_read = 0x0107, |
122 | i40e_aqc_opc_mac_address_write = 0x0108, |
123 | |
124 | /* PXE */ |
125 | i40e_aqc_opc_clear_pxe_mode = 0x0110, |
126 | |
127 | /* WoL commands */ |
128 | i40e_aqc_opc_set_wol_filter = 0x0120, |
129 | i40e_aqc_opc_get_wake_reason = 0x0121, |
130 | |
131 | /* internal switch commands */ |
132 | i40e_aqc_opc_get_switch_config = 0x0200, |
133 | i40e_aqc_opc_add_statistics = 0x0201, |
134 | i40e_aqc_opc_remove_statistics = 0x0202, |
135 | i40e_aqc_opc_set_port_parameters = 0x0203, |
136 | i40e_aqc_opc_get_switch_resource_alloc = 0x0204, |
137 | i40e_aqc_opc_set_switch_config = 0x0205, |
138 | i40e_aqc_opc_rx_ctl_reg_read = 0x0206, |
139 | i40e_aqc_opc_rx_ctl_reg_write = 0x0207, |
140 | |
141 | i40e_aqc_opc_add_vsi = 0x0210, |
142 | i40e_aqc_opc_update_vsi_parameters = 0x0211, |
143 | i40e_aqc_opc_get_vsi_parameters = 0x0212, |
144 | |
145 | i40e_aqc_opc_add_pv = 0x0220, |
146 | i40e_aqc_opc_update_pv_parameters = 0x0221, |
147 | i40e_aqc_opc_get_pv_parameters = 0x0222, |
148 | |
149 | i40e_aqc_opc_add_veb = 0x0230, |
150 | i40e_aqc_opc_update_veb_parameters = 0x0231, |
151 | i40e_aqc_opc_get_veb_parameters = 0x0232, |
152 | |
153 | i40e_aqc_opc_delete_element = 0x0243, |
154 | |
155 | i40e_aqc_opc_add_macvlan = 0x0250, |
156 | i40e_aqc_opc_remove_macvlan = 0x0251, |
157 | i40e_aqc_opc_add_vlan = 0x0252, |
158 | i40e_aqc_opc_remove_vlan = 0x0253, |
159 | i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, |
160 | i40e_aqc_opc_add_tag = 0x0255, |
161 | i40e_aqc_opc_remove_tag = 0x0256, |
162 | i40e_aqc_opc_add_multicast_etag = 0x0257, |
163 | i40e_aqc_opc_remove_multicast_etag = 0x0258, |
164 | i40e_aqc_opc_update_tag = 0x0259, |
165 | i40e_aqc_opc_add_control_packet_filter = 0x025A, |
166 | i40e_aqc_opc_remove_control_packet_filter = 0x025B, |
167 | i40e_aqc_opc_add_cloud_filters = 0x025C, |
168 | i40e_aqc_opc_remove_cloud_filters = 0x025D, |
169 | i40e_aqc_opc_clear_wol_switch_filters = 0x025E, |
170 | |
171 | i40e_aqc_opc_add_mirror_rule = 0x0260, |
172 | i40e_aqc_opc_delete_mirror_rule = 0x0261, |
173 | |
174 | /* Dynamic Device Personalization */ |
175 | i40e_aqc_opc_write_personalization_profile = 0x0270, |
176 | i40e_aqc_opc_get_personalization_profile_list = 0x0271, |
177 | |
178 | /* DCB commands */ |
179 | i40e_aqc_opc_dcb_ignore_pfc = 0x0301, |
180 | i40e_aqc_opc_dcb_updated = 0x0302, |
181 | i40e_aqc_opc_set_dcb_parameters = 0x0303, |
182 | |
183 | /* TX scheduler */ |
184 | i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, |
185 | i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, |
186 | i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, |
187 | i40e_aqc_opc_query_vsi_bw_config = 0x0408, |
188 | i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, |
189 | i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, |
190 | |
191 | i40e_aqc_opc_enable_switching_comp_ets = 0x0413, |
192 | i40e_aqc_opc_modify_switching_comp_ets = 0x0414, |
193 | i40e_aqc_opc_disable_switching_comp_ets = 0x0415, |
194 | i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, |
195 | i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, |
196 | i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, |
197 | i40e_aqc_opc_query_port_ets_config = 0x0419, |
198 | i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, |
199 | i40e_aqc_opc_suspend_port_tx = 0x041B, |
200 | i40e_aqc_opc_resume_port_tx = 0x041C, |
201 | i40e_aqc_opc_configure_partition_bw = 0x041D, |
202 | /* hmc */ |
203 | i40e_aqc_opc_query_hmc_resource_profile = 0x0500, |
204 | i40e_aqc_opc_set_hmc_resource_profile = 0x0501, |
205 | |
206 | /* phy commands*/ |
207 | i40e_aqc_opc_get_phy_abilities = 0x0600, |
208 | i40e_aqc_opc_set_phy_config = 0x0601, |
209 | i40e_aqc_opc_set_mac_config = 0x0603, |
210 | i40e_aqc_opc_set_link_restart_an = 0x0605, |
211 | i40e_aqc_opc_get_link_status = 0x0607, |
212 | i40e_aqc_opc_set_phy_int_mask = 0x0613, |
213 | i40e_aqc_opc_get_local_advt_reg = 0x0614, |
214 | i40e_aqc_opc_set_local_advt_reg = 0x0615, |
215 | i40e_aqc_opc_get_partner_advt = 0x0616, |
216 | i40e_aqc_opc_set_lb_modes = 0x0618, |
217 | i40e_aqc_opc_get_phy_wol_caps = 0x0621, |
218 | i40e_aqc_opc_set_phy_debug = 0x0622, |
219 | i40e_aqc_opc_upload_ext_phy_fm = 0x0625, |
220 | i40e_aqc_opc_run_phy_activity = 0x0626, |
221 | i40e_aqc_opc_set_phy_register = 0x0628, |
222 | i40e_aqc_opc_get_phy_register = 0x0629, |
223 | |
224 | /* NVM commands */ |
225 | i40e_aqc_opc_nvm_read = 0x0701, |
226 | i40e_aqc_opc_nvm_erase = 0x0702, |
227 | i40e_aqc_opc_nvm_update = 0x0703, |
228 | i40e_aqc_opc_nvm_config_read = 0x0704, |
229 | i40e_aqc_opc_nvm_config_write = 0x0705, |
230 | i40e_aqc_opc_oem_post_update = 0x0720, |
231 | i40e_aqc_opc_thermal_sensor = 0x0721, |
232 | |
233 | /* virtualization commands */ |
234 | i40e_aqc_opc_send_msg_to_pf = 0x0801, |
235 | i40e_aqc_opc_send_msg_to_vf = 0x0802, |
236 | i40e_aqc_opc_send_msg_to_peer = 0x0803, |
237 | |
238 | /* alternate structure */ |
239 | i40e_aqc_opc_alternate_write = 0x0900, |
240 | i40e_aqc_opc_alternate_write_indirect = 0x0901, |
241 | i40e_aqc_opc_alternate_read = 0x0902, |
242 | i40e_aqc_opc_alternate_read_indirect = 0x0903, |
243 | i40e_aqc_opc_alternate_write_done = 0x0904, |
244 | i40e_aqc_opc_alternate_set_mode = 0x0905, |
245 | i40e_aqc_opc_alternate_clear_port = 0x0906, |
246 | |
247 | /* LLDP commands */ |
248 | i40e_aqc_opc_lldp_get_mib = 0x0A00, |
249 | i40e_aqc_opc_lldp_update_mib = 0x0A01, |
250 | i40e_aqc_opc_lldp_add_tlv = 0x0A02, |
251 | i40e_aqc_opc_lldp_update_tlv = 0x0A03, |
252 | i40e_aqc_opc_lldp_delete_tlv = 0x0A04, |
253 | i40e_aqc_opc_lldp_stop = 0x0A05, |
254 | i40e_aqc_opc_lldp_start = 0x0A06, |
255 | i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, |
256 | i40e_aqc_opc_lldp_set_local_mib = 0x0A08, |
257 | i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, |
258 | i40e_aqc_opc_lldp_restore = 0x0A0A, |
259 | |
260 | /* Tunnel commands */ |
261 | i40e_aqc_opc_add_udp_tunnel = 0x0B00, |
262 | i40e_aqc_opc_del_udp_tunnel = 0x0B01, |
263 | = 0x0B02, |
264 | = 0x0B03, |
265 | = 0x0B04, |
266 | = 0x0B05, |
267 | |
268 | /* Async Events */ |
269 | i40e_aqc_opc_event_lan_overflow = 0x1001, |
270 | |
271 | /* OEM commands */ |
272 | i40e_aqc_opc_oem_parameter_change = 0xFE00, |
273 | i40e_aqc_opc_oem_device_status_change = 0xFE01, |
274 | i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, |
275 | i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, |
276 | |
277 | /* debug commands */ |
278 | i40e_aqc_opc_debug_read_reg = 0xFF03, |
279 | i40e_aqc_opc_debug_write_reg = 0xFF04, |
280 | i40e_aqc_opc_debug_modify_reg = 0xFF07, |
281 | i40e_aqc_opc_debug_dump_internals = 0xFF08, |
282 | }; |
283 | |
284 | /* command structures and indirect data structures */ |
285 | |
286 | /* Structure naming conventions: |
287 | * - no suffix for direct command descriptor structures |
288 | * - _data for indirect sent data |
289 | * - _resp for indirect return data (data which is both will use _data) |
290 | * - _completion for direct return data |
291 | * - _element_ for repeated elements (may also be _data or _resp) |
292 | * |
293 | * Command structures are expected to overlay the params.raw member of the basic |
294 | * descriptor, and as such cannot exceed 16 bytes in length. |
295 | */ |
296 | |
297 | /* This macro is used to generate a compilation error if a structure |
298 | * is not exactly the correct length. It gives a divide by zero error if the |
299 | * structure is not of the correct size, otherwise it creates an enum that is |
300 | * never used. |
301 | */ |
302 | #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ |
303 | { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } |
304 | |
305 | /* This macro is used extensively to ensure that command structures are 16 |
306 | * bytes in length as they have to map to the raw array of that size. |
307 | */ |
308 | #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) |
309 | |
310 | /* internal (0x00XX) commands */ |
311 | |
312 | /* Get version (direct 0x0001) */ |
313 | struct i40e_aqc_get_version { |
314 | __le32 rom_ver; |
315 | __le32 fw_build; |
316 | __le16 fw_major; |
317 | __le16 fw_minor; |
318 | __le16 api_major; |
319 | __le16 api_minor; |
320 | }; |
321 | |
322 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); |
323 | |
324 | /* Send driver version (indirect 0x0002) */ |
325 | struct i40e_aqc_driver_version { |
326 | u8 driver_major_ver; |
327 | u8 driver_minor_ver; |
328 | u8 driver_build_ver; |
329 | u8 driver_subbuild_ver; |
330 | u8 reserved[4]; |
331 | __le32 address_high; |
332 | __le32 address_low; |
333 | }; |
334 | |
335 | I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); |
336 | |
337 | /* Queue Shutdown (direct 0x0003) */ |
338 | struct i40e_aqc_queue_shutdown { |
339 | __le32 driver_unloading; |
340 | #define I40E_AQ_DRIVER_UNLOADING 0x1 |
341 | u8 reserved[12]; |
342 | }; |
343 | |
344 | I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); |
345 | |
346 | /* Set PF context (0x0004, direct) */ |
347 | struct i40e_aqc_set_pf_context { |
348 | u8 pf_id; |
349 | u8 reserved[15]; |
350 | }; |
351 | |
352 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); |
353 | |
354 | /* Request resource ownership (direct 0x0008) |
355 | * Release resource ownership (direct 0x0009) |
356 | */ |
357 | struct i40e_aqc_request_resource { |
358 | __le16 resource_id; |
359 | __le16 access_type; |
360 | __le32 timeout; |
361 | __le32 resource_number; |
362 | u8 reserved[4]; |
363 | }; |
364 | |
365 | I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); |
366 | |
367 | /* Get function capabilities (indirect 0x000A) |
368 | * Get device capabilities (indirect 0x000B) |
369 | */ |
370 | struct i40e_aqc_list_capabilites { |
371 | u8 command_flags; |
372 | u8 pf_index; |
373 | u8 reserved[2]; |
374 | __le32 count; |
375 | __le32 addr_high; |
376 | __le32 addr_low; |
377 | }; |
378 | |
379 | I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); |
380 | |
381 | struct i40e_aqc_list_capabilities_element_resp { |
382 | __le16 id; |
383 | u8 major_rev; |
384 | u8 minor_rev; |
385 | __le32 number; |
386 | __le32 logical_id; |
387 | __le32 phys_id; |
388 | u8 reserved[16]; |
389 | }; |
390 | |
391 | /* list of caps */ |
392 | |
393 | #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 |
394 | #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 |
395 | #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 |
396 | #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 |
397 | #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 |
398 | #define I40E_AQ_CAP_ID_SRIOV 0x0012 |
399 | #define I40E_AQ_CAP_ID_VF 0x0013 |
400 | #define I40E_AQ_CAP_ID_VMDQ 0x0014 |
401 | #define I40E_AQ_CAP_ID_8021QBG 0x0015 |
402 | #define I40E_AQ_CAP_ID_8021QBR 0x0016 |
403 | #define I40E_AQ_CAP_ID_VSI 0x0017 |
404 | #define I40E_AQ_CAP_ID_DCB 0x0018 |
405 | #define I40E_AQ_CAP_ID_FCOE 0x0021 |
406 | #define I40E_AQ_CAP_ID_ISCSI 0x0022 |
407 | #define 0x0040 |
408 | #define I40E_AQ_CAP_ID_RXQ 0x0041 |
409 | #define I40E_AQ_CAP_ID_TXQ 0x0042 |
410 | #define I40E_AQ_CAP_ID_MSIX 0x0043 |
411 | #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 |
412 | #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 |
413 | #define I40E_AQ_CAP_ID_1588 0x0046 |
414 | #define I40E_AQ_CAP_ID_IWARP 0x0051 |
415 | #define I40E_AQ_CAP_ID_LED 0x0061 |
416 | #define I40E_AQ_CAP_ID_SDP 0x0062 |
417 | #define I40E_AQ_CAP_ID_MDIO 0x0063 |
418 | #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 |
419 | #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 |
420 | #define I40E_AQ_CAP_ID_FLEX10 0x00F1 |
421 | #define I40E_AQ_CAP_ID_CEM 0x00F2 |
422 | |
423 | /* Set CPPM Configuration (direct 0x0103) */ |
424 | struct i40e_aqc_cppm_configuration { |
425 | __le16 command_flags; |
426 | __le16 ttlx; |
427 | __le32 dmacr; |
428 | __le16 dmcth; |
429 | u8 hptc; |
430 | u8 reserved; |
431 | __le32 pfltrc; |
432 | }; |
433 | |
434 | I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); |
435 | |
436 | /* Set ARP Proxy command / response (indirect 0x0104) */ |
437 | struct i40e_aqc_arp_proxy_data { |
438 | __le16 command_flags; |
439 | __le16 table_id; |
440 | __le32 enabled_offloads; |
441 | __le32 ip_addr; |
442 | u8 mac_addr[6]; |
443 | u8 reserved[2]; |
444 | }; |
445 | |
446 | I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); |
447 | |
448 | /* Set NS Proxy Table Entry Command (indirect 0x0105) */ |
449 | struct i40e_aqc_ns_proxy_data { |
450 | __le16 table_idx_mac_addr_0; |
451 | __le16 table_idx_mac_addr_1; |
452 | __le16 table_idx_ipv6_0; |
453 | __le16 table_idx_ipv6_1; |
454 | __le16 control; |
455 | u8 mac_addr_0[6]; |
456 | u8 mac_addr_1[6]; |
457 | u8 local_mac_addr[6]; |
458 | u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ |
459 | u8 ipv6_addr_1[16]; |
460 | }; |
461 | |
462 | I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); |
463 | |
464 | /* Manage LAA Command (0x0106) - obsolete */ |
465 | struct i40e_aqc_mng_laa { |
466 | __le16 command_flags; |
467 | u8 reserved[2]; |
468 | __le32 sal; |
469 | __le16 sah; |
470 | u8 reserved2[6]; |
471 | }; |
472 | |
473 | I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); |
474 | |
475 | /* Manage MAC Address Read Command (indirect 0x0107) */ |
476 | struct i40e_aqc_mac_address_read { |
477 | __le16 command_flags; |
478 | #define I40E_AQC_LAN_ADDR_VALID 0x10 |
479 | #define I40E_AQC_PORT_ADDR_VALID 0x40 |
480 | u8 reserved[6]; |
481 | __le32 addr_high; |
482 | __le32 addr_low; |
483 | }; |
484 | |
485 | I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); |
486 | |
487 | struct i40e_aqc_mac_address_read_data { |
488 | u8 pf_lan_mac[6]; |
489 | u8 pf_san_mac[6]; |
490 | u8 port_mac[6]; |
491 | u8 pf_wol_mac[6]; |
492 | }; |
493 | |
494 | I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); |
495 | |
496 | /* Manage MAC Address Write Command (0x0108) */ |
497 | struct i40e_aqc_mac_address_write { |
498 | __le16 command_flags; |
499 | #define I40E_AQC_MC_MAG_EN 0x0100 |
500 | #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 |
501 | #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 |
502 | #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 |
503 | #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 |
504 | |
505 | __le16 mac_sah; |
506 | __le32 mac_sal; |
507 | u8 reserved[8]; |
508 | }; |
509 | |
510 | I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); |
511 | |
512 | /* PXE commands (0x011x) */ |
513 | |
514 | /* Clear PXE Command and response (direct 0x0110) */ |
515 | struct i40e_aqc_clear_pxe { |
516 | u8 rx_cnt; |
517 | u8 reserved[15]; |
518 | }; |
519 | |
520 | I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); |
521 | |
522 | /* Set WoL Filter (0x0120) */ |
523 | |
524 | struct i40e_aqc_set_wol_filter { |
525 | __le16 filter_index; |
526 | |
527 | __le16 cmd_flags; |
528 | __le16 valid_flags; |
529 | u8 reserved[2]; |
530 | __le32 address_high; |
531 | __le32 address_low; |
532 | }; |
533 | |
534 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); |
535 | |
536 | struct i40e_aqc_set_wol_filter_data { |
537 | u8 filter[128]; |
538 | u8 mask[16]; |
539 | }; |
540 | |
541 | I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); |
542 | |
543 | /* Get Wake Reason (0x0121) */ |
544 | |
545 | struct i40e_aqc_get_wake_reason_completion { |
546 | u8 reserved_1[2]; |
547 | __le16 wake_reason; |
548 | u8 reserved_2[12]; |
549 | }; |
550 | |
551 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); |
552 | |
553 | /* Switch configuration commands (0x02xx) */ |
554 | |
555 | /* Used by many indirect commands that only pass an seid and a buffer in the |
556 | * command |
557 | */ |
558 | struct i40e_aqc_switch_seid { |
559 | __le16 seid; |
560 | u8 reserved[6]; |
561 | __le32 addr_high; |
562 | __le32 addr_low; |
563 | }; |
564 | |
565 | I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); |
566 | |
567 | /* Get Switch Configuration command (indirect 0x0200) |
568 | * uses i40e_aqc_switch_seid for the descriptor |
569 | */ |
570 | struct { |
571 | __le16 ; |
572 | __le16 ; |
573 | u8 [12]; |
574 | }; |
575 | |
576 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); |
577 | |
578 | struct i40e_aqc_switch_config_element_resp { |
579 | u8 element_type; |
580 | u8 revision; |
581 | __le16 seid; |
582 | __le16 uplink_seid; |
583 | __le16 downlink_seid; |
584 | u8 reserved[3]; |
585 | u8 connection_type; |
586 | __le16 scheduler_id; |
587 | __le16 element_info; |
588 | }; |
589 | |
590 | I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); |
591 | |
592 | /* Get Switch Configuration (indirect 0x0200) |
593 | * an array of elements are returned in the response buffer |
594 | * the first in the array is the header, remainder are elements |
595 | */ |
596 | struct i40e_aqc_get_switch_config_resp { |
597 | struct i40e_aqc_get_switch_config_header_resp ; |
598 | struct i40e_aqc_switch_config_element_resp element[1]; |
599 | }; |
600 | |
601 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); |
602 | |
603 | /* Add Statistics (direct 0x0201) |
604 | * Remove Statistics (direct 0x0202) |
605 | */ |
606 | struct i40e_aqc_add_remove_statistics { |
607 | __le16 seid; |
608 | __le16 vlan; |
609 | __le16 stat_index; |
610 | u8 reserved[10]; |
611 | }; |
612 | |
613 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); |
614 | |
615 | /* Set Port Parameters command (direct 0x0203) */ |
616 | struct i40e_aqc_set_port_parameters { |
617 | __le16 command_flags; |
618 | __le16 bad_frame_vsi; |
619 | __le16 default_seid; /* reserved for command */ |
620 | u8 reserved[10]; |
621 | }; |
622 | |
623 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); |
624 | |
625 | /* Get Switch Resource Allocation (indirect 0x0204) */ |
626 | struct i40e_aqc_get_switch_resource_alloc { |
627 | u8 num_entries; /* reserved for command */ |
628 | u8 reserved[7]; |
629 | __le32 addr_high; |
630 | __le32 addr_low; |
631 | }; |
632 | |
633 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); |
634 | |
635 | /* expect an array of these structs in the response buffer */ |
636 | struct i40e_aqc_switch_resource_alloc_element_resp { |
637 | u8 resource_type; |
638 | u8 reserved1; |
639 | __le16 guaranteed; |
640 | __le16 total; |
641 | __le16 used; |
642 | __le16 total_unalloced; |
643 | u8 reserved2[6]; |
644 | }; |
645 | |
646 | I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); |
647 | |
648 | /* Set Switch Configuration (direct 0x0205) */ |
649 | struct i40e_aqc_set_switch_config { |
650 | __le16 flags; |
651 | /* flags used for both fields below */ |
652 | #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 |
653 | __le16 valid_flags; |
654 | /* The ethertype in switch_tag is dropped on ingress and used |
655 | * internally by the switch. Set this to zero for the default |
656 | * of 0x88a8 (802.1ad). Should be zero for firmware API |
657 | * versions lower than 1.7. |
658 | */ |
659 | __le16 switch_tag; |
660 | /* The ethertypes in first_tag and second_tag are used to |
661 | * match the outer and inner VLAN tags (respectively) when HW |
662 | * double VLAN tagging is enabled via the set port parameters |
663 | * AQ command. Otherwise these are both ignored. Set them to |
664 | * zero for their defaults of 0x8100 (802.1Q). Should be zero |
665 | * for firmware API versions lower than 1.7. |
666 | */ |
667 | __le16 first_tag; |
668 | __le16 second_tag; |
669 | /* Next byte is split into following: |
670 | * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 |
671 | * Bit 6 : 0 : Destination Port, 1: source port |
672 | * Bit 5..4 : L4 type |
673 | * 0: rsvd |
674 | * 1: TCP |
675 | * 2: UDP |
676 | * 3: Both TCP and UDP |
677 | * Bits 3:0 Mode |
678 | * 0: default mode |
679 | * 1: L4 port only mode |
680 | * 2: non-tunneled mode |
681 | * 3: tunneled mode |
682 | */ |
683 | #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 |
684 | |
685 | |
686 | #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 |
687 | |
688 | #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 |
689 | u8 mode; |
690 | u8 rsvd5[5]; |
691 | }; |
692 | |
693 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); |
694 | |
695 | /* Read Receive control registers (direct 0x0206) |
696 | * Write Receive control registers (direct 0x0207) |
697 | * used for accessing Rx control registers that can be |
698 | * slow and need special handling when under high Rx load |
699 | */ |
700 | struct i40e_aqc_rx_ctl_reg_read_write { |
701 | __le32 reserved1; |
702 | __le32 address; |
703 | __le32 reserved2; |
704 | __le32 value; |
705 | }; |
706 | |
707 | I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); |
708 | |
709 | /* Add VSI (indirect 0x0210) |
710 | * this indirect command uses struct i40e_aqc_vsi_properties_data |
711 | * as the indirect buffer (128 bytes) |
712 | * |
713 | * Update VSI (indirect 0x211) |
714 | * uses the same data structure as Add VSI |
715 | * |
716 | * Get VSI (indirect 0x0212) |
717 | * uses the same completion and data structure as Add VSI |
718 | */ |
719 | struct i40e_aqc_add_get_update_vsi { |
720 | __le16 uplink_seid; |
721 | u8 connection_type; |
722 | #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 |
723 | u8 reserved1; |
724 | u8 vf_id; |
725 | u8 reserved2; |
726 | __le16 vsi_flags; |
727 | #define I40E_AQ_VSI_TYPE_VF 0x0 |
728 | #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 |
729 | #define I40E_AQ_VSI_TYPE_PF 0x2 |
730 | __le32 addr_high; |
731 | __le32 addr_low; |
732 | }; |
733 | |
734 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); |
735 | |
736 | struct i40e_aqc_add_get_update_vsi_completion { |
737 | __le16 seid; |
738 | __le16 vsi_number; |
739 | __le16 vsi_used; |
740 | __le16 vsi_free; |
741 | __le32 addr_high; |
742 | __le32 addr_low; |
743 | }; |
744 | |
745 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); |
746 | |
747 | struct i40e_aqc_vsi_properties_data { |
748 | /* first 96 byte are written by SW */ |
749 | __le16 valid_sections; |
750 | #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 |
751 | #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 |
752 | #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 |
753 | #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 |
754 | #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 |
755 | #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 |
756 | /* switch section */ |
757 | __le16 switch_id; /* 12bit id combined with flags below */ |
758 | #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 |
759 | #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) |
760 | #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 |
761 | #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 |
762 | u8 sw_reserved[2]; |
763 | /* security section */ |
764 | u8 sec_flags; |
765 | #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 |
766 | #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 |
767 | u8 sec_reserved; |
768 | /* VLAN section */ |
769 | __le16 pvid; /* VLANS include priority bits */ |
770 | __le16 fcoe_pvid; |
771 | u8 port_vlan_flags; |
772 | #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 |
773 | #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ |
774 | I40E_AQ_VSI_PVLAN_MODE_SHIFT) |
775 | #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 |
776 | #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 |
777 | #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 |
778 | #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 |
779 | #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ |
780 | I40E_AQ_VSI_PVLAN_EMOD_SHIFT) |
781 | #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 |
782 | #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 |
783 | #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 |
784 | u8 pvlan_reserved[3]; |
785 | /* ingress egress up sections */ |
786 | __le32 ingress_table; /* bitmap, 3 bits per up */ |
787 | __le32 egress_table; /* same defines as for ingress table */ |
788 | /* cascaded PV section */ |
789 | __le16 cas_pv_tag; |
790 | u8 cas_pv_flags; |
791 | u8 cas_pv_reserved; |
792 | /* queue mapping section */ |
793 | __le16 mapping_flags; |
794 | #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 |
795 | #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 |
796 | __le16 queue_mapping[16]; |
797 | __le16 tc_mapping[8]; |
798 | #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 |
799 | #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 |
800 | /* queueing option section */ |
801 | u8 queueing_opt_flags; |
802 | #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 |
803 | #define 0x40 |
804 | u8 queueing_opt_reserved[3]; |
805 | /* scheduler section */ |
806 | u8 up_enable_bits; |
807 | u8 sched_reserved; |
808 | /* outer up section */ |
809 | __le32 outer_up_table; /* same structure and defines as ingress tbl */ |
810 | u8 cmd_reserved[8]; |
811 | /* last 32 bytes are written by FW */ |
812 | __le16 qs_handle[8]; |
813 | #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF |
814 | __le16 stat_counter_idx; |
815 | __le16 sched_id; |
816 | u8 resp_reserved[12]; |
817 | }; |
818 | |
819 | I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); |
820 | |
821 | /* Add Port Virtualizer (direct 0x0220) |
822 | * also used for update PV (direct 0x0221) but only flags are used |
823 | * (IS_CTRL_PORT only works on add PV) |
824 | */ |
825 | struct i40e_aqc_add_update_pv { |
826 | __le16 command_flags; |
827 | __le16 uplink_seid; |
828 | __le16 connected_seid; |
829 | u8 reserved[10]; |
830 | }; |
831 | |
832 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); |
833 | |
834 | struct i40e_aqc_add_update_pv_completion { |
835 | /* reserved for update; for add also encodes error if rc == ENOSPC */ |
836 | __le16 pv_seid; |
837 | u8 reserved[14]; |
838 | }; |
839 | |
840 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); |
841 | |
842 | /* Get PV Params (direct 0x0222) |
843 | * uses i40e_aqc_switch_seid for the descriptor |
844 | */ |
845 | |
846 | struct i40e_aqc_get_pv_params_completion { |
847 | __le16 seid; |
848 | __le16 default_stag; |
849 | __le16 pv_flags; /* same flags as add_pv */ |
850 | u8 reserved[8]; |
851 | __le16 default_port_seid; |
852 | }; |
853 | |
854 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); |
855 | |
856 | /* Add VEB (direct 0x0230) */ |
857 | struct i40e_aqc_add_veb { |
858 | __le16 uplink_seid; |
859 | __le16 downlink_seid; |
860 | __le16 veb_flags; |
861 | #define I40E_AQC_ADD_VEB_FLOATING 0x1 |
862 | #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 |
863 | #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 |
864 | #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 |
865 | u8 enable_tcs; |
866 | u8 reserved[9]; |
867 | }; |
868 | |
869 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); |
870 | |
871 | struct i40e_aqc_add_veb_completion { |
872 | u8 reserved[6]; |
873 | __le16 switch_seid; |
874 | /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ |
875 | __le16 veb_seid; |
876 | __le16 statistic_index; |
877 | __le16 vebs_used; |
878 | __le16 vebs_free; |
879 | }; |
880 | |
881 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); |
882 | |
883 | /* Get VEB Parameters (direct 0x0232) |
884 | * uses i40e_aqc_switch_seid for the descriptor |
885 | */ |
886 | struct i40e_aqc_get_veb_parameters_completion { |
887 | __le16 seid; |
888 | __le16 switch_id; |
889 | __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ |
890 | __le16 statistic_index; |
891 | __le16 vebs_used; |
892 | __le16 vebs_free; |
893 | u8 reserved[4]; |
894 | }; |
895 | |
896 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); |
897 | |
898 | /* Delete Element (direct 0x0243) |
899 | * uses the generic i40e_aqc_switch_seid |
900 | */ |
901 | |
902 | /* Add MAC-VLAN (indirect 0x0250) */ |
903 | |
904 | /* used for the command for most vlan commands */ |
905 | struct i40e_aqc_macvlan { |
906 | __le16 num_addresses; |
907 | __le16 seid[3]; |
908 | #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 |
909 | __le32 addr_high; |
910 | __le32 addr_low; |
911 | }; |
912 | |
913 | I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); |
914 | |
915 | /* indirect data for command and response */ |
916 | struct i40e_aqc_add_macvlan_element_data { |
917 | u8 mac_addr[6]; |
918 | __le16 vlan_tag; |
919 | __le16 flags; |
920 | #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 |
921 | #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 |
922 | #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 |
923 | __le16 queue_number; |
924 | /* response section */ |
925 | u8 match_method; |
926 | #define I40E_AQC_MM_ERR_NO_RES 0xFF |
927 | u8 reserved1[3]; |
928 | }; |
929 | |
930 | struct i40e_aqc_add_remove_macvlan_completion { |
931 | __le16 perfect_mac_used; |
932 | __le16 perfect_mac_free; |
933 | __le16 unicast_hash_free; |
934 | __le16 multicast_hash_free; |
935 | __le32 addr_high; |
936 | __le32 addr_low; |
937 | }; |
938 | |
939 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); |
940 | |
941 | /* Remove MAC-VLAN (indirect 0x0251) |
942 | * uses i40e_aqc_macvlan for the descriptor |
943 | * data points to an array of num_addresses of elements |
944 | */ |
945 | |
946 | struct i40e_aqc_remove_macvlan_element_data { |
947 | u8 mac_addr[6]; |
948 | __le16 vlan_tag; |
949 | u8 flags; |
950 | #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 |
951 | #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 |
952 | u8 reserved[3]; |
953 | /* reply section */ |
954 | u8 error_code; |
955 | u8 reply_reserved[3]; |
956 | }; |
957 | |
958 | /* Add VLAN (indirect 0x0252) |
959 | * Remove VLAN (indirect 0x0253) |
960 | * use the generic i40e_aqc_macvlan for the command |
961 | */ |
962 | struct i40e_aqc_add_remove_vlan_element_data { |
963 | __le16 vlan_tag; |
964 | u8 vlan_flags; |
965 | u8 reserved; |
966 | u8 result; |
967 | u8 reserved1[3]; |
968 | }; |
969 | |
970 | struct i40e_aqc_add_remove_vlan_completion { |
971 | u8 reserved[4]; |
972 | __le16 vlans_used; |
973 | __le16 vlans_free; |
974 | __le32 addr_high; |
975 | __le32 addr_low; |
976 | }; |
977 | |
978 | /* Set VSI Promiscuous Modes (direct 0x0254) */ |
979 | struct i40e_aqc_set_vsi_promiscuous_modes { |
980 | __le16 promiscuous_flags; |
981 | __le16 valid_flags; |
982 | /* flags used for both fields above */ |
983 | #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 |
984 | #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 |
985 | #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 |
986 | #define I40E_AQC_SET_VSI_DEFAULT 0x08 |
987 | #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 |
988 | #define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000 |
989 | __le16 seid; |
990 | __le16 vlan_tag; |
991 | #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 |
992 | u8 reserved[8]; |
993 | }; |
994 | |
995 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); |
996 | |
997 | /* Add S/E-tag command (direct 0x0255) |
998 | * Uses generic i40e_aqc_add_remove_tag_completion for completion |
999 | */ |
1000 | struct i40e_aqc_add_tag { |
1001 | __le16 flags; |
1002 | __le16 seid; |
1003 | __le16 tag; |
1004 | __le16 queue_number; |
1005 | u8 reserved[8]; |
1006 | }; |
1007 | |
1008 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); |
1009 | |
1010 | struct i40e_aqc_add_remove_tag_completion { |
1011 | u8 reserved[12]; |
1012 | __le16 tags_used; |
1013 | __le16 tags_free; |
1014 | }; |
1015 | |
1016 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); |
1017 | |
1018 | /* Remove S/E-tag command (direct 0x0256) |
1019 | * Uses generic i40e_aqc_add_remove_tag_completion for completion |
1020 | */ |
1021 | struct i40e_aqc_remove_tag { |
1022 | __le16 seid; |
1023 | __le16 tag; |
1024 | u8 reserved[12]; |
1025 | }; |
1026 | |
1027 | I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); |
1028 | |
1029 | /* Add multicast E-Tag (direct 0x0257) |
1030 | * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields |
1031 | * and no external data |
1032 | */ |
1033 | struct i40e_aqc_add_remove_mcast_etag { |
1034 | __le16 pv_seid; |
1035 | __le16 etag; |
1036 | u8 num_unicast_etags; |
1037 | u8 reserved[3]; |
1038 | __le32 addr_high; /* address of array of 2-byte s-tags */ |
1039 | __le32 addr_low; |
1040 | }; |
1041 | |
1042 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); |
1043 | |
1044 | struct i40e_aqc_add_remove_mcast_etag_completion { |
1045 | u8 reserved[4]; |
1046 | __le16 mcast_etags_used; |
1047 | __le16 mcast_etags_free; |
1048 | __le32 addr_high; |
1049 | __le32 addr_low; |
1050 | |
1051 | }; |
1052 | |
1053 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); |
1054 | |
1055 | /* Update S/E-Tag (direct 0x0259) */ |
1056 | struct i40e_aqc_update_tag { |
1057 | __le16 seid; |
1058 | __le16 old_tag; |
1059 | __le16 new_tag; |
1060 | u8 reserved[10]; |
1061 | }; |
1062 | |
1063 | I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); |
1064 | |
1065 | struct i40e_aqc_update_tag_completion { |
1066 | u8 reserved[12]; |
1067 | __le16 tags_used; |
1068 | __le16 tags_free; |
1069 | }; |
1070 | |
1071 | I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); |
1072 | |
1073 | /* Add Control Packet filter (direct 0x025A) |
1074 | * Remove Control Packet filter (direct 0x025B) |
1075 | * uses the i40e_aqc_add_oveb_cloud, |
1076 | * and the generic direct completion structure |
1077 | */ |
1078 | struct i40e_aqc_add_remove_control_packet_filter { |
1079 | u8 mac[6]; |
1080 | __le16 etype; |
1081 | __le16 flags; |
1082 | #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 |
1083 | #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 |
1084 | #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 |
1085 | #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 |
1086 | __le16 seid; |
1087 | __le16 queue; |
1088 | u8 reserved[2]; |
1089 | }; |
1090 | |
1091 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); |
1092 | |
1093 | struct i40e_aqc_add_remove_control_packet_filter_completion { |
1094 | __le16 mac_etype_used; |
1095 | __le16 etype_used; |
1096 | __le16 mac_etype_free; |
1097 | __le16 etype_free; |
1098 | u8 reserved[8]; |
1099 | }; |
1100 | |
1101 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); |
1102 | |
1103 | /* Add Cloud filters (indirect 0x025C) |
1104 | * Remove Cloud filters (indirect 0x025D) |
1105 | * uses the i40e_aqc_add_remove_cloud_filters, |
1106 | * and the generic indirect completion structure |
1107 | */ |
1108 | struct i40e_aqc_add_remove_cloud_filters { |
1109 | u8 num_filters; |
1110 | u8 reserved; |
1111 | __le16 seid; |
1112 | u8 big_buffer_flag; |
1113 | #define I40E_AQC_ADD_CLOUD_CMD_BB 1 |
1114 | u8 reserved2[3]; |
1115 | __le32 addr_high; |
1116 | __le32 addr_low; |
1117 | }; |
1118 | |
1119 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); |
1120 | |
1121 | struct i40e_aqc_cloud_filters_element_data { |
1122 | u8 outer_mac[6]; |
1123 | u8 inner_mac[6]; |
1124 | __le16 inner_vlan; |
1125 | union { |
1126 | struct { |
1127 | u8 reserved[12]; |
1128 | u8 data[4]; |
1129 | } v4; |
1130 | struct { |
1131 | u8 data[16]; |
1132 | } v6; |
1133 | struct { |
1134 | __le16 data[8]; |
1135 | } raw_v6; |
1136 | } ipaddr; |
1137 | __le16 flags; |
1138 | /* 0x0000 reserved */ |
1139 | /* 0x0001 reserved */ |
1140 | /* 0x0002 reserved */ |
1141 | #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 |
1142 | #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 |
1143 | /* 0x0005 reserved */ |
1144 | #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 |
1145 | /* 0x0007 reserved */ |
1146 | /* 0x0008 reserved */ |
1147 | #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 |
1148 | #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A |
1149 | #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B |
1150 | #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C |
1151 | /* 0x000D reserved */ |
1152 | /* 0x000E reserved */ |
1153 | /* 0x000F reserved */ |
1154 | /* 0x0010 to 0x0017 is for custom filters */ |
1155 | #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ |
1156 | #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ |
1157 | #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ |
1158 | |
1159 | #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 |
1160 | #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 |
1161 | |
1162 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 |
1163 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 |
1164 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 |
1165 | |
1166 | |
1167 | __le32 tenant_id; |
1168 | u8 reserved[4]; |
1169 | __le16 queue_number; |
1170 | u8 reserved2[14]; |
1171 | /* response section */ |
1172 | u8 allocation_result; |
1173 | u8 response_reserved[7]; |
1174 | }; |
1175 | |
1176 | I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); |
1177 | |
1178 | /* i40e_aqc_cloud_filters_element_bb is used when |
1179 | * I40E_AQC_CLOUD_CMD_BB flag is set. |
1180 | */ |
1181 | struct i40e_aqc_cloud_filters_element_bb { |
1182 | struct i40e_aqc_cloud_filters_element_data element; |
1183 | u16 general_fields[32]; |
1184 | #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 |
1185 | }; |
1186 | |
1187 | I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); |
1188 | |
1189 | struct i40e_aqc_remove_cloud_filters_completion { |
1190 | __le16 perfect_ovlan_used; |
1191 | __le16 perfect_ovlan_free; |
1192 | __le16 vlan_used; |
1193 | __le16 vlan_free; |
1194 | __le32 addr_high; |
1195 | __le32 addr_low; |
1196 | }; |
1197 | |
1198 | I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); |
1199 | |
1200 | /* Replace filter Command 0x025F |
1201 | * uses the i40e_aqc_replace_cloud_filters, |
1202 | * and the generic indirect completion structure |
1203 | */ |
1204 | struct i40e_filter_data { |
1205 | u8 filter_type; |
1206 | u8 input[3]; |
1207 | }; |
1208 | |
1209 | I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); |
1210 | |
1211 | struct i40e_aqc_replace_cloud_filters_cmd { |
1212 | u8 valid_flags; |
1213 | u8 old_filter_type; |
1214 | u8 new_filter_type; |
1215 | u8 tr_bit; |
1216 | u8 reserved[4]; |
1217 | __le32 addr_high; |
1218 | __le32 addr_low; |
1219 | }; |
1220 | |
1221 | I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); |
1222 | |
1223 | struct i40e_aqc_replace_cloud_filters_cmd_buf { |
1224 | u8 data[32]; |
1225 | struct i40e_filter_data filters[8]; |
1226 | }; |
1227 | |
1228 | I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); |
1229 | |
1230 | /* Add Mirror Rule (indirect or direct 0x0260) |
1231 | * Delete Mirror Rule (indirect or direct 0x0261) |
1232 | * note: some rule types (4,5) do not use an external buffer. |
1233 | * take care to set the flags correctly. |
1234 | */ |
1235 | struct i40e_aqc_add_delete_mirror_rule { |
1236 | __le16 seid; |
1237 | __le16 rule_type; |
1238 | #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 |
1239 | #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ |
1240 | I40E_AQC_MIRROR_RULE_TYPE_SHIFT) |
1241 | #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 |
1242 | #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 |
1243 | #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 |
1244 | __le16 num_entries; |
1245 | __le16 destination; /* VSI for add, rule id for delete */ |
1246 | __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ |
1247 | __le32 addr_low; |
1248 | }; |
1249 | |
1250 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); |
1251 | |
1252 | struct i40e_aqc_add_delete_mirror_rule_completion { |
1253 | u8 reserved[2]; |
1254 | __le16 rule_id; /* only used on add */ |
1255 | __le16 mirror_rules_used; |
1256 | __le16 mirror_rules_free; |
1257 | __le32 addr_high; |
1258 | __le32 addr_low; |
1259 | }; |
1260 | |
1261 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); |
1262 | |
1263 | /* Dynamic Device Personalization */ |
1264 | struct i40e_aqc_write_personalization_profile { |
1265 | u8 flags; |
1266 | u8 reserved[3]; |
1267 | __le32 profile_track_id; |
1268 | __le32 addr_high; |
1269 | __le32 addr_low; |
1270 | }; |
1271 | |
1272 | I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); |
1273 | |
1274 | struct i40e_aqc_write_ddp_resp { |
1275 | __le32 error_offset; |
1276 | __le32 error_info; |
1277 | __le32 addr_high; |
1278 | __le32 addr_low; |
1279 | }; |
1280 | |
1281 | struct i40e_aqc_get_applied_profiles { |
1282 | u8 flags; |
1283 | u8 rsv[3]; |
1284 | __le32 reserved; |
1285 | __le32 addr_high; |
1286 | __le32 addr_low; |
1287 | }; |
1288 | |
1289 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); |
1290 | |
1291 | /* DCB 0x03xx*/ |
1292 | |
1293 | /* PFC Ignore (direct 0x0301) |
1294 | * the command and response use the same descriptor structure |
1295 | */ |
1296 | struct i40e_aqc_pfc_ignore { |
1297 | u8 tc_bitmap; |
1298 | u8 command_flags; /* unused on response */ |
1299 | u8 reserved[14]; |
1300 | }; |
1301 | |
1302 | I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); |
1303 | |
1304 | /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure |
1305 | * with no parameters |
1306 | */ |
1307 | |
1308 | /* TX scheduler 0x04xx */ |
1309 | |
1310 | /* Almost all the indirect commands use |
1311 | * this generic struct to pass the SEID in param0 |
1312 | */ |
1313 | struct i40e_aqc_tx_sched_ind { |
1314 | __le16 vsi_seid; |
1315 | u8 reserved[6]; |
1316 | __le32 addr_high; |
1317 | __le32 addr_low; |
1318 | }; |
1319 | |
1320 | I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); |
1321 | |
1322 | /* Several commands respond with a set of queue set handles */ |
1323 | struct i40e_aqc_qs_handles_resp { |
1324 | __le16 qs_handles[8]; |
1325 | }; |
1326 | |
1327 | /* Configure VSI BW limits (direct 0x0400) */ |
1328 | struct i40e_aqc_configure_vsi_bw_limit { |
1329 | __le16 vsi_seid; |
1330 | u8 reserved[2]; |
1331 | __le16 credit; |
1332 | u8 reserved1[2]; |
1333 | u8 max_credit; /* 0-3, limit = 2^max */ |
1334 | u8 reserved2[7]; |
1335 | }; |
1336 | |
1337 | I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); |
1338 | |
1339 | /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) |
1340 | * responds with i40e_aqc_qs_handles_resp |
1341 | */ |
1342 | struct i40e_aqc_configure_vsi_ets_sla_bw_data { |
1343 | u8 tc_valid_bits; |
1344 | u8 reserved[15]; |
1345 | __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ |
1346 | |
1347 | /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ |
1348 | __le16 tc_bw_max[2]; |
1349 | u8 reserved1[28]; |
1350 | }; |
1351 | |
1352 | I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); |
1353 | |
1354 | /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) |
1355 | * responds with i40e_aqc_qs_handles_resp |
1356 | */ |
1357 | struct i40e_aqc_configure_vsi_tc_bw_data { |
1358 | u8 tc_valid_bits; |
1359 | u8 reserved[3]; |
1360 | u8 tc_bw_credits[8]; |
1361 | u8 reserved1[4]; |
1362 | __le16 qs_handles[8]; |
1363 | }; |
1364 | |
1365 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); |
1366 | |
1367 | /* Query vsi bw configuration (indirect 0x0408) */ |
1368 | struct i40e_aqc_query_vsi_bw_config_resp { |
1369 | u8 tc_valid_bits; |
1370 | u8 tc_suspended_bits; |
1371 | u8 reserved[14]; |
1372 | __le16 qs_handles[8]; |
1373 | u8 reserved1[4]; |
1374 | __le16 port_bw_limit; |
1375 | u8 reserved2[2]; |
1376 | u8 max_bw; /* 0-3, limit = 2^max */ |
1377 | u8 reserved3[23]; |
1378 | }; |
1379 | |
1380 | I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); |
1381 | |
1382 | /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ |
1383 | struct i40e_aqc_query_vsi_ets_sla_config_resp { |
1384 | u8 tc_valid_bits; |
1385 | u8 reserved[3]; |
1386 | u8 share_credits[8]; |
1387 | __le16 credits[8]; |
1388 | |
1389 | /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ |
1390 | __le16 tc_bw_max[2]; |
1391 | }; |
1392 | |
1393 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); |
1394 | |
1395 | /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ |
1396 | struct i40e_aqc_configure_switching_comp_bw_limit { |
1397 | __le16 seid; |
1398 | u8 reserved[2]; |
1399 | __le16 credit; |
1400 | u8 reserved1[2]; |
1401 | u8 max_bw; /* 0-3, limit = 2^max */ |
1402 | u8 reserved2[7]; |
1403 | }; |
1404 | |
1405 | I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); |
1406 | |
1407 | /* Enable Physical Port ETS (indirect 0x0413) |
1408 | * Modify Physical Port ETS (indirect 0x0414) |
1409 | * Disable Physical Port ETS (indirect 0x0415) |
1410 | */ |
1411 | struct i40e_aqc_configure_switching_comp_ets_data { |
1412 | u8 reserved[4]; |
1413 | u8 tc_valid_bits; |
1414 | u8 seepage; |
1415 | u8 tc_strict_priority_flags; |
1416 | u8 reserved1[17]; |
1417 | u8 tc_bw_share_credits[8]; |
1418 | u8 reserved2[96]; |
1419 | }; |
1420 | |
1421 | I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); |
1422 | |
1423 | /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ |
1424 | struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { |
1425 | u8 tc_valid_bits; |
1426 | u8 reserved[15]; |
1427 | __le16 tc_bw_credit[8]; |
1428 | |
1429 | /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ |
1430 | __le16 tc_bw_max[2]; |
1431 | u8 reserved1[28]; |
1432 | }; |
1433 | |
1434 | I40E_CHECK_STRUCT_LEN(0x40, |
1435 | i40e_aqc_configure_switching_comp_ets_bw_limit_data); |
1436 | |
1437 | /* Configure Switching Component Bandwidth Allocation per Tc |
1438 | * (indirect 0x0417) |
1439 | */ |
1440 | struct i40e_aqc_configure_switching_comp_bw_config_data { |
1441 | u8 tc_valid_bits; |
1442 | u8 reserved[2]; |
1443 | u8 absolute_credits; /* bool */ |
1444 | u8 tc_bw_share_credits[8]; |
1445 | u8 reserved1[20]; |
1446 | }; |
1447 | |
1448 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); |
1449 | |
1450 | /* Query Switching Component Configuration (indirect 0x0418) */ |
1451 | struct i40e_aqc_query_switching_comp_ets_config_resp { |
1452 | u8 tc_valid_bits; |
1453 | u8 reserved[35]; |
1454 | __le16 port_bw_limit; |
1455 | u8 reserved1[2]; |
1456 | u8 tc_bw_max; /* 0-3, limit = 2^max */ |
1457 | u8 reserved2[23]; |
1458 | }; |
1459 | |
1460 | I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); |
1461 | |
1462 | /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ |
1463 | struct i40e_aqc_query_port_ets_config_resp { |
1464 | u8 reserved[4]; |
1465 | u8 tc_valid_bits; |
1466 | u8 reserved1; |
1467 | u8 tc_strict_priority_bits; |
1468 | u8 reserved2; |
1469 | u8 tc_bw_share_credits[8]; |
1470 | __le16 tc_bw_limits[8]; |
1471 | |
1472 | /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ |
1473 | __le16 tc_bw_max[2]; |
1474 | u8 reserved3[32]; |
1475 | }; |
1476 | |
1477 | I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); |
1478 | |
1479 | /* Query Switching Component Bandwidth Allocation per Traffic Type |
1480 | * (indirect 0x041A) |
1481 | */ |
1482 | struct i40e_aqc_query_switching_comp_bw_config_resp { |
1483 | u8 tc_valid_bits; |
1484 | u8 reserved[2]; |
1485 | u8 absolute_credits_enable; /* bool */ |
1486 | u8 tc_bw_share_credits[8]; |
1487 | __le16 tc_bw_limits[8]; |
1488 | |
1489 | /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ |
1490 | __le16 tc_bw_max[2]; |
1491 | }; |
1492 | |
1493 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); |
1494 | |
1495 | /* Suspend/resume port TX traffic |
1496 | * (direct 0x041B and 0x041C) uses the generic SEID struct |
1497 | */ |
1498 | |
1499 | /* Configure partition BW |
1500 | * (indirect 0x041D) |
1501 | */ |
1502 | struct i40e_aqc_configure_partition_bw_data { |
1503 | __le16 pf_valid_bits; |
1504 | u8 min_bw[16]; /* guaranteed bandwidth */ |
1505 | u8 max_bw[16]; /* bandwidth limit */ |
1506 | }; |
1507 | |
1508 | I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); |
1509 | |
1510 | /* Get and set the active HMC resource profile and status. |
1511 | * (direct 0x0500) and (direct 0x0501) |
1512 | */ |
1513 | struct i40e_aq_get_set_hmc_resource_profile { |
1514 | u8 pm_profile; |
1515 | u8 pe_vf_enabled; |
1516 | u8 reserved[14]; |
1517 | }; |
1518 | |
1519 | I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); |
1520 | |
1521 | enum i40e_aq_hmc_profile { |
1522 | /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ |
1523 | I40E_HMC_PROFILE_DEFAULT = 1, |
1524 | I40E_HMC_PROFILE_FAVOR_VF = 2, |
1525 | I40E_HMC_PROFILE_EQUAL = 3, |
1526 | }; |
1527 | |
1528 | /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ |
1529 | |
1530 | /* set in param0 for get phy abilities to report qualified modules */ |
1531 | #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 |
1532 | #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 |
1533 | |
1534 | enum i40e_aq_phy_type { |
1535 | I40E_PHY_TYPE_SGMII = 0x0, |
1536 | I40E_PHY_TYPE_1000BASE_KX = 0x1, |
1537 | I40E_PHY_TYPE_10GBASE_KX4 = 0x2, |
1538 | I40E_PHY_TYPE_10GBASE_KR = 0x3, |
1539 | I40E_PHY_TYPE_40GBASE_KR4 = 0x4, |
1540 | I40E_PHY_TYPE_XAUI = 0x5, |
1541 | I40E_PHY_TYPE_XFI = 0x6, |
1542 | I40E_PHY_TYPE_SFI = 0x7, |
1543 | I40E_PHY_TYPE_XLAUI = 0x8, |
1544 | I40E_PHY_TYPE_XLPPI = 0x9, |
1545 | I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, |
1546 | I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, |
1547 | I40E_PHY_TYPE_10GBASE_AOC = 0xC, |
1548 | I40E_PHY_TYPE_40GBASE_AOC = 0xD, |
1549 | I40E_PHY_TYPE_UNRECOGNIZED = 0xE, |
1550 | I40E_PHY_TYPE_UNSUPPORTED = 0xF, |
1551 | I40E_PHY_TYPE_100BASE_TX = 0x11, |
1552 | I40E_PHY_TYPE_1000BASE_T = 0x12, |
1553 | I40E_PHY_TYPE_10GBASE_T = 0x13, |
1554 | I40E_PHY_TYPE_10GBASE_SR = 0x14, |
1555 | I40E_PHY_TYPE_10GBASE_LR = 0x15, |
1556 | I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, |
1557 | I40E_PHY_TYPE_10GBASE_CR1 = 0x17, |
1558 | I40E_PHY_TYPE_40GBASE_CR4 = 0x18, |
1559 | I40E_PHY_TYPE_40GBASE_SR4 = 0x19, |
1560 | I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, |
1561 | I40E_PHY_TYPE_1000BASE_SX = 0x1B, |
1562 | I40E_PHY_TYPE_1000BASE_LX = 0x1C, |
1563 | I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, |
1564 | I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, |
1565 | I40E_PHY_TYPE_25GBASE_KR = 0x1F, |
1566 | I40E_PHY_TYPE_25GBASE_CR = 0x20, |
1567 | I40E_PHY_TYPE_25GBASE_SR = 0x21, |
1568 | I40E_PHY_TYPE_25GBASE_LR = 0x22, |
1569 | I40E_PHY_TYPE_25GBASE_AOC = 0x23, |
1570 | I40E_PHY_TYPE_25GBASE_ACC = 0x24, |
1571 | I40E_PHY_TYPE_2_5GBASE_T = 0x26, |
1572 | I40E_PHY_TYPE_5GBASE_T = 0x27, |
1573 | I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30, |
1574 | I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31, |
1575 | I40E_PHY_TYPE_MAX, |
1576 | I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, |
1577 | I40E_PHY_TYPE_EMPTY = 0xFE, |
1578 | I40E_PHY_TYPE_DEFAULT = 0xFF, |
1579 | }; |
1580 | |
1581 | #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ |
1582 | BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ |
1583 | BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ |
1584 | BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ |
1585 | BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ |
1586 | BIT_ULL(I40E_PHY_TYPE_XAUI) | \ |
1587 | BIT_ULL(I40E_PHY_TYPE_XFI) | \ |
1588 | BIT_ULL(I40E_PHY_TYPE_SFI) | \ |
1589 | BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ |
1590 | BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ |
1591 | BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ |
1592 | BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ |
1593 | BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ |
1594 | BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ |
1595 | BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ |
1596 | BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ |
1597 | BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ |
1598 | BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ |
1599 | BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ |
1600 | BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ |
1601 | BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ |
1602 | BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ |
1603 | BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ |
1604 | BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ |
1605 | BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ |
1606 | BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ |
1607 | BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ |
1608 | BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ |
1609 | BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ |
1610 | BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ |
1611 | BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ |
1612 | BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ |
1613 | BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ |
1614 | BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ |
1615 | BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ |
1616 | BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ |
1617 | BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ |
1618 | BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) |
1619 | |
1620 | #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 |
1621 | #define I40E_LINK_SPEED_100MB_SHIFT 0x1 |
1622 | #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 |
1623 | #define I40E_LINK_SPEED_10GB_SHIFT 0x3 |
1624 | #define I40E_LINK_SPEED_40GB_SHIFT 0x4 |
1625 | #define I40E_LINK_SPEED_20GB_SHIFT 0x5 |
1626 | #define I40E_LINK_SPEED_25GB_SHIFT 0x6 |
1627 | #define I40E_LINK_SPEED_5GB_SHIFT 0x7 |
1628 | |
1629 | enum i40e_aq_link_speed { |
1630 | I40E_LINK_SPEED_UNKNOWN = 0, |
1631 | I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), |
1632 | I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), |
1633 | I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), |
1634 | I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), |
1635 | I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), |
1636 | I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), |
1637 | I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), |
1638 | I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), |
1639 | }; |
1640 | |
1641 | struct i40e_aqc_module_desc { |
1642 | u8 oui[3]; |
1643 | u8 reserved1; |
1644 | u8 part_number[16]; |
1645 | u8 revision[4]; |
1646 | u8 reserved2[8]; |
1647 | }; |
1648 | |
1649 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); |
1650 | |
1651 | struct i40e_aq_get_phy_abilities_resp { |
1652 | __le32 phy_type; /* bitmap using the above enum for offsets */ |
1653 | u8 link_speed; /* bitmap using the above enum bit patterns */ |
1654 | u8 abilities; |
1655 | #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 |
1656 | #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 |
1657 | __le16 eee_capability; |
1658 | __le32 eeer_val; |
1659 | u8 d3_lpan; |
1660 | u8 phy_type_ext; |
1661 | #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 |
1662 | #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 |
1663 | #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 |
1664 | #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 |
1665 | u8 fec_cfg_curr_mod_ext_info; |
1666 | #define I40E_AQ_REQUEST_FEC_KR 0x04 |
1667 | #define I40E_AQ_REQUEST_FEC_RS 0x08 |
1668 | #define I40E_AQ_ENABLE_FEC_AUTO 0x10 |
1669 | |
1670 | u8 ext_comp_code; |
1671 | u8 phy_id[4]; |
1672 | u8 module_type[3]; |
1673 | u8 qualified_module_count; |
1674 | #define I40E_AQ_PHY_MAX_QMS 16 |
1675 | struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; |
1676 | }; |
1677 | |
1678 | I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); |
1679 | |
1680 | /* Set PHY Config (direct 0x0601) */ |
1681 | struct i40e_aq_set_phy_config { /* same bits as above in all */ |
1682 | __le32 phy_type; |
1683 | u8 link_speed; |
1684 | u8 abilities; |
1685 | /* bits 0-2 use the values from get_phy_abilities_resp */ |
1686 | #define I40E_AQ_PHY_ENABLE_LINK 0x08 |
1687 | #define I40E_AQ_PHY_ENABLE_AN 0x10 |
1688 | #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 |
1689 | __le16 eee_capability; |
1690 | __le32 eeer; |
1691 | u8 low_power_ctrl; |
1692 | u8 phy_type_ext; |
1693 | #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 |
1694 | #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 |
1695 | #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 |
1696 | #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 |
1697 | u8 fec_config; |
1698 | #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) |
1699 | #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) |
1700 | #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) |
1701 | #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) |
1702 | #define I40E_AQ_SET_FEC_AUTO BIT(4) |
1703 | #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 |
1704 | #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) |
1705 | u8 reserved; |
1706 | }; |
1707 | |
1708 | I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); |
1709 | |
1710 | /* Set MAC Config command data structure (direct 0x0603) */ |
1711 | struct i40e_aq_set_mac_config { |
1712 | __le16 max_frame_size; |
1713 | u8 params; |
1714 | u8 tx_timer_priority; /* bitmap */ |
1715 | __le16 tx_timer_value; |
1716 | __le16 fc_refresh_threshold; |
1717 | u8 reserved[8]; |
1718 | }; |
1719 | |
1720 | I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); |
1721 | |
1722 | /* Restart Auto-Negotiation (direct 0x605) */ |
1723 | struct i40e_aqc_set_link_restart_an { |
1724 | u8 command; |
1725 | #define I40E_AQ_PHY_RESTART_AN 0x02 |
1726 | #define I40E_AQ_PHY_LINK_ENABLE 0x04 |
1727 | u8 reserved[15]; |
1728 | }; |
1729 | |
1730 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); |
1731 | |
1732 | /* Get Link Status cmd & response data structure (direct 0x0607) */ |
1733 | struct i40e_aqc_get_link_status { |
1734 | __le16 command_flags; /* only field set on command */ |
1735 | #define I40E_AQ_LSE_DISABLE 0x2 |
1736 | #define I40E_AQ_LSE_ENABLE 0x3 |
1737 | /* only response uses this flag */ |
1738 | #define I40E_AQ_LSE_IS_ENABLED 0x1 |
1739 | u8 phy_type; /* i40e_aq_phy_type */ |
1740 | u8 link_speed; /* i40e_aq_link_speed */ |
1741 | u8 link_info; |
1742 | #define I40E_AQ_LINK_UP 0x01 /* obsolete */ |
1743 | #define I40E_AQ_MEDIA_AVAILABLE 0x40 |
1744 | u8 an_info; |
1745 | #define I40E_AQ_AN_COMPLETED 0x01 |
1746 | #define I40E_AQ_LINK_PAUSE_TX 0x20 |
1747 | #define I40E_AQ_LINK_PAUSE_RX 0x40 |
1748 | #define I40E_AQ_QUALIFIED_MODULE 0x80 |
1749 | u8 ext_info; |
1750 | u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ |
1751 | /* Since firmware API 1.7 loopback field keeps power class info as well */ |
1752 | #define I40E_AQ_LOOPBACK_MASK 0x07 |
1753 | __le16 max_frame_size; |
1754 | u8 config; |
1755 | #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 |
1756 | #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 |
1757 | #define I40E_AQ_CONFIG_CRC_ENA 0x04 |
1758 | #define I40E_AQ_CONFIG_PACING_MASK 0x78 |
1759 | union { |
1760 | struct { |
1761 | u8 power_desc; |
1762 | u8 reserved[4]; |
1763 | }; |
1764 | struct { |
1765 | u8 link_type[4]; |
1766 | u8 link_type_ext; |
1767 | }; |
1768 | }; |
1769 | }; |
1770 | |
1771 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); |
1772 | |
1773 | /* Set event mask command (direct 0x613) */ |
1774 | struct i40e_aqc_set_phy_int_mask { |
1775 | u8 reserved[8]; |
1776 | __le16 event_mask; |
1777 | #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 |
1778 | #define I40E_AQ_EVENT_MEDIA_NA 0x0004 |
1779 | #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 |
1780 | u8 reserved1[6]; |
1781 | }; |
1782 | |
1783 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); |
1784 | |
1785 | /* Get Local AN advt register (direct 0x0614) |
1786 | * Set Local AN advt register (direct 0x0615) |
1787 | * Get Link Partner AN advt register (direct 0x0616) |
1788 | */ |
1789 | struct i40e_aqc_an_advt_reg { |
1790 | __le32 local_an_reg0; |
1791 | __le16 local_an_reg1; |
1792 | u8 reserved[10]; |
1793 | }; |
1794 | |
1795 | I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); |
1796 | |
1797 | /* Set Loopback mode (0x0618) */ |
1798 | struct i40e_aqc_set_lb_mode { |
1799 | __le16 lb_mode; |
1800 | #define I40E_LEGACY_LOOPBACK_NVM_VER 0x6000 |
1801 | #define I40E_AQ_LB_MAC_LOCAL 0x01 |
1802 | #define I40E_AQ_LB_PHY_LOCAL 0x05 |
1803 | #define I40E_AQ_LB_PHY_REMOTE 0x06 |
1804 | #define I40E_AQ_LB_MAC_LOCAL_LEGACY 0x04 |
1805 | u8 reserved[14]; |
1806 | }; |
1807 | |
1808 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); |
1809 | |
1810 | /* Set PHY Debug command (0x0622) */ |
1811 | struct i40e_aqc_set_phy_debug { |
1812 | u8 command_flags; |
1813 | /* Disable link manageability on a single port */ |
1814 | #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 |
1815 | /* Disable link manageability on all ports */ |
1816 | #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 |
1817 | u8 reserved[15]; |
1818 | }; |
1819 | |
1820 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); |
1821 | |
1822 | enum i40e_aq_phy_reg_type { |
1823 | I40E_AQC_PHY_REG_INTERNAL = 0x1, |
1824 | I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, |
1825 | I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 |
1826 | }; |
1827 | |
1828 | /* Run PHY Activity (0x0626) */ |
1829 | struct i40e_aqc_run_phy_activity { |
1830 | __le16 activity_id; |
1831 | u8 flags; |
1832 | u8 reserved1; |
1833 | __le32 control; |
1834 | __le32 data; |
1835 | u8 reserved2[4]; |
1836 | }; |
1837 | |
1838 | I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); |
1839 | |
1840 | /* Set PHY Register command (0x0628) */ |
1841 | /* Get PHY Register command (0x0629) */ |
1842 | struct i40e_aqc_phy_register_access { |
1843 | u8 phy_interface; |
1844 | #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 |
1845 | #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 |
1846 | u8 dev_address; |
1847 | u8 cmd_flags; |
1848 | #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01 |
1849 | #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02 |
1850 | #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2 |
1851 | #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \ |
1852 | I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) |
1853 | u8 reserved1; |
1854 | __le32 reg_address; |
1855 | __le32 reg_value; |
1856 | u8 reserved2[4]; |
1857 | }; |
1858 | |
1859 | I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); |
1860 | |
1861 | /* NVM Read command (indirect 0x0701) |
1862 | * NVM Erase commands (direct 0x0702) |
1863 | * NVM Update commands (indirect 0x0703) |
1864 | */ |
1865 | struct i40e_aqc_nvm_update { |
1866 | u8 command_flags; |
1867 | #define I40E_AQ_NVM_LAST_CMD 0x01 |
1868 | #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 |
1869 | #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 |
1870 | #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 |
1871 | #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 |
1872 | #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 |
1873 | u8 module_pointer; |
1874 | __le16 length; |
1875 | __le32 offset; |
1876 | __le32 addr_high; |
1877 | __le32 addr_low; |
1878 | }; |
1879 | |
1880 | I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); |
1881 | |
1882 | /* NVM Config Read (indirect 0x0704) */ |
1883 | struct i40e_aqc_nvm_config_read { |
1884 | __le16 cmd_flags; |
1885 | __le16 element_count; |
1886 | __le16 element_id; /* Feature/field ID */ |
1887 | __le16 element_id_msw; /* MSWord of field ID */ |
1888 | __le32 address_high; |
1889 | __le32 address_low; |
1890 | }; |
1891 | |
1892 | I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); |
1893 | |
1894 | /* NVM Config Write (indirect 0x0705) */ |
1895 | struct i40e_aqc_nvm_config_write { |
1896 | __le16 cmd_flags; |
1897 | __le16 element_count; |
1898 | u8 reserved[4]; |
1899 | __le32 address_high; |
1900 | __le32 address_low; |
1901 | }; |
1902 | |
1903 | I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); |
1904 | |
1905 | /* Used for 0x0704 as well as for 0x0705 commands */ |
1906 | struct i40e_aqc_nvm_config_data_feature { |
1907 | __le16 feature_id; |
1908 | __le16 feature_options; |
1909 | __le16 feature_selection; |
1910 | }; |
1911 | |
1912 | I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); |
1913 | |
1914 | struct i40e_aqc_nvm_config_data_immediate_field { |
1915 | __le32 field_id; |
1916 | __le32 field_value; |
1917 | __le16 field_options; |
1918 | __le16 reserved; |
1919 | }; |
1920 | |
1921 | I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); |
1922 | |
1923 | /* OEM Post Update (indirect 0x0720) |
1924 | * no command data struct used |
1925 | */ |
1926 | struct i40e_aqc_nvm_oem_post_update { |
1927 | u8 sel_data; |
1928 | u8 reserved[7]; |
1929 | }; |
1930 | |
1931 | I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); |
1932 | |
1933 | struct i40e_aqc_nvm_oem_post_update_buffer { |
1934 | u8 str_len; |
1935 | u8 dev_addr; |
1936 | __le16 eeprom_addr; |
1937 | u8 data[36]; |
1938 | }; |
1939 | |
1940 | I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); |
1941 | |
1942 | /* Thermal Sensor (indirect 0x0721) |
1943 | * read or set thermal sensor configs and values |
1944 | * takes a sensor and command specific data buffer, not detailed here |
1945 | */ |
1946 | struct i40e_aqc_thermal_sensor { |
1947 | u8 sensor_action; |
1948 | u8 reserved[7]; |
1949 | __le32 addr_high; |
1950 | __le32 addr_low; |
1951 | }; |
1952 | |
1953 | I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); |
1954 | |
1955 | /* Send to PF command (indirect 0x0801) id is only used by PF |
1956 | * Send to VF command (indirect 0x0802) id is only used by PF |
1957 | * Send to Peer PF command (indirect 0x0803) |
1958 | */ |
1959 | struct i40e_aqc_pf_vf_message { |
1960 | __le32 id; |
1961 | u8 reserved[4]; |
1962 | __le32 addr_high; |
1963 | __le32 addr_low; |
1964 | }; |
1965 | |
1966 | I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); |
1967 | |
1968 | /* Alternate structure */ |
1969 | |
1970 | /* Direct write (direct 0x0900) |
1971 | * Direct read (direct 0x0902) |
1972 | */ |
1973 | struct i40e_aqc_alternate_write { |
1974 | __le32 address0; |
1975 | __le32 data0; |
1976 | __le32 address1; |
1977 | __le32 data1; |
1978 | }; |
1979 | |
1980 | I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); |
1981 | |
1982 | /* Indirect write (indirect 0x0901) |
1983 | * Indirect read (indirect 0x0903) |
1984 | */ |
1985 | |
1986 | struct i40e_aqc_alternate_ind_write { |
1987 | __le32 address; |
1988 | __le32 length; |
1989 | __le32 addr_high; |
1990 | __le32 addr_low; |
1991 | }; |
1992 | |
1993 | I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); |
1994 | |
1995 | /* Done alternate write (direct 0x0904) |
1996 | * uses i40e_aq_desc |
1997 | */ |
1998 | struct i40e_aqc_alternate_write_done { |
1999 | __le16 cmd_flags; |
2000 | u8 reserved[14]; |
2001 | }; |
2002 | |
2003 | I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); |
2004 | |
2005 | /* Set OEM mode (direct 0x0905) */ |
2006 | struct i40e_aqc_alternate_set_mode { |
2007 | __le32 mode; |
2008 | u8 reserved[12]; |
2009 | }; |
2010 | |
2011 | I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); |
2012 | |
2013 | /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ |
2014 | |
2015 | /* async events 0x10xx */ |
2016 | |
2017 | /* Lan Queue Overflow Event (direct, 0x1001) */ |
2018 | struct i40e_aqc_lan_overflow { |
2019 | __le32 prtdcb_rupto; |
2020 | __le32 otx_ctl; |
2021 | u8 reserved[8]; |
2022 | }; |
2023 | |
2024 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); |
2025 | |
2026 | /* Get LLDP MIB (indirect 0x0A00) */ |
2027 | struct i40e_aqc_lldp_get_mib { |
2028 | u8 type; |
2029 | u8 reserved1; |
2030 | #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 |
2031 | #define I40E_AQ_LLDP_MIB_LOCAL 0x0 |
2032 | #define I40E_AQ_LLDP_MIB_REMOTE 0x1 |
2033 | #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC |
2034 | #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 |
2035 | #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 |
2036 | /* TX pause flags use I40E_AQ_LINK_TX_* above */ |
2037 | __le16 local_len; |
2038 | __le16 remote_len; |
2039 | u8 reserved2[2]; |
2040 | __le32 addr_high; |
2041 | __le32 addr_low; |
2042 | }; |
2043 | |
2044 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); |
2045 | |
2046 | /* Configure LLDP MIB Change Event (direct 0x0A01) |
2047 | * also used for the event (with type in the command field) |
2048 | */ |
2049 | struct i40e_aqc_lldp_update_mib { |
2050 | u8 command; |
2051 | #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 |
2052 | u8 reserved[7]; |
2053 | __le32 addr_high; |
2054 | __le32 addr_low; |
2055 | }; |
2056 | |
2057 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); |
2058 | |
2059 | /* Add LLDP TLV (indirect 0x0A02) |
2060 | * Delete LLDP TLV (indirect 0x0A04) |
2061 | */ |
2062 | struct i40e_aqc_lldp_add_tlv { |
2063 | u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ |
2064 | u8 reserved1[1]; |
2065 | __le16 len; |
2066 | u8 reserved2[4]; |
2067 | __le32 addr_high; |
2068 | __le32 addr_low; |
2069 | }; |
2070 | |
2071 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); |
2072 | |
2073 | /* Update LLDP TLV (indirect 0x0A03) */ |
2074 | struct i40e_aqc_lldp_update_tlv { |
2075 | u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ |
2076 | u8 reserved; |
2077 | __le16 old_len; |
2078 | __le16 new_offset; |
2079 | __le16 new_len; |
2080 | __le32 addr_high; |
2081 | __le32 addr_low; |
2082 | }; |
2083 | |
2084 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); |
2085 | |
2086 | /* Stop LLDP (direct 0x0A05) */ |
2087 | struct i40e_aqc_lldp_stop { |
2088 | u8 command; |
2089 | #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 |
2090 | #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 |
2091 | u8 reserved[15]; |
2092 | }; |
2093 | |
2094 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); |
2095 | |
2096 | /* Start LLDP (direct 0x0A06) */ |
2097 | struct i40e_aqc_lldp_start { |
2098 | u8 command; |
2099 | #define I40E_AQ_LLDP_AGENT_START 0x1 |
2100 | #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2 |
2101 | u8 reserved[15]; |
2102 | }; |
2103 | |
2104 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); |
2105 | |
2106 | /* Set DCB (direct 0x0303) */ |
2107 | struct i40e_aqc_set_dcb_parameters { |
2108 | u8 command; |
2109 | #define I40E_AQ_DCB_SET_AGENT 0x1 |
2110 | #define I40E_DCB_VALID 0x1 |
2111 | u8 valid_flags; |
2112 | u8 reserved[14]; |
2113 | }; |
2114 | |
2115 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); |
2116 | |
2117 | /* Get CEE DCBX Oper Config (0x0A07) |
2118 | * uses the generic descriptor struct |
2119 | * returns below as indirect response |
2120 | */ |
2121 | |
2122 | #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 |
2123 | #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) |
2124 | #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 |
2125 | #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) |
2126 | #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 |
2127 | #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) |
2128 | |
2129 | #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 |
2130 | #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) |
2131 | #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 |
2132 | #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) |
2133 | #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 |
2134 | #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) |
2135 | #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 |
2136 | #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) |
2137 | #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB |
2138 | #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) |
2139 | #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 |
2140 | #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) |
2141 | |
2142 | /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with |
2143 | * word boundary layout issues, which the Linux compilers silently deal |
2144 | * with by adding padding, making the actual struct larger than designed. |
2145 | * However, the FW compiler for the NIC is less lenient and complains |
2146 | * about the struct. Hence, the struct defined here has an extra byte in |
2147 | * fields reserved3 and reserved4 to directly acknowledge that padding, |
2148 | * and the new length is used in the length check macro. |
2149 | */ |
2150 | struct i40e_aqc_get_cee_dcb_cfg_v1_resp { |
2151 | u8 reserved1; |
2152 | u8 oper_num_tc; |
2153 | u8 oper_prio_tc[4]; |
2154 | u8 reserved2; |
2155 | u8 oper_tc_bw[8]; |
2156 | u8 oper_pfc_en; |
2157 | u8 reserved3[2]; |
2158 | __le16 oper_app_prio; |
2159 | u8 reserved4[2]; |
2160 | __le16 tlv_status; |
2161 | }; |
2162 | |
2163 | I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); |
2164 | |
2165 | struct i40e_aqc_get_cee_dcb_cfg_resp { |
2166 | u8 oper_num_tc; |
2167 | u8 oper_prio_tc[4]; |
2168 | u8 oper_tc_bw[8]; |
2169 | u8 oper_pfc_en; |
2170 | __le16 oper_app_prio; |
2171 | #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 |
2172 | #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) |
2173 | #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 |
2174 | #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) |
2175 | #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 |
2176 | #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) |
2177 | #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) |
2178 | __le32 tlv_status; |
2179 | #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 |
2180 | #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) |
2181 | #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 |
2182 | #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) |
2183 | #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 |
2184 | #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) |
2185 | u8 reserved[12]; |
2186 | }; |
2187 | |
2188 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); |
2189 | |
2190 | /* Set Local LLDP MIB (indirect 0x0A08) |
2191 | * Used to replace the local MIB of a given LLDP agent. e.g. DCBx |
2192 | */ |
2193 | struct i40e_aqc_lldp_set_local_mib { |
2194 | #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 |
2195 | #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ |
2196 | SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) |
2197 | #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 |
2198 | #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) |
2199 | #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ |
2200 | SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) |
2201 | #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 |
2202 | u8 type; |
2203 | u8 reserved0; |
2204 | __le16 length; |
2205 | u8 reserved1[4]; |
2206 | __le32 address_high; |
2207 | __le32 address_low; |
2208 | }; |
2209 | |
2210 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); |
2211 | |
2212 | /* Stop/Start LLDP Agent (direct 0x0A09) |
2213 | * Used for stopping/starting specific LLDP agent. e.g. DCBx |
2214 | */ |
2215 | struct i40e_aqc_lldp_stop_start_specific_agent { |
2216 | u8 command; |
2217 | u8 reserved[15]; |
2218 | }; |
2219 | |
2220 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); |
2221 | |
2222 | /* Restore LLDP Agent factory settings (direct 0x0A0A) */ |
2223 | struct i40e_aqc_lldp_restore { |
2224 | u8 command; |
2225 | #define I40E_AQ_LLDP_AGENT_RESTORE 0x1 |
2226 | u8 reserved[15]; |
2227 | }; |
2228 | |
2229 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore); |
2230 | |
2231 | /* Add Udp Tunnel command and completion (direct 0x0B00) */ |
2232 | struct i40e_aqc_add_udp_tunnel { |
2233 | __le16 udp_port; |
2234 | u8 reserved0[3]; |
2235 | u8 protocol_type; |
2236 | #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 |
2237 | #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 |
2238 | u8 reserved1[10]; |
2239 | }; |
2240 | |
2241 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); |
2242 | |
2243 | struct i40e_aqc_add_udp_tunnel_completion { |
2244 | __le16 udp_port; |
2245 | u8 filter_entry_index; |
2246 | u8 multiple_pfs; |
2247 | u8 total_filters; |
2248 | u8 reserved[11]; |
2249 | }; |
2250 | |
2251 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); |
2252 | |
2253 | /* remove UDP Tunnel command (0x0B01) */ |
2254 | struct i40e_aqc_remove_udp_tunnel { |
2255 | u8 reserved[2]; |
2256 | u8 index; /* 0 to 15 */ |
2257 | u8 reserved2[13]; |
2258 | }; |
2259 | |
2260 | I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); |
2261 | |
2262 | struct i40e_aqc_del_udp_tunnel_completion { |
2263 | __le16 udp_port; |
2264 | u8 index; /* 0 to 15 */ |
2265 | u8 multiple_pfs; |
2266 | u8 total_filters_used; |
2267 | u8 reserved1[11]; |
2268 | }; |
2269 | |
2270 | I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); |
2271 | |
2272 | struct { |
2273 | #define BIT(15) |
2274 | #define 0 |
2275 | #define (0x3FF << \ |
2276 | I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) |
2277 | __le16 ; |
2278 | u8 [6]; |
2279 | __le32 ; |
2280 | __le32 ; |
2281 | }; |
2282 | |
2283 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); |
2284 | |
2285 | struct { |
2286 | u8 standard_rss_key[0x28]; |
2287 | u8 [0xc]; |
2288 | }; |
2289 | |
2290 | I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); |
2291 | |
2292 | struct { |
2293 | #define BIT(15) |
2294 | #define 0 |
2295 | #define (0x3FF << \ |
2296 | I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) |
2297 | __le16 ; |
2298 | #define 0 |
2299 | #define BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) |
2300 | |
2301 | #define 0 |
2302 | #define 1 |
2303 | __le16 ; |
2304 | u8 [4]; |
2305 | __le32 ; |
2306 | __le32 ; |
2307 | }; |
2308 | |
2309 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); |
2310 | |
2311 | /* tunnel key structure 0x0B10 */ |
2312 | |
2313 | struct i40e_aqc_tunnel_key_structure { |
2314 | u8 key1_off; |
2315 | u8 key2_off; |
2316 | u8 key1_len; /* 0 to 15 */ |
2317 | u8 key2_len; /* 0 to 15 */ |
2318 | u8 flags; |
2319 | u8 network_key_index; |
2320 | u8 reserved[10]; |
2321 | }; |
2322 | |
2323 | I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); |
2324 | |
2325 | /* OEM mode commands (direct 0xFE0x) */ |
2326 | struct i40e_aqc_oem_param_change { |
2327 | __le32 param_type; |
2328 | __le32 param_value1; |
2329 | __le16 param_value2; |
2330 | u8 reserved[6]; |
2331 | }; |
2332 | |
2333 | I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); |
2334 | |
2335 | struct i40e_aqc_oem_state_change { |
2336 | __le32 state; |
2337 | u8 reserved[12]; |
2338 | }; |
2339 | |
2340 | I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); |
2341 | |
2342 | /* Initialize OCSD (0xFE02, direct) */ |
2343 | struct i40e_aqc_opc_oem_ocsd_initialize { |
2344 | u8 type_status; |
2345 | u8 reserved1[3]; |
2346 | __le32 ocsd_memory_block_addr_high; |
2347 | __le32 ocsd_memory_block_addr_low; |
2348 | __le32 requested_update_interval; |
2349 | }; |
2350 | |
2351 | I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); |
2352 | |
2353 | /* Initialize OCBB (0xFE03, direct) */ |
2354 | struct i40e_aqc_opc_oem_ocbb_initialize { |
2355 | u8 type_status; |
2356 | u8 reserved1[3]; |
2357 | __le32 ocbb_memory_block_addr_high; |
2358 | __le32 ocbb_memory_block_addr_low; |
2359 | u8 reserved2[4]; |
2360 | }; |
2361 | |
2362 | I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); |
2363 | |
2364 | /* debug commands */ |
2365 | |
2366 | /* get device id (0xFF00) uses the generic structure */ |
2367 | |
2368 | /* set test more (0xFF01, internal) */ |
2369 | |
2370 | struct i40e_acq_set_test_mode { |
2371 | u8 mode; |
2372 | u8 reserved[3]; |
2373 | u8 command; |
2374 | u8 reserved2[3]; |
2375 | __le32 address_high; |
2376 | __le32 address_low; |
2377 | }; |
2378 | |
2379 | I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); |
2380 | |
2381 | /* Debug Read Register command (0xFF03) |
2382 | * Debug Write Register command (0xFF04) |
2383 | */ |
2384 | struct i40e_aqc_debug_reg_read_write { |
2385 | __le32 reserved; |
2386 | __le32 address; |
2387 | __le32 value_high; |
2388 | __le32 value_low; |
2389 | }; |
2390 | |
2391 | I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); |
2392 | |
2393 | /* Scatter/gather Reg Read (indirect 0xFF05) |
2394 | * Scatter/gather Reg Write (indirect 0xFF06) |
2395 | */ |
2396 | |
2397 | /* i40e_aq_desc is used for the command */ |
2398 | struct i40e_aqc_debug_reg_sg_element_data { |
2399 | __le32 address; |
2400 | __le32 value; |
2401 | }; |
2402 | |
2403 | /* Debug Modify register (direct 0xFF07) */ |
2404 | struct i40e_aqc_debug_modify_reg { |
2405 | __le32 address; |
2406 | __le32 value; |
2407 | __le32 clear_mask; |
2408 | __le32 set_mask; |
2409 | }; |
2410 | |
2411 | I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); |
2412 | |
2413 | /* dump internal data (0xFF08, indirect) */ |
2414 | struct i40e_aqc_debug_dump_internals { |
2415 | u8 cluster_id; |
2416 | u8 table_id; |
2417 | __le16 data_size; |
2418 | __le32 idx; |
2419 | __le32 address_high; |
2420 | __le32 address_low; |
2421 | }; |
2422 | |
2423 | I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); |
2424 | |
2425 | struct i40e_aqc_debug_modify_internals { |
2426 | u8 cluster_id; |
2427 | u8 cluster_specific_params[7]; |
2428 | __le32 address_high; |
2429 | __le32 address_low; |
2430 | }; |
2431 | |
2432 | I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); |
2433 | |
2434 | #endif /* _I40E_ADMINQ_CMD_H_ */ |
2435 | |