1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright(c) 2009 - 2018 Intel Corporation. */ |
3 | |
4 | #ifndef _E1000_REGS_H_ |
5 | #define _E1000_REGS_H_ |
6 | |
7 | #define E1000_CTRL 0x00000 /* Device Control - RW */ |
8 | #define E1000_STATUS 0x00008 /* Device Status - RO */ |
9 | #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ |
10 | #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ |
11 | #define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) |
12 | #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ |
13 | #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ |
14 | #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ |
15 | #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ |
16 | #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ |
17 | #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ |
18 | #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ |
19 | |
20 | /* Convenience macros |
21 | * |
22 | * Note: "_n" is the queue number of the register to be written to. |
23 | * |
24 | * Example usage: |
25 | * E1000_RDBAL_REG(current_rx_queue) |
26 | */ |
27 | #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ |
28 | (0x0C000 + ((_n) * 0x40))) |
29 | #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ |
30 | (0x0C004 + ((_n) * 0x40))) |
31 | #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ |
32 | (0x0C008 + ((_n) * 0x40))) |
33 | #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ |
34 | (0x0C00C + ((_n) * 0x40))) |
35 | #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ |
36 | (0x0C010 + ((_n) * 0x40))) |
37 | #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ |
38 | (0x0C018 + ((_n) * 0x40))) |
39 | #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ |
40 | (0x0C028 + ((_n) * 0x40))) |
41 | #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ |
42 | (0x0E000 + ((_n) * 0x40))) |
43 | #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ |
44 | (0x0E004 + ((_n) * 0x40))) |
45 | #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ |
46 | (0x0E008 + ((_n) * 0x40))) |
47 | #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ |
48 | (0x0E010 + ((_n) * 0x40))) |
49 | #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ |
50 | (0x0E018 + ((_n) * 0x40))) |
51 | #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ |
52 | (0x0E028 + ((_n) * 0x40))) |
53 | #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) |
54 | #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) |
55 | #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ |
56 | (0x054E0 + ((_i - 16) * 8))) |
57 | #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ |
58 | (0x054E4 + ((_i - 16) * 8))) |
59 | |
60 | /* Statistics registers */ |
61 | #define E1000_VFGPRC 0x00F10 |
62 | #define E1000_VFGORC 0x00F18 |
63 | #define E1000_VFMPRC 0x00F3C |
64 | #define E1000_VFGPTC 0x00F14 |
65 | #define E1000_VFGOTC 0x00F34 |
66 | #define E1000_VFGOTLBC 0x00F50 |
67 | #define E1000_VFGPTLBC 0x00F44 |
68 | #define E1000_VFGORLBC 0x00F48 |
69 | #define E1000_VFGPRLBC 0x00F40 |
70 | |
71 | /* These act per VF so an array friendly macro is used */ |
72 | #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) |
73 | #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) |
74 | |
75 | /* Define macros for handling registers */ |
76 | #define er32(reg) readl(hw->hw_addr + E1000_##reg) |
77 | #define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg) |
78 | #define array_er32(reg, offset) \ |
79 | readl(hw->hw_addr + E1000_##reg + (offset << 2)) |
80 | #define array_ew32(reg, offset, val) \ |
81 | writel((val), hw->hw_addr + E1000_##reg + (offset << 2)) |
82 | #define e1e_flush() er32(STATUS) |
83 | |
84 | #endif |
85 | |