1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright(c) 1999 - 2018 Intel Corporation. */ |
3 | |
4 | #ifndef _IXGBE_FCOE_H |
5 | #define _IXGBE_FCOE_H |
6 | |
7 | #include <scsi/fc/fc_fs.h> |
8 | #include <scsi/fc/fc_fcoe.h> |
9 | |
10 | /* shift bits within STAT fo FCSTAT */ |
11 | #define IXGBE_RXDADV_FCSTAT_SHIFT 4 |
12 | |
13 | /* ddp user buffer */ |
14 | #define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */ |
15 | #define IXGBE_FCPTR_ALIGN 16 |
16 | #define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t)) |
17 | #define IXGBE_FCBUFF_4KB 0x0 |
18 | #define IXGBE_FCBUFF_8KB 0x1 |
19 | #define IXGBE_FCBUFF_16KB 0x2 |
20 | #define IXGBE_FCBUFF_64KB 0x3 |
21 | #define IXGBE_FCBUFF_MAX 65536 /* 64KB max */ |
22 | #define IXGBE_FCBUFF_MIN 4096 /* 4KB min */ |
23 | #define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */ |
24 | #define IXGBE_FCOE_DDP_MAX_X550 2048 /* 11 bits xid */ |
25 | |
26 | /* Default traffic class to use for FCoE */ |
27 | #define IXGBE_FCOE_DEFTC 3 |
28 | |
29 | /* fcerr */ |
30 | #define IXGBE_FCERR_BADCRC 0x00100000 |
31 | |
32 | /* FCoE DDP for target mode */ |
33 | #define __IXGBE_FCOE_TARGET 1 |
34 | |
35 | struct ixgbe_fcoe_ddp { |
36 | int len; |
37 | u32 err; |
38 | unsigned int sgc; |
39 | struct scatterlist *sgl; |
40 | dma_addr_t udp; |
41 | u64 *udl; |
42 | struct dma_pool *pool; |
43 | }; |
44 | |
45 | /* per cpu variables */ |
46 | struct ixgbe_fcoe_ddp_pool { |
47 | struct dma_pool *pool; |
48 | u64 noddp; |
49 | u64 noddp_ext_buff; |
50 | }; |
51 | |
52 | struct ixgbe_fcoe { |
53 | struct ixgbe_fcoe_ddp_pool __percpu *ddp_pool; |
54 | atomic_t refcnt; |
55 | spinlock_t lock; |
56 | struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX_X550]; |
57 | void *; |
58 | dma_addr_t ; |
59 | unsigned long mode; |
60 | u8 up; |
61 | }; |
62 | |
63 | #endif /* _IXGBE_FCOE_H */ |
64 | |